Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / a79025c4835496af1960abc6363fe6acd8ca1efd / . / arch / arm / boot / dts / imx53.dtsi
blob: 3aa08f0fda173198dc8cecdc78e44e6e2f1f4c81 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]78 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]79 };
80
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]81 aips@50000000 { /* AIPS1 */
82 compatible = "fsl,aips-bus", "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 reg = <0x50000000 0x10000000>;
86 ranges;
87
88 spba@50000000 {
89 compatible = "fsl,spba-bus", "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 reg = <0x50000000 0x40000>;
93 ranges;
94
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]95 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]96 compatible = "fsl,imx53-esdhc";
97 reg = <0x50004000 0x4000>;
98 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]99 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
100 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]101 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]102 status = "disabled";
103 };
104
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]105 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]106 compatible = "fsl,imx53-esdhc";
107 reg = <0x50008000 0x4000>;
108 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]109 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
110 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]111 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 status = "disabled";
113 };
114
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]115 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]116 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
117 reg = <0x5000c000 0x4000>;
118 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]119 clocks = <&clks 32>, <&clks 33>;
120 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]121 status = "disabled";
122 };
123
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]124 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
128 reg = <0x50010000 0x4000>;
129 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]130 clocks = <&clks 51>, <&clks 52>;
131 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]132 status = "disabled";
133 };
134
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]135 ssi2: ssi@50014000 {
136 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
137 reg = <0x50014000 0x4000>;
138 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]139 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]140 fsl,fifo-depth = <15>;
141 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
142 status = "disabled";
143 };
144
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]145 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]146 compatible = "fsl,imx53-esdhc";
147 reg = <0x50020000 0x4000>;
148 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]149 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
150 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]151 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]152 status = "disabled";
153 };
154
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]155 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]156 compatible = "fsl,imx53-esdhc";
157 reg = <0x50024000 0x4000>;
158 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]159 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
160 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]161 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]162 status = "disabled";
163 };
164 };
165
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame^]166 usbphy0: usbphy@0 {
167 compatible = "usb-nop-xceiv";
168 clocks = <&clks 124>;
169 clock-names = "main_clk";
170 status = "okay";
171 };
172
173 usbphy1: usbphy@1 {
174 compatible = "usb-nop-xceiv";
175 clocks = <&clks 125>;
176 clock-names = "main_clk";
177 status = "okay";
178 };
179
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]180 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]181 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
182 reg = <0x53f80000 0x0200>;
183 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]184 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]185 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame^]186 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]187 status = "disabled";
188 };
189
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]190 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]191 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
192 reg = <0x53f80200 0x0200>;
193 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]194 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]195 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame^]196 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]197 status = "disabled";
198 };
199
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]200 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]201 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
202 reg = <0x53f80400 0x0200>;
203 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]204 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]205 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]206 status = "disabled";
207 };
208
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]209 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]210 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
211 reg = <0x53f80600 0x0200>;
212 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]213 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]214 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]215 status = "disabled";
216 };
217
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]218 usbmisc: usbmisc@53f80800 {
219 #index-cells = <1>;
220 compatible = "fsl,imx53-usbmisc";
221 reg = <0x53f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]222 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]223 };
224
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]225 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]226 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]227 reg = <0x53f84000 0x4000>;
228 interrupts = <50 51>;
229 gpio-controller;
230 #gpio-cells = <2>;
231 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]232 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]233 };
234
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]235 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]236 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]237 reg = <0x53f88000 0x4000>;
238 interrupts = <52 53>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]242 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]243 };
244
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]245 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]246 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]247 reg = <0x53f8c000 0x4000>;
248 interrupts = <54 55>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]252 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]253 };
254
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]255 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]256 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]257 reg = <0x53f90000 0x4000>;
258 interrupts = <56 57>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]262 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]263 };
264
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]265 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]266 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
267 reg = <0x53f98000 0x4000>;
268 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]269 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]270 };
271
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]272 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]273 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
274 reg = <0x53f9c000 0x4000>;
275 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]276 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]277 status = "disabled";
278 };
279
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]280 gpt: timer@53fa0000 {
281 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
282 reg = <0x53fa0000 0x4000>;
283 interrupts = <39>;
284 clocks = <&clks 36>, <&clks 41>;
285 clock-names = "ipg", "per";
286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]288 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]289 compatible = "fsl,imx53-iomuxc";
290 reg = <0x53fa8000 0x4000>;
291
292 audmux {
293 pinctrl_audmux_1: audmuxgrp-1 {
294 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]295 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
296 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
297 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
298 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]299 >;
300 };
301 };
302
303 fec {
304 pinctrl_fec_1: fecgrp-1 {
305 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]306 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
307 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
308 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
309 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
310 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
311 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
312 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
313 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
314 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
315 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]316 >;
317 };
318 };
319
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]320 csi {
321 pinctrl_csi_1: csigrp-1 {
322 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]323 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
324 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
325 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
326 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
327 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
328 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
329 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
330 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
331 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
332 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
333 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
334 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
335 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
336 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
337 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
338 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
339 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
340 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
341 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
342 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
343 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]344 >;
345 };
346 };
347
348 cspi {
349 pinctrl_cspi_1: cspigrp-1 {
350 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]351 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
352 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
353 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]354 >;
355 };
356 };
357
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]358 ecspi1 {
359 pinctrl_ecspi1_1: ecspi1grp-1 {
360 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]361 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
362 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
363 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]364 >;
365 };
366 };
367
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]368 esdhc1 {
369 pinctrl_esdhc1_1: esdhc1grp-1 {
370 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]371 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
372 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
373 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
374 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
375 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
376 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]377 >;
378 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]379
380 pinctrl_esdhc1_2: esdhc1grp-2 {
381 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]382 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
383 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
384 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
385 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
386 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
387 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
388 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
389 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
390 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
391 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]392 >;
393 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]394 };
395
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]396 esdhc2 {
397 pinctrl_esdhc2_1: esdhc2grp-1 {
398 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]399 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
400 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
401 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
402 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
403 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
404 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]405 >;
406 };
407 };
408
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]409 esdhc3 {
410 pinctrl_esdhc3_1: esdhc3grp-1 {
411 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]412 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
413 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
414 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
415 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
416 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
417 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
418 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
419 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
420 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
421 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]422 >;
423 };
424 };
425
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]426 can1 {
427 pinctrl_can1_1: can1grp-1 {
428 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]429 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
430 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]431 >;
432 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]433
434 pinctrl_can1_2: can1grp-2 {
435 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]436 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
437 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]438 >;
439 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]440 };
441
442 can2 {
443 pinctrl_can2_1: can2grp-1 {
444 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]445 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
446 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]447 >;
448 };
449 };
450
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]451 i2c1 {
452 pinctrl_i2c1_1: i2c1grp-1 {
453 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]454 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
455 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]456 >;
457 };
458 };
459
460 i2c2 {
461 pinctrl_i2c2_1: i2c2grp-1 {
462 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]463 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
464 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]465 >;
466 };
467 };
468
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]469 i2c3 {
470 pinctrl_i2c3_1: i2c3grp-1 {
471 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]472 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
473 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]474 >;
475 };
476 };
477
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]478 owire {
479 pinctrl_owire_1: owiregrp-1 {
480 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]481 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]482 >;
483 };
484 };
485
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]486 uart1 {
487 pinctrl_uart1_1: uart1grp-1 {
488 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]489 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
490 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]491 >;
492 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]493
494 pinctrl_uart1_2: uart1grp-2 {
495 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]496 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
497 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]498 >;
499 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]500 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]501
502 uart2 {
503 pinctrl_uart2_1: uart2grp-1 {
504 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]505 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
506 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]507 >;
508 };
509 };
510
511 uart3 {
512 pinctrl_uart3_1: uart3grp-1 {
513 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]514 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
515 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
516 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
517 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]518 >;
519 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]520
521 pinctrl_uart3_2: uart3grp-2 {
522 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]523 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
524 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]525 >;
526 };
527
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]528 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]529
530 uart4 {
531 pinctrl_uart4_1: uart4grp-1 {
532 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]533 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
534 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]535 >;
536 };
537 };
538
539 uart5 {
540 pinctrl_uart5_1: uart5grp-1 {
541 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]542 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
543 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]544 >;
545 };
546 };
547
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]548 };
549
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]550 gpr: iomuxc-gpr@53fa8000 {
551 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
552 reg = <0x53fa8000 0xc>;
553 };
554
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]555 ldb: ldb@53fa8008 {
556 #address-cells = <1>;
557 #size-cells = <0>;
558 compatible = "fsl,imx53-ldb";
559 reg = <0x53fa8008 0x4>;
560 gpr = <&gpr>;
561 clocks = <&clks 122>, <&clks 120>,
562 <&clks 115>, <&clks 116>,
563 <&clks 123>, <&clks 85>;
564 clock-names = "di0_pll", "di1_pll",
565 "di0_sel", "di1_sel",
566 "di0", "di1";
567 status = "disabled";
568
569 lvds-channel@0 {
570 reg = <0>;
571 crtcs = <&ipu 0>;
572 status = "disabled";
573 };
574
575 lvds-channel@1 {
576 reg = <1>;
577 crtcs = <&ipu 1>;
578 status = "disabled";
579 };
580 };
581
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]582 pwm1: pwm@53fb4000 {
583 #pwm-cells = <2>;
584 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
585 reg = <0x53fb4000 0x4000>;
586 clocks = <&clks 37>, <&clks 38>;
587 clock-names = "ipg", "per";
588 interrupts = <61>;
589 };
590
591 pwm2: pwm@53fb8000 {
592 #pwm-cells = <2>;
593 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
594 reg = <0x53fb8000 0x4000>;
595 clocks = <&clks 39>, <&clks 40>;
596 clock-names = "ipg", "per";
597 interrupts = <94>;
598 };
599
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]600 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]601 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
602 reg = <0x53fbc000 0x4000>;
603 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]604 clocks = <&clks 28>, <&clks 29>;
605 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]606 status = "disabled";
607 };
608
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]609 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]610 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
611 reg = <0x53fc0000 0x4000>;
612 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]613 clocks = <&clks 30>, <&clks 31>;
614 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]615 status = "disabled";
616 };
617
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]618 can1: can@53fc8000 {
619 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
620 reg = <0x53fc8000 0x4000>;
621 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]622 clocks = <&clks 158>, <&clks 157>;
623 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]624 status = "disabled";
625 };
626
627 can2: can@53fcc000 {
628 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
629 reg = <0x53fcc000 0x4000>;
630 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]631 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]632 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]633 status = "disabled";
634 };
635
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]636 src: src@53fd0000 {
637 compatible = "fsl,imx53-src", "fsl,imx51-src";
638 reg = <0x53fd0000 0x4000>;
639 #reset-cells = <1>;
640 };
641
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]642 clks: ccm@53fd4000{
643 compatible = "fsl,imx53-ccm";
644 reg = <0x53fd4000 0x4000>;
645 interrupts = <0 71 0x04 0 72 0x04>;
646 #clock-cells = <1>;
647 };
648
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]649 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]650 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]651 reg = <0x53fdc000 0x4000>;
652 interrupts = <103 104>;
653 gpio-controller;
654 #gpio-cells = <2>;
655 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]656 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]657 };
658
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]659 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]660 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]661 reg = <0x53fe0000 0x4000>;
662 interrupts = <105 106>;
663 gpio-controller;
664 #gpio-cells = <2>;
665 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]666 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]667 };
668
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]669 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]670 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]671 reg = <0x53fe4000 0x4000>;
672 interrupts = <107 108>;
673 gpio-controller;
674 #gpio-cells = <2>;
675 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]676 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]677 };
678
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]679 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]680 #address-cells = <1>;
681 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]682 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]683 reg = <0x53fec000 0x4000>;
684 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]685 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]686 status = "disabled";
687 };
688
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]689 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]690 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
691 reg = <0x53ff0000 0x4000>;
692 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]693 clocks = <&clks 65>, <&clks 66>;
694 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]695 status = "disabled";
696 };
697 };
698
699 aips@60000000 { /* AIPS2 */
700 compatible = "fsl,aips-bus", "simple-bus";
701 #address-cells = <1>;
702 #size-cells = <1>;
703 reg = <0x60000000 0x10000000>;
704 ranges;
705
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]706 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]707 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
708 reg = <0x63f90000 0x4000>;
709 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]710 clocks = <&clks 67>, <&clks 68>;
711 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]712 status = "disabled";
713 };
714
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]715 owire: owire@63fa4000 {
716 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
717 reg = <0x63fa4000 0x4000>;
718 clocks = <&clks 159>;
719 status = "disabled";
720 };
721
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]722 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
726 reg = <0x63fac000 0x4000>;
727 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]728 clocks = <&clks 53>, <&clks 54>;
729 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]730 status = "disabled";
731 };
732
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]733 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]734 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
735 reg = <0x63fb0000 0x4000>;
736 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]737 clocks = <&clks 56>, <&clks 56>;
738 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]739 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]740 };
741
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]742 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]743 #address-cells = <1>;
744 #size-cells = <0>;
745 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
746 reg = <0x63fc0000 0x4000>;
747 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]748 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]749 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]750 status = "disabled";
751 };
752
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]753 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]754 #address-cells = <1>;
755 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]756 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]757 reg = <0x63fc4000 0x4000>;
758 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]759 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]760 status = "disabled";
761 };
762
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]763 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]764 #address-cells = <1>;
765 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]766 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]767 reg = <0x63fc8000 0x4000>;
768 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]769 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]770 status = "disabled";
771 };
772
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]773 ssi1: ssi@63fcc000 {
774 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
775 reg = <0x63fcc000 0x4000>;
776 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]777 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]778 fsl,fifo-depth = <15>;
779 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
780 status = "disabled";
781 };
782
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]783 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]784 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
785 reg = <0x63fd0000 0x4000>;
786 status = "disabled";
787 };
788
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]789 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]790 compatible = "fsl,imx53-nand";
791 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
792 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]793 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]794 status = "disabled";
795 };
796
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]797 ssi3: ssi@63fe8000 {
798 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
799 reg = <0x63fe8000 0x4000>;
800 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]801 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]802 fsl,fifo-depth = <15>;
803 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
804 status = "disabled";
805 };
806
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]807 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]808 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
809 reg = <0x63fec000 0x4000>;
810 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]811 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
812 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]813 status = "disabled";
814 };
815 };
816 };
817};