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Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030031 */
32
Yuval Mintz36558c32016-05-11 16:36:17 +030033#include <linux/crc32.h>
Yuval Mintzeff16962016-05-11 16:36:21 +030034#include <linux/etherdevice.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030035#include "qed.h"
36#include "qed_sriov.h"
37#include "qed_vf.h"
38
39static void *qed_vf_pf_prep(struct qed_hwfn *p_hwfn, u16 type, u16 length)
40{
41 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
42 void *p_tlv;
43
44 /* This lock is released when we receive PF's response
45 * in qed_send_msg2pf().
46 * So, qed_vf_pf_prep() and qed_send_msg2pf()
47 * must come in sequence.
48 */
49 mutex_lock(&(p_iov->mutex));
50
51 DP_VERBOSE(p_hwfn,
52 QED_MSG_IOV,
53 "preparing to send 0x%04x tlv over vf pf channel\n",
54 type);
55
56 /* Reset Requst offset */
57 p_iov->offset = (u8 *)p_iov->vf2pf_request;
58
59 /* Clear mailbox - both request and reply */
60 memset(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs));
61 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
62
63 /* Init type and length */
64 p_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, type, length);
65
66 /* Init first tlv header */
67 ((struct vfpf_first_tlv *)p_tlv)->reply_address =
68 (u64)p_iov->pf2vf_reply_phys;
69
70 return p_tlv;
71}
72
Yuval Mintzb0bccb62016-08-22 13:25:12 +030073static void qed_vf_pf_req_end(struct qed_hwfn *p_hwfn, int req_status)
74{
75 union pfvf_tlvs *resp = p_hwfn->vf_iov_info->pf2vf_reply;
76
77 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
78 "VF request status = 0x%x, PF reply status = 0x%x\n",
79 req_status, resp->default_resp.hdr.status);
80
81 mutex_unlock(&(p_hwfn->vf_iov_info->mutex));
82}
83
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030084static int qed_send_msg2pf(struct qed_hwfn *p_hwfn, u8 *done, u32 resp_size)
85{
86 union vfpf_tlvs *p_req = p_hwfn->vf_iov_info->vf2pf_request;
87 struct ustorm_trigger_vf_zone trigger;
88 struct ustorm_vf_zone *zone_data;
89 int rc = 0, time = 100;
90
91 zone_data = (struct ustorm_vf_zone *)PXP_VF_BAR0_START_USDM_ZONE_B;
92
93 /* output tlvs list */
94 qed_dp_tlv_list(p_hwfn, p_req);
95
96 /* need to add the END TLV to the message size */
97 resp_size += sizeof(struct channel_list_end_tlv);
98
99 /* Send TLVs over HW channel */
100 memset(&trigger, 0, sizeof(struct ustorm_trigger_vf_zone));
101 trigger.vf_pf_msg_valid = 1;
102
103 DP_VERBOSE(p_hwfn,
104 QED_MSG_IOV,
105 "VF -> PF [%02x] message: [%08x, %08x] --> %p, %08x --> %p\n",
106 GET_FIELD(p_hwfn->hw_info.concrete_fid,
107 PXP_CONCRETE_FID_PFID),
108 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
109 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
110 &zone_data->non_trigger.vf_pf_msg_addr,
111 *((u32 *)&trigger), &zone_data->trigger);
112
113 REG_WR(p_hwfn,
114 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.lo,
115 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
116
117 REG_WR(p_hwfn,
118 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.hi,
119 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
120
121 /* The message data must be written first, to prevent trigger before
122 * data is written.
123 */
124 wmb();
125
126 REG_WR(p_hwfn, (uintptr_t)&zone_data->trigger, *((u32 *)&trigger));
127
128 /* When PF would be done with the response, it would write back to the
129 * `done' address. Poll until then.
130 */
131 while ((!*done) && time) {
132 msleep(25);
133 time--;
134 }
135
136 if (!*done) {
Mintz, Yuval81e64ef2017-03-19 13:08:12 +0200137 DP_NOTICE(p_hwfn,
138 "VF <-- PF Timeout [Type %d]\n",
139 p_req->first_tlv.tl.type);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300140 rc = -EBUSY;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300141 } else {
Mintz, Yuval81e64ef2017-03-19 13:08:12 +0200142 if ((*done != PFVF_STATUS_SUCCESS) &&
143 (*done != PFVF_STATUS_NO_RESOURCE))
144 DP_NOTICE(p_hwfn,
145 "PF response: %d [Type %d]\n",
146 *done, p_req->first_tlv.tl.type);
147 else
148 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
149 "PF response: %d [Type %d]\n",
150 *done, p_req->first_tlv.tl.type);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300151 }
152
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300153 return rc;
154}
155
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300156static void qed_vf_pf_add_qid(struct qed_hwfn *p_hwfn,
157 struct qed_queue_cid *p_cid)
158{
159 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
160 struct vfpf_qid_tlv *p_qid_tlv;
161
162 /* Only add QIDs for the queue if it was negotiated with PF */
163 if (!(p_iov->acquire_resp.pfdev_info.capabilities &
164 PFVF_ACQUIRE_CAP_QUEUE_QIDS))
165 return;
166
167 p_qid_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
168 CHANNEL_TLV_QID, sizeof(*p_qid_tlv));
169 p_qid_tlv->qid = p_cid->qid_usage_idx;
170}
171
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300172int _qed_vf_pf_release(struct qed_hwfn *p_hwfn, bool b_final)
173{
174 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
175 struct pfvf_def_resp_tlv *resp;
176 struct vfpf_first_tlv *req;
177 u32 size;
178 int rc;
179
180 /* clear mailbox and prep first tlv */
181 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));
182
183 /* add list termination tlv */
184 qed_add_tlv(p_hwfn, &p_iov->offset,
185 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
186
187 resp = &p_iov->pf2vf_reply->default_resp;
188 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
189
190 if (!rc && resp->hdr.status != PFVF_STATUS_SUCCESS)
191 rc = -EAGAIN;
192
193 qed_vf_pf_req_end(p_hwfn, rc);
194 if (!b_final)
195 return rc;
196
197 p_hwfn->b_int_enabled = 0;
198
199 if (p_iov->vf2pf_request)
200 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
201 sizeof(union vfpf_tlvs),
202 p_iov->vf2pf_request,
203 p_iov->vf2pf_request_phys);
204 if (p_iov->pf2vf_reply)
205 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
206 sizeof(union pfvf_tlvs),
207 p_iov->pf2vf_reply, p_iov->pf2vf_reply_phys);
208
209 if (p_iov->bulletin.p_virt) {
210 size = sizeof(struct qed_bulletin_content);
211 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
212 size,
213 p_iov->bulletin.p_virt, p_iov->bulletin.phys);
214 }
215
216 kfree(p_hwfn->vf_iov_info);
217 p_hwfn->vf_iov_info = NULL;
218
219 return rc;
220}
221
222int qed_vf_pf_release(struct qed_hwfn *p_hwfn)
223{
224 return _qed_vf_pf_release(p_hwfn, true);
225}
226
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300227#define VF_ACQUIRE_THRESH 3
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300228static void qed_vf_pf_acquire_reduce_resc(struct qed_hwfn *p_hwfn,
229 struct vf_pf_resc_request *p_req,
230 struct pf_vf_resc *p_resp)
231{
232 DP_VERBOSE(p_hwfn,
233 QED_MSG_IOV,
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300234 "PF unwilling to fullill resource request: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x] cids [%02x/%02x]. Try PF recommended amount\n",
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300235 p_req->num_rxqs,
236 p_resp->num_rxqs,
237 p_req->num_rxqs,
238 p_resp->num_txqs,
239 p_req->num_sbs,
240 p_resp->num_sbs,
241 p_req->num_mac_filters,
242 p_resp->num_mac_filters,
243 p_req->num_vlan_filters,
244 p_resp->num_vlan_filters,
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300245 p_req->num_mc_filters,
246 p_resp->num_mc_filters, p_req->num_cids, p_resp->num_cids);
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300247
248 /* humble our request */
249 p_req->num_txqs = p_resp->num_txqs;
250 p_req->num_rxqs = p_resp->num_rxqs;
251 p_req->num_sbs = p_resp->num_sbs;
252 p_req->num_mac_filters = p_resp->num_mac_filters;
253 p_req->num_vlan_filters = p_resp->num_vlan_filters;
254 p_req->num_mc_filters = p_resp->num_mc_filters;
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300255 p_req->num_cids = p_resp->num_cids;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300256}
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300257
258static int qed_vf_pf_acquire(struct qed_hwfn *p_hwfn)
259{
260 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
261 struct pfvf_acquire_resp_tlv *resp = &p_iov->pf2vf_reply->acquire_resp;
262 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300263 struct vf_pf_resc_request *p_resc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300264 bool resources_acquired = false;
265 struct vfpf_acquire_tlv *req;
266 int rc = 0, attempts = 0;
267
268 /* clear mailbox and prep first tlv */
269 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_ACQUIRE, sizeof(*req));
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300270 p_resc = &req->resc_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300271
272 /* starting filling the request */
273 req->vfdev_info.opaque_fid = p_hwfn->hw_info.opaque_fid;
274
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300275 p_resc->num_rxqs = QED_MAX_VF_CHAINS_PER_PF;
276 p_resc->num_txqs = QED_MAX_VF_CHAINS_PER_PF;
277 p_resc->num_sbs = QED_MAX_VF_CHAINS_PER_PF;
278 p_resc->num_mac_filters = QED_ETH_VF_NUM_MAC_FILTERS;
279 p_resc->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300280 p_resc->num_cids = QED_ETH_VF_DEFAULT_NUM_CIDS;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300281
282 req->vfdev_info.os_type = VFPF_ACQUIRE_OS_LINUX;
283 req->vfdev_info.fw_major = FW_MAJOR_VERSION;
284 req->vfdev_info.fw_minor = FW_MINOR_VERSION;
285 req->vfdev_info.fw_revision = FW_REVISION_VERSION;
286 req->vfdev_info.fw_engineering = FW_ENGINEERING_VERSION;
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300287 req->vfdev_info.eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
288 req->vfdev_info.eth_fp_hsi_minor = ETH_HSI_VER_MINOR;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300289
290 /* Fill capability field with any non-deprecated config we support */
291 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_100G;
292
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300293 /* If we've mapped the doorbell bar, try using queue qids */
Mintz, Yuvalcbb8a122017-06-04 13:31:08 +0300294 if (p_iov->b_doorbell_bar) {
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300295 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_PHYSICAL_BAR |
296 VFPF_ACQUIRE_CAP_QUEUE_QIDS;
Mintz, Yuvalcbb8a122017-06-04 13:31:08 +0300297 p_resc->num_cids = QED_ETH_VF_MAX_NUM_CIDS;
298 }
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300299
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300300 /* pf 2 vf bulletin board address */
301 req->bulletin_addr = p_iov->bulletin.phys;
302 req->bulletin_size = p_iov->bulletin.size;
303
304 /* add list termination tlv */
305 qed_add_tlv(p_hwfn, &p_iov->offset,
306 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
307
308 while (!resources_acquired) {
309 DP_VERBOSE(p_hwfn,
310 QED_MSG_IOV, "attempting to acquire resources\n");
311
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300312 /* Clear response buffer, as this might be a re-send */
313 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
314
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300315 /* send acquire request */
316 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
317 if (rc)
Dan Carpenter66117a92017-04-28 15:56:09 +0300318 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300319
320 /* copy acquire response from buffer to p_hwfn */
321 memcpy(&p_iov->acquire_resp, resp, sizeof(p_iov->acquire_resp));
322
323 attempts++;
324
325 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
326 /* PF agrees to allocate our resources */
327 if (!(resp->pfdev_info.capabilities &
328 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE)) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300329 /* It's possible legacy PF mistakenly accepted;
330 * but we don't care - simply mark it as
331 * legacy and continue.
332 */
333 req->vfdev_info.capabilities |=
334 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300335 }
336 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "resources acquired\n");
337 resources_acquired = true;
338 } else if (resp->hdr.status == PFVF_STATUS_NO_RESOURCE &&
339 attempts < VF_ACQUIRE_THRESH) {
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300340 qed_vf_pf_acquire_reduce_resc(p_hwfn, p_resc,
341 &resp->resc);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300342 } else if (resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED) {
343 if (pfdev_info->major_fp_hsi &&
344 (pfdev_info->major_fp_hsi != ETH_HSI_VER_MAJOR)) {
345 DP_NOTICE(p_hwfn,
346 "PF uses an incompatible fastpath HSI %02x.%02x [VF requires %02x.%02x]. Please change to a VF driver using %02x.xx.\n",
347 pfdev_info->major_fp_hsi,
348 pfdev_info->minor_fp_hsi,
349 ETH_HSI_VER_MAJOR,
350 ETH_HSI_VER_MINOR,
351 pfdev_info->major_fp_hsi);
352 rc = -EINVAL;
353 goto exit;
354 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300355
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300356 if (!pfdev_info->major_fp_hsi) {
357 if (req->vfdev_info.capabilities &
358 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
359 DP_NOTICE(p_hwfn,
360 "PF uses very old drivers. Please change to a VF driver using no later than 8.8.x.x.\n");
361 rc = -EINVAL;
362 goto exit;
363 } else {
364 DP_INFO(p_hwfn,
365 "PF is old - try re-acquire to see if it supports FW-version override\n");
366 req->vfdev_info.capabilities |=
367 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
368 continue;
369 }
370 }
371
372 /* If PF/VF are using same Major, PF must have had
373 * it's reasons. Simply fail.
374 */
375 DP_NOTICE(p_hwfn, "PF rejected acquisition by VF\n");
376 rc = -EINVAL;
377 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300378 } else {
379 DP_ERR(p_hwfn,
380 "PF returned error %d to VF acquisition request\n",
381 resp->hdr.status);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300382 rc = -EAGAIN;
383 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300384 }
385 }
386
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300387 /* Mark the PF as legacy, if needed */
388 if (req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_PRE_FP_HSI)
389 p_iov->b_pre_fp_hsi = true;
390
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300391 /* In case PF doesn't support multi-queue Tx, update the number of
392 * CIDs to reflect the number of queues [older PFs didn't fill that
393 * field].
394 */
395 if (!(resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_QUEUE_QIDS))
396 resp->resc.num_cids = resp->resc.num_rxqs + resp->resc.num_txqs;
397
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300398 /* Update bulletin board size with response from PF */
399 p_iov->bulletin.size = resp->bulletin_size;
400
401 /* get HW info */
402 p_hwfn->cdev->type = resp->pfdev_info.dev_type;
403 p_hwfn->cdev->chip_rev = resp->pfdev_info.chip_rev;
404
405 p_hwfn->cdev->chip_num = pfdev_info->chip_num & 0xffff;
406
407 /* Learn of the possibility of CMT */
408 if (IS_LEAD_HWFN(p_hwfn)) {
409 if (resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_100G) {
410 DP_NOTICE(p_hwfn, "100g VF\n");
411 p_hwfn->cdev->num_hwfns = 2;
412 }
413 }
414
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300415 if (!p_iov->b_pre_fp_hsi &&
416 ETH_HSI_VER_MINOR &&
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300417 (resp->pfdev_info.minor_fp_hsi < ETH_HSI_VER_MINOR)) {
418 DP_INFO(p_hwfn,
419 "PF is using older fastpath HSI; %02x.%02x is configured\n",
420 ETH_HSI_VER_MAJOR, resp->pfdev_info.minor_fp_hsi);
421 }
422
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300423exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300424 qed_vf_pf_req_end(p_hwfn, rc);
425
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300426 return rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300427}
428
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300429u32 qed_vf_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
430{
431 u32 bar_size;
432
433 /* Regview size is fixed */
434 if (bar_id == BAR_ID_0)
435 return 1 << 17;
436
437 /* Doorbell is received from PF */
438 bar_size = p_hwfn->vf_iov_info->acquire_resp.pfdev_info.bar_size;
439 if (bar_size)
440 return 1 << bar_size;
441 return 0;
442}
443
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300444int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
445{
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300446 struct qed_hwfn *p_lead = QED_LEADING_HWFN(p_hwfn->cdev);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300447 struct qed_vf_iov *p_iov;
448 u32 reg;
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300449 int rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300450
451 /* Set number of hwfns - might be overriden once leading hwfn learns
452 * actual configuration from PF.
453 */
454 if (IS_LEAD_HWFN(p_hwfn))
455 p_hwfn->cdev->num_hwfns = 1;
456
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300457 reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;
458 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
459
460 reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;
461 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
462
463 /* Allocate vf sriov info */
464 p_iov = kzalloc(sizeof(*p_iov), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700465 if (!p_iov)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300466 return -ENOMEM;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300467
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300468 /* Doorbells are tricky; Upper-layer has alreday set the hwfn doorbell
469 * value, but there are several incompatibily scenarios where that
470 * would be incorrect and we'd need to override it.
471 */
472 if (!p_hwfn->doorbells) {
473 p_hwfn->doorbells = (u8 __iomem *)p_hwfn->regview +
474 PXP_VF_BAR0_START_DQ;
475 } else if (p_hwfn == p_lead) {
476 /* For leading hw-function, value is always correct, but need
477 * to handle scenario where legacy PF would not support 100g
478 * mapped bars later.
479 */
480 p_iov->b_doorbell_bar = true;
481 } else {
482 /* here, value would be correct ONLY if the leading hwfn
483 * received indication that mapped-bars are supported.
484 */
485 if (p_lead->vf_iov_info->b_doorbell_bar)
486 p_iov->b_doorbell_bar = true;
487 else
488 p_hwfn->doorbells = (u8 __iomem *)
489 p_hwfn->regview + PXP_VF_BAR0_START_DQ;
490 }
491
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300492 /* Allocate vf2pf msg */
493 p_iov->vf2pf_request = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
494 sizeof(union vfpf_tlvs),
495 &p_iov->vf2pf_request_phys,
496 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700497 if (!p_iov->vf2pf_request)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300498 goto free_p_iov;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300499
500 p_iov->pf2vf_reply = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
501 sizeof(union pfvf_tlvs),
502 &p_iov->pf2vf_reply_phys,
503 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700504 if (!p_iov->pf2vf_reply)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300505 goto free_vf2pf_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300506
507 DP_VERBOSE(p_hwfn,
508 QED_MSG_IOV,
509 "VF's Request mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys]\n",
510 p_iov->vf2pf_request,
511 (u64) p_iov->vf2pf_request_phys,
512 p_iov->pf2vf_reply, (u64)p_iov->pf2vf_reply_phys);
513
514 /* Allocate Bulletin board */
515 p_iov->bulletin.size = sizeof(struct qed_bulletin_content);
516 p_iov->bulletin.p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
517 p_iov->bulletin.size,
518 &p_iov->bulletin.phys,
519 GFP_KERNEL);
520 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
521 "VF's bulletin Board [%p virt 0x%llx phys 0x%08x bytes]\n",
522 p_iov->bulletin.p_virt,
523 (u64)p_iov->bulletin.phys, p_iov->bulletin.size);
524
525 mutex_init(&p_iov->mutex);
526
527 p_hwfn->vf_iov_info = p_iov;
528
529 p_hwfn->hw_info.personality = QED_PCI_ETH;
530
Mintz, Yuval1a850bf2017-06-04 13:31:07 +0300531 rc = qed_vf_pf_acquire(p_hwfn);
532
533 /* If VF is 100g using a mapped bar and PF is too old to support that,
534 * acquisition would succeed - but the VF would have no way knowing
535 * the size of the doorbell bar configured in HW and thus will not
536 * know how to split it for 2nd hw-function.
537 * In this case we re-try without the indication of the mapped
538 * doorbell.
539 */
540 if (!rc && p_iov->b_doorbell_bar &&
541 !qed_vf_hw_bar_size(p_hwfn, BAR_ID_1) &&
542 (p_hwfn->cdev->num_hwfns > 1)) {
543 rc = _qed_vf_pf_release(p_hwfn, false);
544 if (rc)
545 return rc;
546
547 p_iov->b_doorbell_bar = false;
548 p_hwfn->doorbells = (u8 __iomem *)p_hwfn->regview +
549 PXP_VF_BAR0_START_DQ;
550 rc = qed_vf_pf_acquire(p_hwfn);
551 }
552
553 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
554 "Regview [%p], Doorbell [%p], Device-doorbell [%p]\n",
555 p_hwfn->regview, p_hwfn->doorbells, p_hwfn->cdev->doorbells);
556
557 return rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300558
559free_vf2pf_request:
560 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
561 sizeof(union vfpf_tlvs),
562 p_iov->vf2pf_request, p_iov->vf2pf_request_phys);
563free_p_iov:
564 kfree(p_iov);
565
566 return -ENOMEM;
567}
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300568#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
569#define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
570 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300571
Chopra, Manisheaf3c0c2017-04-24 10:00:49 -0700572static void
573__qed_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
574 struct qed_tunn_update_type *p_src,
575 enum qed_tunn_clss mask, u8 *p_cls)
576{
577 if (p_src->b_update_mode) {
578 p_req->tun_mode_update_mask |= BIT(mask);
579
580 if (p_src->b_mode_enabled)
581 p_req->tunn_mode |= BIT(mask);
582 }
583
584 *p_cls = p_src->tun_cls;
585}
586
587static void
588qed_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
589 struct qed_tunn_update_type *p_src,
590 enum qed_tunn_clss mask,
591 u8 *p_cls, struct qed_tunn_update_udp_port *p_port,
592 u8 *p_update_port, u16 *p_udp_port)
593{
594 if (p_port->b_update_port) {
595 *p_update_port = 1;
596 *p_udp_port = p_port->port;
597 }
598
599 __qed_vf_prep_tunn_req_tlv(p_req, p_src, mask, p_cls);
600}
601
602void qed_vf_set_vf_start_tunn_update_param(struct qed_tunnel_info *p_tun)
603{
604 if (p_tun->vxlan.b_mode_enabled)
605 p_tun->vxlan.b_update_mode = true;
606 if (p_tun->l2_geneve.b_mode_enabled)
607 p_tun->l2_geneve.b_update_mode = true;
608 if (p_tun->ip_geneve.b_mode_enabled)
609 p_tun->ip_geneve.b_update_mode = true;
610 if (p_tun->l2_gre.b_mode_enabled)
611 p_tun->l2_gre.b_update_mode = true;
612 if (p_tun->ip_gre.b_mode_enabled)
613 p_tun->ip_gre.b_update_mode = true;
614
615 p_tun->b_update_rx_cls = true;
616 p_tun->b_update_tx_cls = true;
617}
618
619static void
620__qed_vf_update_tunn_param(struct qed_tunn_update_type *p_tun,
621 u16 feature_mask, u8 tunn_mode,
622 u8 tunn_cls, enum qed_tunn_mode val)
623{
624 if (feature_mask & BIT(val)) {
625 p_tun->b_mode_enabled = tunn_mode;
626 p_tun->tun_cls = tunn_cls;
627 } else {
628 p_tun->b_mode_enabled = false;
629 }
630}
631
632static void qed_vf_update_tunn_param(struct qed_hwfn *p_hwfn,
633 struct qed_tunnel_info *p_tun,
634 struct pfvf_update_tunn_param_tlv *p_resp)
635{
636 /* Update mode and classes provided by PF */
637 u16 feat_mask = p_resp->tunn_feature_mask;
638
639 __qed_vf_update_tunn_param(&p_tun->vxlan, feat_mask,
640 p_resp->vxlan_mode, p_resp->vxlan_clss,
641 QED_MODE_VXLAN_TUNN);
642 __qed_vf_update_tunn_param(&p_tun->l2_geneve, feat_mask,
643 p_resp->l2geneve_mode,
644 p_resp->l2geneve_clss,
645 QED_MODE_L2GENEVE_TUNN);
646 __qed_vf_update_tunn_param(&p_tun->ip_geneve, feat_mask,
647 p_resp->ipgeneve_mode,
648 p_resp->ipgeneve_clss,
649 QED_MODE_IPGENEVE_TUNN);
650 __qed_vf_update_tunn_param(&p_tun->l2_gre, feat_mask,
651 p_resp->l2gre_mode, p_resp->l2gre_clss,
652 QED_MODE_L2GRE_TUNN);
653 __qed_vf_update_tunn_param(&p_tun->ip_gre, feat_mask,
654 p_resp->ipgre_mode, p_resp->ipgre_clss,
655 QED_MODE_IPGRE_TUNN);
656 p_tun->geneve_port.port = p_resp->geneve_udp_port;
657 p_tun->vxlan_port.port = p_resp->vxlan_udp_port;
658
659 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
660 "tunn mode: vxlan=0x%x, l2geneve=0x%x, ipgeneve=0x%x, l2gre=0x%x, ipgre=0x%x",
661 p_tun->vxlan.b_mode_enabled, p_tun->l2_geneve.b_mode_enabled,
662 p_tun->ip_geneve.b_mode_enabled,
663 p_tun->l2_gre.b_mode_enabled, p_tun->ip_gre.b_mode_enabled);
664}
665
666int qed_vf_pf_tunnel_param_update(struct qed_hwfn *p_hwfn,
667 struct qed_tunnel_info *p_src)
668{
669 struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel;
670 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
671 struct pfvf_update_tunn_param_tlv *p_resp;
672 struct vfpf_update_tunn_param_tlv *p_req;
673 int rc;
674
675 p_req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_TUNN_PARAM,
676 sizeof(*p_req));
677
678 if (p_src->b_update_rx_cls && p_src->b_update_tx_cls)
679 p_req->update_tun_cls = 1;
680
681 qed_vf_prep_tunn_req_tlv(p_req, &p_src->vxlan, QED_MODE_VXLAN_TUNN,
682 &p_req->vxlan_clss, &p_src->vxlan_port,
683 &p_req->update_vxlan_port,
684 &p_req->vxlan_port);
685 qed_vf_prep_tunn_req_tlv(p_req, &p_src->l2_geneve,
686 QED_MODE_L2GENEVE_TUNN,
687 &p_req->l2geneve_clss, &p_src->geneve_port,
688 &p_req->update_geneve_port,
689 &p_req->geneve_port);
690 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->ip_geneve,
691 QED_MODE_IPGENEVE_TUNN,
692 &p_req->ipgeneve_clss);
693 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->l2_gre,
694 QED_MODE_L2GRE_TUNN, &p_req->l2gre_clss);
695 __qed_vf_prep_tunn_req_tlv(p_req, &p_src->ip_gre,
696 QED_MODE_IPGRE_TUNN, &p_req->ipgre_clss);
697
698 /* add list termination tlv */
699 qed_add_tlv(p_hwfn, &p_iov->offset,
700 CHANNEL_TLV_LIST_END,
701 sizeof(struct channel_list_end_tlv));
702
703 p_resp = &p_iov->pf2vf_reply->tunn_param_resp;
704 rc = qed_send_msg2pf(p_hwfn, &p_resp->hdr.status, sizeof(*p_resp));
705
706 if (rc)
707 goto exit;
708
709 if (p_resp->hdr.status != PFVF_STATUS_SUCCESS) {
710 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
711 "Failed to update tunnel parameters\n");
712 rc = -EINVAL;
713 }
714
715 qed_vf_update_tunn_param(p_hwfn, p_tun, p_resp);
716exit:
717 qed_vf_pf_req_end(p_hwfn, rc);
718 return rc;
719}
720
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200721int
722qed_vf_pf_rxq_start(struct qed_hwfn *p_hwfn,
723 struct qed_queue_cid *p_cid,
724 u16 bd_max_bytes,
725 dma_addr_t bd_chain_phys_addr,
726 dma_addr_t cqe_pbl_addr,
727 u16 cqe_pbl_size, void __iomem **pp_prod)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300728{
729 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
730 struct pfvf_start_queue_resp_tlv *resp;
731 struct vfpf_start_rxq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200732 u8 rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300733 int rc;
734
735 /* clear mailbox and prep first tlv */
736 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_RXQ, sizeof(*req));
737
738 req->rx_qid = rx_qid;
739 req->cqe_pbl_addr = cqe_pbl_addr;
740 req->cqe_pbl_size = cqe_pbl_size;
741 req->rxq_addr = bd_chain_phys_addr;
Mintz, Yuvalf604b172017-06-04 13:31:01 +0300742 req->hw_sb = p_cid->sb_igu_id;
743 req->sb_index = p_cid->sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300744 req->bd_max_bytes = bd_max_bytes;
745 req->stat_id = -1;
746
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300747 /* If PF is legacy, we'll need to calculate producers ourselves
748 * as well as clean them.
749 */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200750 if (p_iov->b_pre_fp_hsi) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300751 u8 hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];
752 u32 init_prod_val = 0;
753
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200754 *pp_prod = (u8 __iomem *)
755 p_hwfn->regview +
756 MSTORM_QZONE_START(p_hwfn->cdev) +
757 hw_qid * MSTORM_QZONE_SIZE;
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300758
759 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
760 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
761 (u32 *)(&init_prod_val));
762 }
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300763
764 qed_vf_pf_add_qid(p_hwfn, p_cid);
765
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300766 /* add list termination tlv */
767 qed_add_tlv(p_hwfn, &p_iov->offset,
768 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
769
770 resp = &p_iov->pf2vf_reply->queue_start;
771 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
772 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300773 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300774
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300775 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
776 rc = -EINVAL;
777 goto exit;
778 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300779
780 /* Learn the address of the producer from the response */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200781 if (!p_iov->b_pre_fp_hsi) {
Yuval Mintzb21290b2016-07-27 14:45:21 +0300782 u32 init_prod_val = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300783
784 *pp_prod = (u8 __iomem *)p_hwfn->regview + resp->offset;
785 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
786 "Rxq[0x%02x]: producer at %p [offset 0x%08x]\n",
787 rx_qid, *pp_prod, resp->offset);
788
789 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
Yuval Mintzb21290b2016-07-27 14:45:21 +0300790 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300791 (u32 *)&init_prod_val);
792 }
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300793exit:
794 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300795
796 return rc;
797}
798
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200799int qed_vf_pf_rxq_stop(struct qed_hwfn *p_hwfn,
800 struct qed_queue_cid *p_cid, bool cqe_completion)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300801{
802 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
803 struct vfpf_stop_rxqs_tlv *req;
804 struct pfvf_def_resp_tlv *resp;
805 int rc;
806
807 /* clear mailbox and prep first tlv */
808 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_RXQS, sizeof(*req));
809
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200810 req->rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300811 req->num_rxqs = 1;
812 req->cqe_completion = cqe_completion;
813
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300814 qed_vf_pf_add_qid(p_hwfn, p_cid);
815
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300816 /* add list termination tlv */
817 qed_add_tlv(p_hwfn, &p_iov->offset,
818 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
819
820 resp = &p_iov->pf2vf_reply->default_resp;
821 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
822 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300823 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300824
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300825 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
826 rc = -EINVAL;
827 goto exit;
828 }
829
830exit:
831 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300832
833 return rc;
834}
835
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200836int
837qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
838 struct qed_queue_cid *p_cid,
839 dma_addr_t pbl_addr,
840 u16 pbl_size, void __iomem **pp_doorbell)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300841{
842 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
Yuval Mintz5040acf2016-06-05 13:11:14 +0300843 struct pfvf_start_queue_resp_tlv *resp;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300844 struct vfpf_start_txq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200845 u16 qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300846 int rc;
847
848 /* clear mailbox and prep first tlv */
849 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_TXQ, sizeof(*req));
850
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200851 req->tx_qid = qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300852
853 /* Tx */
854 req->pbl_addr = pbl_addr;
855 req->pbl_size = pbl_size;
Mintz, Yuvalf604b172017-06-04 13:31:01 +0300856 req->hw_sb = p_cid->sb_igu_id;
857 req->sb_index = p_cid->sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300858
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300859 qed_vf_pf_add_qid(p_hwfn, p_cid);
860
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300861 /* add list termination tlv */
862 qed_add_tlv(p_hwfn, &p_iov->offset,
863 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
864
Yuval Mintz5040acf2016-06-05 13:11:14 +0300865 resp = &p_iov->pf2vf_reply->queue_start;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300866 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
867 if (rc)
Yuval Mintz5040acf2016-06-05 13:11:14 +0300868 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300869
Yuval Mintz5040acf2016-06-05 13:11:14 +0300870 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
871 rc = -EINVAL;
872 goto exit;
873 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300874
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200875 /* Modern PFs provide the actual offsets, while legacy
876 * provided only the queue id.
877 */
878 if (!p_iov->b_pre_fp_hsi) {
879 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + resp->offset;
880 } else {
881 u8 cid = p_iov->acquire_resp.resc.cid[qid];
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300882
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200883 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
884 qed_db_addr_vf(cid,
885 DQ_DEMS_LEGACY);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300886 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200887
888 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
Mintz, Yuvalcbb8a122017-06-04 13:31:08 +0300889 "Txq[0x%02x.%02x]: doorbell at %p [offset 0x%08x]\n",
890 qid, p_cid->qid_usage_idx, *pp_doorbell, resp->offset);
Yuval Mintz5040acf2016-06-05 13:11:14 +0300891exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300892 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300893
894 return rc;
895}
896
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200897int qed_vf_pf_txq_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300898{
899 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
900 struct vfpf_stop_txqs_tlv *req;
901 struct pfvf_def_resp_tlv *resp;
902 int rc;
903
904 /* clear mailbox and prep first tlv */
905 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_TXQS, sizeof(*req));
906
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200907 req->tx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300908 req->num_txqs = 1;
909
Mintz, Yuval08bc8f12017-06-04 13:31:06 +0300910 qed_vf_pf_add_qid(p_hwfn, p_cid);
911
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300912 /* add list termination tlv */
913 qed_add_tlv(p_hwfn, &p_iov->offset,
914 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
915
916 resp = &p_iov->pf2vf_reply->default_resp;
917 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
918 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300919 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300920
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300921 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
922 rc = -EINVAL;
923 goto exit;
924 }
925
926exit:
927 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300928
929 return rc;
930}
931
932int qed_vf_pf_vport_start(struct qed_hwfn *p_hwfn,
933 u8 vport_id,
934 u16 mtu,
935 u8 inner_vlan_removal,
936 enum qed_tpa_mode tpa_mode,
Yuval Mintz08feecd2016-05-11 16:36:20 +0300937 u8 max_buffers_per_cqe, u8 only_untagged)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300938{
939 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
940 struct vfpf_vport_start_tlv *req;
941 struct pfvf_def_resp_tlv *resp;
942 int rc, i;
943
944 /* clear mailbox and prep first tlv */
945 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_START, sizeof(*req));
946
947 req->mtu = mtu;
948 req->vport_id = vport_id;
949 req->inner_vlan_removal = inner_vlan_removal;
950 req->tpa_mode = tpa_mode;
951 req->max_buffers_per_cqe = max_buffers_per_cqe;
Yuval Mintz08feecd2016-05-11 16:36:20 +0300952 req->only_untagged = only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300953
954 /* status blocks */
Mintz, Yuval50a20712017-06-01 15:29:09 +0300955 for (i = 0; i < p_hwfn->vf_iov_info->acquire_resp.resc.num_sbs; i++) {
956 struct qed_sb_info *p_sb = p_hwfn->vf_iov_info->sbs_info[i];
957
958 if (p_sb)
959 req->sb_addr[i] = p_sb->sb_phys;
960 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300961
962 /* add list termination tlv */
963 qed_add_tlv(p_hwfn, &p_iov->offset,
964 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
965
966 resp = &p_iov->pf2vf_reply->default_resp;
967 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
968 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300969 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300970
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300971 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
972 rc = -EINVAL;
973 goto exit;
974 }
975
976exit:
977 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300978
979 return rc;
980}
981
982int qed_vf_pf_vport_stop(struct qed_hwfn *p_hwfn)
983{
984 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
985 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
986 int rc;
987
988 /* clear mailbox and prep first tlv */
989 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_TEARDOWN,
990 sizeof(struct vfpf_first_tlv));
991
992 /* add list termination tlv */
993 qed_add_tlv(p_hwfn, &p_iov->offset,
994 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
995
996 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
997 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300998 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300999
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001000 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1001 rc = -EINVAL;
1002 goto exit;
1003 }
1004
1005exit:
1006 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001007
1008 return rc;
1009}
1010
1011static bool
1012qed_vf_handle_vp_update_is_needed(struct qed_hwfn *p_hwfn,
1013 struct qed_sp_vport_update_params *p_data,
1014 u16 tlv)
1015{
1016 switch (tlv) {
1017 case CHANNEL_TLV_VPORT_UPDATE_ACTIVATE:
1018 return !!(p_data->update_vport_active_rx_flg ||
1019 p_data->update_vport_active_tx_flg);
Yuval Mintz17b235c2016-05-11 16:36:18 +03001020 case CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH:
1021 return !!p_data->update_tx_switching_flg;
1022 case CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP:
1023 return !!p_data->update_inner_vlan_removal_flg;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001024 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN:
1025 return !!p_data->update_accept_any_vlan_flg;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001026 case CHANNEL_TLV_VPORT_UPDATE_MCAST:
1027 return !!p_data->update_approx_mcast_flg;
1028 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM:
1029 return !!(p_data->accept_flags.update_rx_mode_config ||
1030 p_data->accept_flags.update_tx_mode_config);
1031 case CHANNEL_TLV_VPORT_UPDATE_RSS:
1032 return !!p_data->rss_params;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001033 case CHANNEL_TLV_VPORT_UPDATE_SGE_TPA:
1034 return !!p_data->sge_tpa_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001035 default:
1036 DP_INFO(p_hwfn, "Unexpected vport-update TLV[%d]\n",
1037 tlv);
1038 return false;
1039 }
1040}
1041
1042static void
1043qed_vf_handle_vp_update_tlvs_resp(struct qed_hwfn *p_hwfn,
1044 struct qed_sp_vport_update_params *p_data)
1045{
1046 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1047 struct pfvf_def_resp_tlv *p_resp;
1048 u16 tlv;
1049
1050 for (tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
1051 tlv < CHANNEL_TLV_VPORT_UPDATE_MAX; tlv++) {
1052 if (!qed_vf_handle_vp_update_is_needed(p_hwfn, p_data, tlv))
1053 continue;
1054
1055 p_resp = (struct pfvf_def_resp_tlv *)
1056 qed_iov_search_list_tlvs(p_hwfn, p_iov->pf2vf_reply,
1057 tlv);
1058 if (p_resp && p_resp->hdr.status)
1059 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1060 "TLV[%d] Configuration %s\n",
1061 tlv,
1062 (p_resp && p_resp->hdr.status) ? "succeeded"
1063 : "failed");
1064 }
1065}
1066
1067int qed_vf_pf_vport_update(struct qed_hwfn *p_hwfn,
1068 struct qed_sp_vport_update_params *p_params)
1069{
1070 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1071 struct vfpf_vport_update_tlv *req;
1072 struct pfvf_def_resp_tlv *resp;
1073 u8 update_rx, update_tx;
1074 u32 resp_size = 0;
1075 u16 size, tlv;
1076 int rc;
1077
1078 resp = &p_iov->pf2vf_reply->default_resp;
1079 resp_size = sizeof(*resp);
1080
1081 update_rx = p_params->update_vport_active_rx_flg;
1082 update_tx = p_params->update_vport_active_tx_flg;
1083
1084 /* clear mailbox and prep header tlv */
1085 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_UPDATE, sizeof(*req));
1086
1087 /* Prepare extended tlvs */
1088 if (update_rx || update_tx) {
1089 struct vfpf_vport_update_activate_tlv *p_act_tlv;
1090
1091 size = sizeof(struct vfpf_vport_update_activate_tlv);
1092 p_act_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1093 CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
1094 size);
1095 resp_size += sizeof(struct pfvf_def_resp_tlv);
1096
1097 if (update_rx) {
1098 p_act_tlv->update_rx = update_rx;
1099 p_act_tlv->active_rx = p_params->vport_active_rx_flg;
1100 }
1101
1102 if (update_tx) {
1103 p_act_tlv->update_tx = update_tx;
1104 p_act_tlv->active_tx = p_params->vport_active_tx_flg;
1105 }
1106 }
1107
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001108 if (p_params->update_tx_switching_flg) {
1109 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
1110
1111 size = sizeof(struct vfpf_vport_update_tx_switch_tlv);
1112 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
1113 p_tx_switch_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1114 tlv, size);
1115 resp_size += sizeof(struct pfvf_def_resp_tlv);
1116
1117 p_tx_switch_tlv->tx_switching = p_params->tx_switching_flg;
1118 }
1119
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001120 if (p_params->update_approx_mcast_flg) {
1121 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
1122
1123 size = sizeof(struct vfpf_vport_update_mcast_bin_tlv);
1124 p_mcast_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
1125 CHANNEL_TLV_VPORT_UPDATE_MCAST, size);
1126 resp_size += sizeof(struct pfvf_def_resp_tlv);
1127
1128 memcpy(p_mcast_tlv->bins, p_params->bins,
1129 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
1130 }
1131
1132 update_rx = p_params->accept_flags.update_rx_mode_config;
1133 update_tx = p_params->accept_flags.update_tx_mode_config;
1134
1135 if (update_rx || update_tx) {
1136 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
1137
1138 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1139 size = sizeof(struct vfpf_vport_update_accept_param_tlv);
1140 p_accept_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
1141 resp_size += sizeof(struct pfvf_def_resp_tlv);
1142
1143 if (update_rx) {
1144 p_accept_tlv->update_rx_mode = update_rx;
1145 p_accept_tlv->rx_accept_filter =
1146 p_params->accept_flags.rx_accept_filter;
1147 }
1148
1149 if (update_tx) {
1150 p_accept_tlv->update_tx_mode = update_tx;
1151 p_accept_tlv->tx_accept_filter =
1152 p_params->accept_flags.tx_accept_filter;
1153 }
1154 }
1155
1156 if (p_params->rss_params) {
1157 struct qed_rss_params *rss_params = p_params->rss_params;
1158 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02001159 int i, table_size;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001160
1161 size = sizeof(struct vfpf_vport_update_rss_tlv);
1162 p_rss_tlv = qed_add_tlv(p_hwfn,
1163 &p_iov->offset,
1164 CHANNEL_TLV_VPORT_UPDATE_RSS, size);
1165 resp_size += sizeof(struct pfvf_def_resp_tlv);
1166
1167 if (rss_params->update_rss_config)
1168 p_rss_tlv->update_rss_flags |=
1169 VFPF_UPDATE_RSS_CONFIG_FLAG;
1170 if (rss_params->update_rss_capabilities)
1171 p_rss_tlv->update_rss_flags |=
1172 VFPF_UPDATE_RSS_CAPS_FLAG;
1173 if (rss_params->update_rss_ind_table)
1174 p_rss_tlv->update_rss_flags |=
1175 VFPF_UPDATE_RSS_IND_TABLE_FLAG;
1176 if (rss_params->update_rss_key)
1177 p_rss_tlv->update_rss_flags |= VFPF_UPDATE_RSS_KEY_FLAG;
1178
1179 p_rss_tlv->rss_enable = rss_params->rss_enable;
1180 p_rss_tlv->rss_caps = rss_params->rss_caps;
1181 p_rss_tlv->rss_table_size_log = rss_params->rss_table_size_log;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02001182
1183 table_size = min_t(int, T_ETH_INDIRECTION_TABLE_SIZE,
1184 1 << p_rss_tlv->rss_table_size_log);
1185 for (i = 0; i < table_size; i++) {
1186 struct qed_queue_cid *p_queue;
1187
1188 p_queue = rss_params->rss_ind_table[i];
1189 p_rss_tlv->rss_ind_table[i] = p_queue->rel.queue_id;
1190 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001191 memcpy(p_rss_tlv->rss_key, rss_params->rss_key,
1192 sizeof(rss_params->rss_key));
1193 }
1194
Yuval Mintz08feecd2016-05-11 16:36:20 +03001195 if (p_params->update_accept_any_vlan_flg) {
1196 struct vfpf_vport_update_accept_any_vlan_tlv *p_any_vlan_tlv;
1197
1198 size = sizeof(struct vfpf_vport_update_accept_any_vlan_tlv);
1199 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1200 p_any_vlan_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
1201
1202 resp_size += sizeof(struct pfvf_def_resp_tlv);
1203 p_any_vlan_tlv->accept_any_vlan = p_params->accept_any_vlan;
1204 p_any_vlan_tlv->update_accept_any_vlan_flg =
1205 p_params->update_accept_any_vlan_flg;
1206 }
1207
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001208 /* add list termination tlv */
1209 qed_add_tlv(p_hwfn, &p_iov->offset,
1210 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1211
1212 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, resp_size);
1213 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001214 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001215
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001216 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1217 rc = -EINVAL;
1218 goto exit;
1219 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001220
1221 qed_vf_handle_vp_update_tlvs_resp(p_hwfn, p_params);
1222
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001223exit:
1224 qed_vf_pf_req_end(p_hwfn, rc);
1225
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001226 return rc;
1227}
1228
Yuval Mintz0b55e272016-05-11 16:36:15 +03001229int qed_vf_pf_reset(struct qed_hwfn *p_hwfn)
1230{
1231 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1232 struct pfvf_def_resp_tlv *resp;
1233 struct vfpf_first_tlv *req;
1234 int rc;
1235
1236 /* clear mailbox and prep first tlv */
1237 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_CLOSE, sizeof(*req));
1238
1239 /* add list termination tlv */
1240 qed_add_tlv(p_hwfn, &p_iov->offset,
1241 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1242
1243 resp = &p_iov->pf2vf_reply->default_resp;
1244 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1245 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001246 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001247
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001248 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1249 rc = -EAGAIN;
1250 goto exit;
1251 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001252
1253 p_hwfn->b_int_enabled = 0;
1254
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001255exit:
1256 qed_vf_pf_req_end(p_hwfn, rc);
1257
1258 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001259}
1260
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001261void qed_vf_pf_filter_mcast(struct qed_hwfn *p_hwfn,
1262 struct qed_filter_mcast *p_filter_cmd)
1263{
1264 struct qed_sp_vport_update_params sp_params;
1265 int i;
1266
1267 memset(&sp_params, 0, sizeof(sp_params));
1268 sp_params.update_approx_mcast_flg = 1;
1269
1270 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1271 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1272 u32 bit;
1273
1274 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1275 __set_bit(bit, sp_params.bins);
1276 }
1277 }
1278
1279 qed_vf_pf_vport_update(p_hwfn, &sp_params);
1280}
1281
1282int qed_vf_pf_filter_ucast(struct qed_hwfn *p_hwfn,
1283 struct qed_filter_ucast *p_ucast)
1284{
1285 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1286 struct vfpf_ucast_filter_tlv *req;
1287 struct pfvf_def_resp_tlv *resp;
1288 int rc;
1289
1290 /* clear mailbox and prep first tlv */
1291 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
1292 req->opcode = (u8) p_ucast->opcode;
1293 req->type = (u8) p_ucast->type;
1294 memcpy(req->mac, p_ucast->mac, ETH_ALEN);
1295 req->vlan = p_ucast->vlan;
1296
1297 /* add list termination tlv */
1298 qed_add_tlv(p_hwfn, &p_iov->offset,
1299 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1300
1301 resp = &p_iov->pf2vf_reply->default_resp;
1302 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1303 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001304 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001305
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001306 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1307 rc = -EAGAIN;
1308 goto exit;
1309 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001310
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001311exit:
1312 qed_vf_pf_req_end(p_hwfn, rc);
1313
1314 return rc;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001315}
1316
Yuval Mintz0b55e272016-05-11 16:36:15 +03001317int qed_vf_pf_int_cleanup(struct qed_hwfn *p_hwfn)
1318{
1319 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1320 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1321 int rc;
1322
1323 /* clear mailbox and prep first tlv */
1324 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_INT_CLEANUP,
1325 sizeof(struct vfpf_first_tlv));
1326
1327 /* add list termination tlv */
1328 qed_add_tlv(p_hwfn, &p_iov->offset,
1329 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1330
1331 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1332 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001333 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001334
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001335 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1336 rc = -EINVAL;
1337 goto exit;
1338 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001339
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001340exit:
1341 qed_vf_pf_req_end(p_hwfn, rc);
1342
1343 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001344}
1345
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001346u16 qed_vf_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1347{
1348 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1349
1350 if (!p_iov) {
1351 DP_NOTICE(p_hwfn, "vf_sriov_info isn't initialized\n");
1352 return 0;
1353 }
1354
1355 return p_iov->acquire_resp.resc.hw_sbs[sb_id].hw_sb_id;
1356}
1357
Mintz, Yuval50a20712017-06-01 15:29:09 +03001358void qed_vf_set_sb_info(struct qed_hwfn *p_hwfn,
1359 u16 sb_id, struct qed_sb_info *p_sb)
1360{
1361 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1362
1363 if (!p_iov) {
1364 DP_NOTICE(p_hwfn, "vf_sriov_info isn't initialized\n");
1365 return;
1366 }
1367
1368 if (sb_id >= PFVF_MAX_SBS_PER_VF) {
1369 DP_NOTICE(p_hwfn, "Can't configure SB %04x\n", sb_id);
1370 return;
1371 }
1372
1373 p_iov->sbs_info[sb_id] = p_sb;
1374}
1375
Yuval Mintz36558c32016-05-11 16:36:17 +03001376int qed_vf_read_bulletin(struct qed_hwfn *p_hwfn, u8 *p_change)
1377{
1378 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1379 struct qed_bulletin_content shadow;
1380 u32 crc, crc_size;
1381
1382 crc_size = sizeof(p_iov->bulletin.p_virt->crc);
1383 *p_change = 0;
1384
1385 /* Need to guarantee PF is not in the middle of writing it */
1386 memcpy(&shadow, p_iov->bulletin.p_virt, p_iov->bulletin.size);
1387
1388 /* If version did not update, no need to do anything */
1389 if (shadow.version == p_iov->bulletin_shadow.version)
1390 return 0;
1391
1392 /* Verify the bulletin we see is valid */
1393 crc = crc32(0, (u8 *)&shadow + crc_size,
1394 p_iov->bulletin.size - crc_size);
1395 if (crc != shadow.crc)
1396 return -EAGAIN;
1397
1398 /* Set the shadow bulletin and process it */
1399 memcpy(&p_iov->bulletin_shadow, &shadow, p_iov->bulletin.size);
1400
1401 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1402 "Read a bulletin update %08x\n", shadow.version);
1403
1404 *p_change = 1;
1405
1406 return 0;
1407}
1408
1409void __qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1410 struct qed_mcp_link_params *p_params,
1411 struct qed_bulletin_content *p_bulletin)
1412{
1413 memset(p_params, 0, sizeof(*p_params));
1414
1415 p_params->speed.autoneg = p_bulletin->req_autoneg;
1416 p_params->speed.advertised_speeds = p_bulletin->req_adv_speed;
1417 p_params->speed.forced_speed = p_bulletin->req_forced_speed;
1418 p_params->pause.autoneg = p_bulletin->req_autoneg_pause;
1419 p_params->pause.forced_rx = p_bulletin->req_forced_rx;
1420 p_params->pause.forced_tx = p_bulletin->req_forced_tx;
1421 p_params->loopback_mode = p_bulletin->req_loopback;
1422}
1423
1424void qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1425 struct qed_mcp_link_params *params)
1426{
1427 __qed_vf_get_link_params(p_hwfn, params,
1428 &(p_hwfn->vf_iov_info->bulletin_shadow));
1429}
1430
1431void __qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1432 struct qed_mcp_link_state *p_link,
1433 struct qed_bulletin_content *p_bulletin)
1434{
1435 memset(p_link, 0, sizeof(*p_link));
1436
1437 p_link->link_up = p_bulletin->link_up;
1438 p_link->speed = p_bulletin->speed;
1439 p_link->full_duplex = p_bulletin->full_duplex;
1440 p_link->an = p_bulletin->autoneg;
1441 p_link->an_complete = p_bulletin->autoneg_complete;
1442 p_link->parallel_detection = p_bulletin->parallel_detection;
1443 p_link->pfc_enabled = p_bulletin->pfc_enabled;
1444 p_link->partner_adv_speed = p_bulletin->partner_adv_speed;
1445 p_link->partner_tx_flow_ctrl_en = p_bulletin->partner_tx_flow_ctrl_en;
1446 p_link->partner_rx_flow_ctrl_en = p_bulletin->partner_rx_flow_ctrl_en;
1447 p_link->partner_adv_pause = p_bulletin->partner_adv_pause;
1448 p_link->sfp_tx_fault = p_bulletin->sfp_tx_fault;
1449}
1450
1451void qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1452 struct qed_mcp_link_state *link)
1453{
1454 __qed_vf_get_link_state(p_hwfn, link,
1455 &(p_hwfn->vf_iov_info->bulletin_shadow));
1456}
1457
1458void __qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1459 struct qed_mcp_link_capabilities *p_link_caps,
1460 struct qed_bulletin_content *p_bulletin)
1461{
1462 memset(p_link_caps, 0, sizeof(*p_link_caps));
1463 p_link_caps->speed_capabilities = p_bulletin->capability_speed;
1464}
1465
1466void qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1467 struct qed_mcp_link_capabilities *p_link_caps)
1468{
1469 __qed_vf_get_link_caps(p_hwfn, p_link_caps,
1470 &(p_hwfn->vf_iov_info->bulletin_shadow));
1471}
1472
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001473void qed_vf_get_num_rxqs(struct qed_hwfn *p_hwfn, u8 *num_rxqs)
1474{
1475 *num_rxqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_rxqs;
1476}
1477
Mintz, Yuval0db711b2017-06-04 13:31:00 +03001478void qed_vf_get_num_txqs(struct qed_hwfn *p_hwfn, u8 *num_txqs)
1479{
1480 *num_txqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_txqs;
1481}
1482
Mintz, Yuvalcbb8a122017-06-04 13:31:08 +03001483void qed_vf_get_num_cids(struct qed_hwfn *p_hwfn, u8 *num_cids)
1484{
1485 *num_cids = p_hwfn->vf_iov_info->acquire_resp.resc.num_cids;
1486}
1487
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001488void qed_vf_get_port_mac(struct qed_hwfn *p_hwfn, u8 *port_mac)
1489{
1490 memcpy(port_mac,
1491 p_hwfn->vf_iov_info->acquire_resp.pfdev_info.port_mac, ETH_ALEN);
1492}
1493
1494void qed_vf_get_num_vlan_filters(struct qed_hwfn *p_hwfn, u8 *num_vlan_filters)
1495{
1496 struct qed_vf_iov *p_vf;
1497
1498 p_vf = p_hwfn->vf_iov_info;
1499 *num_vlan_filters = p_vf->acquire_resp.resc.num_vlan_filters;
1500}
1501
Mintz, Yuvalb0fca312016-10-31 22:26:54 +02001502void qed_vf_get_num_mac_filters(struct qed_hwfn *p_hwfn, u8 *num_mac_filters)
1503{
1504 struct qed_vf_iov *p_vf = p_hwfn->vf_iov_info;
1505
1506 *num_mac_filters = p_vf->acquire_resp.resc.num_mac_filters;
1507}
1508
Yuval Mintzeff16962016-05-11 16:36:21 +03001509bool qed_vf_check_mac(struct qed_hwfn *p_hwfn, u8 *mac)
1510{
1511 struct qed_bulletin_content *bulletin;
1512
1513 bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1514 if (!(bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)))
1515 return true;
1516
1517 /* Forbid VF from changing a MAC enforced by PF */
1518 if (ether_addr_equal(bulletin->mac, mac))
1519 return false;
1520
1521 return false;
1522}
1523
Baoyou Xieba569472016-09-09 09:21:15 +08001524static bool qed_vf_bulletin_get_forced_mac(struct qed_hwfn *hwfn,
1525 u8 *dst_mac, u8 *p_is_forced)
Yuval Mintzeff16962016-05-11 16:36:21 +03001526{
1527 struct qed_bulletin_content *bulletin;
1528
1529 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1530
1531 if (bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) {
1532 if (p_is_forced)
1533 *p_is_forced = 1;
1534 } else if (bulletin->valid_bitmap & (1 << VFPF_BULLETIN_MAC_ADDR)) {
1535 if (p_is_forced)
1536 *p_is_forced = 0;
1537 } else {
1538 return false;
1539 }
1540
1541 ether_addr_copy(dst_mac, bulletin->mac);
1542
1543 return true;
1544}
1545
Chopra, Manish97379f12017-04-24 10:00:48 -07001546static void
1547qed_vf_bulletin_get_udp_ports(struct qed_hwfn *p_hwfn,
1548 u16 *p_vxlan_port, u16 *p_geneve_port)
1549{
1550 struct qed_bulletin_content *p_bulletin;
1551
1552 p_bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1553
1554 *p_vxlan_port = p_bulletin->vxlan_udp_port;
1555 *p_geneve_port = p_bulletin->geneve_udp_port;
1556}
1557
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001558void qed_vf_get_fw_version(struct qed_hwfn *p_hwfn,
1559 u16 *fw_major, u16 *fw_minor,
1560 u16 *fw_rev, u16 *fw_eng)
1561{
1562 struct pf_vf_pfdev_info *info;
1563
1564 info = &p_hwfn->vf_iov_info->acquire_resp.pfdev_info;
1565
1566 *fw_major = info->fw_major;
1567 *fw_minor = info->fw_minor;
1568 *fw_rev = info->fw_rev;
1569 *fw_eng = info->fw_eng;
1570}
Yuval Mintz36558c32016-05-11 16:36:17 +03001571
1572static void qed_handle_bulletin_change(struct qed_hwfn *hwfn)
1573{
Yuval Mintzeff16962016-05-11 16:36:21 +03001574 struct qed_eth_cb_ops *ops = hwfn->cdev->protocol_ops.eth;
1575 u8 mac[ETH_ALEN], is_mac_exist, is_mac_forced;
1576 void *cookie = hwfn->cdev->ops_cookie;
Chopra, Manish97379f12017-04-24 10:00:48 -07001577 u16 vxlan_port, geneve_port;
Yuval Mintzeff16962016-05-11 16:36:21 +03001578
Chopra, Manish97379f12017-04-24 10:00:48 -07001579 qed_vf_bulletin_get_udp_ports(hwfn, &vxlan_port, &geneve_port);
Yuval Mintzeff16962016-05-11 16:36:21 +03001580 is_mac_exist = qed_vf_bulletin_get_forced_mac(hwfn, mac,
1581 &is_mac_forced);
Yuval Mintzc3aaa402016-10-14 05:19:17 -04001582 if (is_mac_exist && cookie)
1583 ops->force_mac(cookie, mac, !!is_mac_forced);
Yuval Mintzeff16962016-05-11 16:36:21 +03001584
Chopra, Manish97379f12017-04-24 10:00:48 -07001585 ops->ports_update(cookie, vxlan_port, geneve_port);
1586
Yuval Mintz36558c32016-05-11 16:36:17 +03001587 /* Always update link configuration according to bulletin */
1588 qed_link_update(hwfn);
1589}
1590
1591void qed_iov_vf_task(struct work_struct *work)
1592{
1593 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1594 iov_task.work);
1595 u8 change = 0;
1596
1597 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
1598 return;
1599
1600 /* Handle bulletin board changes */
1601 qed_vf_read_bulletin(hwfn, &change);
Mintz, Yuval65ed2ff2017-02-20 22:43:39 +02001602 if (test_and_clear_bit(QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG,
1603 &hwfn->iov_task_flags))
1604 change = 1;
Yuval Mintz36558c32016-05-11 16:36:17 +03001605 if (change)
1606 qed_handle_bulletin_change(hwfn);
1607
1608 /* As VF is polling bulletin board, need to constantly re-schedule */
1609 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, HZ);
1610}