blob: 2bb95494377d67bc9e06e2f4d13736825066035c [file] [log] [blame]
Auke Kok9d5c8242008-01-24 02:22:38 -08001/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
Alexander Duyck86d5d382009-02-06 23:23:12 +00004 Copyright(c) 2007-2009 Intel Corporation.
Auke Kok9d5c8242008-01-24 02:22:38 -08005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
Patrick Ohly38c845c2009-02-12 05:03:41 +000037#include <linux/clocksource.h>
Patrick Ohly33af6bc2009-02-12 05:03:43 +000038#include <linux/timecompare.h>
39#include <linux/net_tstamp.h>
Patrick Ohly38c845c2009-02-12 05:03:41 +000040
Auke Kok9d5c8242008-01-24 02:22:38 -080041struct igb_adapter;
42
Alexander Duyck6eb5a7f2008-07-08 15:14:44 -070043/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44#define IGB_START_ITR 648
Auke Kok9d5c8242008-01-24 02:22:38 -080045
Auke Kok9d5c8242008-01-24 02:22:38 -080046/* TX/RX descriptor defines */
47#define IGB_DEFAULT_TXD 256
48#define IGB_MIN_TXD 80
49#define IGB_MAX_TXD 4096
50
51#define IGB_DEFAULT_RXD 256
52#define IGB_MIN_RXD 80
53#define IGB_MAX_RXD 4096
54
55#define IGB_DEFAULT_ITR 3 /* dynamic */
56#define IGB_MAX_ITR_USECS 10000
57#define IGB_MIN_ITR_USECS 10
Alexander Duyck047e0032009-10-27 15:49:27 +000058#define NON_Q_VECTORS 1
59#define MAX_Q_VECTORS 8
Auke Kok9d5c8242008-01-24 02:22:38 -080060
61/* Transmit and receive queues */
Alexander Duycka99955f2009-11-12 18:37:19 +000062#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
63 (hw->mac.type > e1000_82575 ? 8 : 4))
64#define IGB_ABS_MAX_TX_QUEUES 8
65#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
Auke Kok9d5c8242008-01-24 02:22:38 -080066
Alexander Duyck4ae196d2009-02-19 20:40:07 -080067#define IGB_MAX_VF_MC_ENTRIES 30
68#define IGB_MAX_VF_FUNCTIONS 8
69#define IGB_MAX_VFTA_ENTRIES 128
70
71struct vf_data_storage {
72 unsigned char vf_mac_addresses[ETH_ALEN];
73 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
74 u16 num_vf_mc_hashes;
Alexander Duyckae641bd2009-09-03 14:49:33 +000075 u16 vlans_enabled;
Alexander Duyckf2ca0db2009-10-27 23:46:57 +000076 u32 flags;
77 unsigned long last_nack;
Alexander Duyck4ae196d2009-02-19 20:40:07 -080078};
79
Alexander Duyckf2ca0db2009-10-27 23:46:57 +000080#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
Alexander Duyck7d5753f2009-10-27 23:47:16 +000081#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
82#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
Alexander Duyckf2ca0db2009-10-27 23:46:57 +000083
Auke Kok9d5c8242008-01-24 02:22:38 -080084/* RX descriptor control thresholds.
85 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
86 * descriptors available in its onboard memory.
87 * Setting this to 0 disables RX descriptor prefetch.
88 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
89 * available in host memory.
90 * If PTHRESH is 0, this should also be 0.
91 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
92 * descriptors until either it has this many to write back, or the
93 * ITR timer expires.
94 */
Alexander Duyck85b430b2009-10-27 15:50:29 +000095#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
Auke Kok9d5c8242008-01-24 02:22:38 -080096#define IGB_RX_HTHRESH 8
97#define IGB_RX_WTHRESH 1
Alexander Duyck85b430b2009-10-27 15:50:29 +000098#define IGB_TX_PTHRESH 8
99#define IGB_TX_HTHRESH 1
100#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
101 adapter->msix_entries) ? 0 : 16)
Auke Kok9d5c8242008-01-24 02:22:38 -0800102
103/* this is the size past which hardware will drop packets when setting LPE=0 */
104#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
105
106/* Supported Rx Buffer Sizes */
107#define IGB_RXBUFFER_128 128 /* Used for packet split */
Auke Kok9d5c8242008-01-24 02:22:38 -0800108#define IGB_RXBUFFER_1024 1024
109#define IGB_RXBUFFER_2048 2048
Auke Kok9d5c8242008-01-24 02:22:38 -0800110#define IGB_RXBUFFER_16384 16384
111
Alexander Duycke1739522009-02-19 20:39:44 -0800112#define MAX_STD_JUMBO_FRAME_SIZE 9234
Auke Kok9d5c8242008-01-24 02:22:38 -0800113
114/* How many Tx Descriptors do we need to call netif_wake_queue ? */
115#define IGB_TX_QUEUE_WAKE 16
116/* How many Rx Buffers do we bundle into one write to the hardware ? */
117#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
118
119#define AUTO_ALL_MODES 0
120#define IGB_EEPROM_APME 0x0400
121
122#ifndef IGB_MASTER_SLAVE
123/* Switch to override PHY master/slave setting */
124#define IGB_MASTER_SLAVE e1000_ms_hw_default
125#endif
126
127#define IGB_MNG_VLAN_NONE -1
128
129/* wrapper around a pointer to a socket buffer,
130 * so a DMA handle can be stored along with the buffer */
131struct igb_buffer {
132 struct sk_buff *skb;
133 dma_addr_t dma;
134 union {
135 /* TX */
136 struct {
137 unsigned long time_stamp;
Alexander Duyck0e014cb2008-12-26 01:33:18 -0800138 u16 length;
139 u16 next_to_watch;
Auke Kok9d5c8242008-01-24 02:22:38 -0800140 };
141 /* RX */
142 struct {
143 struct page *page;
144 u64 page_dma;
Alexander Duyckbf36c1a2008-07-08 15:11:40 -0700145 unsigned int page_offset;
Auke Kok9d5c8242008-01-24 02:22:38 -0800146 };
147 };
148};
149
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000150struct igb_tx_queue_stats {
Auke Kok9d5c8242008-01-24 02:22:38 -0800151 u64 packets;
152 u64 bytes;
Alexander Duyck04a5fcaa2009-10-27 15:52:27 +0000153 u64 restart_queue;
Auke Kok9d5c8242008-01-24 02:22:38 -0800154};
155
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000156struct igb_rx_queue_stats {
157 u64 packets;
158 u64 bytes;
159 u64 drops;
Alexander Duyck04a5fcaa2009-10-27 15:52:27 +0000160 u64 csum_err;
161 u64 alloc_failed;
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000162};
163
Alexander Duyck047e0032009-10-27 15:49:27 +0000164struct igb_q_vector {
Auke Kok9d5c8242008-01-24 02:22:38 -0800165 struct igb_adapter *adapter; /* backlink */
Alexander Duyck047e0032009-10-27 15:49:27 +0000166 struct igb_ring *rx_ring;
167 struct igb_ring *tx_ring;
168 struct napi_struct napi;
169
170 u32 eims_value;
171 u16 cpu;
172
173 u16 itr_val;
174 u8 set_itr;
175 u8 itr_shift;
176 void __iomem *itr_register;
177
178 char name[IFNAMSIZ + 9];
179};
180
181struct igb_ring {
182 struct igb_q_vector *q_vector; /* backlink to q_vector */
Alexander Duycke694e962009-10-27 15:53:06 +0000183 struct net_device *netdev; /* back pointer to net_device */
Alexander Duyck80785292009-10-27 15:51:47 +0000184 struct pci_dev *pdev; /* pci device for dma mapping */
Alexander Duyck047e0032009-10-27 15:49:27 +0000185 dma_addr_t dma; /* phys address of the ring */
Alexander Duycke694e962009-10-27 15:53:06 +0000186 void *desc; /* descriptor ring memory */
Alexander Duyck047e0032009-10-27 15:49:27 +0000187 unsigned int size; /* length of desc. ring in bytes */
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000188 u16 count; /* number of desc. in the ring */
Auke Kok9d5c8242008-01-24 02:22:38 -0800189 u16 next_to_use;
190 u16 next_to_clean;
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000191 u8 queue_index;
192 u8 reg_idx;
Alexander Duyckfce99e32009-10-27 15:51:27 +0000193 void __iomem *head;
194 void __iomem *tail;
Auke Kok9d5c8242008-01-24 02:22:38 -0800195 struct igb_buffer *buffer_info; /* array of buffer info structs */
196
Auke Kok9d5c8242008-01-24 02:22:38 -0800197 unsigned int total_bytes;
198 unsigned int total_packets;
199
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000200 u32 flags;
201
Auke Kok9d5c8242008-01-24 02:22:38 -0800202 union {
203 /* TX */
204 struct {
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000205 struct igb_tx_queue_stats tx_stats;
Auke Kok9d5c8242008-01-24 02:22:38 -0800206 bool detect_tx_hung;
207 };
208 /* RX */
209 struct {
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000210 struct igb_rx_queue_stats rx_stats;
Alexander Duyck4c844852009-10-27 15:52:07 +0000211 u32 rx_buffer_len;
Auke Kok9d5c8242008-01-24 02:22:38 -0800212 };
213 };
Auke Kok9d5c8242008-01-24 02:22:38 -0800214};
215
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000216#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
217#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
218
219#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
220
221#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
222
Auke Kok9d5c8242008-01-24 02:22:38 -0800223#define E1000_RX_DESC_ADV(R, i) \
224 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
225#define E1000_TX_DESC_ADV(R, i) \
226 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
227#define E1000_TX_CTXTDESC_ADV(R, i) \
228 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
Auke Kok9d5c8242008-01-24 02:22:38 -0800229
Alexander Duyckd7ee5b32009-10-27 15:54:23 +0000230/* igb_desc_unused - calculate if we have unused descriptors */
231static inline int igb_desc_unused(struct igb_ring *ring)
232{
233 if (ring->next_to_clean > ring->next_to_use)
234 return ring->next_to_clean - ring->next_to_use - 1;
235
236 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
237}
238
Auke Kok9d5c8242008-01-24 02:22:38 -0800239/* board specific private data structure */
240
241struct igb_adapter {
242 struct timer_list watchdog_timer;
243 struct timer_list phy_info_timer;
244 struct vlan_group *vlgrp;
245 u16 mng_vlan_id;
246 u32 bd_number;
Auke Kok9d5c8242008-01-24 02:22:38 -0800247 u32 wol;
248 u32 en_mng_pt;
249 u16 link_speed;
250 u16 link_duplex;
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000251
Auke Kok9d5c8242008-01-24 02:22:38 -0800252 unsigned int total_tx_bytes;
253 unsigned int total_tx_packets;
254 unsigned int total_rx_bytes;
255 unsigned int total_rx_packets;
256 /* Interrupt Throttle Rate */
Alexander Duyck4fc82ad2009-10-27 23:45:42 +0000257 u32 rx_itr_setting;
258 u32 tx_itr_setting;
Auke Kok9d5c8242008-01-24 02:22:38 -0800259 u16 tx_itr;
260 u16 rx_itr;
Auke Kok9d5c8242008-01-24 02:22:38 -0800261
262 struct work_struct reset_task;
263 struct work_struct watchdog_task;
264 bool fc_autoneg;
265 u8 tx_timeout_factor;
266 struct timer_list blink_timer;
267 unsigned long led_status;
268
269 /* TX */
270 struct igb_ring *tx_ring; /* One per active queue */
Auke Kok9d5c8242008-01-24 02:22:38 -0800271 unsigned long tx_queue_len;
Auke Kok9d5c8242008-01-24 02:22:38 -0800272 u32 tx_timeout_count;
273
274 /* RX */
275 struct igb_ring *rx_ring; /* One per active queue */
276 int num_tx_queues;
277 int num_rx_queues;
278
Auke Kok9d5c8242008-01-24 02:22:38 -0800279 u32 max_frame_size;
280 u32 min_frame_size;
281
282 /* OS defined structs */
283 struct net_device *netdev;
Auke Kok9d5c8242008-01-24 02:22:38 -0800284 struct pci_dev *pdev;
Patrick Ohly38c845c2009-02-12 05:03:41 +0000285 struct cyclecounter cycles;
286 struct timecounter clock;
Patrick Ohly33af6bc2009-02-12 05:03:43 +0000287 struct timecompare compare;
288 struct hwtstamp_config hwtstamp_config;
Auke Kok9d5c8242008-01-24 02:22:38 -0800289
290 /* structs defined in e1000_hw.h */
291 struct e1000_hw hw;
292 struct e1000_hw_stats stats;
293 struct e1000_phy_info phy_info;
294 struct e1000_phy_stats phy_stats;
295
296 u32 test_icr;
297 struct igb_ring test_tx_ring;
298 struct igb_ring test_rx_ring;
299
300 int msg_enable;
Alexander Duyck047e0032009-10-27 15:49:27 +0000301
302 unsigned int num_q_vectors;
303 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
Auke Kok9d5c8242008-01-24 02:22:38 -0800304 struct msix_entry *msix_entries;
305 u32 eims_enable_mask;
PJ Waskiewicz844290e2008-06-27 11:00:39 -0700306 u32 eims_other;
Auke Kok9d5c8242008-01-24 02:22:38 -0800307
308 /* to not mess up cache alignment, always add to the bottom */
309 unsigned long state;
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700310 unsigned int flags;
Auke Kok9d5c8242008-01-24 02:22:38 -0800311 u32 eeprom_wol;
Taku Izumi42bfd33a2008-06-20 12:10:30 +0900312
Alexander Duyck1bfaf072009-02-19 20:39:23 -0800313 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000314 u16 tx_ring_count;
315 u16 rx_ring_count;
Alexander Duyck1bfaf072009-02-19 20:39:23 -0800316 unsigned int vfs_allocated_count;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800317 struct vf_data_storage *vf_data;
Alexander Duycka99955f2009-11-12 18:37:19 +0000318 u32 rss_queues;
Auke Kok9d5c8242008-01-24 02:22:38 -0800319};
320
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700321#define IGB_FLAG_HAS_MSI (1 << 0)
Alexander Duyckcbd347a2009-02-15 23:59:44 -0800322#define IGB_FLAG_DCA_ENABLED (1 << 1)
323#define IGB_FLAG_QUAD_PORT_A (1 << 2)
Alexander Duyck4fc82ad2009-10-27 23:45:42 +0000324#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700325
Alexander Duyckc5b9bd52009-10-27 23:46:01 +0000326#define IGB_82576_TSYNC_SHIFT 19
Auke Kok9d5c8242008-01-24 02:22:38 -0800327enum e1000_state_t {
328 __IGB_TESTING,
329 __IGB_RESETTING,
330 __IGB_DOWN
331};
332
333enum igb_boards {
334 board_82575,
335};
336
337extern char igb_driver_name[];
338extern char igb_driver_version[];
339
340extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
341extern int igb_up(struct igb_adapter *);
342extern void igb_down(struct igb_adapter *);
343extern void igb_reinit_locked(struct igb_adapter *);
344extern void igb_reset(struct igb_adapter *);
345extern int igb_set_spd_dplx(struct igb_adapter *, u16);
Alexander Duyck80785292009-10-27 15:51:47 +0000346extern int igb_setup_tx_resources(struct igb_ring *);
347extern int igb_setup_rx_resources(struct igb_ring *);
Alexander Duyck68fd9912008-11-20 00:48:10 -0800348extern void igb_free_tx_resources(struct igb_ring *);
349extern void igb_free_rx_resources(struct igb_ring *);
Alexander Duyckd7ee5b32009-10-27 15:54:23 +0000350extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
351extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
352extern void igb_setup_tctl(struct igb_adapter *);
353extern void igb_setup_rctl(struct igb_adapter *);
Alexander Duyckb1a436c2009-10-27 15:54:43 +0000354extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
355extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
356 struct igb_buffer *);
Alexander Duyckd7ee5b32009-10-27 15:54:23 +0000357extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
Auke Kok9d5c8242008-01-24 02:22:38 -0800358extern void igb_update_stats(struct igb_adapter *);
359extern void igb_set_ethtool_ops(struct net_device *);
360
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800361static inline s32 igb_reset_phy(struct e1000_hw *hw)
362{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000363 if (hw->phy.ops.reset)
364 return hw->phy.ops.reset(hw);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800365
366 return 0;
367}
368
369static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
370{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000371 if (hw->phy.ops.read_reg)
372 return hw->phy.ops.read_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800373
374 return 0;
375}
376
377static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
378{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000379 if (hw->phy.ops.write_reg)
380 return hw->phy.ops.write_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800381
382 return 0;
383}
384
385static inline s32 igb_get_phy_info(struct e1000_hw *hw)
386{
387 if (hw->phy.ops.get_phy_info)
388 return hw->phy.ops.get_phy_info(hw);
389
390 return 0;
391}
392
Auke Kok9d5c8242008-01-24 02:22:38 -0800393#endif /* _IGB_H_ */