blob: 308c56a021abb5f4a3634e665e2161444016951c [file] [log] [blame]
Chris Wilson688e6c72016-07-01 17:23:15 +01001/*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
Chris Wilsonc81d4612016-07-01 17:23:25 +010025#include <linux/kthread.h>
Ingo Molnarae7e81c2017-02-01 18:07:51 +010026#include <uapi/linux/sched/types.h>
Chris Wilsonc81d4612016-07-01 17:23:25 +010027
Chris Wilson688e6c72016-07-01 17:23:15 +010028#include "i915_drv.h"
29
Chris Wilson67b807a82017-02-27 20:58:50 +000030static unsigned int __intel_breadcrumbs_wakeup(struct intel_breadcrumbs *b)
Chris Wilson8d769ea2017-02-27 20:58:47 +000031{
Chris Wilson56299fb2017-02-27 20:58:48 +000032 struct intel_wait *wait;
Chris Wilson8d769ea2017-02-27 20:58:47 +000033 unsigned int result = 0;
34
Chris Wilson61d3dc72017-03-03 19:08:24 +000035 lockdep_assert_held(&b->irq_lock);
36
37 wait = b->irq_wait;
Chris Wilson56299fb2017-02-27 20:58:48 +000038 if (wait) {
Chris Wilson8d769ea2017-02-27 20:58:47 +000039 result = ENGINE_WAKEUP_WAITER;
Chris Wilson67b807a82017-02-27 20:58:50 +000040 if (wake_up_process(wait->tsk))
41 result |= ENGINE_WAKEUP_ASLEEP;
Chris Wilson8d769ea2017-02-27 20:58:47 +000042 }
Chris Wilson67b807a82017-02-27 20:58:50 +000043
44 return result;
45}
46
47unsigned int intel_engine_wakeup(struct intel_engine_cs *engine)
48{
49 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilson467221b2017-03-20 14:31:33 +000050 unsigned long flags;
Chris Wilson67b807a82017-02-27 20:58:50 +000051 unsigned int result;
52
Chris Wilson467221b2017-03-20 14:31:33 +000053 spin_lock_irqsave(&b->irq_lock, flags);
Chris Wilson67b807a82017-02-27 20:58:50 +000054 result = __intel_breadcrumbs_wakeup(b);
Chris Wilson467221b2017-03-20 14:31:33 +000055 spin_unlock_irqrestore(&b->irq_lock, flags);
Chris Wilson8d769ea2017-02-27 20:58:47 +000056
57 return result;
58}
59
Chris Wilson2246bea2017-02-17 15:13:00 +000060static unsigned long wait_timeout(void)
61{
62 return round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES);
63}
64
Chris Wilson80166e402017-02-28 08:50:18 +000065static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
66{
67 DRM_DEBUG_DRIVER("%s missed breadcrumb at %pF, irq posted? %s\n",
68 engine->name, __builtin_return_address(0),
69 yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
70 &engine->irq_posted)));
71
72 set_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
73}
74
Chris Wilson83348ba2016-08-09 17:47:51 +010075static void intel_breadcrumbs_hangcheck(unsigned long data)
76{
77 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
78 struct intel_breadcrumbs *b = &engine->breadcrumbs;
79
Chris Wilson67b807a82017-02-27 20:58:50 +000080 if (!b->irq_armed)
Chris Wilson83348ba2016-08-09 17:47:51 +010081 return;
82
Chris Wilson2246bea2017-02-17 15:13:00 +000083 if (b->hangcheck_interrupts != atomic_read(&engine->irq_count)) {
84 b->hangcheck_interrupts = atomic_read(&engine->irq_count);
85 mod_timer(&b->hangcheck, wait_timeout());
Chris Wilson83348ba2016-08-09 17:47:51 +010086 return;
87 }
88
Chris Wilsona6b0a1412017-03-15 22:22:59 +000089 /* We keep the hangcheck timer alive until we disarm the irq, even
Chris Wilson67b807a82017-02-27 20:58:50 +000090 * if there are no waiters at present.
91 *
92 * If the waiter was currently running, assume it hasn't had a chance
Chris Wilson89985672017-02-17 15:13:02 +000093 * to process the pending interrupt (e.g, low priority task on a loaded
94 * system) and wait until it sleeps before declaring a missed interrupt.
Chris Wilson67b807a82017-02-27 20:58:50 +000095 *
96 * If the waiter was asleep (and not even pending a wakeup), then we
97 * must have missed an interrupt as the GPU has stopped advancing
98 * but we still have a waiter. Assuming all batches complete within
99 * DRM_I915_HANGCHECK_JIFFIES [1.5s]!
Chris Wilson89985672017-02-17 15:13:02 +0000100 */
Chris Wilson67b807a82017-02-27 20:58:50 +0000101 if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP) {
Chris Wilson80166e402017-02-28 08:50:18 +0000102 missed_breadcrumb(engine);
Chris Wilson67b807a82017-02-27 20:58:50 +0000103 mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1);
104 } else {
Chris Wilson89985672017-02-17 15:13:02 +0000105 mod_timer(&b->hangcheck, wait_timeout());
Chris Wilson89985672017-02-17 15:13:02 +0000106 }
Chris Wilson83348ba2016-08-09 17:47:51 +0100107}
108
Chris Wilson688e6c72016-07-01 17:23:15 +0100109static void intel_breadcrumbs_fake_irq(unsigned long data)
110{
111 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
Chris Wilson67b807a82017-02-27 20:58:50 +0000112 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilson688e6c72016-07-01 17:23:15 +0100113
Chris Wilsona6b0a1412017-03-15 22:22:59 +0000114 /* The timer persists in case we cannot enable interrupts,
Chris Wilson688e6c72016-07-01 17:23:15 +0100115 * or if we have previously seen seqno/interrupt incoherency
Chris Wilsona6b0a1412017-03-15 22:22:59 +0000116 * ("missed interrupt" syndrome, better known as a "missed breadcrumb").
117 * Here the worker will wake up every jiffie in order to kick the
118 * oldest waiter to do the coherent seqno check.
Chris Wilson688e6c72016-07-01 17:23:15 +0100119 */
Chris Wilson67b807a82017-02-27 20:58:50 +0000120
Tvrtko Ursulina9e64932017-03-06 15:03:20 +0000121 spin_lock_irq(&b->irq_lock);
Chris Wilson67b807a82017-02-27 20:58:50 +0000122 if (!__intel_breadcrumbs_wakeup(b))
123 __intel_engine_disarm_breadcrumbs(engine);
Tvrtko Ursulina9e64932017-03-06 15:03:20 +0000124 spin_unlock_irq(&b->irq_lock);
Chris Wilson67b807a82017-02-27 20:58:50 +0000125 if (!b->irq_armed)
Chris Wilson19d0a572017-02-27 20:58:49 +0000126 return;
127
Chris Wilson67b807a82017-02-27 20:58:50 +0000128 mod_timer(&b->fake_irq, jiffies + 1);
Chris Wilson19d0a572017-02-27 20:58:49 +0000129
130 /* Ensure that even if the GPU hangs, we get woken up.
131 *
132 * However, note that if no one is waiting, we never notice
133 * a gpu hang. Eventually, we will have to wait for a resource
134 * held by the GPU and so trigger a hangcheck. In the most
135 * pathological case, this will be upon memory starvation! To
136 * prevent this, we also queue the hangcheck from the retire
137 * worker.
138 */
139 i915_queue_hangcheck(engine->i915);
Chris Wilson688e6c72016-07-01 17:23:15 +0100140}
141
142static void irq_enable(struct intel_engine_cs *engine)
143{
Chris Wilson3d5564e2016-07-01 17:23:23 +0100144 /* Enabling the IRQ may miss the generation of the interrupt, but
145 * we still need to force the barrier before reading the seqno,
146 * just in case.
147 */
Chris Wilson538b2572017-01-24 15:18:05 +0000148 set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
Chris Wilson31bb59c2016-07-01 17:23:27 +0100149
Chris Wilsonf6168e32016-10-28 13:58:55 +0100150 /* Caller disables interrupts */
151 spin_lock(&engine->i915->irq_lock);
Chris Wilson31bb59c2016-07-01 17:23:27 +0100152 engine->irq_enable(engine);
Chris Wilsonf6168e32016-10-28 13:58:55 +0100153 spin_unlock(&engine->i915->irq_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100154}
155
156static void irq_disable(struct intel_engine_cs *engine)
157{
Chris Wilsonf6168e32016-10-28 13:58:55 +0100158 /* Caller disables interrupts */
159 spin_lock(&engine->i915->irq_lock);
Chris Wilson31bb59c2016-07-01 17:23:27 +0100160 engine->irq_disable(engine);
Chris Wilsonf6168e32016-10-28 13:58:55 +0100161 spin_unlock(&engine->i915->irq_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100162}
163
Chris Wilson67b807a82017-02-27 20:58:50 +0000164void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
165{
166 struct intel_breadcrumbs *b = &engine->breadcrumbs;
167
Chris Wilson61d3dc72017-03-03 19:08:24 +0000168 lockdep_assert_held(&b->irq_lock);
Chris Wilsone1c0c912017-03-06 09:29:15 +0000169 GEM_BUG_ON(b->irq_wait);
Chris Wilson67b807a82017-02-27 20:58:50 +0000170
171 if (b->irq_enabled) {
172 irq_disable(engine);
173 b->irq_enabled = false;
174 }
175
176 b->irq_armed = false;
177}
178
179void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
180{
181 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilsona5cae7b2017-03-15 21:07:24 +0000182 struct intel_wait *wait, *n, *first;
Chris Wilson67b807a82017-02-27 20:58:50 +0000183
184 if (!b->irq_armed)
185 return;
186
Chris Wilson67b807a82017-02-27 20:58:50 +0000187 /* We only disarm the irq when we are idle (all requests completed),
Chris Wilsone1c0c912017-03-06 09:29:15 +0000188 * so if the bottom-half remains asleep, it missed the request
Chris Wilson67b807a82017-02-27 20:58:50 +0000189 * completion.
190 */
Chris Wilson67b807a82017-02-27 20:58:50 +0000191
Chris Wilsone1c0c912017-03-06 09:29:15 +0000192 spin_lock_irq(&b->rb_lock);
Chris Wilsona5cae7b2017-03-15 21:07:24 +0000193
194 spin_lock(&b->irq_lock);
195 first = fetch_and_zero(&b->irq_wait);
196 __intel_engine_disarm_breadcrumbs(engine);
197 spin_unlock(&b->irq_lock);
198
Chris Wilsone1c0c912017-03-06 09:29:15 +0000199 rbtree_postorder_for_each_entry_safe(wait, n, &b->waiters, node) {
200 RB_CLEAR_NODE(&wait->node);
Chris Wilsona5cae7b2017-03-15 21:07:24 +0000201 if (wake_up_process(wait->tsk) && wait == first)
Chris Wilsone1c0c912017-03-06 09:29:15 +0000202 missed_breadcrumb(engine);
203 }
204 b->waiters = RB_ROOT;
205
Chris Wilsone1c0c912017-03-06 09:29:15 +0000206 spin_unlock_irq(&b->rb_lock);
Chris Wilson67b807a82017-02-27 20:58:50 +0000207}
208
Chris Wilson6ef98ea2017-02-17 15:13:03 +0000209static bool use_fake_irq(const struct intel_breadcrumbs *b)
210{
211 const struct intel_engine_cs *engine =
212 container_of(b, struct intel_engine_cs, breadcrumbs);
213
214 if (!test_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings))
215 return false;
216
217 /* Only start with the heavy weight fake irq timer if we have not
218 * seen any interrupts since enabling it the first time. If the
219 * interrupts are still arriving, it means we made a mistake in our
220 * engine->seqno_barrier(), a timing error that should be transient
221 * and unlikely to reoccur.
222 */
223 return atomic_read(&engine->irq_count) == b->hangcheck_interrupts;
224}
225
Chris Wilson67b807a82017-02-27 20:58:50 +0000226static void enable_fake_irq(struct intel_breadcrumbs *b)
227{
228 /* Ensure we never sleep indefinitely */
229 if (!b->irq_enabled || use_fake_irq(b))
230 mod_timer(&b->fake_irq, jiffies + 1);
231 else
232 mod_timer(&b->hangcheck, wait_timeout());
233}
234
Chris Wilson04171312016-07-06 12:39:00 +0100235static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
Chris Wilson688e6c72016-07-01 17:23:15 +0100236{
237 struct intel_engine_cs *engine =
238 container_of(b, struct intel_engine_cs, breadcrumbs);
239 struct drm_i915_private *i915 = engine->i915;
Chris Wilson688e6c72016-07-01 17:23:15 +0100240
Chris Wilson61d3dc72017-03-03 19:08:24 +0000241 lockdep_assert_held(&b->irq_lock);
Chris Wilson67b807a82017-02-27 20:58:50 +0000242 if (b->irq_armed)
Chris Wilson04171312016-07-06 12:39:00 +0100243 return;
Chris Wilson688e6c72016-07-01 17:23:15 +0100244
Chris Wilson67b807a82017-02-27 20:58:50 +0000245 /* The breadcrumb irq will be disarmed on the interrupt after the
246 * waiters are signaled. This gives us a single interrupt window in
247 * which we can add a new waiter and avoid the cost of re-enabling
248 * the irq.
249 */
250 b->irq_armed = true;
251 GEM_BUG_ON(b->irq_enabled);
252
Chris Wilsonf97fbf92017-02-13 17:15:14 +0000253 if (I915_SELFTEST_ONLY(b->mock)) {
254 /* For our mock objects we want to avoid interaction
255 * with the real hardware (which is not set up). So
256 * we simply pretend we have enabled the powerwell
257 * and the irq, and leave it up to the mock
258 * implementation to call intel_engine_wakeup()
259 * itself when it wants to simulate a user interrupt,
260 */
Chris Wilsonf97fbf92017-02-13 17:15:14 +0000261 return;
262 }
263
Chris Wilson688e6c72016-07-01 17:23:15 +0100264 /* Since we are waiting on a request, the GPU should be busy
Chris Wilson67b807a82017-02-27 20:58:50 +0000265 * and should have its own rpm reference. This is tracked
266 * by i915->gt.awake, we can forgo holding our own wakref
267 * for the interrupt as before i915->gt.awake is released (when
268 * the driver is idle) we disarm the breadcrumbs.
Chris Wilson688e6c72016-07-01 17:23:15 +0100269 */
Chris Wilson688e6c72016-07-01 17:23:15 +0100270
271 /* No interrupts? Kick the waiter every jiffie! */
272 if (intel_irqs_enabled(i915)) {
Chris Wilson3d5564e2016-07-01 17:23:23 +0100273 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
Chris Wilson688e6c72016-07-01 17:23:15 +0100274 irq_enable(engine);
Chris Wilson688e6c72016-07-01 17:23:15 +0100275 b->irq_enabled = true;
276 }
277
Chris Wilson67b807a82017-02-27 20:58:50 +0000278 enable_fake_irq(b);
Chris Wilson688e6c72016-07-01 17:23:15 +0100279}
280
281static inline struct intel_wait *to_wait(struct rb_node *node)
282{
Chris Wilsond8567862016-12-20 10:40:03 +0000283 return rb_entry(node, struct intel_wait, node);
Chris Wilson688e6c72016-07-01 17:23:15 +0100284}
285
286static inline void __intel_breadcrumbs_finish(struct intel_breadcrumbs *b,
287 struct intel_wait *wait)
288{
Chris Wilson61d3dc72017-03-03 19:08:24 +0000289 lockdep_assert_held(&b->rb_lock);
Chris Wilson908a6cb2017-03-15 21:07:25 +0000290 GEM_BUG_ON(b->irq_wait == wait);
Chris Wilson688e6c72016-07-01 17:23:15 +0100291
292 /* This request is completed, so remove it from the tree, mark it as
Chris Wilsona6b0a1412017-03-15 22:22:59 +0000293 * complete, and *then* wake up the associated task. N.B. when the
294 * task wakes up, it will find the empty rb_node, discern that it
295 * has already been removed from the tree and skip the serialisation
296 * of the b->rb_lock and b->irq_lock. This means that the destruction
297 * of the intel_wait is not serialised with the interrupt handler
298 * by the waiter - it must instead be serialised by the caller.
Chris Wilson688e6c72016-07-01 17:23:15 +0100299 */
300 rb_erase(&wait->node, &b->waiters);
301 RB_CLEAR_NODE(&wait->node);
302
303 wake_up_process(wait->tsk); /* implicit smp_wmb() */
304}
305
Chris Wilsonb66255f2017-03-03 17:14:22 +0000306static inline void __intel_breadcrumbs_next(struct intel_engine_cs *engine,
307 struct rb_node *next)
308{
309 struct intel_breadcrumbs *b = &engine->breadcrumbs;
310
Chris Wilson61d3dc72017-03-03 19:08:24 +0000311 spin_lock(&b->irq_lock);
Chris Wilsonb66255f2017-03-03 17:14:22 +0000312 GEM_BUG_ON(!b->irq_armed);
Chris Wilson429732e2017-03-15 21:07:23 +0000313 GEM_BUG_ON(!b->irq_wait);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000314 b->irq_wait = to_wait(next);
315 spin_unlock(&b->irq_lock);
Chris Wilsonb66255f2017-03-03 17:14:22 +0000316
317 /* We always wake up the next waiter that takes over as the bottom-half
318 * as we may delegate not only the irq-seqno barrier to the next waiter
319 * but also the task of waking up concurrent waiters.
320 */
321 if (next)
322 wake_up_process(to_wait(next)->tsk);
323}
324
Chris Wilson688e6c72016-07-01 17:23:15 +0100325static bool __intel_engine_add_wait(struct intel_engine_cs *engine,
326 struct intel_wait *wait)
327{
328 struct intel_breadcrumbs *b = &engine->breadcrumbs;
329 struct rb_node **p, *parent, *completed;
330 bool first;
331 u32 seqno;
332
333 /* Insert the request into the retirement ordered list
334 * of waiters by walking the rbtree. If we are the oldest
335 * seqno in the tree (the first to be retired), then
336 * set ourselves as the bottom-half.
337 *
338 * As we descend the tree, prune completed branches since we hold the
339 * spinlock we know that the first_waiter must be delayed and can
340 * reduce some of the sequential wake up latency if we take action
341 * ourselves and wake up the completed tasks in parallel. Also, by
342 * removing stale elements in the tree, we may be able to reduce the
343 * ping-pong between the old bottom-half and ourselves as first-waiter.
344 */
345 first = true;
346 parent = NULL;
347 completed = NULL;
Chris Wilson1b7744e2016-07-01 17:23:17 +0100348 seqno = intel_engine_get_seqno(engine);
Chris Wilson688e6c72016-07-01 17:23:15 +0100349
350 /* If the request completed before we managed to grab the spinlock,
351 * return now before adding ourselves to the rbtree. We let the
352 * current bottom-half handle any pending wakeups and instead
353 * try and get out of the way quickly.
354 */
355 if (i915_seqno_passed(seqno, wait->seqno)) {
356 RB_CLEAR_NODE(&wait->node);
357 return first;
358 }
359
360 p = &b->waiters.rb_node;
361 while (*p) {
362 parent = *p;
363 if (wait->seqno == to_wait(parent)->seqno) {
364 /* We have multiple waiters on the same seqno, select
365 * the highest priority task (that with the smallest
366 * task->prio) to serve as the bottom-half for this
367 * group.
368 */
369 if (wait->tsk->prio > to_wait(parent)->tsk->prio) {
370 p = &parent->rb_right;
371 first = false;
372 } else {
373 p = &parent->rb_left;
374 }
375 } else if (i915_seqno_passed(wait->seqno,
376 to_wait(parent)->seqno)) {
377 p = &parent->rb_right;
378 if (i915_seqno_passed(seqno, to_wait(parent)->seqno))
379 completed = parent;
380 else
381 first = false;
382 } else {
383 p = &parent->rb_left;
384 }
385 }
386 rb_link_node(&wait->node, parent, p);
387 rb_insert_color(&wait->node, &b->waiters);
Chris Wilson688e6c72016-07-01 17:23:15 +0100388
Chris Wilson688e6c72016-07-01 17:23:15 +0100389 if (first) {
Chris Wilson61d3dc72017-03-03 19:08:24 +0000390 spin_lock(&b->irq_lock);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000391 b->irq_wait = wait;
Chris Wilson04171312016-07-06 12:39:00 +0100392 /* After assigning ourselves as the new bottom-half, we must
393 * perform a cursory check to prevent a missed interrupt.
394 * Either we miss the interrupt whilst programming the hardware,
395 * or if there was a previous waiter (for a later seqno) they
396 * may be woken instead of us (due to the inherent race
Chris Wilsonaca34b62016-07-06 12:39:02 +0100397 * in the unlocked read of b->irq_seqno_bh in the irq handler)
398 * and so we miss the wake up.
Chris Wilson04171312016-07-06 12:39:00 +0100399 */
400 __intel_breadcrumbs_enable_irq(b);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000401 spin_unlock(&b->irq_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100402 }
Chris Wilson429732e2017-03-15 21:07:23 +0000403
404 if (completed) {
Chris Wilsona6b0a1412017-03-15 22:22:59 +0000405 /* Advance the bottom-half (b->irq_wait) before we wake up
406 * the waiters who may scribble over their intel_wait
407 * just as the interrupt handler is dereferencing it via
408 * b->irq_wait.
409 */
Chris Wilson429732e2017-03-15 21:07:23 +0000410 if (!first) {
411 struct rb_node *next = rb_next(completed);
412 GEM_BUG_ON(next == &wait->node);
413 __intel_breadcrumbs_next(engine, next);
414 }
415
416 do {
417 struct intel_wait *crumb = to_wait(completed);
418 completed = rb_prev(completed);
419 __intel_breadcrumbs_finish(b, crumb);
420 } while (completed);
421 }
422
Chris Wilson61d3dc72017-03-03 19:08:24 +0000423 GEM_BUG_ON(!b->irq_wait);
Chris Wilson429732e2017-03-15 21:07:23 +0000424 GEM_BUG_ON(!b->irq_armed);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000425 GEM_BUG_ON(rb_first(&b->waiters) != &b->irq_wait->node);
Chris Wilson688e6c72016-07-01 17:23:15 +0100426
427 return first;
428}
429
430bool intel_engine_add_wait(struct intel_engine_cs *engine,
431 struct intel_wait *wait)
432{
433 struct intel_breadcrumbs *b = &engine->breadcrumbs;
434 bool first;
435
Chris Wilson61d3dc72017-03-03 19:08:24 +0000436 spin_lock_irq(&b->rb_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100437 first = __intel_engine_add_wait(engine, wait);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000438 spin_unlock_irq(&b->rb_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100439
440 return first;
441}
442
Chris Wilson688e6c72016-07-01 17:23:15 +0100443static inline bool chain_wakeup(struct rb_node *rb, int priority)
444{
445 return rb && to_wait(rb)->tsk->prio <= priority;
446}
447
Chris Wilsonc81d4612016-07-01 17:23:25 +0100448static inline int wakeup_priority(struct intel_breadcrumbs *b,
449 struct task_struct *tsk)
450{
451 if (tsk == b->signaler)
452 return INT_MIN;
453 else
454 return tsk->prio;
455}
456
Chris Wilson9eb143b2017-02-23 07:44:16 +0000457static void __intel_engine_remove_wait(struct intel_engine_cs *engine,
458 struct intel_wait *wait)
Chris Wilson688e6c72016-07-01 17:23:15 +0100459{
460 struct intel_breadcrumbs *b = &engine->breadcrumbs;
461
Chris Wilson61d3dc72017-03-03 19:08:24 +0000462 lockdep_assert_held(&b->rb_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100463
464 if (RB_EMPTY_NODE(&wait->node))
Chris Wilson9eb143b2017-02-23 07:44:16 +0000465 goto out;
Chris Wilson688e6c72016-07-01 17:23:15 +0100466
Chris Wilson61d3dc72017-03-03 19:08:24 +0000467 if (b->irq_wait == wait) {
Chris Wilsonc81d4612016-07-01 17:23:25 +0100468 const int priority = wakeup_priority(b, wait->tsk);
Chris Wilson688e6c72016-07-01 17:23:15 +0100469 struct rb_node *next;
Chris Wilson688e6c72016-07-01 17:23:15 +0100470
Chris Wilson688e6c72016-07-01 17:23:15 +0100471 /* We are the current bottom-half. Find the next candidate,
472 * the first waiter in the queue on the remaining oldest
473 * request. As multiple seqnos may complete in the time it
474 * takes us to wake up and find the next waiter, we have to
475 * wake up that waiter for it to perform its own coherent
476 * completion check.
477 */
478 next = rb_next(&wait->node);
479 if (chain_wakeup(next, priority)) {
480 /* If the next waiter is already complete,
481 * wake it up and continue onto the next waiter. So
482 * if have a small herd, they will wake up in parallel
483 * rather than sequentially, which should reduce
484 * the overall latency in waking all the completed
485 * clients.
486 *
487 * However, waking up a chain adds extra latency to
488 * the first_waiter. This is undesirable if that
489 * waiter is a high priority task.
490 */
Chris Wilson1b7744e2016-07-01 17:23:17 +0100491 u32 seqno = intel_engine_get_seqno(engine);
Chris Wilson688e6c72016-07-01 17:23:15 +0100492
493 while (i915_seqno_passed(seqno, to_wait(next)->seqno)) {
494 struct rb_node *n = rb_next(next);
495
496 __intel_breadcrumbs_finish(b, to_wait(next));
497 next = n;
498 if (!chain_wakeup(next, priority))
499 break;
500 }
501 }
502
Chris Wilsonb66255f2017-03-03 17:14:22 +0000503 __intel_breadcrumbs_next(engine, next);
Chris Wilson688e6c72016-07-01 17:23:15 +0100504 } else {
505 GEM_BUG_ON(rb_first(&b->waiters) == &wait->node);
506 }
507
508 GEM_BUG_ON(RB_EMPTY_NODE(&wait->node));
509 rb_erase(&wait->node, &b->waiters);
510
Chris Wilson9eb143b2017-02-23 07:44:16 +0000511out:
Chris Wilson61d3dc72017-03-03 19:08:24 +0000512 GEM_BUG_ON(b->irq_wait == wait);
Chris Wilson688e6c72016-07-01 17:23:15 +0100513 GEM_BUG_ON(rb_first(&b->waiters) !=
Chris Wilson61d3dc72017-03-03 19:08:24 +0000514 (b->irq_wait ? &b->irq_wait->node : NULL));
Chris Wilson9eb143b2017-02-23 07:44:16 +0000515}
516
517void intel_engine_remove_wait(struct intel_engine_cs *engine,
518 struct intel_wait *wait)
519{
520 struct intel_breadcrumbs *b = &engine->breadcrumbs;
521
522 /* Quick check to see if this waiter was already decoupled from
523 * the tree by the bottom-half to avoid contention on the spinlock
524 * by the herd.
525 */
Chris Wilson908a6cb2017-03-15 21:07:25 +0000526 if (RB_EMPTY_NODE(&wait->node)) {
527 GEM_BUG_ON(READ_ONCE(b->irq_wait) == wait);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000528 return;
Chris Wilson908a6cb2017-03-15 21:07:25 +0000529 }
Chris Wilson9eb143b2017-02-23 07:44:16 +0000530
Chris Wilson61d3dc72017-03-03 19:08:24 +0000531 spin_lock_irq(&b->rb_lock);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000532 __intel_engine_remove_wait(engine, wait);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000533 spin_unlock_irq(&b->rb_lock);
Chris Wilson688e6c72016-07-01 17:23:15 +0100534}
535
Chris Wilsond6a22892017-02-23 07:44:17 +0000536static bool signal_valid(const struct drm_i915_gem_request *request)
537{
538 return intel_wait_check_request(&request->signaling.wait, request);
539}
540
541static bool signal_complete(const struct drm_i915_gem_request *request)
Chris Wilsonc81d4612016-07-01 17:23:25 +0100542{
Chris Wilsonb3850852016-07-01 17:23:26 +0100543 if (!request)
Chris Wilsonc81d4612016-07-01 17:23:25 +0100544 return false;
545
546 /* If another process served as the bottom-half it may have already
547 * signalled that this wait is already completed.
548 */
Chris Wilsonb3850852016-07-01 17:23:26 +0100549 if (intel_wait_complete(&request->signaling.wait))
Chris Wilsond6a22892017-02-23 07:44:17 +0000550 return signal_valid(request);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100551
552 /* Carefully check if the request is complete, giving time for the
553 * seqno to be visible or if the GPU hung.
554 */
Chris Wilsonb3850852016-07-01 17:23:26 +0100555 if (__i915_request_irq_complete(request))
Chris Wilsonc81d4612016-07-01 17:23:25 +0100556 return true;
557
558 return false;
559}
560
Chris Wilsonb3850852016-07-01 17:23:26 +0100561static struct drm_i915_gem_request *to_signaler(struct rb_node *rb)
Chris Wilsonc81d4612016-07-01 17:23:25 +0100562{
Chris Wilsond8567862016-12-20 10:40:03 +0000563 return rb_entry(rb, struct drm_i915_gem_request, signaling.node);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100564}
565
566static void signaler_set_rtpriority(void)
567{
568 struct sched_param param = { .sched_priority = 1 };
569
570 sched_setscheduler_nocheck(current, SCHED_FIFO, &param);
571}
572
573static int intel_breadcrumbs_signaler(void *arg)
574{
575 struct intel_engine_cs *engine = arg;
576 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilsonb3850852016-07-01 17:23:26 +0100577 struct drm_i915_gem_request *request;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100578
579 /* Install ourselves with high priority to reduce signalling latency */
580 signaler_set_rtpriority();
581
582 do {
583 set_current_state(TASK_INTERRUPTIBLE);
584
585 /* We are either woken up by the interrupt bottom-half,
586 * or by a client adding a new signaller. In both cases,
587 * the GPU seqno may have advanced beyond our oldest signal.
588 * If it has, propagate the signal, remove the waiter and
589 * check again with the next oldest signal. Otherwise we
590 * need to wait for a new interrupt from the GPU or for
591 * a new client.
592 */
Chris Wilsoncced5e22017-02-23 07:44:15 +0000593 rcu_read_lock();
594 request = rcu_dereference(b->first_signal);
595 if (request)
596 request = i915_gem_request_get_rcu(request);
597 rcu_read_unlock();
Chris Wilsonb3850852016-07-01 17:23:26 +0100598 if (signal_complete(request)) {
Chris Wilson7c9e9342017-01-24 11:00:09 +0000599 local_bh_disable();
600 dma_fence_signal(&request->fence);
601 local_bh_enable(); /* kick start the tasklets */
602
Chris Wilson61d3dc72017-03-03 19:08:24 +0000603 spin_lock_irq(&b->rb_lock);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000604
Chris Wilsonc81d4612016-07-01 17:23:25 +0100605 /* Wake up all other completed waiters and select the
606 * next bottom-half for the next user interrupt.
607 */
Chris Wilson9eb143b2017-02-23 07:44:16 +0000608 __intel_engine_remove_wait(engine,
609 &request->signaling.wait);
Chris Wilson5590af32016-09-09 14:11:54 +0100610
Chris Wilsonc81d4612016-07-01 17:23:25 +0100611 /* Find the next oldest signal. Note that as we have
612 * not been holding the lock, another client may
613 * have installed an even older signal than the one
614 * we just completed - so double check we are still
615 * the oldest before picking the next one.
616 */
Chris Wilsoncced5e22017-02-23 07:44:15 +0000617 if (request == rcu_access_pointer(b->first_signal)) {
Chris Wilsonb3850852016-07-01 17:23:26 +0100618 struct rb_node *rb =
619 rb_next(&request->signaling.node);
Chris Wilsoncced5e22017-02-23 07:44:15 +0000620 rcu_assign_pointer(b->first_signal,
621 rb ? to_signaler(rb) : NULL);
Chris Wilsonb3850852016-07-01 17:23:26 +0100622 }
623 rb_erase(&request->signaling.node, &b->signals);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000624 RB_CLEAR_NODE(&request->signaling.node);
625
Chris Wilson61d3dc72017-03-03 19:08:24 +0000626 spin_unlock_irq(&b->rb_lock);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100627
Chris Wilsone8a261e2016-07-20 13:31:49 +0100628 i915_gem_request_put(request);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100629 } else {
Chris Wilsond6a22892017-02-23 07:44:17 +0000630 DEFINE_WAIT(exec);
631
Chris Wilsonb1becb82017-04-03 11:51:24 +0100632 if (kthread_should_park())
633 kthread_parkme();
634
Chris Wilsoncced5e22017-02-23 07:44:15 +0000635 if (kthread_should_stop()) {
636 GEM_BUG_ON(request);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100637 break;
Chris Wilsoncced5e22017-02-23 07:44:15 +0000638 }
Chris Wilsonc81d4612016-07-01 17:23:25 +0100639
Chris Wilsond6a22892017-02-23 07:44:17 +0000640 if (request)
641 add_wait_queue(&request->execute, &exec);
642
Chris Wilsonc81d4612016-07-01 17:23:25 +0100643 schedule();
Chris Wilsonfe3288b2017-02-12 17:20:01 +0000644
Chris Wilsond6a22892017-02-23 07:44:17 +0000645 if (request)
646 remove_wait_queue(&request->execute, &exec);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100647 }
Chris Wilsoncced5e22017-02-23 07:44:15 +0000648 i915_gem_request_put(request);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100649 } while (1);
650 __set_current_state(TASK_RUNNING);
651
652 return 0;
653}
654
Chris Wilsonb3850852016-07-01 17:23:26 +0100655void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
Chris Wilsonc81d4612016-07-01 17:23:25 +0100656{
657 struct intel_engine_cs *engine = request->engine;
658 struct intel_breadcrumbs *b = &engine->breadcrumbs;
659 struct rb_node *parent, **p;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100660 bool first, wakeup;
Chris Wilson754c9fd2017-02-23 07:44:14 +0000661 u32 seqno;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100662
Chris Wilsonf6168e32016-10-28 13:58:55 +0100663 /* Note that we may be called from an interrupt handler on another
664 * device (e.g. nouveau signaling a fence completion causing us
665 * to submit a request, and so enable signaling). As such,
Chris Wilsona6b0a1412017-03-15 22:22:59 +0000666 * we need to make sure that all other users of b->rb_lock protect
Chris Wilsonf6168e32016-10-28 13:58:55 +0100667 * against interrupts, i.e. use spin_lock_irqsave.
668 */
669
670 /* locked by dma_fence_enable_sw_signaling() (irqsafe fence->lock) */
Chris Wilsone60a8702017-03-02 11:51:30 +0000671 GEM_BUG_ON(!irqs_disabled());
Chris Wilson67520412017-03-02 13:28:01 +0000672 lockdep_assert_held(&request->lock);
Chris Wilson754c9fd2017-02-23 07:44:14 +0000673
674 seqno = i915_gem_request_global_seqno(request);
675 if (!seqno)
Chris Wilson65e47602016-10-28 13:58:49 +0100676 return;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100677
Chris Wilsonb3850852016-07-01 17:23:26 +0100678 request->signaling.wait.tsk = b->signaler;
Chris Wilson56299fb2017-02-27 20:58:48 +0000679 request->signaling.wait.request = request;
Chris Wilson754c9fd2017-02-23 07:44:14 +0000680 request->signaling.wait.seqno = seqno;
Chris Wilsone8a261e2016-07-20 13:31:49 +0100681 i915_gem_request_get(request);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100682
Chris Wilson61d3dc72017-03-03 19:08:24 +0000683 spin_lock(&b->rb_lock);
Chris Wilson4a50d202016-07-26 12:01:50 +0100684
Chris Wilsonc81d4612016-07-01 17:23:25 +0100685 /* First add ourselves into the list of waiters, but register our
686 * bottom-half as the signaller thread. As per usual, only the oldest
687 * waiter (not just signaller) is tasked as the bottom-half waking
688 * up all completed waiters after the user interrupt.
689 *
690 * If we are the oldest waiter, enable the irq (after which we
691 * must double check that the seqno did not complete).
692 */
Chris Wilsonb3850852016-07-01 17:23:26 +0100693 wakeup = __intel_engine_add_wait(engine, &request->signaling.wait);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100694
695 /* Now insert ourselves into the retirement ordered list of signals
696 * on this engine. We track the oldest seqno as that will be the
697 * first signal to complete.
698 */
Chris Wilsonc81d4612016-07-01 17:23:25 +0100699 parent = NULL;
700 first = true;
701 p = &b->signals.rb_node;
702 while (*p) {
703 parent = *p;
Chris Wilson754c9fd2017-02-23 07:44:14 +0000704 if (i915_seqno_passed(seqno,
705 to_signaler(parent)->signaling.wait.seqno)) {
Chris Wilsonc81d4612016-07-01 17:23:25 +0100706 p = &parent->rb_right;
707 first = false;
708 } else {
709 p = &parent->rb_left;
710 }
711 }
Chris Wilsonb3850852016-07-01 17:23:26 +0100712 rb_link_node(&request->signaling.node, parent, p);
713 rb_insert_color(&request->signaling.node, &b->signals);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100714 if (first)
Chris Wilsoncced5e22017-02-23 07:44:15 +0000715 rcu_assign_pointer(b->first_signal, request);
Chris Wilsonb3850852016-07-01 17:23:26 +0100716
Chris Wilson61d3dc72017-03-03 19:08:24 +0000717 spin_unlock(&b->rb_lock);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100718
719 if (wakeup)
720 wake_up_process(b->signaler);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100721}
722
Chris Wilson9eb143b2017-02-23 07:44:16 +0000723void intel_engine_cancel_signaling(struct drm_i915_gem_request *request)
724{
725 struct intel_engine_cs *engine = request->engine;
726 struct intel_breadcrumbs *b = &engine->breadcrumbs;
727
Chris Wilsone60a8702017-03-02 11:51:30 +0000728 GEM_BUG_ON(!irqs_disabled());
Chris Wilson67520412017-03-02 13:28:01 +0000729 lockdep_assert_held(&request->lock);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000730 GEM_BUG_ON(!request->signaling.wait.seqno);
731
Chris Wilson61d3dc72017-03-03 19:08:24 +0000732 spin_lock(&b->rb_lock);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000733
734 if (!RB_EMPTY_NODE(&request->signaling.node)) {
735 if (request == rcu_access_pointer(b->first_signal)) {
736 struct rb_node *rb =
737 rb_next(&request->signaling.node);
738 rcu_assign_pointer(b->first_signal,
739 rb ? to_signaler(rb) : NULL);
740 }
741 rb_erase(&request->signaling.node, &b->signals);
742 RB_CLEAR_NODE(&request->signaling.node);
743 i915_gem_request_put(request);
744 }
745
746 __intel_engine_remove_wait(engine, &request->signaling.wait);
747
Chris Wilson61d3dc72017-03-03 19:08:24 +0000748 spin_unlock(&b->rb_lock);
Chris Wilson9eb143b2017-02-23 07:44:16 +0000749
750 request->signaling.wait.seqno = 0;
751}
752
Chris Wilson688e6c72016-07-01 17:23:15 +0100753int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
754{
755 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100756 struct task_struct *tsk;
Chris Wilson688e6c72016-07-01 17:23:15 +0100757
Chris Wilson61d3dc72017-03-03 19:08:24 +0000758 spin_lock_init(&b->rb_lock);
759 spin_lock_init(&b->irq_lock);
760
Chris Wilson688e6c72016-07-01 17:23:15 +0100761 setup_timer(&b->fake_irq,
762 intel_breadcrumbs_fake_irq,
763 (unsigned long)engine);
Chris Wilson83348ba2016-08-09 17:47:51 +0100764 setup_timer(&b->hangcheck,
765 intel_breadcrumbs_hangcheck,
766 (unsigned long)engine);
Chris Wilson688e6c72016-07-01 17:23:15 +0100767
Chris Wilsonc81d4612016-07-01 17:23:25 +0100768 /* Spawn a thread to provide a common bottom-half for all signals.
769 * As this is an asynchronous interface we cannot steal the current
770 * task for handling the bottom-half to the user interrupt, therefore
771 * we create a thread to do the coherent seqno dance after the
772 * interrupt and then signal the waitqueue (via the dma-buf/fence).
773 */
774 tsk = kthread_run(intel_breadcrumbs_signaler, engine,
775 "i915/signal:%d", engine->id);
776 if (IS_ERR(tsk))
777 return PTR_ERR(tsk);
778
779 b->signaler = tsk;
780
Chris Wilson688e6c72016-07-01 17:23:15 +0100781 return 0;
782}
783
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100784static void cancel_fake_irq(struct intel_engine_cs *engine)
785{
786 struct intel_breadcrumbs *b = &engine->breadcrumbs;
787
788 del_timer_sync(&b->hangcheck);
789 del_timer_sync(&b->fake_irq);
790 clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
791}
792
793void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
794{
795 struct intel_breadcrumbs *b = &engine->breadcrumbs;
796
797 cancel_fake_irq(engine);
Chris Wilson61d3dc72017-03-03 19:08:24 +0000798 spin_lock_irq(&b->irq_lock);
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100799
Chris Wilson67b807a82017-02-27 20:58:50 +0000800 if (b->irq_enabled)
801 irq_enable(engine);
802 else
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100803 irq_disable(engine);
Chris Wilson67b807a82017-02-27 20:58:50 +0000804
805 /* We set the IRQ_BREADCRUMB bit when we enable the irq presuming the
806 * GPU is active and may have already executed the MI_USER_INTERRUPT
807 * before the CPU is ready to receive. However, the engine is currently
808 * idle (we haven't started it yet), there is no possibility for a
809 * missed interrupt as we enabled the irq and so we can clear the
810 * immediate wakeup (until a real interrupt arrives for the waiter).
811 */
812 clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
813
814 if (b->irq_armed)
815 enable_fake_irq(b);
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100816
Chris Wilson61d3dc72017-03-03 19:08:24 +0000817 spin_unlock_irq(&b->irq_lock);
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100818}
819
Chris Wilson688e6c72016-07-01 17:23:15 +0100820void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
821{
822 struct intel_breadcrumbs *b = &engine->breadcrumbs;
823
Chris Wilson381744f2016-11-21 11:07:59 +0000824 /* The engines should be idle and all requests accounted for! */
Chris Wilson61d3dc72017-03-03 19:08:24 +0000825 WARN_ON(READ_ONCE(b->irq_wait));
Chris Wilson381744f2016-11-21 11:07:59 +0000826 WARN_ON(!RB_EMPTY_ROOT(&b->waiters));
Chris Wilsoncced5e22017-02-23 07:44:15 +0000827 WARN_ON(rcu_access_pointer(b->first_signal));
Chris Wilson381744f2016-11-21 11:07:59 +0000828 WARN_ON(!RB_EMPTY_ROOT(&b->signals));
829
Chris Wilsonc81d4612016-07-01 17:23:25 +0100830 if (!IS_ERR_OR_NULL(b->signaler))
831 kthread_stop(b->signaler);
832
Chris Wilsonad07dfc2016-10-07 07:53:26 +0100833 cancel_fake_irq(engine);
Chris Wilson688e6c72016-07-01 17:23:15 +0100834}
835
Chris Wilson9b6586a2017-02-23 07:44:08 +0000836bool intel_breadcrumbs_busy(struct intel_engine_cs *engine)
Chris Wilsonc81d4612016-07-01 17:23:25 +0100837{
Chris Wilson9b6586a2017-02-23 07:44:08 +0000838 struct intel_breadcrumbs *b = &engine->breadcrumbs;
839 bool busy = false;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100840
Chris Wilson61d3dc72017-03-03 19:08:24 +0000841 spin_lock_irq(&b->rb_lock);
Chris Wilson6a5d1db2016-11-08 14:37:19 +0000842
Chris Wilson61d3dc72017-03-03 19:08:24 +0000843 if (b->irq_wait) {
844 wake_up_process(b->irq_wait->tsk);
Chris Wilson4bd66392017-03-15 21:07:22 +0000845 busy = true;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100846 }
847
Chris Wilsoncced5e22017-02-23 07:44:15 +0000848 if (rcu_access_pointer(b->first_signal)) {
Chris Wilson9b6586a2017-02-23 07:44:08 +0000849 wake_up_process(b->signaler);
Chris Wilson4bd66392017-03-15 21:07:22 +0000850 busy = true;
Chris Wilson9b6586a2017-02-23 07:44:08 +0000851 }
852
Chris Wilson61d3dc72017-03-03 19:08:24 +0000853 spin_unlock_irq(&b->rb_lock);
Chris Wilson9b6586a2017-02-23 07:44:08 +0000854
855 return busy;
Chris Wilsonc81d4612016-07-01 17:23:25 +0100856}
Chris Wilsonf97fbf92017-02-13 17:15:14 +0000857
858#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
859#include "selftests/intel_breadcrumbs.c"
860#endif