blob: 36c107e2058a9566e2de2687c3c3ad0bd6ec4c23 [file] [log] [blame]
Zhi Wang82d375d2016-07-05 12:40:49 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
26 *
27 * Contributors:
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 *
32 */
33
34#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +080035#include "gvt.h"
36#include "i915_pvinfo.h"
Zhi Wang82d375d2016-07-05 12:40:49 -040037
Ping Gao23736d12016-10-26 09:38:52 +080038void populate_pvinfo_page(struct intel_vgpu *vgpu)
Zhi Wang82d375d2016-07-05 12:40:49 -040039{
40 /* setup the ballooning information */
41 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
46 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
47 vgpu_aperture_gmadr_base(vgpu);
48 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
49 vgpu_aperture_sz(vgpu);
50 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
51 vgpu_hidden_gmadr_base(vgpu);
52 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
53 vgpu_hidden_sz(vgpu);
54
55 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
56
57 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
58 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
59 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
60 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
61 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
62 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
63
64 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
65}
66
Ping Gaobc90d092017-03-30 00:36:37 +080067#define VGPU_MAX_WEIGHT 16
68#define VGPU_WEIGHT(vgpu_num) \
69 (VGPU_MAX_WEIGHT / (vgpu_num))
70
Zhenyu Wang191020b2017-02-23 14:46:23 +080071static struct {
72 unsigned int low_mm;
73 unsigned int high_mm;
74 unsigned int fence;
Ping Gaobc90d092017-03-30 00:36:37 +080075
76 /* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
77 * with a weight of 4 on a contended host, different vGPU type has
78 * different weight set. Legal weights range from 1 to 16.
79 */
80 unsigned int weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +080081 enum intel_vgpu_edid edid;
Zhenyu Wang191020b2017-02-23 14:46:23 +080082 char *name;
83} vgpu_types[] = {
84/* Fixed vGPU type table */
Ping Gaobc90d092017-03-30 00:36:37 +080085 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
86 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
87 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
88 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
Zhenyu Wang191020b2017-02-23 14:46:23 +080089};
90
Zhi Wang82d375d2016-07-05 12:40:49 -040091/**
Zhenyu Wang1f31c822016-11-03 18:38:31 +080092 * intel_gvt_init_vgpu_types - initialize vGPU type list
93 * @gvt : GVT device
94 *
95 * Initialize vGPU type list based on available resource.
96 *
97 */
98int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
99{
100 unsigned int num_types;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800101 unsigned int i, low_avail, high_avail;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800102 unsigned int min_low;
103
104 /* vGPU type name is defined as GVTg_Vx_y which contains
Zhenyu Wang191020b2017-02-23 14:46:23 +0800105 * physical GPU generation type (e.g V4 as BDW server, V5 as
106 * SKL server).
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800107 *
108 * Depend on physical SKU resource, might see vGPU types like
109 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
110 * different types of vGPU on same physical GPU depending on
111 * available resource. Each vGPU type will have "avail_instance"
112 * to indicate how many vGPU instance can be created for this
113 * type.
114 *
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800115 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800116 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
117 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800118 num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800119
120 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
121 GFP_KERNEL);
122 if (!gvt->types)
123 return -ENOMEM;
124
125 min_low = MB_TO_BYTES(32);
126 for (i = 0; i < num_types; ++i) {
Zhenyu Wang191020b2017-02-23 14:46:23 +0800127 if (low_avail / vgpu_types[i].low_mm == 0)
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800128 break;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800129
130 gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
131 gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
132 gvt->types[i].fence = vgpu_types[i].fence;
Ping Gaobc90d092017-03-30 00:36:37 +0800133
134 if (vgpu_types[i].weight < 1 ||
135 vgpu_types[i].weight > VGPU_MAX_WEIGHT)
136 return -EINVAL;
137
138 gvt->types[i].weight = vgpu_types[i].weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800139 gvt->types[i].resolution = vgpu_types[i].edid;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800140 gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
141 high_avail / vgpu_types[i].high_mm);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800142
143 if (IS_GEN8(gvt->dev_priv))
Zhenyu Wang191020b2017-02-23 14:46:23 +0800144 sprintf(gvt->types[i].name, "GVTg_V4_%s",
145 vgpu_types[i].name);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800146 else if (IS_GEN9(gvt->dev_priv))
Zhenyu Wang191020b2017-02-23 14:46:23 +0800147 sprintf(gvt->types[i].name, "GVTg_V5_%s",
148 vgpu_types[i].name);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800149
Ping Gaobc90d092017-03-30 00:36:37 +0800150 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
Zhenyu Wang191020b2017-02-23 14:46:23 +0800151 i, gvt->types[i].name,
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800152 gvt->types[i].avail_instance,
153 gvt->types[i].low_gm_size,
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800154 gvt->types[i].high_gm_size, gvt->types[i].fence,
Ping Gaobc90d092017-03-30 00:36:37 +0800155 gvt->types[i].weight,
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800156 vgpu_edid_str(gvt->types[i].resolution));
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800157 }
158
159 gvt->num_types = i;
160 return 0;
161}
162
163void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
164{
165 kfree(gvt->types);
166}
167
168static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
169{
170 int i;
171 unsigned int low_gm_avail, high_gm_avail, fence_avail;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800172 unsigned int low_gm_min, high_gm_min, fence_min;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800173
174 /* Need to depend on maxium hw resource size but keep on
175 * static config for now.
176 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800177 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800178 gvt->gm.vgpu_allocated_low_gm_size;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800179 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800180 gvt->gm.vgpu_allocated_high_gm_size;
181 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
182 gvt->fence.vgpu_allocated_fence_num;
183
184 for (i = 0; i < gvt->num_types; i++) {
185 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
186 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
187 fence_min = fence_avail / gvt->types[i].fence;
Zhenyu Wang191020b2017-02-23 14:46:23 +0800188 gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
189 fence_min);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800190
Zhenyu Wang191020b2017-02-23 14:46:23 +0800191 gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
192 i, gvt->types[i].name,
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800193 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
194 gvt->types[i].high_gm_size, gvt->types[i].fence);
195 }
196}
197
198/**
Zhi Wang82d375d2016-07-05 12:40:49 -0400199 * intel_gvt_destroy_vgpu - destroy a virtual GPU
200 * @vgpu: virtual GPU
201 *
202 * This function is called when user wants to destroy a virtual GPU.
203 *
204 */
205void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
206{
207 struct intel_gvt *gvt = vgpu->gvt;
208
209 mutex_lock(&gvt->lock);
210
211 vgpu->active = false;
212 idr_remove(&gvt->vgpu_idr, vgpu->id);
213
Zhi Wang4b639602016-05-01 17:09:58 -0400214 if (atomic_read(&vgpu->running_workload_num)) {
215 mutex_unlock(&gvt->lock);
216 intel_gvt_wait_vgpu_idle(vgpu);
217 mutex_lock(&gvt->lock);
218 }
219
220 intel_vgpu_stop_schedule(vgpu);
221 intel_vgpu_clean_sched_policy(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400222 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400223 intel_vgpu_clean_execlist(vgpu);
Zhi Wang04d348a2016-04-25 18:28:56 -0400224 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400225 intel_vgpu_clean_opregion(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800226 intel_vgpu_clean_gtt(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400227 intel_gvt_hypervisor_detach_vgpu(vgpu);
228 intel_vgpu_free_resource(vgpu);
Changbin Ducdcc4342017-01-13 11:16:00 +0800229 intel_vgpu_clean_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400230 vfree(vgpu);
231
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800232 intel_gvt_update_vgpu_types(gvt);
Zhi Wang82d375d2016-07-05 12:40:49 -0400233 mutex_unlock(&gvt->lock);
234}
235
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800236static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
Zhi Wang82d375d2016-07-05 12:40:49 -0400237 struct intel_vgpu_creation_params *param)
238{
239 struct intel_vgpu *vgpu;
240 int ret;
241
242 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
243 param->handle, param->low_gm_sz, param->high_gm_sz,
244 param->fence_sz);
245
246 vgpu = vzalloc(sizeof(*vgpu));
247 if (!vgpu)
248 return ERR_PTR(-ENOMEM);
249
250 mutex_lock(&gvt->lock);
251
252 ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL);
253 if (ret < 0)
254 goto out_free_vgpu;
255
256 vgpu->id = ret;
257 vgpu->handle = param->handle;
258 vgpu->gvt = gvt;
Ping Gaobc90d092017-03-30 00:36:37 +0800259 vgpu->sched_ctl.weight = param->weight;
Zhi Wang17865712016-05-01 19:02:37 -0400260 bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
Zhi Wang82d375d2016-07-05 12:40:49 -0400261
Changbin Du536fc232017-01-13 11:15:58 +0800262 intel_vgpu_init_cfg_space(vgpu, param->primary);
Zhi Wang82d375d2016-07-05 12:40:49 -0400263
Changbin Ducdcc4342017-01-13 11:16:00 +0800264 ret = intel_vgpu_init_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400265 if (ret)
Jike Song4e537892017-01-06 15:16:22 +0800266 goto out_clean_idr;
Zhi Wang82d375d2016-07-05 12:40:49 -0400267
268 ret = intel_vgpu_alloc_resource(vgpu, param);
269 if (ret)
270 goto out_clean_vgpu_mmio;
271
272 populate_pvinfo_page(vgpu);
273
274 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
275 if (ret)
276 goto out_clean_vgpu_resource;
277
Zhi Wang2707e442016-03-28 23:23:16 +0800278 ret = intel_vgpu_init_gtt(vgpu);
279 if (ret)
280 goto out_detach_hypervisor_vgpu;
281
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800282 ret = intel_vgpu_init_display(vgpu, param->resolution);
Zhi Wang04d348a2016-04-25 18:28:56 -0400283 if (ret)
Jike Song8f897432016-11-03 18:38:32 +0800284 goto out_clean_gtt;
Zhi Wang04d348a2016-04-25 18:28:56 -0400285
Zhi Wang8453d672016-05-01 02:48:25 -0400286 ret = intel_vgpu_init_execlist(vgpu);
287 if (ret)
288 goto out_clean_display;
289
Zhi Wange4734052016-05-01 07:42:16 -0400290 ret = intel_vgpu_init_gvt_context(vgpu);
291 if (ret)
292 goto out_clean_execlist;
293
Zhi Wang4b639602016-05-01 17:09:58 -0400294 ret = intel_vgpu_init_sched_policy(vgpu);
295 if (ret)
296 goto out_clean_shadow_ctx;
297
Zhi Wang82d375d2016-07-05 12:40:49 -0400298 vgpu->active = true;
299 mutex_unlock(&gvt->lock);
300
301 return vgpu;
302
Zhi Wang4b639602016-05-01 17:09:58 -0400303out_clean_shadow_ctx:
304 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400305out_clean_execlist:
306 intel_vgpu_clean_execlist(vgpu);
Zhi Wang8453d672016-05-01 02:48:25 -0400307out_clean_display:
308 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400309out_clean_gtt:
310 intel_vgpu_clean_gtt(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800311out_detach_hypervisor_vgpu:
312 intel_gvt_hypervisor_detach_vgpu(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400313out_clean_vgpu_resource:
314 intel_vgpu_free_resource(vgpu);
315out_clean_vgpu_mmio:
Changbin Ducdcc4342017-01-13 11:16:00 +0800316 intel_vgpu_clean_mmio(vgpu);
Jike Song4e537892017-01-06 15:16:22 +0800317out_clean_idr:
318 idr_remove(&gvt->vgpu_idr, vgpu->id);
Zhi Wang82d375d2016-07-05 12:40:49 -0400319out_free_vgpu:
320 vfree(vgpu);
321 mutex_unlock(&gvt->lock);
322 return ERR_PTR(ret);
323}
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800324
325/**
326 * intel_gvt_create_vgpu - create a virtual GPU
327 * @gvt: GVT device
328 * @type: type of the vGPU to create
329 *
330 * This function is called when user wants to create a virtual GPU.
331 *
332 * Returns:
333 * pointer to intel_vgpu, error pointer if failed.
334 */
335struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
336 struct intel_vgpu_type *type)
337{
338 struct intel_vgpu_creation_params param;
339 struct intel_vgpu *vgpu;
340
341 param.handle = 0;
Du, Changbine992fae2016-11-21 17:08:14 +0800342 param.primary = 1;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800343 param.low_gm_sz = type->low_gm_size;
344 param.high_gm_sz = type->high_gm_size;
345 param.fence_sz = type->fence;
Ping Gaobc90d092017-03-30 00:36:37 +0800346 param.weight = type->weight;
Zhenyu Wangd1a513b2017-02-24 10:58:21 +0800347 param.resolution = type->resolution;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800348
349 /* XXX current param based on MB */
350 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
351 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
352
353 vgpu = __intel_gvt_create_vgpu(gvt, &param);
354 if (IS_ERR(vgpu))
355 return vgpu;
356
357 /* calculate left instance change for types */
358 intel_gvt_update_vgpu_types(gvt);
359
360 return vgpu;
361}
Jike Song9ec1e662016-11-03 18:38:35 +0800362
363/**
Changbin Ducfe65f42017-01-13 11:16:02 +0800364 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
365 * @vgpu: virtual GPU
366 * @dmlr: vGPU Device Model Level Reset or GT Reset
367 * @engine_mask: engines to reset for GT reset
368 *
369 * This function is called when user wants to reset a virtual GPU through
370 * device model reset or GT reset. The caller should hold the gvt lock.
371 *
372 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
373 * the whole vGPU to default state as when it is created. This vGPU function
374 * is required both for functionary and security concerns.The ultimate goal
375 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
376 * assign a vGPU to a virtual machine we must isse such reset first.
377 *
378 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
379 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
380 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
381 * the reset request. Guest driver can issue a GT reset by programming the
382 * virtual GDRST register to reset specific virtual GPU engine or all
383 * engines.
384 *
385 * The parameter dev_level is to identify if we will do DMLR or GT reset.
386 * The parameter engine_mask is to specific the engines that need to be
387 * resetted. If value ALL_ENGINES is given for engine_mask, it means
388 * the caller requests a full GT reset that we will reset all virtual
389 * GPU engines. For FLR, engine_mask is ignored.
390 */
391void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
392 unsigned int engine_mask)
393{
394 struct intel_gvt *gvt = vgpu->gvt;
395 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
396
397 gvt_dbg_core("------------------------------------------\n");
398 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
399 vgpu->id, dmlr, engine_mask);
400 vgpu->resetting = true;
401
402 intel_vgpu_stop_schedule(vgpu);
403 /*
404 * The current_vgpu will set to NULL after stopping the
405 * scheduler when the reset is triggered by current vgpu.
406 */
407 if (scheduler->current_vgpu == NULL) {
408 mutex_unlock(&gvt->lock);
409 intel_gvt_wait_vgpu_idle(vgpu);
410 mutex_lock(&gvt->lock);
411 }
412
413 intel_vgpu_reset_execlist(vgpu, dmlr ? ALL_ENGINES : engine_mask);
414
415 /* full GPU reset or device model level reset */
416 if (engine_mask == ALL_ENGINES || dmlr) {
417 intel_vgpu_reset_gtt(vgpu, dmlr);
418 intel_vgpu_reset_resource(vgpu);
419 intel_vgpu_reset_mmio(vgpu);
420 populate_pvinfo_page(vgpu);
Changbin Du6294b612017-02-14 14:50:18 +0800421 intel_vgpu_reset_display(vgpu);
Changbin Ducfe65f42017-01-13 11:16:02 +0800422
Min Hefd64be62017-02-17 15:02:36 +0800423 if (dmlr) {
Changbin Ducfe65f42017-01-13 11:16:02 +0800424 intel_vgpu_reset_cfg_space(vgpu);
Min Hefd64be62017-02-17 15:02:36 +0800425 /* only reset the failsafe mode when dmlr reset */
426 vgpu->failsafe = false;
427 vgpu->pv_notified = false;
428 }
Changbin Ducfe65f42017-01-13 11:16:02 +0800429 }
430
431 vgpu->resetting = false;
432 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
433 gvt_dbg_core("------------------------------------------\n");
434}
435
436/**
437 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
Jike Song9ec1e662016-11-03 18:38:35 +0800438 * @vgpu: virtual GPU
439 *
440 * This function is called when user wants to reset a virtual GPU.
441 *
442 */
443void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
444{
Changbin Ducfe65f42017-01-13 11:16:02 +0800445 mutex_lock(&vgpu->gvt->lock);
446 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
447 mutex_unlock(&vgpu->gvt->lock);
Jike Song9ec1e662016-11-03 18:38:35 +0800448}