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Emmanuel Grumbachab697a92011-07-11 07:35:34 -07001/******************************************************************************
2 *
Johannes Berg128e63e2013-01-21 21:39:26 +01003 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
Emmanuel Grumbachab697a92011-07-11 07:35:34 -07004 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#ifndef __iwl_trans_int_pcie_h__
30#define __iwl_trans_int_pcie_h__
31
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070032#include <linux/spinlock.h>
33#include <linux/interrupt.h>
34#include <linux/skbuff.h>
Johannes Berg13df1aa2012-03-06 13:31:00 -080035#include <linux/wait.h>
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070036#include <linux/pci.h>
Johannes Berg7c5ba4a2012-04-09 17:46:54 -070037#include <linux/timer.h>
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070038
Emmanuel Grumbachdda61a42011-08-25 23:11:11 -070039#include "iwl-fh.h"
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070040#include "iwl-csr.h"
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070041#include "iwl-trans.h"
42#include "iwl-debug.h"
43#include "iwl-io.h"
Emmanuel Grumbach02e38352012-02-09 16:08:15 +020044#include "iwl-op-mode.h"
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070045
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -070046struct iwl_host_cmd;
Emmanuel Grumbachdda61a42011-08-25 23:11:11 -070047
Emmanuel Grumbachab697a92011-07-11 07:35:34 -070048/*This file includes the declaration that are internal to the
49 * trans_pcie layer */
50
Johannes Berg48a2d662012-03-05 11:24:39 -080051struct iwl_rx_mem_buffer {
52 dma_addr_t page_dma;
53 struct page *page;
54 struct list_head list;
55};
56
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070057/**
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -070058 * struct isr_statistics - interrupt statistics
59 *
60 */
61struct isr_statistics {
62 u32 hw;
63 u32 sw;
64 u32 err_code;
65 u32 sch;
66 u32 alive;
67 u32 rfkill;
68 u32 ctkill;
69 u32 wakeup;
70 u32 rx;
71 u32 tx;
72 u32 unhandled;
73};
74
75/**
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +020076 * struct iwl_rxq - Rx queue
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -070077 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
78 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
79 * @pool:
80 * @queue:
81 * @read: Shared index to newest available Rx buffer
82 * @write: Shared index to oldest written Rx packet
83 * @free_count: Number of pre-allocated buffers in rx_free
84 * @write_actual:
85 * @rx_free: list of free SKBs for use
86 * @rx_used: List of Rx buffers with no SKB
87 * @need_update: flag to indicate we need to update read/write index
88 * @rb_stts: driver's pointer to receive buffer status
89 * @rb_stts_dma: bus address of receive buffer status
90 * @lock:
91 *
92 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
93 */
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +020094struct iwl_rxq {
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -070095 __le32 *bd;
96 dma_addr_t bd_dma;
97 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
98 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
99 u32 read;
100 u32 write;
101 u32 free_count;
102 u32 write_actual;
103 struct list_head rx_free;
104 struct list_head rx_used;
105 int need_update;
106 struct iwl_rb_status *rb_stts;
107 dma_addr_t rb_stts_dma;
108 spinlock_t lock;
109};
110
Emmanuel Grumbacha72b8b02011-08-25 23:11:13 -0700111struct iwl_dma_ptr {
112 dma_addr_t dma;
113 void *addr;
114 size_t size;
115};
116
Johannes Bergbffc66c2012-03-05 11:24:42 -0800117/**
118 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
119 * @index -- current index
120 * @n_bd -- total number of entries in queue (must be power of 2)
121 */
122static inline int iwl_queue_inc_wrap(int index, int n_bd)
123{
124 return ++index & (n_bd - 1);
125}
126
127/**
128 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
129 * @index -- current index
130 * @n_bd -- total number of entries in queue (must be power of 2)
131 */
132static inline int iwl_queue_dec_wrap(int index, int n_bd)
133{
134 return --index & (n_bd - 1);
135}
136
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700137struct iwl_cmd_meta {
138 /* only for SYNC commands, iff the reply skb is wanted */
139 struct iwl_host_cmd *source;
Johannes Bergc14c7372012-04-16 14:48:08 -0700140 u32 flags;
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700141};
142
143/*
144 * Generic queue structure
145 *
146 * Contains common data for Rx and Tx queues.
147 *
148 * Note the difference between n_bd and n_window: the hardware
149 * always assumes 256 descriptors, so n_bd is always 256 (unless
150 * there might be HW changes in the future). For the normal TX
151 * queues, n_window, which is the size of the software queue data
152 * is also 256; however, for the command queue, n_window is only
153 * 32 since we don't need so many commands pending. Since the HW
154 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
155 * the software buffers (in the variables @meta, @txb in struct
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200156 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
157 * the same struct) have 256.
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700158 * This means that we end up with the following:
159 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
160 * SW entries: | 0 | ... | 31 |
161 * where N is a number between 0 and 7. This means that the SW
162 * data is a window overlayed over the HW queue.
163 */
164struct iwl_queue {
165 int n_bd; /* number of BDs in this queue */
166 int write_ptr; /* 1-st empty entry (index) host_w*/
167 int read_ptr; /* last used entry (index) host_r*/
168 /* use for monitoring and recovering the stuck queue */
169 dma_addr_t dma_addr; /* physical addr for BD's */
170 int n_window; /* safe queue window */
171 u32 id;
172 int low_mark; /* low watermark, resume queue if free
173 * space more than this */
174 int high_mark; /* high watermark, stop queue if free
175 * space less than this */
176};
177
Johannes Bergbf8440e2012-03-19 17:12:06 +0100178#define TFD_TX_CMD_SLOTS 256
179#define TFD_CMD_SLOTS 32
180
Johannes Berg8a964f42013-02-25 16:01:34 +0100181/*
182 * The FH will write back to the first TB only, so we need
183 * to copy some data into the buffer regardless of whether
Johannes Berg38c0f3342013-02-27 13:18:50 +0100184 * it should be mapped or not. This indicates how big the
185 * first TB must be to include the scratch buffer. Since
186 * the scratch is 4 bytes at offset 12, it's 16 now. If we
187 * make it bigger then allocations will be bigger and copy
188 * slower, so that's probably not useful.
Johannes Berg8a964f42013-02-25 16:01:34 +0100189 */
Johannes Berg38c0f3342013-02-27 13:18:50 +0100190#define IWL_HCMD_SCRATCHBUF_SIZE 16
Johannes Berg8a964f42013-02-25 16:01:34 +0100191
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200192struct iwl_pcie_txq_entry {
Johannes Bergbf8440e2012-03-19 17:12:06 +0100193 struct iwl_device_cmd *cmd;
194 struct sk_buff *skb;
Johannes Bergf4feb8a2012-10-19 14:24:43 +0200195 /* buffer to free after command completes */
196 const void *free_buf;
Johannes Bergbf8440e2012-03-19 17:12:06 +0100197 struct iwl_cmd_meta meta;
198};
199
Johannes Berg38c0f3342013-02-27 13:18:50 +0100200struct iwl_pcie_txq_scratch_buf {
201 struct iwl_cmd_header hdr;
202 u8 buf[8];
203 __le32 scratch;
204};
205
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700206/**
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200207 * struct iwl_txq - Tx Queue for DMA
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700208 * @q: generic Rx/Tx queue descriptor
Johannes Bergbf8440e2012-03-19 17:12:06 +0100209 * @tfds: transmit frame descriptors (DMA memory)
Johannes Berg38c0f3342013-02-27 13:18:50 +0100210 * @scratchbufs: start of command headers, including scratch buffers, for
211 * the writeback -- this is DMA memory and an array holding one buffer
212 * for each command on the queue
213 * @scratchbufs_dma: DMA address for the scratchbufs start
Johannes Bergbf8440e2012-03-19 17:12:06 +0100214 * @entries: transmit entries (driver state)
215 * @lock: queue lock
216 * @stuck_timer: timer that fires if queue gets stuck
217 * @trans_pcie: pointer back to transport (for timer)
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700218 * @need_update: indicates need to update read/write index
Johannes Bergbf8440e2012-03-19 17:12:06 +0100219 * @active: stores if queue is active
Johannes Berg68972c42013-06-11 19:05:27 +0200220 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700221 *
222 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
223 * descriptors) and required locking structures.
224 */
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200225struct iwl_txq {
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700226 struct iwl_queue q;
227 struct iwl_tfd *tfds;
Johannes Berg38c0f3342013-02-27 13:18:50 +0100228 struct iwl_pcie_txq_scratch_buf *scratchbufs;
229 dma_addr_t scratchbufs_dma;
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200230 struct iwl_pcie_txq_entry *entries;
Johannes Berg015c15e2012-03-05 11:24:24 -0800231 spinlock_t lock;
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700232 struct timer_list stuck_timer;
233 struct iwl_trans_pcie *trans_pcie;
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700234 u8 need_update;
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700235 u8 active;
Johannes Berg68972c42013-06-11 19:05:27 +0200236 bool ampdu;
Emmanuel Grumbach522376d2011-09-06 09:31:19 -0700237};
238
Johannes Berg38c0f3342013-02-27 13:18:50 +0100239static inline dma_addr_t
240iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
241{
242 return txq->scratchbufs_dma +
243 sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
244}
245
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700246/**
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700247 * struct iwl_trans_pcie - PCIe transport specific data
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700248 * @rxq: all the RX queue data
249 * @rx_replenish: work that will be called when buffers need to be allocated
Emmanuel Grumbach9130bab2012-03-26 08:51:09 -0700250 * @drv - pointer to iwl_drv
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700251 * @trans: pointer to the generic transport area
Emmanuel Grumbach105183b2011-08-25 23:11:02 -0700252 * @scd_base_addr: scheduler sram base address in SRAM
253 * @scd_bc_tbls: pointer to the byte count table of the scheduler
Emmanuel Grumbach9d6b2cb2011-08-25 23:11:12 -0700254 * @kw: keep warm address
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800255 * @pci_dev: basic pci-network driver stuff
256 * @hw_base: pci hardware address support
Johannes Berg13df1aa2012-03-06 13:31:00 -0800257 * @ucode_write_complete: indicates that the ucode has been copied.
258 * @ucode_write_waitq: wait queue for uCode load
Don Fry9a716862012-03-07 09:52:32 -0800259 * @status - transport specific status flags
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800260 * @cmd_queue - command queue number
Johannes Bergb2cf4102012-04-09 17:46:51 -0700261 * @rx_buf_size_8k: 8 kB RX buffer size
Emmanuel Grumbach046db342012-12-05 15:07:54 +0200262 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
Johannes Bergb2cf4102012-04-09 17:46:51 -0700263 * @rx_page_order: page order for receive buffer size
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700264 * @wd_timeout: queue watchdog timeout (jiffies)
Lilach Edelsteine56b04e2013-01-16 11:34:49 +0200265 * @reg_lock: protect hw register access
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700266 */
267struct iwl_trans_pcie {
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200268 struct iwl_rxq rxq;
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700269 struct work_struct rx_replenish;
270 struct iwl_trans *trans;
Emmanuel Grumbach9130bab2012-03-26 08:51:09 -0700271 struct iwl_drv *drv;
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700272
273 /* INT ICT Table */
274 __le32 *ict_tbl;
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700275 dma_addr_t ict_tbl_dma;
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700276 int ict_index;
277 u32 inta;
278 bool use_ict;
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -0700279 struct isr_statistics isr_stats;
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700280
Johannes Berg7b114882012-02-05 13:55:11 -0800281 spinlock_t irq_lock;
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700282 u32 inta_mask;
Emmanuel Grumbach105183b2011-08-25 23:11:02 -0700283 u32 scd_base_addr;
284 struct iwl_dma_ptr scd_bc_tbls;
Emmanuel Grumbach9d6b2cb2011-08-25 23:11:12 -0700285 struct iwl_dma_ptr kw;
Emmanuel Grumbache13c0c52011-08-25 23:11:24 -0700286
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200287 struct iwl_txq *txq;
Johannes Berg9eae88f2012-03-15 13:26:52 -0700288 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700289 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800290
291 /* PCI bus related data */
292 struct pci_dev *pci_dev;
293 void __iomem *hw_base;
Johannes Berg13df1aa2012-03-06 13:31:00 -0800294
295 bool ucode_write_complete;
296 wait_queue_head_t ucode_write_waitq;
Emmanuel Grumbachf946b522012-10-25 17:25:52 +0200297 wait_queue_head_t wait_command_queue;
298
Don Fry9a716862012-03-07 09:52:32 -0800299 unsigned long status;
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800300 u8 cmd_queue;
Emmanuel Grumbachb04db9a2012-06-21 11:53:44 +0300301 u8 cmd_fifo;
Johannes Bergd663ee72012-03-10 13:00:07 -0800302 u8 n_no_reclaim_cmds;
303 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
Johannes Bergb2cf4102012-04-09 17:46:51 -0700304
305 bool rx_buf_size_8k;
Emmanuel Grumbach046db342012-12-05 15:07:54 +0200306 bool bc_table_dword;
Johannes Bergb2cf4102012-04-09 17:46:51 -0700307 u32 rx_page_order;
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700308
Johannes Bergd9fb6462012-03-26 08:23:39 -0700309 const char **command_names;
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700310
311 /* queue watchdog */
312 unsigned long wd_timeout;
Lilach Edelsteine56b04e2013-01-16 11:34:49 +0200313
314 /*protect hw register */
315 spinlock_t reg_lock;
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700316};
317
Emmanuel Grumbachb55e57f2012-11-14 12:32:50 +0200318/**
319 * enum iwl_pcie_status: status of the PCIe transport
320 * @STATUS_HCMD_ACTIVE: a SYNC command is being processed
321 * @STATUS_DEVICE_ENABLED: APM is enabled
322 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
323 * @STATUS_INT_ENABLED: interrupts are enabled
324 * @STATUS_RFKILL: the HW RFkill switch is in KILL position
325 * @STATUS_FW_ERROR: the fw is in error state
326 */
327enum iwl_pcie_status {
Emmanuel Grumbachf946b522012-10-25 17:25:52 +0200328 STATUS_HCMD_ACTIVE,
329 STATUS_DEVICE_ENABLED,
330 STATUS_TPOWER_PMI,
331 STATUS_INT_ENABLED,
332 STATUS_RFKILL,
Johannes Bergd18aa872012-11-06 16:36:21 +0100333 STATUS_FW_ERROR,
Emmanuel Grumbachf946b522012-10-25 17:25:52 +0200334};
Don Fry01d651d2012-03-23 08:34:31 -0700335
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -0700336#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
337 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
338
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700339static inline struct iwl_trans *
340iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
341{
342 return container_of((void *)trans_pcie, struct iwl_trans,
343 trans_specific);
344}
345
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200346/*
347 * Convention: trans API functions: iwl_trans_pcie_XXX
348 * Other functions: iwl_pcie_XXX
349 */
Johannes Bergd1ff5252012-04-12 06:24:30 -0700350struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
351 const struct pci_device_id *ent,
352 const struct iwl_cfg *cfg);
353void iwl_trans_pcie_free(struct iwl_trans *trans);
354
Emmanuel Grumbach253a6342011-07-11 07:39:46 -0700355/*****************************************************
356* RX
357******************************************************/
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200358int iwl_pcie_rx_init(struct iwl_trans *trans);
Johannes Berg2bfb5092012-12-27 21:43:48 +0100359irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200360int iwl_pcie_rx_stop(struct iwl_trans *trans);
361void iwl_pcie_rx_free(struct iwl_trans *trans);
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700362
Emmanuel Grumbach253a6342011-07-11 07:39:46 -0700363/*****************************************************
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200364* ICT - interrupt handling
Emmanuel Grumbach1a361cd2011-07-11 07:44:57 -0700365******************************************************/
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200366irqreturn_t iwl_pcie_isr_ict(int irq, void *data);
367int iwl_pcie_alloc_ict(struct iwl_trans *trans);
368void iwl_pcie_free_ict(struct iwl_trans *trans);
369void iwl_pcie_reset_ict(struct iwl_trans *trans);
370void iwl_pcie_disable_ict(struct iwl_trans *trans);
Emmanuel Grumbach1a361cd2011-07-11 07:44:57 -0700371
Emmanuel Grumbach1a361cd2011-07-11 07:44:57 -0700372/*****************************************************
Emmanuel Grumbach253a6342011-07-11 07:39:46 -0700373* TX / HCMD
374******************************************************/
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200375int iwl_pcie_tx_init(struct iwl_trans *trans);
376void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
377int iwl_pcie_tx_stop(struct iwl_trans *trans);
378void iwl_pcie_tx_free(struct iwl_trans *trans);
379void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
380 int sta_id, int tid, int frame_limit, u16 ssn);
381void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
382int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
383 struct iwl_device_cmd *dev_cmd, int txq_id);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200384void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200385int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200386void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
387 struct iwl_rx_cmd_buffer *rxb, int handler_status);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200388void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
389 struct sk_buff_head *skbs);
Johannes Bergddaf5a52013-01-08 11:25:44 +0100390void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
391
Emmanuel Grumbach7ff94702011-08-25 23:10:54 -0700392/*****************************************************
393* Error handling
394******************************************************/
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200395int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf);
396void iwl_pcie_dump_csr(struct iwl_trans *trans);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -0700397
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700398/*****************************************************
399* Helpers
400******************************************************/
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700401static inline void iwl_disable_interrupts(struct iwl_trans *trans)
402{
Don Fry83626402012-03-07 09:52:37 -0800403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
404 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700405
406 /* disable interrupts from uCode/NIC to host */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200407 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700408
409 /* acknowledge/clear/reset any interrupts still pending
410 * from uCode or flow handler (Rx/Tx DMA) */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200411 iwl_write32(trans, CSR_INT, 0xffffffff);
412 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700413 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
414}
415
416static inline void iwl_enable_interrupts(struct iwl_trans *trans)
417{
Don Fry83626402012-03-07 09:52:37 -0800418 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700419
420 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
Don Fry83626402012-03-07 09:52:37 -0800421 set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200422 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
Emmanuel Grumbach0c325762011-08-25 23:10:53 -0700423}
424
Stanislaw Gruszka8722c892012-03-07 09:52:28 -0800425static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
426{
427 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
428 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
429}
430
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700431static inline void iwl_wake_queue(struct iwl_trans *trans,
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200432 struct iwl_txq *txq)
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700433{
Johannes Berg9eae88f2012-03-15 13:26:52 -0700434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700435
Johannes Berg9eae88f2012-03-15 13:26:52 -0700436 if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
437 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
438 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
Emmanuel Grumbach81a3de12011-11-10 06:55:24 -0800439 }
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700440}
441
442static inline void iwl_stop_queue(struct iwl_trans *trans,
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200443 struct iwl_txq *txq)
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700444{
Johannes Berg9eae88f2012-03-15 13:26:52 -0700445 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbache20d43412011-08-25 23:11:31 -0700446
Johannes Berg9eae88f2012-03-15 13:26:52 -0700447 if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
448 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
449 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
450 } else
451 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
452 txq->q.id);
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700453}
454
Emmanuel Grumbach6ca6ebc2012-11-14 23:38:08 +0200455static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700456{
457 return q->write_ptr >= q->read_ptr ?
458 (i >= q->read_ptr && i < q->write_ptr) :
459 !(i < q->read_ptr && i >= q->write_ptr);
460}
461
462static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
463{
464 return index & (q->n_window - 1);
465}
466
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200467static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
468 u8 cmd)
Johannes Bergd9fb6462012-03-26 08:23:39 -0700469{
470 if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
471 return "UNKNOWN";
472 return trans_pcie->command_names[cmd];
473}
474
Emmanuel Grumbach8d425512012-03-28 11:00:58 +0200475static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
476{
477 return !(iwl_read32(trans, CSR_GP_CNTRL) &
478 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
479}
480
Emmanuel Grumbachab697a92011-07-11 07:35:34 -0700481#endif /* __iwl_trans_int_pcie_h__ */