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gerrit-public.fairphone.software / kernel / msm-5.4 / be086e7c53f1fac51eed14523b28f2214b548dd2 / . / drivers / net / ethernet / qlogic / qed / qed_roce.h
blob: 3ccc08a7c9959108382cbbb9f8fd8c592441bd28 [file] [log] [blame]
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]1/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +0200[diff] [blame]2 * Copyright (c) 2015-2017 QLogic Corporation
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef _QED_ROCE_H
33#define _QED_ROCE_H
34#include <linux/types.h>
35#include <linux/bitops.h>
36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/slab.h>
39#include <linux/spinlock.h>
40#include <linux/qed/qed_if.h>
41#include <linux/qed/qed_roce_if.h>
42#include "qed.h"
43#include "qed_dev_api.h"
44#include "qed_hsi.h"
Ram Amraniabd49672016-10-01 22:00:01 +0300[diff] [blame]45#include "qed_ll2.h"
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]46
47#define QED_RDMA_MAX_FMR (RDMA_MAX_TIDS)
48#define QED_RDMA_MAX_P_KEY (1)
49#define QED_RDMA_MAX_WQE (0x7FFF)
50#define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF)
51#define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000)
52#define QED_RDMA_ACK_DELAY (15)
53#define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL)
54#define QED_RDMA_MAX_CQS (RDMA_MAX_CQS)
55#define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS)
56/* Add 1 for header element */
57#define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
58#define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
59#define QED_RDMA_SRQ_WQE_ELEM_SIZE (16)
60#define QED_RDMA_MAX_SRQS (32 * 1024)
61
62#define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
63#define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
64
65enum qed_rdma_toggle_bit {
66 QED_RDMA_TOGGLE_BIT_CLEAR = 0,
67 QED_RDMA_TOGGLE_BIT_SET = 1
68};
69
70struct qed_bmap {
71 unsigned long *bitmap;
72 u32 max_count;
73};
74
75struct qed_rdma_info {
76 /* spin lock to protect bitmaps */
77 spinlock_t lock;
78
79 struct qed_bmap cq_map;
80 struct qed_bmap pd_map;
81 struct qed_bmap tid_map;
82 struct qed_bmap qp_map;
83 struct qed_bmap srq_map;
84 struct qed_bmap cid_map;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200[diff] [blame^]85 struct qed_bmap real_cid_map;
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]86 struct qed_bmap dpi_map;
87 struct qed_bmap toggle_bits;
88 struct qed_rdma_events events;
89 struct qed_rdma_device *dev;
90 struct qed_rdma_port *port;
91 u32 last_tid;
92 u8 num_cnqs;
93 u32 num_qps;
94 u32 num_mrs;
95 u16 queue_zone_base;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200[diff] [blame^]96 u16 max_queue_zones;
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]97 enum protocol_type proto;
98};
99
Ram Amranif1093942016-10-01 21:59:59 +0300[diff] [blame]100struct qed_rdma_qp {
101 struct regpair qp_handle;
102 struct regpair qp_handle_async;
103 u32 qpid;
104 u16 icid;
105 enum qed_roce_qp_state cur_state;
106 bool use_srq;
107 bool signal_all;
108 bool fmr_and_reserved_lkey;
109
110 bool incoming_rdma_read_en;
111 bool incoming_rdma_write_en;
112 bool incoming_atomic_en;
113 bool e2e_flow_control_en;
114
115 u16 pd;
116 u16 pkey;
117 u32 dest_qp;
118 u16 mtu;
119 u16 srq_id;
120 u8 traffic_class_tos;
121 u8 hop_limit_ttl;
122 u16 dpi;
123 u32 flow_label;
124 bool lb_indication;
125 u16 vlan_id;
126 u32 ack_timeout;
127 u8 retry_cnt;
128 u8 rnr_retry_cnt;
129 u8 min_rnr_nak_timer;
130 bool sqd_async;
131 union qed_gid sgid;
132 union qed_gid dgid;
133 enum roce_mode roce_mode;
134 u16 udp_src_port;
135 u8 stats_queue;
136
137 /* requeseter */
138 u8 max_rd_atomic_req;
139 u32 sq_psn;
140 u16 sq_cq_id;
141 u16 sq_num_pages;
142 dma_addr_t sq_pbl_ptr;
143 void *orq;
144 dma_addr_t orq_phys_addr;
145 u8 orq_num_pages;
146 bool req_offloaded;
147
148 /* responder */
149 u8 max_rd_atomic_resp;
150 u32 rq_psn;
151 u16 rq_cq_id;
152 u16 rq_num_pages;
153 dma_addr_t rq_pbl_ptr;
154 void *irq;
155 dma_addr_t irq_phys_addr;
156 u8 irq_num_pages;
157 bool resp_offloaded;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200[diff] [blame^]158 u32 cq_prod;
Ram Amranif1093942016-10-01 21:59:59 +0300[diff] [blame]159
160 u8 remote_mac_addr[6];
161 u8 local_mac_addr[6];
162
163 void *shared_queue;
164 dma_addr_t shared_queue_phys_addr;
165};
166
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame]167#if IS_ENABLED(CONFIG_QED_RDMA)
168void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200[diff] [blame^]169void qed_roce_async_event(struct qed_hwfn *p_hwfn,
170 u8 fw_event_code, union rdma_eqe_data *rdma_data);
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame]171void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
172 u8 connection_handle,
173 void *cookie,
174 dma_addr_t first_frag_addr,
175 bool b_last_fragment, bool b_last_packet);
176void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
177 u8 connection_handle,
178 void *cookie,
179 dma_addr_t first_frag_addr,
180 bool b_last_fragment, bool b_last_packet);
181void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
182 u8 connection_handle,
183 void *cookie,
184 dma_addr_t rx_buf_addr,
185 u16 data_length,
186 u8 data_length_error,
187 u16 parse_flags,
188 u16 vlan,
189 u32 src_mac_addr_hi,
190 u16 src_mac_addr_lo, bool b_last_packet);
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]191#else
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame]192static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {}
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200[diff] [blame^]193static inline void qed_roce_async_event(struct qed_hwfn *p_hwfn,
194 u8 fw_event_code,
195 union rdma_eqe_data *rdma_data) {}
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame]196static inline void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
197 u8 connection_handle,
198 void *cookie,
199 dma_addr_t first_frag_addr,
200 bool b_last_fragment,
201 bool b_last_packet) {}
202static inline void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
203 u8 connection_handle,
204 void *cookie,
205 dma_addr_t first_frag_addr,
206 bool b_last_fragment,
207 bool b_last_packet) {}
208static inline void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
209 u8 connection_handle,
210 void *cookie,
211 dma_addr_t rx_buf_addr,
212 u16 data_length,
213 u8 data_length_error,
214 u16 parse_flags,
215 u16 vlan,
216 u32 src_mac_addr_hi,
217 u16 src_mac_addr_lo,
218 bool b_last_packet) {}
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]219#endif
220#endif