blob: f3d751a342f00266f2604c0b4367abb9e8fa4958 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Mark Rutlandbff60792015-07-31 15:46:16 +010023 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010024 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000025 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070026 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000027 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000028 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010029 select EDAC_SUPPORT
Laura Abbottd4932f92014-10-09 15:26:44 -070030 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010031 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010032 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000033 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070034 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010035 select GENERIC_IRQ_PROBE
36 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010037 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010038 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070039 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010040 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000041 select GENERIC_STRNCPY_FROM_USER
42 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010043 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010044 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010046 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010047 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010048 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080049 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000050 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000051 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070053 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010054 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010055 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010056 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010057 select HAVE_CMPXCHG_LOCAL
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070058 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070059 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_DMA_API_DEBUG
61 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000062 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010063 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000064 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010065 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090066 select HAVE_FUNCTION_TRACER
67 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010068 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000071 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010073 select HAVE_PERF_REGS
74 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070075 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010076 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010077 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020078 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010079 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010080 select NO_BOOTMEM
81 select OF
82 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010083 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010084 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000085 select POWER_RESET
86 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010087 select RTC_LIB
88 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070089 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070090 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010091 help
92 ARM 64-bit (AArch64) Linux support.
93
94config 64BIT
95 def_bool y
96
97config ARCH_PHYS_ADDR_T_64BIT
98 def_bool y
99
100config MMU
101 def_bool y
102
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700103config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100104 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100105
106config STACKTRACE_SUPPORT
107 def_bool y
108
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100109config ILLEGAL_POINTER_VALUE
110 hex
111 default 0xdead000000000000
112
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100113config LOCKDEP_SUPPORT
114 def_bool y
115
116config TRACE_IRQFLAGS_SUPPORT
117 def_bool y
118
Will Deaconc209f792014-03-14 17:47:05 +0000119config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100120 def_bool y
121
Dave P Martin9fb74102015-07-24 16:37:48 +0100122config GENERIC_BUG
123 def_bool y
124 depends on BUG
125
126config GENERIC_BUG_RELATIVE_POINTERS
127 def_bool y
128 depends on GENERIC_BUG
129
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100130config GENERIC_HWEIGHT
131 def_bool y
132
133config GENERIC_CSUM
134 def_bool y
135
136config GENERIC_CALIBRATE_DELAY
137 def_bool y
138
Catalin Marinas19e76402014-02-27 12:09:22 +0000139config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100140 def_bool y
141
Steve Capper29e56942014-10-09 15:29:25 -0700142config HAVE_GENERIC_RCU_GUP
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145config ARCH_DMA_ADDR_T_64BIT
146 def_bool y
147
148config NEED_DMA_MAP_STATE
149 def_bool y
150
151config NEED_SG_DMA_LENGTH
152 def_bool y
153
Will Deacon4b3dc962015-05-29 18:28:44 +0100154config SMP
155 def_bool y
156
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100157config SWIOTLB
158 def_bool y
159
160config IOMMU_HELPER
161 def_bool SWIOTLB
162
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100163config KERNEL_MODE_NEON
164 def_bool y
165
Rob Herring92cc15f2014-04-18 17:19:59 -0500166config FIX_EARLYCON_MEM
167 def_bool y
168
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700169config PGTABLE_LEVELS
170 int
171 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
172 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
173 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
174 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
175
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100176source "init/Kconfig"
177
178source "kernel/Kconfig.freezer"
179
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100180menu "Platform selection"
181
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900182config ARCH_EXYNOS
183 bool
184 help
185 This enables support for Samsung Exynos SoC family
186
187config ARCH_EXYNOS7
188 bool "ARMv8 based Samsung Exynos7"
189 select ARCH_EXYNOS
190 select COMMON_CLK_SAMSUNG
191 select HAVE_S3C2410_WATCHDOG if WATCHDOG
192 select HAVE_S3C_RTC if RTC_CLASS
193 select PINCTRL
194 select PINCTRL_EXYNOS
195
196 help
197 This enables support for Samsung Exynos7 SoC family
198
Olof Johansson5118a6a2015-01-27 16:19:11 -0800199config ARCH_FSL_LS2085A
200 bool "Freescale LS2085A SOC"
201 help
202 This enables support for Freescale LS2085A SOC.
203
Bintian Wang85fe9462015-01-06 09:30:36 +0800204config ARCH_HISI
205 bool "Hisilicon SoC Family"
206 help
207 This enables support for Hisilicon ARMv8 SoC family
208
Eddie Huang4727a6f2015-12-01 10:14:00 +0100209config ARCH_MEDIATEK
210 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
211 select ARM_GIC
Yingjoe Chen0a233cd2015-03-06 14:24:50 +0800212 select PINCTRL
Eddie Huang4727a6f2015-12-01 10:14:00 +0100213 help
214 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
215
Abhimanyu Kapurd7f64a42013-10-15 21:11:09 -0700216config ARCH_QCOM
217 bool "Qualcomm Platforms"
218 select PINCTRL
219 help
220 This enables support for the ARMv8 based Qualcomm chipsets.
221
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700222config ARCH_SEATTLE
223 bool "AMD Seattle SoC Family"
224 help
225 This enables support for AMD Seattle SOC Family
226
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700227config ARCH_TEGRA
228 bool "NVIDIA Tegra SoC Family"
229 select ARCH_HAS_RESET_CONTROLLER
230 select ARCH_REQUIRE_GPIOLIB
231 select CLKDEV_LOOKUP
232 select CLKSRC_MMIO
233 select CLKSRC_OF
234 select GENERIC_CLOCKEVENTS
235 select HAVE_CLK
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700236 select PINCTRL
237 select RESET_CONTROLLER
238 help
239 This enables support for the NVIDIA Tegra SoC family.
240
241config ARCH_TEGRA_132_SOC
242 bool "NVIDIA Tegra132 SoC"
243 depends on ARCH_TEGRA
244 select PINCTRL_TEGRA124
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700245 select USB_ULPI if USB_PHY
246 select USB_ULPI_VIEWPORT if USB_PHY
247 help
248 Enable support for NVIDIA Tegra132 SoC, based on the Denver
249 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
250 but contains an NVIDIA Denver CPU complex in place of
251 Tegra124's "4+1" Cortex-A15 CPU complex.
252
Zhizhou Zhangc4bb7992015-03-11 02:27:08 +0000253config ARCH_SPRD
254 bool "Spreadtrum SoC platform"
255 help
256 Support for Spreadtrum ARM based SoCs
257
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530258config ARCH_THUNDER
259 bool "Cavium Inc. Thunder SoC Family"
260 help
261 This enables support for Cavium's Thunder Family of SoCs.
262
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100263config ARCH_VEXPRESS
264 bool "ARMv8 software model (Versatile Express)"
265 select ARCH_REQUIRE_GPIOLIB
266 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000267 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100268 select VEXPRESS_CONFIG
269 help
270 This enables support for the ARMv8 software model (Versatile
271 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100272
Vinayak Kale15942852013-04-24 10:06:57 +0100273config ARCH_XGENE
274 bool "AppliedMicro X-Gene SOC Family"
275 help
276 This enables support for AppliedMicro X-Gene SOC Family
277
Michal Simek5d1b79d2015-03-09 09:41:04 +0100278config ARCH_ZYNQMP
279 bool "Xilinx ZynqMP Family"
280 help
281 This enables support for Xilinx ZynqMP Family
282
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100283endmenu
284
285menu "Bus support"
286
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100287config PCI
288 bool "PCI support"
289 help
290 This feature enables support for PCI bus system. If you say Y
291 here, the kernel will include drivers and infrastructure code
292 to support PCI bus devices.
293
294config PCI_DOMAINS
295 def_bool PCI
296
297config PCI_DOMAINS_GENERIC
298 def_bool PCI
299
300config PCI_SYSCALL
301 def_bool PCI
302
303source "drivers/pci/Kconfig"
304source "drivers/pci/pcie/Kconfig"
305source "drivers/pci/hotplug/Kconfig"
306
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100307endmenu
308
309menu "Kernel Features"
310
Andre Przywarac0a01b82014-11-14 15:54:12 +0000311menu "ARM errata workarounds via the alternatives framework"
312
313config ARM64_ERRATUM_826319
314 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
315 default y
316 help
317 This option adds an alternative code sequence to work around ARM
318 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
319 AXI master interface and an L2 cache.
320
321 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
322 and is unable to accept a certain write via this interface, it will
323 not progress on read data presented on the read data channel and the
324 system can deadlock.
325
326 The workaround promotes data cache clean instructions to
327 data cache clean-and-invalidate.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
331
332 If unsure, say Y.
333
334config ARM64_ERRATUM_827319
335 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
336 default y
337 help
338 This option adds an alternative code sequence to work around ARM
339 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
340 master interface and an L2 cache.
341
342 Under certain conditions this erratum can cause a clean line eviction
343 to occur at the same time as another transaction to the same address
344 on the AMBA 5 CHI interface, which can cause data corruption if the
345 interconnect reorders the two transactions.
346
347 The workaround promotes data cache clean instructions to
348 data cache clean-and-invalidate.
349 Please note that this does not necessarily enable the workaround,
350 as it depends on the alternative framework, which will only patch
351 the kernel if an affected CPU is detected.
352
353 If unsure, say Y.
354
355config ARM64_ERRATUM_824069
356 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
357 default y
358 help
359 This option adds an alternative code sequence to work around ARM
360 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
361 to a coherent interconnect.
362
363 If a Cortex-A53 processor is executing a store or prefetch for
364 write instruction at the same time as a processor in another
365 cluster is executing a cache maintenance operation to the same
366 address, then this erratum might cause a clean cache line to be
367 incorrectly marked as dirty.
368
369 The workaround promotes data cache clean instructions to
370 data cache clean-and-invalidate.
371 Please note that this option does not necessarily enable the
372 workaround, as it depends on the alternative framework, which will
373 only patch the kernel if an affected CPU is detected.
374
375 If unsure, say Y.
376
377config ARM64_ERRATUM_819472
378 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
379 default y
380 help
381 This option adds an alternative code sequence to work around ARM
382 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
383 present when it is connected to a coherent interconnect.
384
385 If the processor is executing a load and store exclusive sequence at
386 the same time as a processor in another cluster is executing a cache
387 maintenance operation to the same address, then this erratum might
388 cause data corruption.
389
390 The workaround promotes data cache clean instructions to
391 data cache clean-and-invalidate.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
395
396 If unsure, say Y.
397
398config ARM64_ERRATUM_832075
399 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
400 default y
401 help
402 This option adds an alternative code sequence to work around ARM
403 erratum 832075 on Cortex-A57 parts up to r1p2.
404
405 Affected Cortex-A57 parts might deadlock when exclusive load/store
406 instructions to Write-Back memory are mixed with Device loads.
407
408 The workaround is to promote device loads to use Load-Acquire
409 semantics.
410 Please note that this does not necessarily enable the workaround,
411 as it depends on the alternative framework, which will only patch
412 the kernel if an affected CPU is detected.
413
414 If unsure, say Y.
415
Will Deacon905e8c52015-03-23 19:07:02 +0000416config ARM64_ERRATUM_845719
417 bool "Cortex-A53: 845719: a load might read incorrect data"
418 depends on COMPAT
419 default y
420 help
421 This option adds an alternative code sequence to work around ARM
422 erratum 845719 on Cortex-A53 parts up to r0p4.
423
424 When running a compat (AArch32) userspace on an affected Cortex-A53
425 part, a load at EL0 from a virtual address that matches the bottom 32
426 bits of the virtual address used by a recent load at (AArch64) EL1
427 might return incorrect data.
428
429 The workaround is to write the contextidr_el1 register on exception
430 return to a 32-bit task.
431 Please note that this does not necessarily enable the workaround,
432 as it depends on the alternative framework, which will only patch
433 the kernel if an affected CPU is detected.
434
435 If unsure, say Y.
436
Andre Przywarac0a01b82014-11-14 15:54:12 +0000437endmenu
438
439
Jungseok Leee41ceed2014-05-12 10:40:38 +0100440choice
441 prompt "Page size"
442 default ARM64_4K_PAGES
443 help
444 Page size (translation granule) configuration.
445
446config ARM64_4K_PAGES
447 bool "4KB"
448 help
449 This feature enables 4KB pages support.
450
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100451config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100452 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100453 help
454 This feature enables 64KB pages support (4KB by default)
455 allowing only two levels of page tables and faster TLB
456 look-up. AArch32 emulation is not available when this feature
457 is enabled.
458
Jungseok Leee41ceed2014-05-12 10:40:38 +0100459endchoice
460
461choice
462 prompt "Virtual address space size"
463 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
464 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
465 help
466 Allows choosing one of multiple possible virtual address
467 space sizes. The level of translation table is determined by
468 a combination of page size and virtual address space size.
469
470config ARM64_VA_BITS_39
471 bool "39-bit"
472 depends on ARM64_4K_PAGES
473
474config ARM64_VA_BITS_42
475 bool "42-bit"
476 depends on ARM64_64K_PAGES
477
Jungseok Leec79b954b2014-05-12 18:40:51 +0900478config ARM64_VA_BITS_48
479 bool "48-bit"
Jungseok Leec79b954b2014-05-12 18:40:51 +0900480
Jungseok Leee41ceed2014-05-12 10:40:38 +0100481endchoice
482
483config ARM64_VA_BITS
484 int
485 default 39 if ARM64_VA_BITS_39
486 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b954b2014-05-12 18:40:51 +0900487 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100488
Will Deacona8720132013-10-11 14:52:19 +0100489config CPU_BIG_ENDIAN
490 bool "Build big-endian kernel"
491 help
492 Say Y if you plan on running a kernel in big-endian mode.
493
Mark Brownf6e763b2014-03-04 07:51:17 +0000494config SCHED_MC
495 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000496 help
497 Multi-core scheduler support improves the CPU scheduler's decision
498 making when dealing with multi-core CPU chips at a cost of slightly
499 increased overhead in some places. If unsure say N here.
500
501config SCHED_SMT
502 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000503 help
504 Improves the CPU scheduler's decision making when dealing with
505 MultiThreading at a cost of slightly increased overhead in some
506 places. If unsure say N here.
507
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100508config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000509 int "Maximum number of CPUs (2-4096)"
510 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100511 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100512 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100513
Mark Rutland9327e2c2013-10-24 20:30:18 +0100514config HOTPLUG_CPU
515 bool "Support for hot-pluggable CPUs"
Mark Rutland9327e2c2013-10-24 20:30:18 +0100516 help
517 Say Y here to experiment with turning CPUs off and on. CPUs
518 can be controlled through /sys/devices/system/cpu.
519
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100520source kernel/Kconfig.preempt
521
522config HZ
523 int
524 default 100
525
526config ARCH_HAS_HOLES_MEMORYMODEL
527 def_bool y if SPARSEMEM
528
529config ARCH_SPARSEMEM_ENABLE
530 def_bool y
531 select SPARSEMEM_VMEMMAP_ENABLE
532
533config ARCH_SPARSEMEM_DEFAULT
534 def_bool ARCH_SPARSEMEM_ENABLE
535
536config ARCH_SELECT_MEMORY_MODEL
537 def_bool ARCH_SPARSEMEM_ENABLE
538
539config HAVE_ARCH_PFN_VALID
540 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
541
542config HW_PERF_EVENTS
543 bool "Enable hardware performance counter support for perf events"
544 depends on PERF_EVENTS
545 default y
546 help
547 Enable hardware performance counter support for perf events. If
548 disabled, perf events will use software events only.
549
Steve Capper084bd292013-04-10 13:48:00 +0100550config SYS_SUPPORTS_HUGETLBFS
551 def_bool y
552
553config ARCH_WANT_GENERAL_HUGETLB
554 def_bool y
555
556config ARCH_WANT_HUGE_PMD_SHARE
557 def_bool y if !ARM64_64K_PAGES
558
Steve Capperaf074842013-04-19 16:23:57 +0100559config HAVE_ARCH_TRANSPARENT_HUGEPAGE
560 def_bool y
561
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100562config ARCH_HAS_CACHE_LINE_SIZE
563 def_bool y
564
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100565source "mm/Kconfig"
566
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000567config SECCOMP
568 bool "Enable seccomp to safely compute untrusted bytecode"
569 ---help---
570 This kernel feature is useful for number crunching applications
571 that may need to compute untrusted bytecode during their
572 execution. By using pipes or other transports made available to
573 the process as file descriptors supporting the read/write
574 syscalls, it's possible to isolate those applications in
575 their own address space using seccomp. Once seccomp is
576 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
577 and the task is only allowed to execute a few safe syscalls
578 defined by each seccomp mode.
579
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000580config XEN_DOM0
581 def_bool y
582 depends on XEN
583
584config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700585 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000586 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000587 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000588 help
589 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
590
Steve Capperd03bb142013-04-25 15:19:21 +0100591config FORCE_MAX_ZONEORDER
592 int
593 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
594 default "11"
595
Will Deacon1b907f42014-11-20 16:51:10 +0000596menuconfig ARMV8_DEPRECATED
597 bool "Emulate deprecated/obsolete ARMv8 instructions"
598 depends on COMPAT
599 help
600 Legacy software support may require certain instructions
601 that have been deprecated or obsoleted in the architecture.
602
603 Enable this config to enable selective emulation of these
604 features.
605
606 If unsure, say Y
607
608if ARMV8_DEPRECATED
609
610config SWP_EMULATION
611 bool "Emulate SWP/SWPB instructions"
612 help
613 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
614 they are always undefined. Say Y here to enable software
615 emulation of these instructions for userspace using LDXR/STXR.
616
617 In some older versions of glibc [<=2.8] SWP is used during futex
618 trylock() operations with the assumption that the code will not
619 be preempted. This invalid assumption may be more likely to fail
620 with SWP emulation enabled, leading to deadlock of the user
621 application.
622
623 NOTE: when accessing uncached shared regions, LDXR/STXR rely
624 on an external transaction monitoring block called a global
625 monitor to maintain update atomicity. If your system does not
626 implement a global monitor, this option can cause programs that
627 perform SWP operations to uncached memory to deadlock.
628
629 If unsure, say Y
630
631config CP15_BARRIER_EMULATION
632 bool "Emulate CP15 Barrier instructions"
633 help
634 The CP15 barrier instructions - CP15ISB, CP15DSB, and
635 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
636 strongly recommended to use the ISB, DSB, and DMB
637 instructions instead.
638
639 Say Y here to enable software emulation of these
640 instructions for AArch32 userspace code. When this option is
641 enabled, CP15 barrier usage is traced which can help
642 identify software that needs updating.
643
644 If unsure, say Y
645
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000646config SETEND_EMULATION
647 bool "Emulate SETEND instruction"
648 help
649 The SETEND instruction alters the data-endianness of the
650 AArch32 EL0, and is deprecated in ARMv8.
651
652 Say Y here to enable software emulation of the instruction
653 for AArch32 userspace code.
654
655 Note: All the cpus on the system must have mixed endian support at EL0
656 for this feature to be enabled. If a new CPU - which doesn't support mixed
657 endian - is hotplugged in after this feature has been enabled, there could
658 be unexpected results in the applications.
659
660 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000661endif
662
Will Deacon0e4a0702015-07-27 15:54:13 +0100663menu "ARMv8.1 architectural features"
664
665config ARM64_HW_AFDBM
666 bool "Support for hardware updates of the Access and Dirty page flags"
667 default y
668 help
669 The ARMv8.1 architecture extensions introduce support for
670 hardware updates of the access and dirty information in page
671 table entries. When enabled in TCR_EL1 (HA and HD bits) on
672 capable processors, accesses to pages with PTE_AF cleared will
673 set this bit instead of raising an access flag fault.
674 Similarly, writes to read-only pages with the DBM bit set will
675 clear the read-only bit (AP[2]) instead of raising a
676 permission fault.
677
678 Kernels built with this configuration option enabled continue
679 to work on pre-ARMv8.1 hardware and the performance impact is
680 minimal. If unsure, say Y.
681
682config ARM64_PAN
683 bool "Enable support for Privileged Access Never (PAN)"
684 default y
685 help
686 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
687 prevents the kernel or hypervisor from accessing user-space (EL0)
688 memory directly.
689
690 Choosing this option will cause any unprotected (not using
691 copy_to_user et al) memory access to fail with a permission fault.
692
693 The feature is detected at runtime, and will remain as a 'nop'
694 instruction if the cpu does not implement the feature.
695
696config ARM64_LSE_ATOMICS
697 bool "Atomic instructions"
698 help
699 As part of the Large System Extensions, ARMv8.1 introduces new
700 atomic instructions that are designed specifically to scale in
701 very large systems.
702
703 Say Y here to make use of these instructions for the in-kernel
704 atomic routines. This incurs a small overhead on CPUs that do
705 not support these instructions and requires the kernel to be
706 built with binutils >= 2.25.
707
708endmenu
709
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100710endmenu
711
712menu "Boot options"
713
714config CMDLINE
715 string "Default kernel command string"
716 default ""
717 help
718 Provide a set of default command-line options at build time by
719 entering them here. As a minimum, you should specify the the
720 root device (e.g. root=/dev/nfs).
721
722config CMDLINE_FORCE
723 bool "Always use the default kernel command string"
724 help
725 Always use the default kernel command string, even if the boot
726 loader passes other arguments to the kernel.
727 This is useful if you cannot or don't want to change the
728 command-line options your boot loader passes to the kernel.
729
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200730config EFI_STUB
731 bool
732
Mark Salterf84d0272014-04-15 21:59:30 -0400733config EFI
734 bool "UEFI runtime support"
735 depends on OF && !CPU_BIG_ENDIAN
736 select LIBFDT
737 select UCS2_STRING
738 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200739 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200740 select EFI_STUB
741 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400742 default y
743 help
744 This option provides support for runtime services provided
745 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400746 clock, and platform reset). A UEFI stub is also provided to
747 allow the kernel to be booted as an EFI application. This
748 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400749
Yi Lid1ae8c02014-10-04 23:46:43 +0800750config DMI
751 bool "Enable support for SMBIOS (DMI) tables"
752 depends on EFI
753 default y
754 help
755 This enables SMBIOS/DMI feature for systems.
756
757 This option is only useful on systems that have UEFI firmware.
758 However, even with this option, the resultant kernel should
759 continue to boot on existing non-UEFI platforms.
760
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100761endmenu
762
763menu "Userspace binary formats"
764
765source "fs/Kconfig.binfmt"
766
767config COMPAT
768 bool "Kernel support for 32-bit EL0"
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000769 depends on !ARM64_64K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100770 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700771 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500772 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500773 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100774 help
775 This option enables support for a 32-bit EL0 running under a 64-bit
776 kernel at EL1. AArch32-specific components such as system calls,
777 the user helper functions, VFP support and the ptrace interface are
778 handled appropriately by the kernel.
779
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000780 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
781 will only be able to execute AArch32 binaries that were compiled with
782 64k aligned segments.
783
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100784 If you want to execute 32-bit userspace applications, say Y.
785
786config SYSVIPC_COMPAT
787 def_bool y
788 depends on COMPAT && SYSVIPC
789
790endmenu
791
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000792menu "Power management options"
793
794source "kernel/power/Kconfig"
795
796config ARCH_SUSPEND_POSSIBLE
797 def_bool y
798
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000799endmenu
800
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100801menu "CPU Power Management"
802
803source "drivers/cpuidle/Kconfig"
804
Rob Herring52e7e812014-02-24 11:27:57 +0900805source "drivers/cpufreq/Kconfig"
806
807endmenu
808
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100809source "net/Kconfig"
810
811source "drivers/Kconfig"
812
Mark Salterf84d0272014-04-15 21:59:30 -0400813source "drivers/firmware/Kconfig"
814
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000815source "drivers/acpi/Kconfig"
816
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100817source "fs/Kconfig"
818
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100819source "arch/arm64/kvm/Kconfig"
820
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100821source "arch/arm64/Kconfig.debug"
822
823source "security/Kconfig"
824
825source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800826if CRYPTO
827source "arch/arm64/crypto/Kconfig"
828endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100829
830source "lib/Kconfig"