blob: 9c2a60f01517843471aaaeb03bd1655c19166a87 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
Jiri Pirko6cf3c972016-07-05 11:27:39 +020042#include <linux/rhashtable.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020043#include <linux/bitops.h>
44#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010045#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020046#include <linux/dcbnl.h>
Jiri Pirko5e9c16c2016-07-04 08:23:04 +020047#include <linux/in6.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020048#include <net/switchdev.h>
49
Elad Raz3a49b4f2016-01-10 21:06:28 +010050#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020051#include "core.h"
52
53#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel99724c12016-07-04 08:23:14 +020054#define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
55
56#define MLXSW_SP_RFID_BASE 15360
57#define MLXSW_SP_RIF_MAX 800
Ido Schimmel7f71eb42015-12-15 16:03:37 +010058
Jiri Pirko0d65fc12015-12-03 12:12:28 +010059#define MLXSW_SP_LAG_MAX 64
60#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
Elad Raz53ae6282016-01-10 21:06:26 +010062#define MLXSW_SP_MID_MAX 7000
63
Ido Schimmel18f1e702016-02-26 17:32:31 +010064#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
65
Jiri Pirko53342022016-07-04 08:23:08 +020066#define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
67#define MLXSW_SP_LPM_TREE_MAX 22
68#define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
69
Jiri Pirko6b75c482016-07-04 08:23:09 +020070#define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
71
Ido Schimmel18f1e702016-02-26 17:32:31 +010072#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
73
Ido Schimmel1a198442016-04-06 17:10:02 +020074#define MLXSW_SP_BYTES_PER_CELL 96
75
76#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020077#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020078
Ido Schimmel9f7ec052016-04-06 17:10:14 +020079/* Maximum delay buffer needed in case of PAUSE frames, in cells.
80 * Assumes 100m cable and maximum MTU.
81 */
82#define MLXSW_SP_PAUSE_DELAY 612
83
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020084#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
85
86static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
87{
88 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
89 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
90}
91
Jiri Pirko56ade8f2015-10-16 14:01:37 +020092struct mlxsw_sp_port;
93
Jiri Pirko0d65fc12015-12-03 12:12:28 +010094struct mlxsw_sp_upper {
95 struct net_device *dev;
96 unsigned int ref_count;
97};
98
Ido Schimmeld0ec8752016-06-20 23:04:12 +020099struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +0200100 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100101 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200102 unsigned int ref_count;
103 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200104 struct mlxsw_sp_rif *r;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200105 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100106};
107
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200108struct mlxsw_sp_rif {
109 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200110 unsigned int ref_count;
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200111 struct mlxsw_sp_fid *f;
112 unsigned char addr[ETH_ALEN];
113 int mtu;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200114 u16 rif;
115};
116
Elad Raz3a49b4f2016-01-10 21:06:28 +0100117struct mlxsw_sp_mid {
118 struct list_head list;
119 unsigned char addr[ETH_ALEN];
120 u16 vid;
121 u16 mid;
122 unsigned int ref_count;
123};
124
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100125static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
126{
127 return MLXSW_SP_VFID_BASE + vfid;
128}
129
Ido Schimmelaac78a42015-12-15 16:03:42 +0100130static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
131{
132 return fid - MLXSW_SP_VFID_BASE;
133}
134
135static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
136{
Ido Schimmel99724c12016-07-04 08:23:14 +0200137 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
138}
139
140static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
141{
142 return fid >= MLXSW_SP_RFID_BASE;
143}
144
145static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
146{
147 return MLXSW_SP_RFID_BASE + rif;
Ido Schimmelaac78a42015-12-15 16:03:42 +0100148}
149
Jiri Pirko078f9c72016-04-14 18:19:19 +0200150struct mlxsw_sp_sb_pr {
151 enum mlxsw_reg_sbpr_mode mode;
152 u32 size;
153};
154
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200155struct mlxsw_cp_sb_occ {
156 u32 cur;
157 u32 max;
158};
159
Jiri Pirko078f9c72016-04-14 18:19:19 +0200160struct mlxsw_sp_sb_cm {
161 u32 min_buff;
162 u32 max_buff;
163 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200164 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200165};
166
167struct mlxsw_sp_sb_pm {
168 u32 min_buff;
169 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200170 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200171};
172
173#define MLXSW_SP_SB_POOL_COUNT 4
174#define MLXSW_SP_SB_TC_COUNT 8
175
176struct mlxsw_sp_sb {
177 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
178 struct {
179 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
180 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
181 } ports[MLXSW_PORT_MAX_PORTS];
182};
183
Jiri Pirko5e9c16c2016-07-04 08:23:04 +0200184#define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
185
186struct mlxsw_sp_prefix_usage {
187 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
188};
189
Jiri Pirko53342022016-07-04 08:23:08 +0200190enum mlxsw_sp_l3proto {
191 MLXSW_SP_L3_PROTO_IPV4,
192 MLXSW_SP_L3_PROTO_IPV6,
193};
194
195struct mlxsw_sp_lpm_tree {
196 u8 id; /* tree ID */
197 unsigned int ref_count;
198 enum mlxsw_sp_l3proto proto;
199 struct mlxsw_sp_prefix_usage prefix_usage;
200};
201
Jiri Pirko6b75c482016-07-04 08:23:09 +0200202struct mlxsw_sp_fib;
203
204struct mlxsw_sp_vr {
205 u16 id; /* virtual router ID */
206 bool used;
207 enum mlxsw_sp_l3proto proto;
208 u32 tb_id; /* kernel fib table id */
209 struct mlxsw_sp_lpm_tree *lpm_tree;
210 struct mlxsw_sp_fib *fib;
211};
212
Jiri Pirko53342022016-07-04 08:23:08 +0200213struct mlxsw_sp_router {
214 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
Jiri Pirko6b75c482016-07-04 08:23:09 +0200215 struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX];
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200216 struct rhashtable neigh_ht;
Yotam Gigic723c7352016-07-05 11:27:43 +0200217 struct {
218 struct delayed_work dw;
219 unsigned long interval; /* ms */
220 } neighs_update;
Jiri Pirko53342022016-07-04 08:23:08 +0200221};
222
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200223struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100224 struct {
225 struct list_head list;
Ido Schimmel99724c12016-07-04 08:23:14 +0200226 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200227 } vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100228 struct {
229 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200230 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100231 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200232 struct list_head fids; /* VLAN-aware bridge FIDs */
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200233 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200234 struct mlxsw_sp_port **ports;
235 struct mlxsw_core *core;
236 const struct mlxsw_bus_info *bus_info;
237 unsigned char base_mac[ETH_ALEN];
238 struct {
239 struct delayed_work dw;
240#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
241 unsigned int interval; /* ms */
242 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800243#define MLXSW_SP_MIN_AGEING_TIME 10
244#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200245#define MLXSW_SP_DEFAULT_AGEING_TIME 300
246 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100247 struct mlxsw_sp_upper master_bridge;
248 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100249 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200250 struct mlxsw_sp_sb sb;
Jiri Pirko53342022016-07-04 08:23:08 +0200251 struct mlxsw_sp_router router;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200252};
253
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100254static inline struct mlxsw_sp_upper *
255mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
256{
257 return &mlxsw_sp->lags[lag_id];
258}
259
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200260struct mlxsw_sp_port_pcpu_stats {
261 u64 rx_packets;
262 u64 rx_bytes;
263 u64 tx_packets;
264 u64 tx_bytes;
265 struct u64_stats_sync syncp;
266 u32 tx_dropped;
267};
268
269struct mlxsw_sp_port {
Jiri Pirko932762b2016-04-08 19:11:21 +0200270 struct mlxsw_core_port core_port; /* must be first */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200271 struct net_device *dev;
272 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
273 struct mlxsw_sp *mlxsw_sp;
274 u8 local_port;
275 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100276 u8 learning:1,
277 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100278 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100279 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100280 lagged:1,
281 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200282 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100283 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100284 struct {
285 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200286 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100287 u16 vid;
288 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200289 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200290 u8 tx_pause:1,
291 rx_pause:1;
292 } link;
293 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200294 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200295 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200296 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200297 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200298 struct {
299 u8 module;
300 u8 width;
301 u8 lane;
302 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200303 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100304 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100305 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200306 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100307 struct list_head vports_list;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200308};
309
Jiri Pirko7ce856a2016-07-04 08:23:12 +0200310struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
311void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
312
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200313static inline bool
314mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
315{
316 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
317}
318
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100319static inline struct mlxsw_sp_port *
320mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
321{
322 struct mlxsw_sp_port *mlxsw_sp_port;
323 u8 local_port;
324
325 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
326 lag_id, port_index);
327 mlxsw_sp_port = mlxsw_sp->ports[local_port];
328 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
329}
330
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100331static inline u16
332mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
333{
334 return mlxsw_sp_vport->vport.vid;
335}
336
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200337static inline bool
338mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
339{
340 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
341
342 return vid != 0;
343}
344
Ido Schimmel41b996c2016-06-20 23:04:17 +0200345static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
346 struct mlxsw_sp_fid *f)
347{
348 mlxsw_sp_vport->vport.f = f;
349}
350
351static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200352mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100353{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200354 return mlxsw_sp_vport->vport.f;
355}
356
357static inline struct net_device *
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +0200358mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel41b996c2016-06-20 23:04:17 +0200359{
360 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
361
Ido Schimmel56918b62016-06-20 23:04:18 +0200362 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100363}
364
365static inline struct mlxsw_sp_port *
366mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
367{
368 struct mlxsw_sp_port *mlxsw_sp_vport;
369
370 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
371 vport.list) {
372 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
373 return mlxsw_sp_vport;
374 }
375
376 return NULL;
377}
378
Ido Schimmelaac78a42015-12-15 16:03:42 +0100379static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200380mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
381 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100382{
383 struct mlxsw_sp_port *mlxsw_sp_vport;
384
385 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
386 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200387 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
388
Ido Schimmel56918b62016-06-20 23:04:18 +0200389 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100390 return mlxsw_sp_vport;
391 }
392
393 return NULL;
394}
395
Ido Schimmel701b1862016-07-04 08:23:16 +0200396static inline struct mlxsw_sp_fid *mlxsw_sp_fid_find(struct mlxsw_sp *mlxsw_sp,
397 u16 fid)
398{
399 struct mlxsw_sp_fid *f;
400
401 list_for_each_entry(f, &mlxsw_sp->fids, list)
402 if (f->fid == fid)
403 return f;
404
405 return NULL;
406}
407
408static inline struct mlxsw_sp_fid *
409mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp,
410 const struct net_device *br_dev)
411{
412 struct mlxsw_sp_fid *f;
413
414 list_for_each_entry(f, &mlxsw_sp->vfids.list, list)
415 if (f->dev == br_dev)
416 return f;
417
418 return NULL;
419}
420
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200421static inline struct mlxsw_sp_rif *
422mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
423 const struct net_device *dev)
424{
425 int i;
426
427 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
428 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
429 return mlxsw_sp->rifs[i];
430
431 return NULL;
432}
433
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200434enum mlxsw_sp_flood_table {
435 MLXSW_SP_FLOOD_TABLE_UC,
436 MLXSW_SP_FLOOD_TABLE_BM,
437};
438
439int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200440void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200441int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200442int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
443 unsigned int sb_index, u16 pool_index,
444 struct devlink_sb_pool_info *pool_info);
445int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
446 unsigned int sb_index, u16 pool_index, u32 size,
447 enum devlink_sb_threshold_type threshold_type);
448int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
449 unsigned int sb_index, u16 pool_index,
450 u32 *p_threshold);
451int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
452 unsigned int sb_index, u16 pool_index,
453 u32 threshold);
454int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
455 unsigned int sb_index, u16 tc_index,
456 enum devlink_sb_pool_type pool_type,
457 u16 *p_pool_index, u32 *p_threshold);
458int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
459 unsigned int sb_index, u16 tc_index,
460 enum devlink_sb_pool_type pool_type,
461 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200462int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
463 unsigned int sb_index);
464int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
465 unsigned int sb_index);
466int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
467 unsigned int sb_index, u16 pool_index,
468 u32 *p_cur, u32 *p_max);
469int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
470 unsigned int sb_index, u16 tc_index,
471 enum devlink_sb_pool_type pool_type,
472 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200473
474int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
475void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
476int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
477void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
478void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
479int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
480 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
481 u16 vid);
482int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
483 u16 vid_end, bool is_member, bool untagged);
484int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
485 u16 vid);
Ido Schimmele6060022016-06-20 23:04:11 +0200486int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200487 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100488void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100489int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200490int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200491int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
492 bool adding);
Ido Schimmel701b1862016-07-04 08:23:16 +0200493struct mlxsw_sp_fid *mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid);
494void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fid *f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +0200495void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
496 struct mlxsw_sp_rif *r);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200497int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
498 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
499 bool dwrr, u8 dwrr_weight);
500int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
501 u8 switch_prio, u8 tclass);
502int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200503 u8 *prio_tc, bool pause_en,
504 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200505int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
506 enum mlxsw_reg_qeec_hr hr, u8 index,
507 u8 next_index, u32 maxrate);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200508
Ido Schimmelf00817d2016-04-06 17:10:09 +0200509#ifdef CONFIG_MLXSW_SPECTRUM_DCB
510
511int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
512void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
513
514#else
515
516static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
517{
518 return 0;
519}
520
521static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
522{}
523
524#endif
525
Ido Schimmel464dce12016-07-02 11:00:15 +0200526int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
527void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko61c503f2016-07-04 08:23:11 +0200528int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port,
529 const struct switchdev_obj_ipv4_fib *fib4,
530 struct switchdev_trans *trans);
531int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port,
532 const struct switchdev_obj_ipv4_fib *fib4);
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200533int mlxsw_sp_router_neigh_construct(struct net_device *dev,
534 struct neighbour *n);
535void mlxsw_sp_router_neigh_destroy(struct net_device *dev,
536 struct neighbour *n);
Ido Schimmel464dce12016-07-02 11:00:15 +0200537
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200538#endif