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Russell King96f60e32012-08-15 13:59:49 +01001/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <drm/drmP.h>
Russell King98fb74f2015-06-15 10:17:57 +010010#include <drm/drm_plane_helper.h>
Russell King96f60e32012-08-15 13:59:49 +010011#include "armada_crtc.h"
12#include "armada_drm.h"
13#include "armada_fb.h"
14#include "armada_gem.h"
15#include "armada_hw.h"
16#include <drm/armada_drm.h>
17#include "armada_ioctlP.h"
Russell Kingc8a220c2016-05-17 13:51:08 +010018#include "armada_trace.h"
Russell King96f60e32012-08-15 13:59:49 +010019
Russell King28a2aeb2015-07-15 18:11:23 +010020struct armada_ovl_plane_properties {
Russell King96f60e32012-08-15 13:59:49 +010021 uint32_t colorkey_yr;
22 uint32_t colorkey_ug;
23 uint32_t colorkey_vb;
24#define K2R(val) (((val) >> 0) & 0xff)
25#define K2G(val) (((val) >> 8) & 0xff)
26#define K2B(val) (((val) >> 16) & 0xff)
27 int16_t brightness;
28 uint16_t contrast;
29 uint16_t saturation;
30 uint32_t colorkey_mode;
31};
32
Russell King28a2aeb2015-07-15 18:11:23 +010033struct armada_ovl_plane {
Russell King561f60b2015-07-15 18:11:24 +010034 struct armada_plane base;
Russell King96f60e32012-08-15 13:59:49 +010035 struct drm_framebuffer *old_fb;
36 uint32_t src_hw;
37 uint32_t dst_hw;
38 uint32_t dst_yx;
39 uint32_t ctrl0;
40 struct {
Russell King4a8506d2015-08-07 09:33:05 +010041 struct armada_plane_work work;
Russell King96f60e32012-08-15 13:59:49 +010042 struct armada_regs regs[13];
Russell King96f60e32012-08-15 13:59:49 +010043 } vbl;
Russell King28a2aeb2015-07-15 18:11:23 +010044 struct armada_ovl_plane_properties prop;
Russell King96f60e32012-08-15 13:59:49 +010045};
Russell King561f60b2015-07-15 18:11:24 +010046#define drm_to_armada_ovl_plane(p) \
47 container_of(p, struct armada_ovl_plane, base.base)
Russell King96f60e32012-08-15 13:59:49 +010048
49
50static void
Russell King28a2aeb2015-07-15 18:11:23 +010051armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
Russell King96f60e32012-08-15 13:59:49 +010052 struct armada_crtc *dcrtc)
53{
54 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
55 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
56 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
57
58 writel_relaxed(prop->brightness << 16 | prop->contrast,
59 dcrtc->base + LCD_SPU_CONTRAST);
60 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
61 writel_relaxed(prop->saturation << 16,
62 dcrtc->base + LCD_SPU_SATURATION);
63 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
64
65 spin_lock_irq(&dcrtc->irq_lock);
66 armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
67 CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
68 dcrtc->base + LCD_SPU_DMA_CTRL1);
69
70 armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
71 spin_unlock_irq(&dcrtc->irq_lock);
72}
73
Russell Kingfecfdb22015-07-15 18:11:24 +010074static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
75 struct drm_framebuffer *fb)
76{
77 struct drm_framebuffer *old_fb;
78
Russell King66377ef2015-07-15 18:11:24 +010079 old_fb = xchg(&dplane->old_fb, fb);
Russell Kingfecfdb22015-07-15 18:11:24 +010080
81 if (old_fb)
Russell King561f60b2015-07-15 18:11:24 +010082 armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
Russell Kingfecfdb22015-07-15 18:11:24 +010083}
84
Russell King96f60e32012-08-15 13:59:49 +010085/* === Plane support === */
Russell King4a8506d2015-08-07 09:33:05 +010086static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
87 struct armada_plane *plane, struct armada_plane_work *work)
Russell King96f60e32012-08-15 13:59:49 +010088{
Russell King4a8506d2015-08-07 09:33:05 +010089 struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base);
Russell King96f60e32012-08-15 13:59:49 +010090
Russell Kingc8a220c2016-05-17 13:51:08 +010091 trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base);
92
Russell King96f60e32012-08-15 13:59:49 +010093 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
Russell Kingfecfdb22015-07-15 18:11:24 +010094 armada_ovl_retire_fb(dplane, NULL);
Russell King96f60e32012-08-15 13:59:49 +010095}
96
Russell King96f60e32012-08-15 13:59:49 +010097static int
Russell King28a2aeb2015-07-15 18:11:23 +010098armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
Russell King96f60e32012-08-15 13:59:49 +010099 struct drm_framebuffer *fb,
100 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
101 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
102{
Russell King28a2aeb2015-07-15 18:11:23 +0100103 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100104 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King98fb74f2015-06-15 10:17:57 +0100105 struct drm_rect src = {
106 .x1 = src_x,
107 .y1 = src_y,
108 .x2 = src_x + src_w,
109 .y2 = src_y + src_h,
110 };
111 struct drm_rect dest = {
112 .x1 = crtc_x,
113 .y1 = crtc_y,
114 .x2 = crtc_x + crtc_w,
115 .y2 = crtc_y + crtc_h,
116 };
117 const struct drm_rect clip = {
118 .x2 = crtc->mode.hdisplay,
119 .y2 = crtc->mode.vdisplay,
120 };
Russell King96f60e32012-08-15 13:59:49 +0100121 uint32_t val, ctrl0;
122 unsigned idx = 0;
Russell King98fb74f2015-06-15 10:17:57 +0100123 bool visible;
Russell King96f60e32012-08-15 13:59:49 +0100124 int ret;
125
Russell Kingc8a220c2016-05-17 13:51:08 +0100126 trace_armada_ovl_plane_update(plane, crtc, fb,
127 crtc_x, crtc_y, crtc_w, crtc_h,
128 src_x, src_y, src_w, src_h);
129
Russell King98fb74f2015-06-15 10:17:57 +0100130 ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
Ville Syrjälä9b8b0132016-06-17 17:13:10 +0300131 BIT(DRM_ROTATE_0),
Russell King98fb74f2015-06-15 10:17:57 +0100132 0, INT_MAX, true, false, &visible);
133 if (ret)
134 return ret;
135
Russell King96f60e32012-08-15 13:59:49 +0100136 ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
137 CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
138 CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
139
140 /* Does the position/size result in nothing to display? */
Russell King98fb74f2015-06-15 10:17:57 +0100141 if (!visible)
Russell King96f60e32012-08-15 13:59:49 +0100142 ctrl0 &= ~CFG_DMA_ENA;
Russell King96f60e32012-08-15 13:59:49 +0100143
144 if (!dcrtc->plane) {
145 dcrtc->plane = plane;
146 armada_ovl_update_attr(&dplane->prop, dcrtc);
147 }
148
149 /* FIXME: overlay on an interlaced display */
150 /* Just updating the position/size? */
151 if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
Russell King98fb74f2015-06-15 10:17:57 +0100152 val = (drm_rect_height(&src) & 0xffff0000) |
153 drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100154 dplane->src_hw = val;
155 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100156
157 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100158 dplane->dst_hw = val;
159 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100160
161 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100162 dplane->dst_yx = val;
163 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100164
Russell King96f60e32012-08-15 13:59:49 +0100165 return 0;
166 } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
167 /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
168 armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
169 dcrtc->base + LCD_SPU_SRAM_PARA1);
170 }
171
Russell King4a8506d2015-08-07 09:33:05 +0100172 if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
173 armada_drm_plane_work_cancel(dcrtc, &dplane->base);
Russell King96f60e32012-08-15 13:59:49 +0100174
175 if (plane->fb != fb) {
176 struct armada_gem_object *obj = drm_fb_obj(fb);
Russell King73068ce2015-06-15 10:18:02 +0100177 uint32_t addr[3], pixel_format;
178 int i, num_planes, hsub;
Russell King96f60e32012-08-15 13:59:49 +0100179
180 /*
181 * Take a reference on the new framebuffer - we want to
182 * hold on to it while the hardware is displaying it.
183 */
184 drm_framebuffer_reference(fb);
185
Russell Kingfecfdb22015-07-15 18:11:24 +0100186 if (plane->fb)
187 armada_ovl_retire_fb(dplane, plane->fb);
Russell King96f60e32012-08-15 13:59:49 +0100188
Russell King98fb74f2015-06-15 10:17:57 +0100189 src_y = src.y1 >> 16;
190 src_x = src.x1 >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100191
Russell King73068ce2015-06-15 10:18:02 +0100192 pixel_format = fb->pixel_format;
193 hsub = drm_format_horz_chroma_subsampling(pixel_format);
194 num_planes = drm_format_num_planes(pixel_format);
195
196 /*
197 * Annoyingly, shifting a YUYV-format image by one pixel
198 * causes the U/V planes to toggle. Toggle the UV swap.
199 * (Unfortunately, this causes momentary colour flickering.)
200 */
201 if (src_x & (hsub - 1) && num_planes == 1)
202 ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
203
204 for (i = 0; i < num_planes; i++)
205 addr[i] = obj->dev_addr + fb->offsets[i] +
206 src_y * fb->pitches[i] +
207 src_x * drm_format_plane_cpp(pixel_format, i);
208 for (; i < ARRAY_SIZE(addr); i++)
209 addr[i] = 0;
210
211 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100212 LCD_SPU_DMA_START_ADDR_Y0);
Russell King73068ce2015-06-15 10:18:02 +0100213 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100214 LCD_SPU_DMA_START_ADDR_U0);
Russell King73068ce2015-06-15 10:18:02 +0100215 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100216 LCD_SPU_DMA_START_ADDR_V0);
Russell King73068ce2015-06-15 10:18:02 +0100217 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100218 LCD_SPU_DMA_START_ADDR_Y1);
Russell King73068ce2015-06-15 10:18:02 +0100219 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100220 LCD_SPU_DMA_START_ADDR_U1);
Russell King73068ce2015-06-15 10:18:02 +0100221 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100222 LCD_SPU_DMA_START_ADDR_V1);
223
224 val = fb->pitches[0] << 16 | fb->pitches[0];
225 armada_reg_queue_set(dplane->vbl.regs, idx, val,
226 LCD_SPU_DMA_PITCH_YC);
227 val = fb->pitches[1] << 16 | fb->pitches[2];
228 armada_reg_queue_set(dplane->vbl.regs, idx, val,
229 LCD_SPU_DMA_PITCH_UV);
230 }
231
Russell King98fb74f2015-06-15 10:17:57 +0100232 val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100233 if (dplane->src_hw != val) {
234 dplane->src_hw = val;
235 armada_reg_queue_set(dplane->vbl.regs, idx, val,
236 LCD_SPU_DMA_HPXL_VLN);
237 }
Russell King98fb74f2015-06-15 10:17:57 +0100238
239 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100240 if (dplane->dst_hw != val) {
241 dplane->dst_hw = val;
242 armada_reg_queue_set(dplane->vbl.regs, idx, val,
243 LCD_SPU_DZM_HPXL_VLN);
244 }
Russell King98fb74f2015-06-15 10:17:57 +0100245
246 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100247 if (dplane->dst_yx != val) {
248 dplane->dst_yx = val;
249 armada_reg_queue_set(dplane->vbl.regs, idx, val,
250 LCD_SPU_DMA_OVSA_HPXL_VLN);
251 }
Russell King98fb74f2015-06-15 10:17:57 +0100252
Russell King96f60e32012-08-15 13:59:49 +0100253 if (dplane->ctrl0 != ctrl0) {
254 dplane->ctrl0 = ctrl0;
255 armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
256 CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
257 CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
258 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
259 CFG_YUV2RGB) | CFG_DMA_ENA,
260 LCD_SPU_DMA_CTRL0);
261 }
262 if (idx) {
263 armada_reg_queue_end(dplane->vbl.regs, idx);
Russell King4a8506d2015-08-07 09:33:05 +0100264 armada_drm_plane_work_queue(dcrtc, &dplane->base,
265 &dplane->vbl.work);
Russell King96f60e32012-08-15 13:59:49 +0100266 }
267 return 0;
268}
269
Russell King28a2aeb2015-07-15 18:11:23 +0100270static int armada_ovl_plane_disable(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100271{
Russell King28a2aeb2015-07-15 18:11:23 +0100272 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100273 struct drm_framebuffer *fb;
274 struct armada_crtc *dcrtc;
275
Russell King561f60b2015-07-15 18:11:24 +0100276 if (!dplane->base.base.crtc)
Russell King96f60e32012-08-15 13:59:49 +0100277 return 0;
278
Russell King561f60b2015-07-15 18:11:24 +0100279 dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
Russell King96f60e32012-08-15 13:59:49 +0100280
Russell King4a8506d2015-08-07 09:33:05 +0100281 armada_drm_plane_work_cancel(dcrtc, &dplane->base);
Russell King58326802015-07-15 18:11:25 +0100282 armada_drm_crtc_plane_disable(dcrtc, plane);
Russell King96f60e32012-08-15 13:59:49 +0100283
Russell King4a8506d2015-08-07 09:33:05 +0100284 dcrtc->plane = NULL;
285 dplane->ctrl0 = 0;
286
Russell King66377ef2015-07-15 18:11:24 +0100287 fb = xchg(&dplane->old_fb, NULL);
Russell King96f60e32012-08-15 13:59:49 +0100288 if (fb)
289 drm_framebuffer_unreference(fb);
290
291 return 0;
292}
293
Russell King28a2aeb2015-07-15 18:11:23 +0100294static void armada_ovl_plane_destroy(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100295{
Russell King28a2aeb2015-07-15 18:11:23 +0100296 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King41dbb2d2015-06-15 10:13:30 +0100297
298 drm_plane_cleanup(plane);
299
300 kfree(dplane);
Russell King96f60e32012-08-15 13:59:49 +0100301}
302
Russell King28a2aeb2015-07-15 18:11:23 +0100303static int armada_ovl_plane_set_property(struct drm_plane *plane,
Russell King96f60e32012-08-15 13:59:49 +0100304 struct drm_property *property, uint64_t val)
305{
306 struct armada_private *priv = plane->dev->dev_private;
Russell King28a2aeb2015-07-15 18:11:23 +0100307 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100308 bool update_attr = false;
309
310 if (property == priv->colorkey_prop) {
311#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
312 dplane->prop.colorkey_yr = CCC(K2R(val));
313 dplane->prop.colorkey_ug = CCC(K2G(val));
314 dplane->prop.colorkey_vb = CCC(K2B(val));
315#undef CCC
316 update_attr = true;
317 } else if (property == priv->colorkey_min_prop) {
318 dplane->prop.colorkey_yr &= ~0x00ff0000;
319 dplane->prop.colorkey_yr |= K2R(val) << 16;
320 dplane->prop.colorkey_ug &= ~0x00ff0000;
321 dplane->prop.colorkey_ug |= K2G(val) << 16;
322 dplane->prop.colorkey_vb &= ~0x00ff0000;
323 dplane->prop.colorkey_vb |= K2B(val) << 16;
324 update_attr = true;
325 } else if (property == priv->colorkey_max_prop) {
326 dplane->prop.colorkey_yr &= ~0xff000000;
327 dplane->prop.colorkey_yr |= K2R(val) << 24;
328 dplane->prop.colorkey_ug &= ~0xff000000;
329 dplane->prop.colorkey_ug |= K2G(val) << 24;
330 dplane->prop.colorkey_vb &= ~0xff000000;
331 dplane->prop.colorkey_vb |= K2B(val) << 24;
332 update_attr = true;
333 } else if (property == priv->colorkey_val_prop) {
334 dplane->prop.colorkey_yr &= ~0x0000ff00;
335 dplane->prop.colorkey_yr |= K2R(val) << 8;
336 dplane->prop.colorkey_ug &= ~0x0000ff00;
337 dplane->prop.colorkey_ug |= K2G(val) << 8;
338 dplane->prop.colorkey_vb &= ~0x0000ff00;
339 dplane->prop.colorkey_vb |= K2B(val) << 8;
340 update_attr = true;
341 } else if (property == priv->colorkey_alpha_prop) {
342 dplane->prop.colorkey_yr &= ~0x000000ff;
343 dplane->prop.colorkey_yr |= K2R(val);
344 dplane->prop.colorkey_ug &= ~0x000000ff;
345 dplane->prop.colorkey_ug |= K2G(val);
346 dplane->prop.colorkey_vb &= ~0x000000ff;
347 dplane->prop.colorkey_vb |= K2B(val);
348 update_attr = true;
349 } else if (property == priv->colorkey_mode_prop) {
350 dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
351 dplane->prop.colorkey_mode |= CFG_CKMODE(val);
352 update_attr = true;
353 } else if (property == priv->brightness_prop) {
354 dplane->prop.brightness = val - 256;
355 update_attr = true;
356 } else if (property == priv->contrast_prop) {
357 dplane->prop.contrast = val;
358 update_attr = true;
359 } else if (property == priv->saturation_prop) {
360 dplane->prop.saturation = val;
361 update_attr = true;
362 }
363
Russell King561f60b2015-07-15 18:11:24 +0100364 if (update_attr && dplane->base.base.crtc)
Russell King96f60e32012-08-15 13:59:49 +0100365 armada_ovl_update_attr(&dplane->prop,
Russell King561f60b2015-07-15 18:11:24 +0100366 drm_to_armada_crtc(dplane->base.base.crtc));
Russell King96f60e32012-08-15 13:59:49 +0100367
368 return 0;
369}
370
Russell King28a2aeb2015-07-15 18:11:23 +0100371static const struct drm_plane_funcs armada_ovl_plane_funcs = {
372 .update_plane = armada_ovl_plane_update,
373 .disable_plane = armada_ovl_plane_disable,
374 .destroy = armada_ovl_plane_destroy,
375 .set_property = armada_ovl_plane_set_property,
Russell King96f60e32012-08-15 13:59:49 +0100376};
377
Russell King28a2aeb2015-07-15 18:11:23 +0100378static const uint32_t armada_ovl_formats[] = {
Russell King96f60e32012-08-15 13:59:49 +0100379 DRM_FORMAT_UYVY,
380 DRM_FORMAT_YUYV,
381 DRM_FORMAT_YUV420,
382 DRM_FORMAT_YVU420,
383 DRM_FORMAT_YUV422,
384 DRM_FORMAT_YVU422,
385 DRM_FORMAT_VYUY,
386 DRM_FORMAT_YVYU,
387 DRM_FORMAT_ARGB8888,
388 DRM_FORMAT_ABGR8888,
389 DRM_FORMAT_XRGB8888,
390 DRM_FORMAT_XBGR8888,
391 DRM_FORMAT_RGB888,
392 DRM_FORMAT_BGR888,
393 DRM_FORMAT_ARGB1555,
394 DRM_FORMAT_ABGR1555,
395 DRM_FORMAT_RGB565,
396 DRM_FORMAT_BGR565,
397};
398
399static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
400 { CKMODE_DISABLE, "disabled" },
401 { CKMODE_Y, "Y component" },
402 { CKMODE_U, "U component" },
403 { CKMODE_V, "V component" },
404 { CKMODE_RGB, "RGB" },
405 { CKMODE_R, "R component" },
406 { CKMODE_G, "G component" },
407 { CKMODE_B, "B component" },
408};
409
410static int armada_overlay_create_properties(struct drm_device *dev)
411{
412 struct armada_private *priv = dev->dev_private;
413
414 if (priv->colorkey_prop)
415 return 0;
416
417 priv->colorkey_prop = drm_property_create_range(dev, 0,
418 "colorkey", 0, 0xffffff);
419 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
420 "colorkey_min", 0, 0xffffff);
421 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
422 "colorkey_max", 0, 0xffffff);
423 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
424 "colorkey_val", 0, 0xffffff);
425 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
426 "colorkey_alpha", 0, 0xffffff);
427 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
428 "colorkey_mode",
429 armada_drm_colorkey_enum_list,
430 ARRAY_SIZE(armada_drm_colorkey_enum_list));
431 priv->brightness_prop = drm_property_create_range(dev, 0,
432 "brightness", 0, 256 + 255);
433 priv->contrast_prop = drm_property_create_range(dev, 0,
434 "contrast", 0, 0x7fff);
435 priv->saturation_prop = drm_property_create_range(dev, 0,
436 "saturation", 0, 0x7fff);
437
438 if (!priv->colorkey_prop)
439 return -ENOMEM;
440
441 return 0;
442}
443
444int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
445{
446 struct armada_private *priv = dev->dev_private;
447 struct drm_mode_object *mobj;
Russell King28a2aeb2015-07-15 18:11:23 +0100448 struct armada_ovl_plane *dplane;
Russell King96f60e32012-08-15 13:59:49 +0100449 int ret;
450
451 ret = armada_overlay_create_properties(dev);
452 if (ret)
453 return ret;
454
455 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
456 if (!dplane)
457 return -ENOMEM;
458
Russell King5740d272015-07-15 18:11:25 +0100459 ret = armada_drm_plane_init(&dplane->base);
460 if (ret) {
461 kfree(dplane);
462 return ret;
463 }
464
Russell King4a8506d2015-08-07 09:33:05 +0100465 dplane->vbl.work.fn = armada_ovl_plane_work;
Russell King96f60e32012-08-15 13:59:49 +0100466
Russell King561f60b2015-07-15 18:11:24 +0100467 ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
Russell Kingd563c242015-07-15 18:11:24 +0100468 &armada_ovl_plane_funcs,
469 armada_ovl_formats,
470 ARRAY_SIZE(armada_ovl_formats),
Ville Syrjäläb0b3b792015-12-09 16:19:55 +0200471 DRM_PLANE_TYPE_OVERLAY, NULL);
Russell King28a2aeb2015-07-15 18:11:23 +0100472 if (ret) {
473 kfree(dplane);
474 return ret;
475 }
Russell King96f60e32012-08-15 13:59:49 +0100476
477 dplane->prop.colorkey_yr = 0xfefefe00;
478 dplane->prop.colorkey_ug = 0x01010100;
479 dplane->prop.colorkey_vb = 0x01010100;
480 dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
481 dplane->prop.brightness = 0;
482 dplane->prop.contrast = 0x4000;
483 dplane->prop.saturation = 0x4000;
484
Russell King561f60b2015-07-15 18:11:24 +0100485 mobj = &dplane->base.base.base;
Russell King96f60e32012-08-15 13:59:49 +0100486 drm_object_attach_property(mobj, priv->colorkey_prop,
487 0x0101fe);
488 drm_object_attach_property(mobj, priv->colorkey_min_prop,
489 0x0101fe);
490 drm_object_attach_property(mobj, priv->colorkey_max_prop,
491 0x0101fe);
492 drm_object_attach_property(mobj, priv->colorkey_val_prop,
493 0x0101fe);
494 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
495 0x000000);
496 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
497 CKMODE_RGB);
498 drm_object_attach_property(mobj, priv->brightness_prop, 256);
499 drm_object_attach_property(mobj, priv->contrast_prop,
500 dplane->prop.contrast);
501 drm_object_attach_property(mobj, priv->saturation_prop,
502 dplane->prop.saturation);
503
504 return 0;
505}