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Chunfeng Yundf2069a2016-10-19 10:28:23 +08001/*
2 * Copyright (C) 2016 MediaTek Inc.
3 *
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/dma-mapping.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080024#include <linux/pinctrl/consumer.h>
Chunfeng Yundf2069a2016-10-19 10:28:23 +080025#include <linux/platform_device.h>
26
27#include "mtu3.h"
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080028#include "mtu3_dr.h"
Chunfeng Yundf2069a2016-10-19 10:28:23 +080029
30/* u2-port0 should be powered on and enabled; */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080031int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
Chunfeng Yundf2069a2016-10-19 10:28:23 +080032{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080033 void __iomem *ibase = ssusb->ippc_base;
Chunfeng Yundf2069a2016-10-19 10:28:23 +080034 u32 value, check_val;
35 int ret;
36
37 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
38 SSUSB_REF_RST_B_STS;
39
40 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
41 (check_val == (value & check_val)), 100, 20000);
42 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080043 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080044 return ret;
45 }
46
47 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
48 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
49 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080050 dev_err(ssusb->dev, "mac2 clock is not stable\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080051 return ret;
52 }
53
54 return 0;
55}
56
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080057static int ssusb_phy_init(struct ssusb_mtk *ssusb)
58{
59 int i;
60 int ret;
61
62 for (i = 0; i < ssusb->num_phys; i++) {
63 ret = phy_init(ssusb->phys[i]);
64 if (ret)
65 goto exit_phy;
66 }
67 return 0;
68
69exit_phy:
70 for (; i > 0; i--)
71 phy_exit(ssusb->phys[i - 1]);
72
73 return ret;
74}
75
76static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
77{
78 int i;
79
80 for (i = 0; i < ssusb->num_phys; i++)
81 phy_exit(ssusb->phys[i]);
82
83 return 0;
84}
85
86static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
87{
88 int i;
89 int ret;
90
91 for (i = 0; i < ssusb->num_phys; i++) {
92 ret = phy_power_on(ssusb->phys[i]);
93 if (ret)
94 goto power_off_phy;
95 }
96 return 0;
97
98power_off_phy:
99 for (; i > 0; i--)
100 phy_power_off(ssusb->phys[i - 1]);
101
102 return ret;
103}
104
105static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
106{
107 unsigned int i;
108
109 for (i = 0; i < ssusb->num_phys; i++)
110 phy_power_off(ssusb->phys[i]);
111}
112
113static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800114{
115 int ret = 0;
116
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800117 ret = regulator_enable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800118 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800119 dev_err(ssusb->dev, "failed to enable vusb33\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800120 goto vusb33_err;
121 }
122
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800123 ret = clk_prepare_enable(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800124 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800125 dev_err(ssusb->dev, "failed to enable sys_clk\n");
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800126 goto sys_clk_err;
127 }
128
129 ret = clk_prepare_enable(ssusb->ref_clk);
130 if (ret) {
131 dev_err(ssusb->dev, "failed to enable ref_clk\n");
132 goto ref_clk_err;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800133 }
134
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800135 ret = ssusb_phy_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800136 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800137 dev_err(ssusb->dev, "failed to init phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800138 goto phy_init_err;
139 }
140
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800141 ret = ssusb_phy_power_on(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800142 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800143 dev_err(ssusb->dev, "failed to power on phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800144 goto phy_err;
145 }
146
147 return 0;
148
149phy_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800150 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800151phy_init_err:
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800152 clk_disable_unprepare(ssusb->ref_clk);
153ref_clk_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800154 clk_disable_unprepare(ssusb->sys_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800155sys_clk_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800156 regulator_disable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800157vusb33_err:
158
159 return ret;
160}
161
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800162static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800163{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800164 clk_disable_unprepare(ssusb->sys_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800165 clk_disable_unprepare(ssusb->ref_clk);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800166 regulator_disable(ssusb->vusb33);
167 ssusb_phy_power_off(ssusb);
168 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800169}
170
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800171static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800172{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800173 /* reset whole ip (xhci & u3d) */
174 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800175 udelay(1);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800176 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800177}
178
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800179static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
180{
181 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
182
183 otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
184 if (IS_ERR(otg_sx->id_pinctrl)) {
185 dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
186 return PTR_ERR(otg_sx->id_pinctrl);
187 }
188
189 otg_sx->id_float =
190 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
191 if (IS_ERR(otg_sx->id_float)) {
192 dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
193 return PTR_ERR(otg_sx->id_float);
194 }
195
196 otg_sx->id_ground =
197 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
198 if (IS_ERR(otg_sx->id_ground)) {
199 dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
200 return PTR_ERR(otg_sx->id_ground);
201 }
202
203 return 0;
204}
205
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800206static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800207{
208 struct device_node *node = pdev->dev.of_node;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800209 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800210 struct device *dev = &pdev->dev;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800211 struct regulator *vbus;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800212 struct resource *res;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800213 int i;
214 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800215
Chunfeng Yun5cbf2d62017-01-18 14:08:22 +0800216 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
217 if (IS_ERR(ssusb->vusb33)) {
218 dev_err(dev, "failed to get vusb33\n");
219 return PTR_ERR(ssusb->vusb33);
220 }
221
222 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
223 if (IS_ERR(ssusb->sys_clk)) {
224 dev_err(dev, "failed to get sys clock\n");
225 return PTR_ERR(ssusb->sys_clk);
226 }
227
Chunfeng Yunca12cb72017-02-07 14:13:32 +0800228 /*
229 * reference clock is usually a "fixed-clock", make it optional
230 * for backward compatibility and ignore the error if it does
231 * not exist.
232 */
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800233 ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
234 if (IS_ERR(ssusb->ref_clk)) {
Chunfeng Yunca12cb72017-02-07 14:13:32 +0800235 if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER)
236 return -EPROBE_DEFER;
237
238 ssusb->ref_clk = NULL;
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800239 }
240
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800241 ssusb->num_phys = of_count_phandle_with_args(node,
242 "phys", "#phy-cells");
243 if (ssusb->num_phys > 0) {
244 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
245 sizeof(*ssusb->phys), GFP_KERNEL);
246 if (!ssusb->phys)
247 return -ENOMEM;
248 } else {
249 ssusb->num_phys = 0;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800250 }
251
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800252 for (i = 0; i < ssusb->num_phys; i++) {
253 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
254 if (IS_ERR(ssusb->phys[i])) {
255 dev_err(dev, "failed to get phy-%d\n", i);
256 return PTR_ERR(ssusb->phys[i]);
257 }
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800258 }
259
260 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800261 ssusb->ippc_base = devm_ioremap_resource(dev, res);
262 if (IS_ERR(ssusb->ippc_base)) {
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800263 dev_err(dev, "failed to map memory for ippc\n");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800264 return PTR_ERR(ssusb->ippc_base);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800265 }
266
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800267 ssusb->dr_mode = usb_get_dr_mode(dev);
268 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
269 dev_err(dev, "dr_mode is error\n");
270 return -EINVAL;
271 }
272
273 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
274 return 0;
275
276 /* if host role is supported */
277 ret = ssusb_wakeup_of_property_parse(ssusb, node);
278 if (ret)
279 return ret;
280
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800281 if (ssusb->dr_mode != USB_DR_MODE_OTG)
282 return 0;
283
284 /* if dual-role mode is supported */
285 vbus = devm_regulator_get(&pdev->dev, "vbus");
286 if (IS_ERR(vbus)) {
287 dev_err(dev, "failed to get vbus\n");
288 return PTR_ERR(vbus);
289 }
290 otg_sx->vbus = vbus;
291
292 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
293 otg_sx->manual_drd_enabled =
294 of_property_read_bool(node, "enable-manual-drd");
295
296 if (of_property_read_bool(node, "extcon")) {
297 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
298 if (IS_ERR(otg_sx->edev)) {
299 dev_err(ssusb->dev, "couldn't get extcon device\n");
300 return -EPROBE_DEFER;
301 }
302 if (otg_sx->manual_drd_enabled) {
303 ret = get_iddig_pinctrl(ssusb);
304 if (ret)
305 return ret;
306 }
307 }
308
309 dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n",
310 ssusb->dr_mode, otg_sx->is_u3_drd);
311
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800312 return 0;
313}
314
315static int mtu3_probe(struct platform_device *pdev)
316{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800317 struct device_node *node = pdev->dev.of_node;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800318 struct device *dev = &pdev->dev;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800319 struct ssusb_mtk *ssusb;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800320 int ret = -ENOMEM;
321
322 /* all elements are set to ZERO as default value */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800323 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
324 if (!ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800325 return -ENOMEM;
326
327 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
328 if (ret) {
329 dev_err(dev, "No suitable DMA config available\n");
330 return -ENOTSUPP;
331 }
332
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800333 platform_set_drvdata(pdev, ssusb);
334 ssusb->dev = dev;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800335
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800336 ret = get_ssusb_rscs(pdev, ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800337 if (ret)
338 return ret;
339
340 /* enable power domain */
341 pm_runtime_enable(dev);
342 pm_runtime_get_sync(dev);
343 device_enable_async_suspend(dev);
344
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800345 ret = ssusb_rscs_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800346 if (ret)
347 goto comm_init_err;
348
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800349 ssusb_ip_sw_reset(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800350
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800351 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
352 ssusb->dr_mode = USB_DR_MODE_HOST;
353 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
354 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
355
356 /* default as host */
357 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
358
359 switch (ssusb->dr_mode) {
360 case USB_DR_MODE_PERIPHERAL:
361 ret = ssusb_gadget_init(ssusb);
362 if (ret) {
363 dev_err(dev, "failed to initialize gadget\n");
364 goto comm_exit;
365 }
366 break;
367 case USB_DR_MODE_HOST:
368 ret = ssusb_host_init(ssusb, node);
369 if (ret) {
370 dev_err(dev, "failed to initialize host\n");
371 goto comm_exit;
372 }
373 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800374 case USB_DR_MODE_OTG:
375 ret = ssusb_gadget_init(ssusb);
376 if (ret) {
377 dev_err(dev, "failed to initialize gadget\n");
378 goto comm_exit;
379 }
380
381 ret = ssusb_host_init(ssusb, node);
382 if (ret) {
383 dev_err(dev, "failed to initialize host\n");
384 goto gadget_exit;
385 }
386
387 ssusb_otg_switch_init(ssusb);
388 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800389 default:
390 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
391 ret = -EINVAL;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800392 goto comm_exit;
393 }
394
395 return 0;
396
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800397gadget_exit:
398 ssusb_gadget_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800399comm_exit:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800400 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800401comm_init_err:
402 pm_runtime_put_sync(dev);
403 pm_runtime_disable(dev);
404
405 return ret;
406}
407
408static int mtu3_remove(struct platform_device *pdev)
409{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800410 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800411
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800412 switch (ssusb->dr_mode) {
413 case USB_DR_MODE_PERIPHERAL:
414 ssusb_gadget_exit(ssusb);
415 break;
416 case USB_DR_MODE_HOST:
417 ssusb_host_exit(ssusb);
418 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800419 case USB_DR_MODE_OTG:
420 ssusb_otg_switch_exit(ssusb);
421 ssusb_gadget_exit(ssusb);
422 ssusb_host_exit(ssusb);
423 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800424 default:
425 return -EINVAL;
426 }
427
428 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800429 pm_runtime_put_sync(&pdev->dev);
430 pm_runtime_disable(&pdev->dev);
431
432 return 0;
433}
434
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800435/*
436 * when support dual-role mode, we reject suspend when
437 * it works as device mode;
438 */
439static int __maybe_unused mtu3_suspend(struct device *dev)
440{
441 struct platform_device *pdev = to_platform_device(dev);
442 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
443
444 dev_dbg(dev, "%s\n", __func__);
445
446 /* REVISIT: disconnect it for only device mode? */
447 if (!ssusb->is_host)
448 return 0;
449
450 ssusb_host_disable(ssusb, true);
451 ssusb_phy_power_off(ssusb);
452 clk_disable_unprepare(ssusb->sys_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800453 clk_disable_unprepare(ssusb->ref_clk);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800454 ssusb_wakeup_enable(ssusb);
455
456 return 0;
457}
458
459static int __maybe_unused mtu3_resume(struct device *dev)
460{
461 struct platform_device *pdev = to_platform_device(dev);
462 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
463
464 dev_dbg(dev, "%s\n", __func__);
465
466 if (!ssusb->is_host)
467 return 0;
468
469 ssusb_wakeup_disable(ssusb);
470 clk_prepare_enable(ssusb->sys_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800471 clk_prepare_enable(ssusb->ref_clk);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800472 ssusb_phy_power_on(ssusb);
473 ssusb_host_enable(ssusb);
474
475 return 0;
476}
477
478static const struct dev_pm_ops mtu3_pm_ops = {
479 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
480};
481
482#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
483
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800484#ifdef CONFIG_OF
485
486static const struct of_device_id mtu3_of_match[] = {
487 {.compatible = "mediatek,mt8173-mtu3",},
488 {},
489};
490
491MODULE_DEVICE_TABLE(of, mtu3_of_match);
492
493#endif
494
495static struct platform_driver mtu3_driver = {
496 .probe = mtu3_probe,
497 .remove = mtu3_remove,
498 .driver = {
499 .name = MTU3_DRIVER_NAME,
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800500 .pm = DEV_PM_OPS,
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800501 .of_match_table = of_match_ptr(mtu3_of_match),
502 },
503};
504module_platform_driver(mtu3_driver);
505
506MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
507MODULE_LICENSE("GPL v2");
508MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");