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gerrit-public.fairphone.software / kernel / msm-5.4 / d0ce2d170585b7061a08af061d64ebb08c6782dd / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: 5d81c5360b9cc5aabc16f6c9fd25df874f1094c7 [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19#include "ar9003_eeprom.h"
20
21#define COMP_HDR_LEN 4
22#define COMP_CKSUM_LEN 2
23
24#define AR_CH0_TOP (0x00016288)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]25#define AR_CH0_TOP_XPABIASLVL (0x300)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]26#define AR_CH0_TOP_XPABIASLVL_S (8)
27
28#define AR_CH0_THERM (0x00016290)
Vasanthakumar Thiagarajan52a0e242010-11-10 05:03:11 -0800[diff] [blame]29#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31#define AR_CH0_THERM_XPASHORT2GND 0x4
32#define AR_CH0_THERM_XPASHORT2GND_S 2
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]33
34#define AR_SWITCH_TABLE_COM_ALL (0xffff)
35#define AR_SWITCH_TABLE_COM_ALL_S (0)
36
37#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38#define AR_SWITCH_TABLE_COM2_ALL_S (0)
39
40#define AR_SWITCH_TABLE_ALL (0xfff)
41#define AR_SWITCH_TABLE_ALL_S (0)
42
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]43#define LE16(x) __constant_cpu_to_le16(x)
44#define LE32(x) __constant_cpu_to_le32(x)
45
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]46/* Local defines to distinguish between extension and control CTL's */
47#define EXT_ADDITIVE (0x8000)
48#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53#define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54#define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55#define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
56
57#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
59
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]60#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
61
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame^]62#define EEPROM_DATA_LEN_9485 1088
63
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]64static int ar9003_hw_power_interpolate(int32_t x,
65 int32_t *px, int32_t *py, u_int16_t np);
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]66
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]67static const struct ar9300_eeprom ar9300_default = {
68 .eepromVersion = 2,
69 .templateVersion = 2,
70 .macAddr = {1, 2, 3, 4, 5, 6},
71 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
72 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
73 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]74 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]75 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
76 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]77 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]78 .eepMisc = 0,
79 },
80 .rfSilent = 0,
81 .blueToothOptions = 0,
82 .deviceCap = 0,
83 .deviceType = 5, /* takes lower byte in eeprom location */
84 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
85 .params_for_tuning_caps = {0, 0},
86 .featureEnable = 0x0c,
87 /*
88 * bit0 - enable tx temp comp - disabled
89 * bit1 - enable tx volt comp - disabled
90 * bit2 - enable fastClock - enabled
91 * bit3 - enable doubling - enabled
92 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]93 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]94 */
95 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
96 .eepromWriteEnableGpio = 3,
97 .wlanDisableGpio = 0,
98 .wlanLedGpio = 8,
99 .rxBandSelectGpio = 0xff,
100 .txrxgain = 0,
101 .swreg = 0,
102 },
103 .modalHeader2G = {
104 /* ar9300_modal_eep_header 2g */
105 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]106 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]107 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]108 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]109
110 /*
111 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
112 * rx1, rx12, b (2 bits each)
113 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]114 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]115
116 /*
117 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
118 * for ar9280 (0xa20c/b20c 5:0)
119 */
120 .xatten1DB = {0, 0, 0},
121
122 /*
123 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
124 * for ar9280 (0xa20c/b20c 16:12
125 */
126 .xatten1Margin = {0, 0, 0},
127 .tempSlope = 36,
128 .voltSlope = 0,
129
130 /*
131 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
132 * channels in usual fbin coding format
133 */
134 .spurChans = {0, 0, 0, 0, 0},
135
136 /*
137 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
138 * if the register is per chain
139 */
140 .noiseFloorThreshCh = {-1, 0, 0},
141 .ob = {1, 1, 1},/* 3 chain */
142 .db_stage2 = {1, 1, 1}, /* 3 chain */
143 .db_stage3 = {0, 0, 0},
144 .db_stage4 = {0, 0, 0},
145 .xpaBiasLvl = 0,
146 .txFrameToDataStart = 0x0e,
147 .txFrameToPaOn = 0x0e,
148 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
149 .antennaGain = 0,
150 .switchSettling = 0x2c,
151 .adcDesiredSize = -30,
152 .txEndToXpaOff = 0,
153 .txEndToRxOn = 0x2,
154 .txFrameToXpaOn = 0xe,
155 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]156 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
157 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]158 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]160 },
161 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]162 .base_ext1 = {
163 .ant_div_control = 0,
164 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
165 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]166 .calFreqPier2G = {
167 FREQ2FBIN(2412, 1),
168 FREQ2FBIN(2437, 1),
169 FREQ2FBIN(2472, 1),
170 },
171 /* ar9300_cal_data_per_freq_op_loop 2g */
172 .calPierData2G = {
173 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
174 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
175 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
176 },
177 .calTarget_freqbin_Cck = {
178 FREQ2FBIN(2412, 1),
179 FREQ2FBIN(2484, 1),
180 },
181 .calTarget_freqbin_2G = {
182 FREQ2FBIN(2412, 1),
183 FREQ2FBIN(2437, 1),
184 FREQ2FBIN(2472, 1)
185 },
186 .calTarget_freqbin_2GHT20 = {
187 FREQ2FBIN(2412, 1),
188 FREQ2FBIN(2437, 1),
189 FREQ2FBIN(2472, 1)
190 },
191 .calTarget_freqbin_2GHT40 = {
192 FREQ2FBIN(2412, 1),
193 FREQ2FBIN(2437, 1),
194 FREQ2FBIN(2472, 1)
195 },
196 .calTargetPowerCck = {
197 /* 1L-5L,5S,11L,11S */
198 { {36, 36, 36, 36} },
199 { {36, 36, 36, 36} },
200 },
201 .calTargetPower2G = {
202 /* 6-24,36,48,54 */
203 { {32, 32, 28, 24} },
204 { {32, 32, 28, 24} },
205 { {32, 32, 28, 24} },
206 },
207 .calTargetPower2GHT20 = {
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
211 },
212 .calTargetPower2GHT40 = {
213 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
214 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
215 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
216 },
217 .ctlIndex_2G = {
218 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
219 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
220 },
221 .ctl_freqbin_2G = {
222 {
223 FREQ2FBIN(2412, 1),
224 FREQ2FBIN(2417, 1),
225 FREQ2FBIN(2457, 1),
226 FREQ2FBIN(2462, 1)
227 },
228 {
229 FREQ2FBIN(2412, 1),
230 FREQ2FBIN(2417, 1),
231 FREQ2FBIN(2462, 1),
232 0xFF,
233 },
234
235 {
236 FREQ2FBIN(2412, 1),
237 FREQ2FBIN(2417, 1),
238 FREQ2FBIN(2462, 1),
239 0xFF,
240 },
241 {
242 FREQ2FBIN(2422, 1),
243 FREQ2FBIN(2427, 1),
244 FREQ2FBIN(2447, 1),
245 FREQ2FBIN(2452, 1)
246 },
247
248 {
249 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
250 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
251 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
252 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
253 },
254
255 {
256 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
257 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
258 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
259 0,
260 },
261
262 {
263 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
264 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
265 FREQ2FBIN(2472, 1),
266 0,
267 },
268
269 {
270 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
271 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
272 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
273 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
274 },
275
276 {
277 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
278 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
279 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
280 },
281
282 {
283 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
284 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
285 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
286 0
287 },
288
289 {
290 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
291 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
292 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
293 0
294 },
295
296 {
297 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
298 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
299 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]300 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]301 }
302 },
303 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]304 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
305 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
306 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]307
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]308 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
309 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
310 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]311
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]312 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
313 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
314 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]315
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]316 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
317 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
318 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]319 },
320 .modalHeader5G = {
321 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]322 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]323 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]324 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]325 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
326 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]327 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]328 },
329 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
330 .xatten1DB = {0, 0, 0},
331
332 /*
333 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
334 * for merlin (0xa20c/b20c 16:12
335 */
336 .xatten1Margin = {0, 0, 0},
337 .tempSlope = 68,
338 .voltSlope = 0,
339 /* spurChans spur channels in usual fbin coding format */
340 .spurChans = {0, 0, 0, 0, 0},
341 /* noiseFloorThreshCh Check if the register is per chain */
342 .noiseFloorThreshCh = {-1, 0, 0},
343 .ob = {3, 3, 3}, /* 3 chain */
344 .db_stage2 = {3, 3, 3}, /* 3 chain */
345 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
346 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
347 .xpaBiasLvl = 0,
348 .txFrameToDataStart = 0x0e,
349 .txFrameToPaOn = 0x0e,
350 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
351 .antennaGain = 0,
352 .switchSettling = 0x2d,
353 .adcDesiredSize = -30,
354 .txEndToXpaOff = 0,
355 .txEndToRxOn = 0x2,
356 .txFrameToXpaOn = 0xe,
357 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]358 .papdRateMaskHt20 = LE32(0x0c80c080),
359 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]360 .futureModal = {
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]362 },
363 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]364 .base_ext2 = {
365 .tempSlopeLow = 0,
366 .tempSlopeHigh = 0,
367 .xatten1DBLow = {0, 0, 0},
368 .xatten1MarginLow = {0, 0, 0},
369 .xatten1DBHigh = {0, 0, 0},
370 .xatten1MarginHigh = {0, 0, 0}
371 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]372 .calFreqPier5G = {
373 FREQ2FBIN(5180, 0),
374 FREQ2FBIN(5220, 0),
375 FREQ2FBIN(5320, 0),
376 FREQ2FBIN(5400, 0),
377 FREQ2FBIN(5500, 0),
378 FREQ2FBIN(5600, 0),
379 FREQ2FBIN(5725, 0),
380 FREQ2FBIN(5825, 0)
381 },
382 .calPierData5G = {
383 {
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 },
393 {
394 {0, 0, 0, 0, 0},
395 {0, 0, 0, 0, 0},
396 {0, 0, 0, 0, 0},
397 {0, 0, 0, 0, 0},
398 {0, 0, 0, 0, 0},
399 {0, 0, 0, 0, 0},
400 {0, 0, 0, 0, 0},
401 {0, 0, 0, 0, 0},
402 },
403 {
404 {0, 0, 0, 0, 0},
405 {0, 0, 0, 0, 0},
406 {0, 0, 0, 0, 0},
407 {0, 0, 0, 0, 0},
408 {0, 0, 0, 0, 0},
409 {0, 0, 0, 0, 0},
410 {0, 0, 0, 0, 0},
411 {0, 0, 0, 0, 0},
412 },
413
414 },
415 .calTarget_freqbin_5G = {
416 FREQ2FBIN(5180, 0),
417 FREQ2FBIN(5220, 0),
418 FREQ2FBIN(5320, 0),
419 FREQ2FBIN(5400, 0),
420 FREQ2FBIN(5500, 0),
421 FREQ2FBIN(5600, 0),
422 FREQ2FBIN(5725, 0),
423 FREQ2FBIN(5825, 0)
424 },
425 .calTarget_freqbin_5GHT20 = {
426 FREQ2FBIN(5180, 0),
427 FREQ2FBIN(5240, 0),
428 FREQ2FBIN(5320, 0),
429 FREQ2FBIN(5500, 0),
430 FREQ2FBIN(5700, 0),
431 FREQ2FBIN(5745, 0),
432 FREQ2FBIN(5725, 0),
433 FREQ2FBIN(5825, 0)
434 },
435 .calTarget_freqbin_5GHT40 = {
436 FREQ2FBIN(5180, 0),
437 FREQ2FBIN(5240, 0),
438 FREQ2FBIN(5320, 0),
439 FREQ2FBIN(5500, 0),
440 FREQ2FBIN(5700, 0),
441 FREQ2FBIN(5745, 0),
442 FREQ2FBIN(5725, 0),
443 FREQ2FBIN(5825, 0)
444 },
445 .calTargetPower5G = {
446 /* 6-24,36,48,54 */
447 { {20, 20, 20, 10} },
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
450 { {20, 20, 20, 10} },
451 { {20, 20, 20, 10} },
452 { {20, 20, 20, 10} },
453 { {20, 20, 20, 10} },
454 { {20, 20, 20, 10} },
455 },
456 .calTargetPower5GHT20 = {
457 /*
458 * 0_8_16,1-3_9-11_17-19,
459 * 4,5,6,7,12,13,14,15,20,21,22,23
460 */
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
466 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
467 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 },
470 .calTargetPower5GHT40 = {
471 /*
472 * 0_8_16,1-3_9-11_17-19,
473 * 4,5,6,7,12,13,14,15,20,21,22,23
474 */
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
479 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
481 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
482 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
483 },
484 .ctlIndex_5G = {
485 0x10, 0x16, 0x18, 0x40, 0x46,
486 0x48, 0x30, 0x36, 0x38
487 },
488 .ctl_freqbin_5G = {
489 {
490 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
491 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
492 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
493 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
494 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
495 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
496 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
497 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
498 },
499 {
500 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
501 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
502 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
503 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
504 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
505 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
506 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
507 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
508 },
509
510 {
511 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
512 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
513 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
514 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
515 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
516 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
517 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
518 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
519 },
520
521 {
522 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
523 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
524 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
525 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
526 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
527 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
528 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
529 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
530 },
531
532 {
533 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
534 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
535 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
536 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
537 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
538 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
539 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
540 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
541 },
542
543 {
544 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
545 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
546 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
547 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
548 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
549 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
550 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
551 /* Data[5].ctlEdges[7].bChannel */ 0xFF
552 },
553
554 {
555 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
556 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
557 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
558 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
559 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
560 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
561 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
562 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
563 },
564
565 {
566 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
567 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
568 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
569 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
570 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
571 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
572 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
573 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
574 },
575
576 {
577 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
578 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
579 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
580 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
581 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
582 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
583 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
584 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
585 }
586 },
587 .ctlPowerData_5G = {
588 {
589 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]590 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
591 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]592 }
593 },
594 {
595 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]596 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]598 }
599 },
600 {
601 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]602 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]604 }
605 },
606 {
607 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]608 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
609 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]610 }
611 },
612 {
613 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]614 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
615 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]616 }
617 },
618 {
619 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]620 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
621 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]622 }
623 },
624 {
625 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]626 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
627 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]628 }
629 },
630 {
631 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]632 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
633 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]634 }
635 },
636 {
637 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]638 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
639 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]640 }
641 },
642 }
643};
644
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]645static const struct ar9300_eeprom ar9300_x113 = {
646 .eepromVersion = 2,
647 .templateVersion = 6,
648 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
649 .custData = {"x113-023-f0000"},
650 .baseEepHeader = {
651 .regDmn = { LE16(0), LE16(0x1f) },
652 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
653 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]654 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]655 .eepMisc = 0,
656 },
657 .rfSilent = 0,
658 .blueToothOptions = 0,
659 .deviceCap = 0,
660 .deviceType = 5, /* takes lower byte in eeprom location */
661 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
662 .params_for_tuning_caps = {0, 0},
663 .featureEnable = 0x0d,
664 /*
665 * bit0 - enable tx temp comp - disabled
666 * bit1 - enable tx volt comp - disabled
667 * bit2 - enable fastClock - enabled
668 * bit3 - enable doubling - enabled
669 * bit4 - enable internal regulator - disabled
670 * bit5 - enable pa predistortion - disabled
671 */
672 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
673 .eepromWriteEnableGpio = 6,
674 .wlanDisableGpio = 0,
675 .wlanLedGpio = 8,
676 .rxBandSelectGpio = 0xff,
677 .txrxgain = 0x21,
678 .swreg = 0,
679 },
680 .modalHeader2G = {
681 /* ar9300_modal_eep_header 2g */
682 /* 4 idle,t1,t2,b(4 bits per setting) */
683 .antCtrlCommon = LE32(0x110),
684 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
685 .antCtrlCommon2 = LE32(0x44444),
686
687 /*
688 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
689 * rx1, rx12, b (2 bits each)
690 */
691 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
692
693 /*
694 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
695 * for ar9280 (0xa20c/b20c 5:0)
696 */
697 .xatten1DB = {0, 0, 0},
698
699 /*
700 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
701 * for ar9280 (0xa20c/b20c 16:12
702 */
703 .xatten1Margin = {0, 0, 0},
704 .tempSlope = 25,
705 .voltSlope = 0,
706
707 /*
708 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
709 * channels in usual fbin coding format
710 */
711 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
712
713 /*
714 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
715 * if the register is per chain
716 */
717 .noiseFloorThreshCh = {-1, 0, 0},
718 .ob = {1, 1, 1},/* 3 chain */
719 .db_stage2 = {1, 1, 1}, /* 3 chain */
720 .db_stage3 = {0, 0, 0},
721 .db_stage4 = {0, 0, 0},
722 .xpaBiasLvl = 0,
723 .txFrameToDataStart = 0x0e,
724 .txFrameToPaOn = 0x0e,
725 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
726 .antennaGain = 0,
727 .switchSettling = 0x2c,
728 .adcDesiredSize = -30,
729 .txEndToXpaOff = 0,
730 .txEndToRxOn = 0x2,
731 .txFrameToXpaOn = 0xe,
732 .thresh62 = 28,
733 .papdRateMaskHt20 = LE32(0x0c80c080),
734 .papdRateMaskHt40 = LE32(0x0080c080),
735 .futureModal = {
736 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
737 },
738 },
739 .base_ext1 = {
740 .ant_div_control = 0,
741 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
742 },
743 .calFreqPier2G = {
744 FREQ2FBIN(2412, 1),
745 FREQ2FBIN(2437, 1),
746 FREQ2FBIN(2472, 1),
747 },
748 /* ar9300_cal_data_per_freq_op_loop 2g */
749 .calPierData2G = {
750 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
751 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
752 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
753 },
754 .calTarget_freqbin_Cck = {
755 FREQ2FBIN(2412, 1),
756 FREQ2FBIN(2472, 1),
757 },
758 .calTarget_freqbin_2G = {
759 FREQ2FBIN(2412, 1),
760 FREQ2FBIN(2437, 1),
761 FREQ2FBIN(2472, 1)
762 },
763 .calTarget_freqbin_2GHT20 = {
764 FREQ2FBIN(2412, 1),
765 FREQ2FBIN(2437, 1),
766 FREQ2FBIN(2472, 1)
767 },
768 .calTarget_freqbin_2GHT40 = {
769 FREQ2FBIN(2412, 1),
770 FREQ2FBIN(2437, 1),
771 FREQ2FBIN(2472, 1)
772 },
773 .calTargetPowerCck = {
774 /* 1L-5L,5S,11L,11S */
775 { {34, 34, 34, 34} },
776 { {34, 34, 34, 34} },
777 },
778 .calTargetPower2G = {
779 /* 6-24,36,48,54 */
780 { {34, 34, 32, 32} },
781 { {34, 34, 32, 32} },
782 { {34, 34, 32, 32} },
783 },
784 .calTargetPower2GHT20 = {
785 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
786 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
787 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
788 },
789 .calTargetPower2GHT40 = {
790 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
791 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
792 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
793 },
794 .ctlIndex_2G = {
795 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
796 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
797 },
798 .ctl_freqbin_2G = {
799 {
800 FREQ2FBIN(2412, 1),
801 FREQ2FBIN(2417, 1),
802 FREQ2FBIN(2457, 1),
803 FREQ2FBIN(2462, 1)
804 },
805 {
806 FREQ2FBIN(2412, 1),
807 FREQ2FBIN(2417, 1),
808 FREQ2FBIN(2462, 1),
809 0xFF,
810 },
811
812 {
813 FREQ2FBIN(2412, 1),
814 FREQ2FBIN(2417, 1),
815 FREQ2FBIN(2462, 1),
816 0xFF,
817 },
818 {
819 FREQ2FBIN(2422, 1),
820 FREQ2FBIN(2427, 1),
821 FREQ2FBIN(2447, 1),
822 FREQ2FBIN(2452, 1)
823 },
824
825 {
826 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
829 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
830 },
831
832 {
833 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
834 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
835 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
836 0,
837 },
838
839 {
840 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
841 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
842 FREQ2FBIN(2472, 1),
843 0,
844 },
845
846 {
847 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
848 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
849 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
850 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
851 },
852
853 {
854 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
855 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
856 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
857 },
858
859 {
860 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
861 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
862 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
863 0
864 },
865
866 {
867 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
868 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
869 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
870 0
871 },
872
873 {
874 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
875 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
876 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
877 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
878 }
879 },
880 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]881 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
882 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
883 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]884
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]885 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
886 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
887 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]888
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]889 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
890 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
891 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]892
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]893 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
894 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
895 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]896 },
897 .modalHeader5G = {
898 /* 4 idle,t1,t2,b (4 bits per setting) */
899 .antCtrlCommon = LE32(0x220),
900 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
901 .antCtrlCommon2 = LE32(0x11111),
902 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
903 .antCtrlChain = {
904 LE16(0x150), LE16(0x150), LE16(0x150),
905 },
906 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
907 .xatten1DB = {0, 0, 0},
908
909 /*
910 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
911 * for merlin (0xa20c/b20c 16:12
912 */
913 .xatten1Margin = {0, 0, 0},
914 .tempSlope = 68,
915 .voltSlope = 0,
916 /* spurChans spur channels in usual fbin coding format */
917 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
918 /* noiseFloorThreshCh Check if the register is per chain */
919 .noiseFloorThreshCh = {-1, 0, 0},
920 .ob = {3, 3, 3}, /* 3 chain */
921 .db_stage2 = {3, 3, 3}, /* 3 chain */
922 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
923 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
924 .xpaBiasLvl = 0,
925 .txFrameToDataStart = 0x0e,
926 .txFrameToPaOn = 0x0e,
927 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
928 .antennaGain = 0,
929 .switchSettling = 0x2d,
930 .adcDesiredSize = -30,
931 .txEndToXpaOff = 0,
932 .txEndToRxOn = 0x2,
933 .txFrameToXpaOn = 0xe,
934 .thresh62 = 28,
935 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
936 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
937 .futureModal = {
938 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
939 },
940 },
941 .base_ext2 = {
942 .tempSlopeLow = 72,
943 .tempSlopeHigh = 105,
944 .xatten1DBLow = {0, 0, 0},
945 .xatten1MarginLow = {0, 0, 0},
946 .xatten1DBHigh = {0, 0, 0},
947 .xatten1MarginHigh = {0, 0, 0}
948 },
949 .calFreqPier5G = {
950 FREQ2FBIN(5180, 0),
951 FREQ2FBIN(5240, 0),
952 FREQ2FBIN(5320, 0),
953 FREQ2FBIN(5400, 0),
954 FREQ2FBIN(5500, 0),
955 FREQ2FBIN(5600, 0),
956 FREQ2FBIN(5745, 0),
957 FREQ2FBIN(5785, 0)
958 },
959 .calPierData5G = {
960 {
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 },
970 {
971 {0, 0, 0, 0, 0},
972 {0, 0, 0, 0, 0},
973 {0, 0, 0, 0, 0},
974 {0, 0, 0, 0, 0},
975 {0, 0, 0, 0, 0},
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 },
980 {
981 {0, 0, 0, 0, 0},
982 {0, 0, 0, 0, 0},
983 {0, 0, 0, 0, 0},
984 {0, 0, 0, 0, 0},
985 {0, 0, 0, 0, 0},
986 {0, 0, 0, 0, 0},
987 {0, 0, 0, 0, 0},
988 {0, 0, 0, 0, 0},
989 },
990
991 },
992 .calTarget_freqbin_5G = {
993 FREQ2FBIN(5180, 0),
994 FREQ2FBIN(5220, 0),
995 FREQ2FBIN(5320, 0),
996 FREQ2FBIN(5400, 0),
997 FREQ2FBIN(5500, 0),
998 FREQ2FBIN(5600, 0),
999 FREQ2FBIN(5745, 0),
1000 FREQ2FBIN(5785, 0)
1001 },
1002 .calTarget_freqbin_5GHT20 = {
1003 FREQ2FBIN(5180, 0),
1004 FREQ2FBIN(5240, 0),
1005 FREQ2FBIN(5320, 0),
1006 FREQ2FBIN(5400, 0),
1007 FREQ2FBIN(5500, 0),
1008 FREQ2FBIN(5700, 0),
1009 FREQ2FBIN(5745, 0),
1010 FREQ2FBIN(5825, 0)
1011 },
1012 .calTarget_freqbin_5GHT40 = {
1013 FREQ2FBIN(5190, 0),
1014 FREQ2FBIN(5230, 0),
1015 FREQ2FBIN(5320, 0),
1016 FREQ2FBIN(5410, 0),
1017 FREQ2FBIN(5510, 0),
1018 FREQ2FBIN(5670, 0),
1019 FREQ2FBIN(5755, 0),
1020 FREQ2FBIN(5825, 0)
1021 },
1022 .calTargetPower5G = {
1023 /* 6-24,36,48,54 */
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1027 { {42, 40, 40, 34} },
1028 { {42, 40, 40, 34} },
1029 { {42, 40, 40, 34} },
1030 { {42, 40, 40, 34} },
1031 { {42, 40, 40, 34} },
1032 },
1033 .calTargetPower5GHT20 = {
1034 /*
1035 * 0_8_16,1-3_9-11_17-19,
1036 * 4,5,6,7,12,13,14,15,20,21,22,23
1037 */
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1040 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1041 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1042 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1043 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1044 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1045 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1046 },
1047 .calTargetPower5GHT40 = {
1048 /*
1049 * 0_8_16,1-3_9-11_17-19,
1050 * 4,5,6,7,12,13,14,15,20,21,22,23
1051 */
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1054 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1055 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1056 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1057 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1058 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1059 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1060 },
1061 .ctlIndex_5G = {
1062 0x10, 0x16, 0x18, 0x40, 0x46,
1063 0x48, 0x30, 0x36, 0x38
1064 },
1065 .ctl_freqbin_5G = {
1066 {
1067 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1068 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1069 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1070 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1071 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1072 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1073 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1074 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1075 },
1076 {
1077 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1078 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1079 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1080 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1081 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1082 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1083 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1084 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1085 },
1086
1087 {
1088 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1089 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1090 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1091 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1092 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1093 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1094 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1095 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1096 },
1097
1098 {
1099 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1100 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1101 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1102 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1103 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1104 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1105 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1106 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1107 },
1108
1109 {
1110 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1111 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1112 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1113 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1114 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1115 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1116 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1117 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1118 },
1119
1120 {
1121 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1122 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1123 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1124 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1125 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1126 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1127 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1128 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1129 },
1130
1131 {
1132 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1133 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1134 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1135 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1136 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1137 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1138 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1139 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1140 },
1141
1142 {
1143 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1144 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1145 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1146 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1147 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1148 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1149 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1150 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1151 },
1152
1153 {
1154 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1155 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1156 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1157 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1158 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1159 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1160 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1161 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1162 }
1163 },
1164 .ctlPowerData_5G = {
1165 {
1166 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1169 }
1170 },
1171 {
1172 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1175 }
1176 },
1177 {
1178 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1179 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1181 }
1182 },
1183 {
1184 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1185 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1186 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1187 }
1188 },
1189 {
1190 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1191 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1192 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1193 }
1194 },
1195 {
1196 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1197 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1198 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1199 }
1200 },
1201 {
1202 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1203 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1204 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1205 }
1206 },
1207 {
1208 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1209 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1210 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1211 }
1212 },
1213 {
1214 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1215 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1216 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1217 }
1218 },
1219 }
1220};
1221
1222
1223static const struct ar9300_eeprom ar9300_h112 = {
1224 .eepromVersion = 2,
1225 .templateVersion = 3,
1226 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1227 .custData = {"h112-241-f0000"},
1228 .baseEepHeader = {
1229 .regDmn = { LE16(0), LE16(0x1f) },
1230 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1231 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1232 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1233 .eepMisc = 0,
1234 },
1235 .rfSilent = 0,
1236 .blueToothOptions = 0,
1237 .deviceCap = 0,
1238 .deviceType = 5, /* takes lower byte in eeprom location */
1239 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1240 .params_for_tuning_caps = {0, 0},
1241 .featureEnable = 0x0d,
1242 /*
1243 * bit0 - enable tx temp comp - disabled
1244 * bit1 - enable tx volt comp - disabled
1245 * bit2 - enable fastClock - enabled
1246 * bit3 - enable doubling - enabled
1247 * bit4 - enable internal regulator - disabled
1248 * bit5 - enable pa predistortion - disabled
1249 */
1250 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1251 .eepromWriteEnableGpio = 6,
1252 .wlanDisableGpio = 0,
1253 .wlanLedGpio = 8,
1254 .rxBandSelectGpio = 0xff,
1255 .txrxgain = 0x10,
1256 .swreg = 0,
1257 },
1258 .modalHeader2G = {
1259 /* ar9300_modal_eep_header 2g */
1260 /* 4 idle,t1,t2,b(4 bits per setting) */
1261 .antCtrlCommon = LE32(0x110),
1262 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1263 .antCtrlCommon2 = LE32(0x44444),
1264
1265 /*
1266 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1267 * rx1, rx12, b (2 bits each)
1268 */
1269 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1270
1271 /*
1272 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1273 * for ar9280 (0xa20c/b20c 5:0)
1274 */
1275 .xatten1DB = {0, 0, 0},
1276
1277 /*
1278 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1279 * for ar9280 (0xa20c/b20c 16:12
1280 */
1281 .xatten1Margin = {0, 0, 0},
1282 .tempSlope = 25,
1283 .voltSlope = 0,
1284
1285 /*
1286 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1287 * channels in usual fbin coding format
1288 */
1289 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1290
1291 /*
1292 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1293 * if the register is per chain
1294 */
1295 .noiseFloorThreshCh = {-1, 0, 0},
1296 .ob = {1, 1, 1},/* 3 chain */
1297 .db_stage2 = {1, 1, 1}, /* 3 chain */
1298 .db_stage3 = {0, 0, 0},
1299 .db_stage4 = {0, 0, 0},
1300 .xpaBiasLvl = 0,
1301 .txFrameToDataStart = 0x0e,
1302 .txFrameToPaOn = 0x0e,
1303 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1304 .antennaGain = 0,
1305 .switchSettling = 0x2c,
1306 .adcDesiredSize = -30,
1307 .txEndToXpaOff = 0,
1308 .txEndToRxOn = 0x2,
1309 .txFrameToXpaOn = 0xe,
1310 .thresh62 = 28,
1311 .papdRateMaskHt20 = LE32(0x80c080),
1312 .papdRateMaskHt40 = LE32(0x80c080),
1313 .futureModal = {
1314 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1315 },
1316 },
1317 .base_ext1 = {
1318 .ant_div_control = 0,
1319 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1320 },
1321 .calFreqPier2G = {
1322 FREQ2FBIN(2412, 1),
1323 FREQ2FBIN(2437, 1),
1324 FREQ2FBIN(2472, 1),
1325 },
1326 /* ar9300_cal_data_per_freq_op_loop 2g */
1327 .calPierData2G = {
1328 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1329 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1330 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1331 },
1332 .calTarget_freqbin_Cck = {
1333 FREQ2FBIN(2412, 1),
1334 FREQ2FBIN(2484, 1),
1335 },
1336 .calTarget_freqbin_2G = {
1337 FREQ2FBIN(2412, 1),
1338 FREQ2FBIN(2437, 1),
1339 FREQ2FBIN(2472, 1)
1340 },
1341 .calTarget_freqbin_2GHT20 = {
1342 FREQ2FBIN(2412, 1),
1343 FREQ2FBIN(2437, 1),
1344 FREQ2FBIN(2472, 1)
1345 },
1346 .calTarget_freqbin_2GHT40 = {
1347 FREQ2FBIN(2412, 1),
1348 FREQ2FBIN(2437, 1),
1349 FREQ2FBIN(2472, 1)
1350 },
1351 .calTargetPowerCck = {
1352 /* 1L-5L,5S,11L,11S */
1353 { {34, 34, 34, 34} },
1354 { {34, 34, 34, 34} },
1355 },
1356 .calTargetPower2G = {
1357 /* 6-24,36,48,54 */
1358 { {34, 34, 32, 32} },
1359 { {34, 34, 32, 32} },
1360 { {34, 34, 32, 32} },
1361 },
1362 .calTargetPower2GHT20 = {
1363 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1364 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1365 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1366 },
1367 .calTargetPower2GHT40 = {
1368 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1369 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1370 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1371 },
1372 .ctlIndex_2G = {
1373 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1374 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1375 },
1376 .ctl_freqbin_2G = {
1377 {
1378 FREQ2FBIN(2412, 1),
1379 FREQ2FBIN(2417, 1),
1380 FREQ2FBIN(2457, 1),
1381 FREQ2FBIN(2462, 1)
1382 },
1383 {
1384 FREQ2FBIN(2412, 1),
1385 FREQ2FBIN(2417, 1),
1386 FREQ2FBIN(2462, 1),
1387 0xFF,
1388 },
1389
1390 {
1391 FREQ2FBIN(2412, 1),
1392 FREQ2FBIN(2417, 1),
1393 FREQ2FBIN(2462, 1),
1394 0xFF,
1395 },
1396 {
1397 FREQ2FBIN(2422, 1),
1398 FREQ2FBIN(2427, 1),
1399 FREQ2FBIN(2447, 1),
1400 FREQ2FBIN(2452, 1)
1401 },
1402
1403 {
1404 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1405 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1406 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1407 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1408 },
1409
1410 {
1411 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1412 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1413 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1414 0,
1415 },
1416
1417 {
1418 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1419 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420 FREQ2FBIN(2472, 1),
1421 0,
1422 },
1423
1424 {
1425 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1426 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1427 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1428 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1429 },
1430
1431 {
1432 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1433 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1434 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1435 },
1436
1437 {
1438 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1439 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1440 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1441 0
1442 },
1443
1444 {
1445 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1446 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1447 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1448 0
1449 },
1450
1451 {
1452 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1453 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1454 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1455 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1456 }
1457 },
1458 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1459 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1460 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1461 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1462
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1463 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
1464 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1465 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1466
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1467 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1468 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1469 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1470
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1471 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1472 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1473 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1474 },
1475 .modalHeader5G = {
1476 /* 4 idle,t1,t2,b (4 bits per setting) */
1477 .antCtrlCommon = LE32(0x220),
1478 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1479 .antCtrlCommon2 = LE32(0x44444),
1480 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1481 .antCtrlChain = {
1482 LE16(0x150), LE16(0x150), LE16(0x150),
1483 },
1484 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1485 .xatten1DB = {0, 0, 0},
1486
1487 /*
1488 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1489 * for merlin (0xa20c/b20c 16:12
1490 */
1491 .xatten1Margin = {0, 0, 0},
1492 .tempSlope = 45,
1493 .voltSlope = 0,
1494 /* spurChans spur channels in usual fbin coding format */
1495 .spurChans = {0, 0, 0, 0, 0},
1496 /* noiseFloorThreshCh Check if the register is per chain */
1497 .noiseFloorThreshCh = {-1, 0, 0},
1498 .ob = {3, 3, 3}, /* 3 chain */
1499 .db_stage2 = {3, 3, 3}, /* 3 chain */
1500 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1501 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1502 .xpaBiasLvl = 0,
1503 .txFrameToDataStart = 0x0e,
1504 .txFrameToPaOn = 0x0e,
1505 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1506 .antennaGain = 0,
1507 .switchSettling = 0x2d,
1508 .adcDesiredSize = -30,
1509 .txEndToXpaOff = 0,
1510 .txEndToRxOn = 0x2,
1511 .txFrameToXpaOn = 0xe,
1512 .thresh62 = 28,
1513 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1514 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1515 .futureModal = {
1516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1517 },
1518 },
1519 .base_ext2 = {
1520 .tempSlopeLow = 40,
1521 .tempSlopeHigh = 50,
1522 .xatten1DBLow = {0, 0, 0},
1523 .xatten1MarginLow = {0, 0, 0},
1524 .xatten1DBHigh = {0, 0, 0},
1525 .xatten1MarginHigh = {0, 0, 0}
1526 },
1527 .calFreqPier5G = {
1528 FREQ2FBIN(5180, 0),
1529 FREQ2FBIN(5220, 0),
1530 FREQ2FBIN(5320, 0),
1531 FREQ2FBIN(5400, 0),
1532 FREQ2FBIN(5500, 0),
1533 FREQ2FBIN(5600, 0),
1534 FREQ2FBIN(5700, 0),
1535 FREQ2FBIN(5825, 0)
1536 },
1537 .calPierData5G = {
1538 {
1539 {0, 0, 0, 0, 0},
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 },
1548 {
1549 {0, 0, 0, 0, 0},
1550 {0, 0, 0, 0, 0},
1551 {0, 0, 0, 0, 0},
1552 {0, 0, 0, 0, 0},
1553 {0, 0, 0, 0, 0},
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 },
1558 {
1559 {0, 0, 0, 0, 0},
1560 {0, 0, 0, 0, 0},
1561 {0, 0, 0, 0, 0},
1562 {0, 0, 0, 0, 0},
1563 {0, 0, 0, 0, 0},
1564 {0, 0, 0, 0, 0},
1565 {0, 0, 0, 0, 0},
1566 {0, 0, 0, 0, 0},
1567 },
1568
1569 },
1570 .calTarget_freqbin_5G = {
1571 FREQ2FBIN(5180, 0),
1572 FREQ2FBIN(5240, 0),
1573 FREQ2FBIN(5320, 0),
1574 FREQ2FBIN(5400, 0),
1575 FREQ2FBIN(5500, 0),
1576 FREQ2FBIN(5600, 0),
1577 FREQ2FBIN(5700, 0),
1578 FREQ2FBIN(5825, 0)
1579 },
1580 .calTarget_freqbin_5GHT20 = {
1581 FREQ2FBIN(5180, 0),
1582 FREQ2FBIN(5240, 0),
1583 FREQ2FBIN(5320, 0),
1584 FREQ2FBIN(5400, 0),
1585 FREQ2FBIN(5500, 0),
1586 FREQ2FBIN(5700, 0),
1587 FREQ2FBIN(5745, 0),
1588 FREQ2FBIN(5825, 0)
1589 },
1590 .calTarget_freqbin_5GHT40 = {
1591 FREQ2FBIN(5180, 0),
1592 FREQ2FBIN(5240, 0),
1593 FREQ2FBIN(5320, 0),
1594 FREQ2FBIN(5400, 0),
1595 FREQ2FBIN(5500, 0),
1596 FREQ2FBIN(5700, 0),
1597 FREQ2FBIN(5745, 0),
1598 FREQ2FBIN(5825, 0)
1599 },
1600 .calTargetPower5G = {
1601 /* 6-24,36,48,54 */
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1605 { {30, 30, 28, 24} },
1606 { {30, 30, 28, 24} },
1607 { {30, 30, 28, 24} },
1608 { {30, 30, 28, 24} },
1609 { {30, 30, 28, 24} },
1610 },
1611 .calTargetPower5GHT20 = {
1612 /*
1613 * 0_8_16,1-3_9-11_17-19,
1614 * 4,5,6,7,12,13,14,15,20,21,22,23
1615 */
1616 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1617 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1618 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1619 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1620 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1621 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1622 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1623 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1624 },
1625 .calTargetPower5GHT40 = {
1626 /*
1627 * 0_8_16,1-3_9-11_17-19,
1628 * 4,5,6,7,12,13,14,15,20,21,22,23
1629 */
1630 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1631 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1632 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1633 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1634 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1635 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1636 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1637 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1638 },
1639 .ctlIndex_5G = {
1640 0x10, 0x16, 0x18, 0x40, 0x46,
1641 0x48, 0x30, 0x36, 0x38
1642 },
1643 .ctl_freqbin_5G = {
1644 {
1645 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1646 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1647 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1648 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1649 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1650 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1651 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1652 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1653 },
1654 {
1655 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1656 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1657 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1658 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1659 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1660 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1661 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1662 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1663 },
1664
1665 {
1666 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1667 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1668 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1669 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1670 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1671 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1672 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1673 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1674 },
1675
1676 {
1677 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1678 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1679 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1680 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1681 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1682 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1684 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1685 },
1686
1687 {
1688 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1689 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1690 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1691 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1692 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1693 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1694 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1695 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1696 },
1697
1698 {
1699 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1700 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1701 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1702 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1703 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1704 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1705 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1706 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1707 },
1708
1709 {
1710 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1711 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1712 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1713 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1714 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1715 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1716 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1717 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1718 },
1719
1720 {
1721 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1722 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1723 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1724 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1725 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1726 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1727 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1728 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1729 },
1730
1731 {
1732 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1733 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1734 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1735 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1736 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1737 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1738 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1739 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1740 }
1741 },
1742 .ctlPowerData_5G = {
1743 {
1744 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1745 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1746 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1747 }
1748 },
1749 {
1750 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1751 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1752 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1753 }
1754 },
1755 {
1756 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1757 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1758 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1759 }
1760 },
1761 {
1762 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1763 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1764 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1765 }
1766 },
1767 {
1768 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1769 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1770 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1771 }
1772 },
1773 {
1774 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1775 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1776 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1777 }
1778 },
1779 {
1780 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1781 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1782 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1783 }
1784 },
1785 {
1786 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1787 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1788 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1789 }
1790 },
1791 {
1792 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]1793 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1794 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1795 }
1796 },
1797 }
1798};
1799
1800
1801static const struct ar9300_eeprom ar9300_x112 = {
1802 .eepromVersion = 2,
1803 .templateVersion = 5,
1804 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1805 .custData = {"x112-041-f0000"},
1806 .baseEepHeader = {
1807 .regDmn = { LE16(0), LE16(0x1f) },
1808 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1809 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1810 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1811 .eepMisc = 0,
1812 },
1813 .rfSilent = 0,
1814 .blueToothOptions = 0,
1815 .deviceCap = 0,
1816 .deviceType = 5, /* takes lower byte in eeprom location */
1817 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1818 .params_for_tuning_caps = {0, 0},
1819 .featureEnable = 0x0d,
1820 /*
1821 * bit0 - enable tx temp comp - disabled
1822 * bit1 - enable tx volt comp - disabled
1823 * bit2 - enable fastclock - enabled
1824 * bit3 - enable doubling - enabled
1825 * bit4 - enable internal regulator - disabled
1826 * bit5 - enable pa predistortion - disabled
1827 */
1828 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1829 .eepromWriteEnableGpio = 6,
1830 .wlanDisableGpio = 0,
1831 .wlanLedGpio = 8,
1832 .rxBandSelectGpio = 0xff,
1833 .txrxgain = 0x0,
1834 .swreg = 0,
1835 },
1836 .modalHeader2G = {
1837 /* ar9300_modal_eep_header 2g */
1838 /* 4 idle,t1,t2,b(4 bits per setting) */
1839 .antCtrlCommon = LE32(0x110),
1840 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1841 .antCtrlCommon2 = LE32(0x22222),
1842
1843 /*
1844 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1845 * rx1, rx12, b (2 bits each)
1846 */
1847 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1848
1849 /*
1850 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1851 * for ar9280 (0xa20c/b20c 5:0)
1852 */
1853 .xatten1DB = {0x1b, 0x1b, 0x1b},
1854
1855 /*
1856 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1857 * for ar9280 (0xa20c/b20c 16:12
1858 */
1859 .xatten1Margin = {0x15, 0x15, 0x15},
1860 .tempSlope = 50,
1861 .voltSlope = 0,
1862
1863 /*
1864 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1865 * channels in usual fbin coding format
1866 */
1867 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1868
1869 /*
1870 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1871 * if the register is per chain
1872 */
1873 .noiseFloorThreshCh = {-1, 0, 0},
1874 .ob = {1, 1, 1},/* 3 chain */
1875 .db_stage2 = {1, 1, 1}, /* 3 chain */
1876 .db_stage3 = {0, 0, 0},
1877 .db_stage4 = {0, 0, 0},
1878 .xpaBiasLvl = 0,
1879 .txFrameToDataStart = 0x0e,
1880 .txFrameToPaOn = 0x0e,
1881 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1882 .antennaGain = 0,
1883 .switchSettling = 0x2c,
1884 .adcDesiredSize = -30,
1885 .txEndToXpaOff = 0,
1886 .txEndToRxOn = 0x2,
1887 .txFrameToXpaOn = 0xe,
1888 .thresh62 = 28,
1889 .papdRateMaskHt20 = LE32(0x0c80c080),
1890 .papdRateMaskHt40 = LE32(0x0080c080),
1891 .futureModal = {
1892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1893 },
1894 },
1895 .base_ext1 = {
1896 .ant_div_control = 0,
1897 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1898 },
1899 .calFreqPier2G = {
1900 FREQ2FBIN(2412, 1),
1901 FREQ2FBIN(2437, 1),
1902 FREQ2FBIN(2472, 1),
1903 },
1904 /* ar9300_cal_data_per_freq_op_loop 2g */
1905 .calPierData2G = {
1906 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1907 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1908 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1909 },
1910 .calTarget_freqbin_Cck = {
1911 FREQ2FBIN(2412, 1),
1912 FREQ2FBIN(2472, 1),
1913 },
1914 .calTarget_freqbin_2G = {
1915 FREQ2FBIN(2412, 1),
1916 FREQ2FBIN(2437, 1),
1917 FREQ2FBIN(2472, 1)
1918 },
1919 .calTarget_freqbin_2GHT20 = {
1920 FREQ2FBIN(2412, 1),
1921 FREQ2FBIN(2437, 1),
1922 FREQ2FBIN(2472, 1)
1923 },
1924 .calTarget_freqbin_2GHT40 = {
1925 FREQ2FBIN(2412, 1),
1926 FREQ2FBIN(2437, 1),
1927 FREQ2FBIN(2472, 1)
1928 },
1929 .calTargetPowerCck = {
1930 /* 1L-5L,5S,11L,11s */
1931 { {38, 38, 38, 38} },
1932 { {38, 38, 38, 38} },
1933 },
1934 .calTargetPower2G = {
1935 /* 6-24,36,48,54 */
1936 { {38, 38, 36, 34} },
1937 { {38, 38, 36, 34} },
1938 { {38, 38, 34, 32} },
1939 },
1940 .calTargetPower2GHT20 = {
1941 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1942 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1943 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1944 },
1945 .calTargetPower2GHT40 = {
1946 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1947 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1948 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1949 },
1950 .ctlIndex_2G = {
1951 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1952 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1953 },
1954 .ctl_freqbin_2G = {
1955 {
1956 FREQ2FBIN(2412, 1),
1957 FREQ2FBIN(2417, 1),
1958 FREQ2FBIN(2457, 1),
1959 FREQ2FBIN(2462, 1)
1960 },
1961 {
1962 FREQ2FBIN(2412, 1),
1963 FREQ2FBIN(2417, 1),
1964 FREQ2FBIN(2462, 1),
1965 0xFF,
1966 },
1967
1968 {
1969 FREQ2FBIN(2412, 1),
1970 FREQ2FBIN(2417, 1),
1971 FREQ2FBIN(2462, 1),
1972 0xFF,
1973 },
1974 {
1975 FREQ2FBIN(2422, 1),
1976 FREQ2FBIN(2427, 1),
1977 FREQ2FBIN(2447, 1),
1978 FREQ2FBIN(2452, 1)
1979 },
1980
1981 {
1982 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1983 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1984 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1985 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1986 },
1987
1988 {
1989 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1990 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1991 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1992 0,
1993 },
1994
1995 {
1996 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1997 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1998 FREQ2FBIN(2472, 1),
1999 0,
2000 },
2001
2002 {
2003 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2004 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2005 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2006 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2007 },
2008
2009 {
2010 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2011 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2012 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2013 },
2014
2015 {
2016 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2017 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2018 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2019 0
2020 },
2021
2022 {
2023 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2024 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2025 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2026 0
2027 },
2028
2029 {
2030 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2031 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2032 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2033 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2034 }
2035 },
2036 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2037 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2038 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2039 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2040
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2041 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2042 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2043 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2044
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2045 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2046 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2047 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2048
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2049 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2050 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2051 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2052 },
2053 .modalHeader5G = {
2054 /* 4 idle,t1,t2,b (4 bits per setting) */
2055 .antCtrlCommon = LE32(0x110),
2056 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2057 .antCtrlCommon2 = LE32(0x22222),
2058 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2059 .antCtrlChain = {
2060 LE16(0x0), LE16(0x0), LE16(0x0),
2061 },
2062 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2063 .xatten1DB = {0x13, 0x19, 0x17},
2064
2065 /*
2066 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2067 * for merlin (0xa20c/b20c 16:12
2068 */
2069 .xatten1Margin = {0x19, 0x19, 0x19},
2070 .tempSlope = 70,
2071 .voltSlope = 15,
2072 /* spurChans spur channels in usual fbin coding format */
2073 .spurChans = {0, 0, 0, 0, 0},
2074 /* noiseFloorThreshch check if the register is per chain */
2075 .noiseFloorThreshCh = {-1, 0, 0},
2076 .ob = {3, 3, 3}, /* 3 chain */
2077 .db_stage2 = {3, 3, 3}, /* 3 chain */
2078 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2079 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2080 .xpaBiasLvl = 0,
2081 .txFrameToDataStart = 0x0e,
2082 .txFrameToPaOn = 0x0e,
2083 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2084 .antennaGain = 0,
2085 .switchSettling = 0x2d,
2086 .adcDesiredSize = -30,
2087 .txEndToXpaOff = 0,
2088 .txEndToRxOn = 0x2,
2089 .txFrameToXpaOn = 0xe,
2090 .thresh62 = 28,
2091 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2092 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2093 .futureModal = {
2094 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2095 },
2096 },
2097 .base_ext2 = {
2098 .tempSlopeLow = 72,
2099 .tempSlopeHigh = 105,
2100 .xatten1DBLow = {0x10, 0x14, 0x10},
2101 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2102 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2103 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2104 },
2105 .calFreqPier5G = {
2106 FREQ2FBIN(5180, 0),
2107 FREQ2FBIN(5220, 0),
2108 FREQ2FBIN(5320, 0),
2109 FREQ2FBIN(5400, 0),
2110 FREQ2FBIN(5500, 0),
2111 FREQ2FBIN(5600, 0),
2112 FREQ2FBIN(5700, 0),
2113 FREQ2FBIN(5785, 0)
2114 },
2115 .calPierData5G = {
2116 {
2117 {0, 0, 0, 0, 0},
2118 {0, 0, 0, 0, 0},
2119 {0, 0, 0, 0, 0},
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 },
2126 {
2127 {0, 0, 0, 0, 0},
2128 {0, 0, 0, 0, 0},
2129 {0, 0, 0, 0, 0},
2130 {0, 0, 0, 0, 0},
2131 {0, 0, 0, 0, 0},
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 },
2136 {
2137 {0, 0, 0, 0, 0},
2138 {0, 0, 0, 0, 0},
2139 {0, 0, 0, 0, 0},
2140 {0, 0, 0, 0, 0},
2141 {0, 0, 0, 0, 0},
2142 {0, 0, 0, 0, 0},
2143 {0, 0, 0, 0, 0},
2144 {0, 0, 0, 0, 0},
2145 },
2146
2147 },
2148 .calTarget_freqbin_5G = {
2149 FREQ2FBIN(5180, 0),
2150 FREQ2FBIN(5220, 0),
2151 FREQ2FBIN(5320, 0),
2152 FREQ2FBIN(5400, 0),
2153 FREQ2FBIN(5500, 0),
2154 FREQ2FBIN(5600, 0),
2155 FREQ2FBIN(5725, 0),
2156 FREQ2FBIN(5825, 0)
2157 },
2158 .calTarget_freqbin_5GHT20 = {
2159 FREQ2FBIN(5180, 0),
2160 FREQ2FBIN(5220, 0),
2161 FREQ2FBIN(5320, 0),
2162 FREQ2FBIN(5400, 0),
2163 FREQ2FBIN(5500, 0),
2164 FREQ2FBIN(5600, 0),
2165 FREQ2FBIN(5725, 0),
2166 FREQ2FBIN(5825, 0)
2167 },
2168 .calTarget_freqbin_5GHT40 = {
2169 FREQ2FBIN(5180, 0),
2170 FREQ2FBIN(5220, 0),
2171 FREQ2FBIN(5320, 0),
2172 FREQ2FBIN(5400, 0),
2173 FREQ2FBIN(5500, 0),
2174 FREQ2FBIN(5600, 0),
2175 FREQ2FBIN(5725, 0),
2176 FREQ2FBIN(5825, 0)
2177 },
2178 .calTargetPower5G = {
2179 /* 6-24,36,48,54 */
2180 { {32, 32, 28, 26} },
2181 { {32, 32, 28, 26} },
2182 { {32, 32, 28, 26} },
2183 { {32, 32, 26, 24} },
2184 { {32, 32, 26, 24} },
2185 { {32, 32, 24, 22} },
2186 { {30, 30, 24, 22} },
2187 { {30, 30, 24, 22} },
2188 },
2189 .calTargetPower5GHT20 = {
2190 /*
2191 * 0_8_16,1-3_9-11_17-19,
2192 * 4,5,6,7,12,13,14,15,20,21,22,23
2193 */
2194 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2195 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2196 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2197 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2198 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2199 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2200 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2201 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2202 },
2203 .calTargetPower5GHT40 = {
2204 /*
2205 * 0_8_16,1-3_9-11_17-19,
2206 * 4,5,6,7,12,13,14,15,20,21,22,23
2207 */
2208 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2209 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2210 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2211 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2212 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2213 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2214 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2215 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2216 },
2217 .ctlIndex_5G = {
2218 0x10, 0x16, 0x18, 0x40, 0x46,
2219 0x48, 0x30, 0x36, 0x38
2220 },
2221 .ctl_freqbin_5G = {
2222 {
2223 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2224 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2225 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2226 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2227 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2228 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2229 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2230 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2231 },
2232 {
2233 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2234 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2235 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2236 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2237 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2238 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2239 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2240 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2241 },
2242
2243 {
2244 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2245 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2246 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2247 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2248 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2249 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2250 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2251 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2252 },
2253
2254 {
2255 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2256 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2257 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2258 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2259 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2260 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2261 /* Data[3].ctledges[6].bchannel */ 0xFF,
2262 /* Data[3].ctledges[7].bchannel */ 0xFF,
2263 },
2264
2265 {
2266 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2267 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2268 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2269 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2270 /* Data[4].ctledges[4].bchannel */ 0xFF,
2271 /* Data[4].ctledges[5].bchannel */ 0xFF,
2272 /* Data[4].ctledges[6].bchannel */ 0xFF,
2273 /* Data[4].ctledges[7].bchannel */ 0xFF,
2274 },
2275
2276 {
2277 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2278 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2279 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2280 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2281 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2282 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2283 /* Data[5].ctledges[6].bchannel */ 0xFF,
2284 /* Data[5].ctledges[7].bchannel */ 0xFF
2285 },
2286
2287 {
2288 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2289 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2290 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2291 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2292 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2293 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2294 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2295 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2296 },
2297
2298 {
2299 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2300 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2301 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2302 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2303 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2304 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2305 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2306 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2307 },
2308
2309 {
2310 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2311 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2312 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2313 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2314 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2315 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2316 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2317 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2318 }
2319 },
2320 .ctlPowerData_5G = {
2321 {
2322 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2323 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2324 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2325 }
2326 },
2327 {
2328 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2329 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2331 }
2332 },
2333 {
2334 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2335 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2336 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2337 }
2338 },
2339 {
2340 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2341 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2342 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2343 }
2344 },
2345 {
2346 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2347 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2348 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2349 }
2350 },
2351 {
2352 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2353 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2354 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2355 }
2356 },
2357 {
2358 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2359 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2360 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2361 }
2362 },
2363 {
2364 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2365 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2366 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2367 }
2368 },
2369 {
2370 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2371 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2372 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2373 }
2374 },
2375 }
2376};
2377
2378static const struct ar9300_eeprom ar9300_h116 = {
2379 .eepromVersion = 2,
2380 .templateVersion = 4,
2381 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2382 .custData = {"h116-041-f0000"},
2383 .baseEepHeader = {
2384 .regDmn = { LE16(0), LE16(0x1f) },
2385 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2386 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2387 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2388 .eepMisc = 0,
2389 },
2390 .rfSilent = 0,
2391 .blueToothOptions = 0,
2392 .deviceCap = 0,
2393 .deviceType = 5, /* takes lower byte in eeprom location */
2394 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2395 .params_for_tuning_caps = {0, 0},
2396 .featureEnable = 0x0d,
2397 /*
2398 * bit0 - enable tx temp comp - disabled
2399 * bit1 - enable tx volt comp - disabled
2400 * bit2 - enable fastClock - enabled
2401 * bit3 - enable doubling - enabled
2402 * bit4 - enable internal regulator - disabled
2403 * bit5 - enable pa predistortion - disabled
2404 */
2405 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2406 .eepromWriteEnableGpio = 6,
2407 .wlanDisableGpio = 0,
2408 .wlanLedGpio = 8,
2409 .rxBandSelectGpio = 0xff,
2410 .txrxgain = 0x10,
2411 .swreg = 0,
2412 },
2413 .modalHeader2G = {
2414 /* ar9300_modal_eep_header 2g */
2415 /* 4 idle,t1,t2,b(4 bits per setting) */
2416 .antCtrlCommon = LE32(0x110),
2417 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2418 .antCtrlCommon2 = LE32(0x44444),
2419
2420 /*
2421 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2422 * rx1, rx12, b (2 bits each)
2423 */
2424 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2425
2426 /*
2427 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2428 * for ar9280 (0xa20c/b20c 5:0)
2429 */
2430 .xatten1DB = {0x1f, 0x1f, 0x1f},
2431
2432 /*
2433 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2434 * for ar9280 (0xa20c/b20c 16:12
2435 */
2436 .xatten1Margin = {0x12, 0x12, 0x12},
2437 .tempSlope = 25,
2438 .voltSlope = 0,
2439
2440 /*
2441 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2442 * channels in usual fbin coding format
2443 */
2444 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2445
2446 /*
2447 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2448 * if the register is per chain
2449 */
2450 .noiseFloorThreshCh = {-1, 0, 0},
2451 .ob = {1, 1, 1},/* 3 chain */
2452 .db_stage2 = {1, 1, 1}, /* 3 chain */
2453 .db_stage3 = {0, 0, 0},
2454 .db_stage4 = {0, 0, 0},
2455 .xpaBiasLvl = 0,
2456 .txFrameToDataStart = 0x0e,
2457 .txFrameToPaOn = 0x0e,
2458 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2459 .antennaGain = 0,
2460 .switchSettling = 0x2c,
2461 .adcDesiredSize = -30,
2462 .txEndToXpaOff = 0,
2463 .txEndToRxOn = 0x2,
2464 .txFrameToXpaOn = 0xe,
2465 .thresh62 = 28,
2466 .papdRateMaskHt20 = LE32(0x0c80C080),
2467 .papdRateMaskHt40 = LE32(0x0080C080),
2468 .futureModal = {
2469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2470 },
2471 },
2472 .base_ext1 = {
2473 .ant_div_control = 0,
2474 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2475 },
2476 .calFreqPier2G = {
2477 FREQ2FBIN(2412, 1),
2478 FREQ2FBIN(2437, 1),
2479 FREQ2FBIN(2472, 1),
2480 },
2481 /* ar9300_cal_data_per_freq_op_loop 2g */
2482 .calPierData2G = {
2483 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2484 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2485 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2486 },
2487 .calTarget_freqbin_Cck = {
2488 FREQ2FBIN(2412, 1),
2489 FREQ2FBIN(2472, 1),
2490 },
2491 .calTarget_freqbin_2G = {
2492 FREQ2FBIN(2412, 1),
2493 FREQ2FBIN(2437, 1),
2494 FREQ2FBIN(2472, 1)
2495 },
2496 .calTarget_freqbin_2GHT20 = {
2497 FREQ2FBIN(2412, 1),
2498 FREQ2FBIN(2437, 1),
2499 FREQ2FBIN(2472, 1)
2500 },
2501 .calTarget_freqbin_2GHT40 = {
2502 FREQ2FBIN(2412, 1),
2503 FREQ2FBIN(2437, 1),
2504 FREQ2FBIN(2472, 1)
2505 },
2506 .calTargetPowerCck = {
2507 /* 1L-5L,5S,11L,11S */
2508 { {34, 34, 34, 34} },
2509 { {34, 34, 34, 34} },
2510 },
2511 .calTargetPower2G = {
2512 /* 6-24,36,48,54 */
2513 { {34, 34, 32, 32} },
2514 { {34, 34, 32, 32} },
2515 { {34, 34, 32, 32} },
2516 },
2517 .calTargetPower2GHT20 = {
2518 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2519 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2520 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2521 },
2522 .calTargetPower2GHT40 = {
2523 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2524 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2525 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2526 },
2527 .ctlIndex_2G = {
2528 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2529 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2530 },
2531 .ctl_freqbin_2G = {
2532 {
2533 FREQ2FBIN(2412, 1),
2534 FREQ2FBIN(2417, 1),
2535 FREQ2FBIN(2457, 1),
2536 FREQ2FBIN(2462, 1)
2537 },
2538 {
2539 FREQ2FBIN(2412, 1),
2540 FREQ2FBIN(2417, 1),
2541 FREQ2FBIN(2462, 1),
2542 0xFF,
2543 },
2544
2545 {
2546 FREQ2FBIN(2412, 1),
2547 FREQ2FBIN(2417, 1),
2548 FREQ2FBIN(2462, 1),
2549 0xFF,
2550 },
2551 {
2552 FREQ2FBIN(2422, 1),
2553 FREQ2FBIN(2427, 1),
2554 FREQ2FBIN(2447, 1),
2555 FREQ2FBIN(2452, 1)
2556 },
2557
2558 {
2559 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2560 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2561 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2562 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2563 },
2564
2565 {
2566 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2567 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2568 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2569 0,
2570 },
2571
2572 {
2573 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2574 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2575 FREQ2FBIN(2472, 1),
2576 0,
2577 },
2578
2579 {
2580 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2581 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2582 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2583 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2584 },
2585
2586 {
2587 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2588 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2589 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2590 },
2591
2592 {
2593 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2594 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2595 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2596 0
2597 },
2598
2599 {
2600 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2601 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2602 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2603 0
2604 },
2605
2606 {
2607 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2608 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2609 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2610 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2611 }
2612 },
2613 .ctlPowerData_2G = {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2614 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2615 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2616 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2617
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2618 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2619 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2620 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2621
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2622 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2623 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2624 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2625
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2626 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2627 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2628 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2629 },
2630 .modalHeader5G = {
2631 /* 4 idle,t1,t2,b (4 bits per setting) */
2632 .antCtrlCommon = LE32(0x220),
2633 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2634 .antCtrlCommon2 = LE32(0x44444),
2635 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2636 .antCtrlChain = {
2637 LE16(0x150), LE16(0x150), LE16(0x150),
2638 },
2639 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2640 .xatten1DB = {0x19, 0x19, 0x19},
2641
2642 /*
2643 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2644 * for merlin (0xa20c/b20c 16:12
2645 */
2646 .xatten1Margin = {0x14, 0x14, 0x14},
2647 .tempSlope = 70,
2648 .voltSlope = 0,
2649 /* spurChans spur channels in usual fbin coding format */
2650 .spurChans = {0, 0, 0, 0, 0},
2651 /* noiseFloorThreshCh Check if the register is per chain */
2652 .noiseFloorThreshCh = {-1, 0, 0},
2653 .ob = {3, 3, 3}, /* 3 chain */
2654 .db_stage2 = {3, 3, 3}, /* 3 chain */
2655 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2656 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2657 .xpaBiasLvl = 0,
2658 .txFrameToDataStart = 0x0e,
2659 .txFrameToPaOn = 0x0e,
2660 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2661 .antennaGain = 0,
2662 .switchSettling = 0x2d,
2663 .adcDesiredSize = -30,
2664 .txEndToXpaOff = 0,
2665 .txEndToRxOn = 0x2,
2666 .txFrameToXpaOn = 0xe,
2667 .thresh62 = 28,
2668 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2669 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2670 .futureModal = {
2671 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2672 },
2673 },
2674 .base_ext2 = {
2675 .tempSlopeLow = 35,
2676 .tempSlopeHigh = 50,
2677 .xatten1DBLow = {0, 0, 0},
2678 .xatten1MarginLow = {0, 0, 0},
2679 .xatten1DBHigh = {0, 0, 0},
2680 .xatten1MarginHigh = {0, 0, 0}
2681 },
2682 .calFreqPier5G = {
2683 FREQ2FBIN(5180, 0),
2684 FREQ2FBIN(5220, 0),
2685 FREQ2FBIN(5320, 0),
2686 FREQ2FBIN(5400, 0),
2687 FREQ2FBIN(5500, 0),
2688 FREQ2FBIN(5600, 0),
2689 FREQ2FBIN(5700, 0),
2690 FREQ2FBIN(5785, 0)
2691 },
2692 .calPierData5G = {
2693 {
2694 {0, 0, 0, 0, 0},
2695 {0, 0, 0, 0, 0},
2696 {0, 0, 0, 0, 0},
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 },
2703 {
2704 {0, 0, 0, 0, 0},
2705 {0, 0, 0, 0, 0},
2706 {0, 0, 0, 0, 0},
2707 {0, 0, 0, 0, 0},
2708 {0, 0, 0, 0, 0},
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 },
2713 {
2714 {0, 0, 0, 0, 0},
2715 {0, 0, 0, 0, 0},
2716 {0, 0, 0, 0, 0},
2717 {0, 0, 0, 0, 0},
2718 {0, 0, 0, 0, 0},
2719 {0, 0, 0, 0, 0},
2720 {0, 0, 0, 0, 0},
2721 {0, 0, 0, 0, 0},
2722 },
2723
2724 },
2725 .calTarget_freqbin_5G = {
2726 FREQ2FBIN(5180, 0),
2727 FREQ2FBIN(5240, 0),
2728 FREQ2FBIN(5320, 0),
2729 FREQ2FBIN(5400, 0),
2730 FREQ2FBIN(5500, 0),
2731 FREQ2FBIN(5600, 0),
2732 FREQ2FBIN(5700, 0),
2733 FREQ2FBIN(5825, 0)
2734 },
2735 .calTarget_freqbin_5GHT20 = {
2736 FREQ2FBIN(5180, 0),
2737 FREQ2FBIN(5240, 0),
2738 FREQ2FBIN(5320, 0),
2739 FREQ2FBIN(5400, 0),
2740 FREQ2FBIN(5500, 0),
2741 FREQ2FBIN(5700, 0),
2742 FREQ2FBIN(5745, 0),
2743 FREQ2FBIN(5825, 0)
2744 },
2745 .calTarget_freqbin_5GHT40 = {
2746 FREQ2FBIN(5180, 0),
2747 FREQ2FBIN(5240, 0),
2748 FREQ2FBIN(5320, 0),
2749 FREQ2FBIN(5400, 0),
2750 FREQ2FBIN(5500, 0),
2751 FREQ2FBIN(5700, 0),
2752 FREQ2FBIN(5745, 0),
2753 FREQ2FBIN(5825, 0)
2754 },
2755 .calTargetPower5G = {
2756 /* 6-24,36,48,54 */
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2760 { {30, 30, 28, 24} },
2761 { {30, 30, 28, 24} },
2762 { {30, 30, 28, 24} },
2763 { {30, 30, 28, 24} },
2764 { {30, 30, 28, 24} },
2765 },
2766 .calTargetPower5GHT20 = {
2767 /*
2768 * 0_8_16,1-3_9-11_17-19,
2769 * 4,5,6,7,12,13,14,15,20,21,22,23
2770 */
2771 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2772 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2773 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2774 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2775 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2776 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2777 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2778 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2779 },
2780 .calTargetPower5GHT40 = {
2781 /*
2782 * 0_8_16,1-3_9-11_17-19,
2783 * 4,5,6,7,12,13,14,15,20,21,22,23
2784 */
2785 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2786 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2787 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2788 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2789 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2790 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2791 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2792 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2793 },
2794 .ctlIndex_5G = {
2795 0x10, 0x16, 0x18, 0x40, 0x46,
2796 0x48, 0x30, 0x36, 0x38
2797 },
2798 .ctl_freqbin_5G = {
2799 {
2800 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2801 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2802 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2803 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2804 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2805 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2806 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2807 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2808 },
2809 {
2810 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2811 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2812 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2813 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2814 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2815 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2816 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2817 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2818 },
2819
2820 {
2821 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2822 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2823 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2824 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2825 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2826 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2827 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2828 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2829 },
2830
2831 {
2832 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2833 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2834 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2835 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2836 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2837 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2838 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2839 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2840 },
2841
2842 {
2843 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2844 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2845 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2846 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2847 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2848 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2849 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2850 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2851 },
2852
2853 {
2854 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2855 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2856 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2857 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2858 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2859 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2860 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2861 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2862 },
2863
2864 {
2865 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2866 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2867 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2868 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2869 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2870 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2871 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2872 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2873 },
2874
2875 {
2876 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2877 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2878 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2879 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2880 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2881 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2882 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2883 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2884 },
2885
2886 {
2887 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2888 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2889 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2890 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2891 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2892 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2893 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2894 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2895 }
2896 },
2897 .ctlPowerData_5G = {
2898 {
2899 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2900 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2902 }
2903 },
2904 {
2905 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2906 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2908 }
2909 },
2910 {
2911 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2912 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2913 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2914 }
2915 },
2916 {
2917 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2918 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2919 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2920 }
2921 },
2922 {
2923 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2924 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2925 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2926 }
2927 },
2928 {
2929 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2930 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2931 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2932 }
2933 },
2934 {
2935 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2936 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2937 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2938 }
2939 },
2940 {
2941 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2942 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2943 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2944 }
2945 },
2946 {
2947 {
John W. Linville09f921f2010-12-02 15:46:37 -0500[diff] [blame]2948 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2949 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2950 }
2951 },
2952 }
2953};
2954
2955
2956static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2957 &ar9300_default,
2958 &ar9300_x112,
2959 &ar9300_h116,
2960 &ar9300_h112,
2961 &ar9300_x113,
2962};
2963
2964static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2965{
2966#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2967 int it;
2968
2969 for (it = 0; it < N_LOOP; it++)
2970 if (ar9300_eep_templates[it]->templateVersion == id)
2971 return ar9300_eep_templates[it];
2972 return NULL;
2973#undef N_LOOP
2974}
2975
2976
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2977static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2978{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2979 if (fbin == AR5416_BCHAN_UNUSED)
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2980 return fbin;
2981
2982 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2983}
2984
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2985static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2986{
2987 return 0;
2988}
2989
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2990static int interpolate(int x, int xa, int xb, int ya, int yb)
2991{
2992 int bf, factor, plus;
2993
2994 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2995 factor = bf / 2;
2996 plus = bf % 2;
2997 return ya + factor + plus;
2998}
2999
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3000static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3001 enum eeprom_param param)
3002{
3003 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3004 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3005
3006 switch (param) {
3007 case EEP_MAC_LSW:
3008 return eep->macAddr[0] << 8 | eep->macAddr[1];
3009 case EEP_MAC_MID:
3010 return eep->macAddr[2] << 8 | eep->macAddr[3];
3011 case EEP_MAC_MSW:
3012 return eep->macAddr[4] << 8 | eep->macAddr[5];
3013 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3014 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3015 case EEP_REG_1:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3016 return le16_to_cpu(pBase->regDmn[1]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3017 case EEP_OP_CAP:
3018 return pBase->deviceCap;
3019 case EEP_OP_MODE:
3020 return pBase->opCapFlags.opFlags;
3021 case EEP_RF_SILENT:
3022 return pBase->rfSilent;
3023 case EEP_TX_MASK:
3024 return (pBase->txrxMask >> 4) & 0xf;
3025 case EEP_RX_MASK:
3026 return pBase->txrxMask & 0xf;
3027 case EEP_DRIVE_STRENGTH:
3028#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3029 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3030 case EEP_INTERNAL_REGULATOR:
3031 /* Bit 4 is internal regulator flag */
3032 return (pBase->featureEnable & 0x10) >> 4;
3033 case EEP_SWREG:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3034 return le32_to_cpu(pBase->swreg);
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]3035 case EEP_PAPRD:
3036 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]3037 case EEP_CHAIN_MASK_REDUCE:
3038 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3039 case EEP_ANT_DIV_CTL1:
3040 return le32_to_cpu(eep->base_ext1.ant_div_control);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3041 default:
3042 return 0;
3043 }
3044}
3045
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3046static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3047 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3048{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3049 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3050
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3051 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3052 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3053
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3054 *buffer = (val >> (8 * (address % 2))) & 0xff;
3055 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3056}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3057
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3058static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3059 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3060{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3061 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3062
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3063 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3064 return false;
3065
3066 buffer[0] = val >> 8;
3067 buffer[1] = val & 0xff;
3068
3069 return true;
3070}
3071
3072static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3073 int count)
3074{
3075 struct ath_common *common = ath9k_hw_common(ah);
3076 int i;
3077
3078 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3079 ath_dbg(common, ATH_DBG_EEPROM,
3080 "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3081 return false;
3082 }
3083
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3084 /*
3085 * Since we're reading the bytes in reverse order from a little-endian
3086 * word stream, an even address means we only use the lower half of
3087 * the 16-bit word at that address
3088 */
3089 if (address % 2 == 0) {
3090 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3091 goto error;
3092
3093 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3094 }
3095
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3096 for (i = 0; i < count / 2; i++) {
3097 if (!ar9300_eeprom_read_word(common, address, buffer))
3098 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3099
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3100 address -= 2;
3101 buffer += 2;
3102 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3103
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3104 if (count % 2)
3105 if (!ar9300_eeprom_read_byte(common, address, buffer))
3106 goto error;
3107
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3108 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3109
3110error:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3111 ath_dbg(common, ATH_DBG_EEPROM,
3112 "unable to read eeprom region at offset %d\n", address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3113 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3114}
3115
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3116static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3117{
3118 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3119
3120 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3121 AR9300_OTP_STATUS_VALID, 1000))
3122 return false;
3123
3124 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3125 return true;
3126}
3127
3128static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3129 int count)
3130{
3131 u32 data;
3132 int i;
3133
3134 for (i = 0; i < count; i++) {
3135 int offset = 8 * ((address - i) % 4);
3136 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3137 return false;
3138
3139 buffer[i] = (data >> offset) & 0xff;
3140 }
3141
3142 return true;
3143}
3144
3145
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3146static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3147 int *length, int *major, int *minor)
3148{
3149 unsigned long value[4];
3150
3151 value[0] = best[0];
3152 value[1] = best[1];
3153 value[2] = best[2];
3154 value[3] = best[3];
3155 *code = ((value[0] >> 5) & 0x0007);
3156 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3157 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3158 *major = (value[2] & 0x000f);
3159 *minor = (value[3] & 0x00ff);
3160}
3161
3162static u16 ar9300_comp_cksum(u8 *data, int dsize)
3163{
3164 int it, checksum = 0;
3165
3166 for (it = 0; it < dsize; it++) {
3167 checksum += data[it];
3168 checksum &= 0xffff;
3169 }
3170
3171 return checksum;
3172}
3173
3174static bool ar9300_uncompress_block(struct ath_hw *ah,
3175 u8 *mptr,
3176 int mdataSize,
3177 u8 *block,
3178 int size)
3179{
3180 int it;
3181 int spot;
3182 int offset;
3183 int length;
3184 struct ath_common *common = ath9k_hw_common(ah);
3185
3186 spot = 0;
3187
3188 for (it = 0; it < size; it += (length+2)) {
3189 offset = block[it];
3190 offset &= 0xff;
3191 spot += offset;
3192 length = block[it+1];
3193 length &= 0xff;
3194
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3195 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3196 ath_dbg(common, ATH_DBG_EEPROM,
3197 "Restore at %d: spot=%d offset=%d length=%d\n",
3198 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3199 memcpy(&mptr[spot], &block[it+2], length);
3200 spot += length;
3201 } else if (length > 0) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3202 ath_dbg(common, ATH_DBG_EEPROM,
3203 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3204 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3205 return false;
3206 }
3207 }
3208 return true;
3209}
3210
3211static int ar9300_compress_decision(struct ath_hw *ah,
3212 int it,
3213 int code,
3214 int reference,
3215 u8 *mptr,
3216 u8 *word, int length, int mdata_size)
3217{
3218 struct ath_common *common = ath9k_hw_common(ah);
3219 u8 *dptr;
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3220 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3221
3222 switch (code) {
3223 case _CompressNone:
3224 if (length != mdata_size) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3225 ath_dbg(common, ATH_DBG_EEPROM,
3226 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3227 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3228 return -1;
3229 }
3230 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3231 ath_dbg(common, ATH_DBG_EEPROM,
3232 "restored eeprom %d: uncompressed, length %d\n",
3233 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3234 break;
3235 case _CompressBlock:
3236 if (reference == 0) {
3237 dptr = mptr;
3238 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3239 eep = ar9003_eeprom_struct_find_by_id(reference);
3240 if (eep == NULL) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3241 ath_dbg(common, ATH_DBG_EEPROM,
3242 "cant find reference eeprom struct %d\n",
3243 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3244 return -1;
3245 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3246 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3247 }
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3248 ath_dbg(common, ATH_DBG_EEPROM,
3249 "restore eeprom %d: block, reference %d, length %d\n",
3250 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3251 ar9300_uncompress_block(ah, mptr, mdata_size,
3252 (u8 *) (word + COMP_HDR_LEN), length);
3253 break;
3254 default:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3255 ath_dbg(common, ATH_DBG_EEPROM,
3256 "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3257 return -1;
3258 }
3259 return 0;
3260}
3261
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3262typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3263 int count);
3264
3265static bool ar9300_check_header(void *data)
3266{
3267 u32 *word = data;
3268 return !(*word == 0 || *word == ~0);
3269}
3270
3271static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3272 int base_addr)
3273{
3274 u8 header[4];
3275
3276 if (!read(ah, base_addr, header, 4))
3277 return false;
3278
3279 return ar9300_check_header(header);
3280}
3281
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3282static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3283 int mdata_size)
3284{
3285 struct ath_common *common = ath9k_hw_common(ah);
3286 u16 *data = (u16 *) mptr;
3287 int i;
3288
3289 for (i = 0; i < mdata_size / 2; i++, data++)
3290 ath9k_hw_nvram_read(common, i, data);
3291
3292 return 0;
3293}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3294/*
3295 * Read the configuration data from the eeprom.
3296 * The data can be put in any specified memory buffer.
3297 *
3298 * Returns -1 on error.
3299 * Returns address of next memory location on success.
3300 */
3301static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3302 u8 *mptr, int mdata_size)
3303{
3304#define MDEFAULT 15
3305#define MSTATE 100
3306 int cptr;
3307 u8 *word;
3308 int code;
3309 int reference, length, major, minor;
3310 int osize;
3311 int it;
3312 u16 checksum, mchecksum;
3313 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3314 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3315
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3316 if (ath9k_hw_use_flash(ah))
3317 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3318
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3319 word = kzalloc(2048, GFP_KERNEL);
3320 if (!word)
3321 return -1;
3322
3323 memcpy(mptr, &ar9300_default, mdata_size);
3324
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3325 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3326 if (AR_SREV_9485(ah))
3327 cptr = AR9300_BASE_ADDR_4K;
3328 else
3329 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3330 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3331 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3332 if (ar9300_check_eeprom_header(ah, read, cptr))
3333 goto found;
3334
3335 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3336 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3337 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3338 if (ar9300_check_eeprom_header(ah, read, cptr))
3339 goto found;
3340
3341 read = ar9300_read_otp;
3342 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3343 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3344 "Trying OTP accesss at Address 0x%04x\n", cptr);
3345 if (ar9300_check_eeprom_header(ah, read, cptr))
3346 goto found;
3347
3348 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3349 ath_dbg(common, ATH_DBG_EEPROM,
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3350 "Trying OTP accesss at Address 0x%04x\n", cptr);
3351 if (ar9300_check_eeprom_header(ah, read, cptr))
3352 goto found;
3353
3354 goto fail;
3355
3356found:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3357 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3358
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3359 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3360 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3361 goto fail;
3362
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3363 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3364 break;
3365
3366 ar9300_comp_hdr_unpack(word, &code, &reference,
3367 &length, &major, &minor);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3368 ath_dbg(common, ATH_DBG_EEPROM,
3369 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3370 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3371 if ((!AR_SREV_9485(ah) && length >= 1024) ||
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame^]3372 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3373 ath_dbg(common, ATH_DBG_EEPROM,
3374 "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3375 cptr -= COMP_HDR_LEN;
3376 continue;
3377 }
3378
3379 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3380 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3381 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3382 mchecksum = word[COMP_HDR_LEN + osize] |
3383 (word[COMP_HDR_LEN + osize + 1] << 8);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3384 ath_dbg(common, ATH_DBG_EEPROM,
3385 "checksum %x %x\n", checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3386 if (checksum == mchecksum) {
3387 ar9300_compress_decision(ah, it, code, reference, mptr,
3388 word, length, mdata_size);
3389 } else {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3390 ath_dbg(common, ATH_DBG_EEPROM,
3391 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3392 }
3393 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3394 }
3395
3396 kfree(word);
3397 return cptr;
3398
3399fail:
3400 kfree(word);
3401 return -1;
3402}
3403
3404/*
3405 * Restore the configuration structure by reading the eeprom.
3406 * This function destroys any existing in-memory structure
3407 * content.
3408 */
3409static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3410{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3411 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3412
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3413 if (ar9300_eeprom_restore_internal(ah, mptr,
3414 sizeof(struct ar9300_eeprom)) < 0)
3415 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3416
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3417 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3418}
3419
3420/* XXX: review hardware docs */
3421static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3422{
3423 return ah->eeprom.ar9300_eep.eepromVersion;
3424}
3425
3426/* XXX: could be read from the eepromVersion, not sure yet */
3427static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3428{
3429 return 0;
3430}
3431
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3432static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3433{
3434 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3435
3436 if (is2ghz)
3437 return eep->modalHeader2G.xpaBiasLvl;
3438 else
3439 return eep->modalHeader5G.xpaBiasLvl;
3440}
3441
3442static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3443{
3444 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3445
3446 if (AR_SREV_9485(ah))
3447 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3448 else {
3449 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3450 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
3451 bias >> 2);
3452 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3453 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3454}
3455
3456static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3457{
3458 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3459 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3460
3461 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3462 val = eep->modalHeader2G.antCtrlCommon;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3463 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3464 val = eep->modalHeader5G.antCtrlCommon;
3465 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3466}
3467
3468static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3469{
3470 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3471 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3472
3473 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3474 val = eep->modalHeader2G.antCtrlCommon2;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3475 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3476 val = eep->modalHeader5G.antCtrlCommon2;
3477 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3478}
3479
3480static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3481 int chain,
3482 bool is2ghz)
3483{
3484 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3485 __le16 val = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3486
3487 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3488 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3489 val = eep->modalHeader2G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3490 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3491 val = eep->modalHeader5G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3492 }
3493
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3494 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3495}
3496
3497static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3498{
3499 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3500 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3501
3502 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3503 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3504
3505 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3506 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3507
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3508 if (!AR_SREV_9485(ah)) {
3509 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3510 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
3511 value);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3512
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3513 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3514 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
3515 value);
3516 }
3517
3518 if (AR_SREV_9485(ah)) {
3519 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3520 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3521 value);
3522 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3523 value >> 6);
3524 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3525 value >> 7);
3526 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3527}
3528
3529static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3530{
3531 int drive_strength;
3532 unsigned long reg;
3533
3534 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3535
3536 if (!drive_strength)
3537 return;
3538
3539 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3540 reg &= ~0x00ffffc0;
3541 reg |= 0x5 << 21;
3542 reg |= 0x5 << 18;
3543 reg |= 0x5 << 15;
3544 reg |= 0x5 << 12;
3545 reg |= 0x5 << 9;
3546 reg |= 0x5 << 6;
3547 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3548
3549 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3550 reg &= ~0xffffffe0;
3551 reg |= 0x5 << 29;
3552 reg |= 0x5 << 26;
3553 reg |= 0x5 << 23;
3554 reg |= 0x5 << 20;
3555 reg |= 0x5 << 17;
3556 reg |= 0x5 << 14;
3557 reg |= 0x5 << 11;
3558 reg |= 0x5 << 8;
3559 reg |= 0x5 << 5;
3560 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3561
3562 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3563 reg &= ~0xff800000;
3564 reg |= 0x5 << 29;
3565 reg |= 0x5 << 26;
3566 reg |= 0x5 << 23;
3567 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3568}
3569
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3570static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3571 struct ath9k_channel *chan)
3572{
3573 int f[3], t[3];
3574 u16 value;
3575 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3576
3577 if (chain >= 0 && chain < 3) {
3578 if (IS_CHAN_2GHZ(chan))
3579 return eep->modalHeader2G.xatten1DB[chain];
3580 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3581 t[0] = eep->base_ext2.xatten1DBLow[chain];
3582 f[0] = 5180;
3583 t[1] = eep->modalHeader5G.xatten1DB[chain];
3584 f[1] = 5500;
3585 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3586 f[2] = 5785;
3587 value = ar9003_hw_power_interpolate((s32) chan->channel,
3588 f, t, 3);
3589 return value;
3590 } else
3591 return eep->modalHeader5G.xatten1DB[chain];
3592 }
3593
3594 return 0;
3595}
3596
3597
3598static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3599 struct ath9k_channel *chan)
3600{
3601 int f[3], t[3];
3602 u16 value;
3603 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3604
3605 if (chain >= 0 && chain < 3) {
3606 if (IS_CHAN_2GHZ(chan))
3607 return eep->modalHeader2G.xatten1Margin[chain];
3608 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3609 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3610 f[0] = 5180;
3611 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3612 f[1] = 5500;
3613 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3614 f[2] = 5785;
3615 value = ar9003_hw_power_interpolate((s32) chan->channel,
3616 f, t, 3);
3617 return value;
3618 } else
3619 return eep->modalHeader5G.xatten1Margin[chain];
3620 }
3621
3622 return 0;
3623}
3624
3625static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3626{
3627 int i;
3628 u16 value;
3629 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3630 AR_PHY_EXT_ATTEN_CTL_1,
3631 AR_PHY_EXT_ATTEN_CTL_2,
3632 };
3633
3634 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3635 for (i = 0; i < 3; i++) {
3636 value = ar9003_hw_atten_chain_get(ah, i, chan);
3637 REG_RMW_FIELD(ah, ext_atten_reg[i],
3638 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3639
3640 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3641 REG_RMW_FIELD(ah, ext_atten_reg[i],
3642 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3643 }
3644}
3645
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3646static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3647{
3648 int timeout = 100;
3649
3650 while (pmu_set != REG_READ(ah, pmu_reg)) {
3651 if (timeout-- == 0)
3652 return false;
3653 REG_WRITE(ah, pmu_reg, pmu_set);
3654 udelay(10);
3655 }
3656
3657 return true;
3658}
3659
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3660static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3661{
3662 int internal_regulator =
3663 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3664
3665 if (internal_regulator) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3666 if (AR_SREV_9485(ah)) {
3667 int reg_pmu_set;
3668
3669 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3670 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3671 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3672 return;
3673
3674 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3675 (7 << 14) | (6 << 17) | (1 << 20) |
3676 (3 << 24) | (1 << 28);
3677
3678 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3679 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3680 return;
3681
3682 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3683 | (4 << 26);
3684 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3685 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3686 return;
3687
3688 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3689 | (1 << 21);
3690 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3691 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3692 return;
3693 } else {
3694 /* Internal regulator is ON. Write swreg register. */
3695 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3696 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3697 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3698 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3699 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3700 /* Set REG_CONTROL1.SWREG_PROGRAM */
3701 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3702 REG_READ(ah,
3703 AR_RTC_REG_CONTROL1) |
3704 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3705 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3706 } else {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3707 if (AR_SREV_9485(ah)) {
3708 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3709 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3710 AR_PHY_PMU2_PGM))
3711 udelay(10);
3712
3713 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3714 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3715 AR_PHY_PMU1_PWD))
3716 udelay(10);
3717 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3718 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3719 AR_PHY_PMU2_PGM))
3720 udelay(10);
3721 } else
3722 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3723 (REG_READ(ah,
3724 AR_RTC_SLEEP_CLK) |
3725 AR_RTC_FORCE_SWREG_PRD));
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3726 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3727
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3728}
3729
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3730static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3731{
3732 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3733 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3734
3735 if (eep->baseEepHeader.featureEnable & 0x40) {
3736 tuning_caps_param &= 0x7f;
3737 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3738 tuning_caps_param);
3739 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3740 tuning_caps_param);
3741 }
3742}
3743
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3744static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3745 struct ath9k_channel *chan)
3746{
3747 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3748 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3749 ar9003_hw_drive_strength_apply(ah);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3750 ar9003_hw_atten_apply(ah, chan);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3751 ar9003_hw_internal_regulator_apply(ah);
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3752 if (AR_SREV_9485(ah))
3753 ar9003_hw_apply_tuning_caps(ah);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3754}
3755
3756static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3757 struct ath9k_channel *chan)
3758{
3759}
3760
3761/*
3762 * Returns the interpolated y value corresponding to the specified x value
3763 * from the np ordered pairs of data (px,py).
3764 * The pairs do not have to be in any order.
3765 * If the specified x value is less than any of the px,
3766 * the returned y value is equal to the py for the lowest px.
3767 * If the specified x value is greater than any of the px,
3768 * the returned y value is equal to the py for the highest px.
3769 */
3770static int ar9003_hw_power_interpolate(int32_t x,
3771 int32_t *px, int32_t *py, u_int16_t np)
3772{
3773 int ip = 0;
3774 int lx = 0, ly = 0, lhave = 0;
3775 int hx = 0, hy = 0, hhave = 0;
3776 int dx = 0;
3777 int y = 0;
3778
3779 lhave = 0;
3780 hhave = 0;
3781
3782 /* identify best lower and higher x calibration measurement */
3783 for (ip = 0; ip < np; ip++) {
3784 dx = x - px[ip];
3785
3786 /* this measurement is higher than our desired x */
3787 if (dx <= 0) {
3788 if (!hhave || dx > (x - hx)) {
3789 /* new best higher x measurement */
3790 hx = px[ip];
3791 hy = py[ip];
3792 hhave = 1;
3793 }
3794 }
3795 /* this measurement is lower than our desired x */
3796 if (dx >= 0) {
3797 if (!lhave || dx < (x - lx)) {
3798 /* new best lower x measurement */
3799 lx = px[ip];
3800 ly = py[ip];
3801 lhave = 1;
3802 }
3803 }
3804 }
3805
3806 /* the low x is good */
3807 if (lhave) {
3808 /* so is the high x */
3809 if (hhave) {
3810 /* they're the same, so just pick one */
3811 if (hx == lx)
3812 y = ly;
3813 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]3814 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3815 } else /* only low is good, use it */
3816 y = ly;
3817 } else if (hhave) /* only high is good, use it */
3818 y = hy;
3819 else /* nothing is good,this should never happen unless np=0, ???? */
3820 y = -(1 << 30);
3821 return y;
3822}
3823
3824static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3825 u16 rateIndex, u16 freq, bool is2GHz)
3826{
3827 u16 numPiers, i;
3828 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3829 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3830 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3831 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3832 u8 *pFreqBin;
3833
3834 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3835 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3836 pEepromTargetPwr = eep->calTargetPower2G;
3837 pFreqBin = eep->calTarget_freqbin_2G;
3838 } else {
3839 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3840 pEepromTargetPwr = eep->calTargetPower5G;
3841 pFreqBin = eep->calTarget_freqbin_5G;
3842 }
3843
3844 /*
3845 * create array of channels and targetpower from
3846 * targetpower piers stored on eeprom
3847 */
3848 for (i = 0; i < numPiers; i++) {
3849 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3850 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3851 }
3852
3853 /* interpolate to get target power for given frequency */
3854 return (u8) ar9003_hw_power_interpolate((s32) freq,
3855 freqArray,
3856 targetPowerArray, numPiers);
3857}
3858
3859static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3860 u16 rateIndex,
3861 u16 freq, bool is2GHz)
3862{
3863 u16 numPiers, i;
3864 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3865 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3866 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3867 struct cal_tgt_pow_ht *pEepromTargetPwr;
3868 u8 *pFreqBin;
3869
3870 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]3871 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3872 pEepromTargetPwr = eep->calTargetPower2GHT20;
3873 pFreqBin = eep->calTarget_freqbin_2GHT20;
3874 } else {
3875 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3876 pEepromTargetPwr = eep->calTargetPower5GHT20;
3877 pFreqBin = eep->calTarget_freqbin_5GHT20;
3878 }
3879
3880 /*
3881 * create array of channels and targetpower
3882 * from targetpower piers stored on eeprom
3883 */
3884 for (i = 0; i < numPiers; i++) {
3885 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3886 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3887 }
3888
3889 /* interpolate to get target power for given frequency */
3890 return (u8) ar9003_hw_power_interpolate((s32) freq,
3891 freqArray,
3892 targetPowerArray, numPiers);
3893}
3894
3895static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3896 u16 rateIndex,
3897 u16 freq, bool is2GHz)
3898{
3899 u16 numPiers, i;
3900 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3901 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3902 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3903 struct cal_tgt_pow_ht *pEepromTargetPwr;
3904 u8 *pFreqBin;
3905
3906 if (is2GHz) {
3907 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3908 pEepromTargetPwr = eep->calTargetPower2GHT40;
3909 pFreqBin = eep->calTarget_freqbin_2GHT40;
3910 } else {
3911 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3912 pEepromTargetPwr = eep->calTargetPower5GHT40;
3913 pFreqBin = eep->calTarget_freqbin_5GHT40;
3914 }
3915
3916 /*
3917 * create array of channels and targetpower from
3918 * targetpower piers stored on eeprom
3919 */
3920 for (i = 0; i < numPiers; i++) {
3921 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3922 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3923 }
3924
3925 /* interpolate to get target power for given frequency */
3926 return (u8) ar9003_hw_power_interpolate((s32) freq,
3927 freqArray,
3928 targetPowerArray, numPiers);
3929}
3930
3931static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3932 u16 rateIndex, u16 freq)
3933{
3934 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3935 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3936 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3937 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3938 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3939 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3940
3941 /*
3942 * create array of channels and targetpower from
3943 * targetpower piers stored on eeprom
3944 */
3945 for (i = 0; i < numPiers; i++) {
3946 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3947 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3948 }
3949
3950 /* interpolate to get target power for given frequency */
3951 return (u8) ar9003_hw_power_interpolate((s32) freq,
3952 freqArray,
3953 targetPowerArray, numPiers);
3954}
3955
3956/* Set tx power registers to array of values passed in */
3957static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3958{
3959#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3960 /* make sure forced gain is not set */
3961 REG_WRITE(ah, 0xa458, 0);
3962
3963 /* Write the OFDM power per rate set */
3964
3965 /* 6 (LSB), 9, 12, 18 (MSB) */
3966 REG_WRITE(ah, 0xa3c0,
3967 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3968 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3969 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3970 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3971
3972 /* 24 (LSB), 36, 48, 54 (MSB) */
3973 REG_WRITE(ah, 0xa3c4,
3974 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3975 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3976 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3977 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3978
3979 /* Write the CCK power per rate set */
3980
3981 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3982 REG_WRITE(ah, 0xa3c8,
3983 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3984 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3985 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3986 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3987
3988 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3989 REG_WRITE(ah, 0xa3cc,
3990 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3991 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3992 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3993 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3994 );
3995
3996 /* Write the HT20 power per rate set */
3997
3998 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3999 REG_WRITE(ah, 0xa3d0,
4000 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4001 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4002 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4003 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4004 );
4005
4006 /* 6 (LSB), 7, 12, 13 (MSB) */
4007 REG_WRITE(ah, 0xa3d4,
4008 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4009 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4010 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4011 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4012 );
4013
4014 /* 14 (LSB), 15, 20, 21 */
4015 REG_WRITE(ah, 0xa3e4,
4016 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4017 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4018 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4019 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4020 );
4021
4022 /* Mixed HT20 and HT40 rates */
4023
4024 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4025 REG_WRITE(ah, 0xa3e8,
4026 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4027 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4028 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4029 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4030 );
4031
4032 /*
4033 * Write the HT40 power per rate set
4034 * correct PAR difference between HT40 and HT20/LEGACY
4035 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4036 */
4037 REG_WRITE(ah, 0xa3d8,
4038 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4039 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4040 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4041 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4042 );
4043
4044 /* 6 (LSB), 7, 12, 13 (MSB) */
4045 REG_WRITE(ah, 0xa3dc,
4046 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4047 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4048 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4049 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4050 );
4051
4052 /* 14 (LSB), 15, 20, 21 */
4053 REG_WRITE(ah, 0xa3ec,
4054 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4055 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4056 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4057 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4058 );
4059
4060 return 0;
4061#undef POW_SM
4062}
4063
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4064static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4065 u8 *targetPowerValT2)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4066{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4067 /* XXX: hard code for now, need to get from eeprom struct */
4068 u8 ht40PowerIncForPdadc = 0;
4069 bool is2GHz = false;
4070 unsigned int i = 0;
4071 struct ath_common *common = ath9k_hw_common(ah);
4072
4073 if (freq < 4000)
4074 is2GHz = true;
4075
4076 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4077 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4078 is2GHz);
4079 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4080 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4081 is2GHz);
4082 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4083 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4084 is2GHz);
4085 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4086 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4087 is2GHz);
4088 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4089 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4090 freq);
4091 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4092 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4093 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4094 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4095 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4096 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4097 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4098 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4099 is2GHz);
4100 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4101 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4102 freq, is2GHz);
4103 targetPowerValT2[ALL_TARGET_HT20_4] =
4104 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4105 is2GHz);
4106 targetPowerValT2[ALL_TARGET_HT20_5] =
4107 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4108 is2GHz);
4109 targetPowerValT2[ALL_TARGET_HT20_6] =
4110 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4111 is2GHz);
4112 targetPowerValT2[ALL_TARGET_HT20_7] =
4113 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4114 is2GHz);
4115 targetPowerValT2[ALL_TARGET_HT20_12] =
4116 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4117 is2GHz);
4118 targetPowerValT2[ALL_TARGET_HT20_13] =
4119 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4120 is2GHz);
4121 targetPowerValT2[ALL_TARGET_HT20_14] =
4122 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4123 is2GHz);
4124 targetPowerValT2[ALL_TARGET_HT20_15] =
4125 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4126 is2GHz);
4127 targetPowerValT2[ALL_TARGET_HT20_20] =
4128 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4129 is2GHz);
4130 targetPowerValT2[ALL_TARGET_HT20_21] =
4131 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4132 is2GHz);
4133 targetPowerValT2[ALL_TARGET_HT20_22] =
4134 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4135 is2GHz);
4136 targetPowerValT2[ALL_TARGET_HT20_23] =
4137 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4138 is2GHz);
4139 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4140 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4141 is2GHz) + ht40PowerIncForPdadc;
4142 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4143 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4144 freq,
4145 is2GHz) + ht40PowerIncForPdadc;
4146 targetPowerValT2[ALL_TARGET_HT40_4] =
4147 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4148 is2GHz) + ht40PowerIncForPdadc;
4149 targetPowerValT2[ALL_TARGET_HT40_5] =
4150 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4151 is2GHz) + ht40PowerIncForPdadc;
4152 targetPowerValT2[ALL_TARGET_HT40_6] =
4153 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4154 is2GHz) + ht40PowerIncForPdadc;
4155 targetPowerValT2[ALL_TARGET_HT40_7] =
4156 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4157 is2GHz) + ht40PowerIncForPdadc;
4158 targetPowerValT2[ALL_TARGET_HT40_12] =
4159 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4160 is2GHz) + ht40PowerIncForPdadc;
4161 targetPowerValT2[ALL_TARGET_HT40_13] =
4162 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4163 is2GHz) + ht40PowerIncForPdadc;
4164 targetPowerValT2[ALL_TARGET_HT40_14] =
4165 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4166 is2GHz) + ht40PowerIncForPdadc;
4167 targetPowerValT2[ALL_TARGET_HT40_15] =
4168 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4169 is2GHz) + ht40PowerIncForPdadc;
4170 targetPowerValT2[ALL_TARGET_HT40_20] =
4171 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4172 is2GHz) + ht40PowerIncForPdadc;
4173 targetPowerValT2[ALL_TARGET_HT40_21] =
4174 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4175 is2GHz) + ht40PowerIncForPdadc;
4176 targetPowerValT2[ALL_TARGET_HT40_22] =
4177 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4178 is2GHz) + ht40PowerIncForPdadc;
4179 targetPowerValT2[ALL_TARGET_HT40_23] =
4180 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4181 is2GHz) + ht40PowerIncForPdadc;
4182
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4183 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4184 ath_dbg(common, ATH_DBG_EEPROM,
4185 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4186 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4187}
4188
4189static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4190 int mode,
4191 int ipier,
4192 int ichain,
4193 int *pfrequency,
4194 int *pcorrection,
4195 int *ptemperature, int *pvoltage)
4196{
4197 u8 *pCalPier;
4198 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4199 int is2GHz;
4200 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4201 struct ath_common *common = ath9k_hw_common(ah);
4202
4203 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4204 ath_dbg(common, ATH_DBG_EEPROM,
4205 "Invalid chain index, must be less than %d\n",
4206 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4207 return -1;
4208 }
4209
4210 if (mode) { /* 5GHz */
4211 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4212 ath_dbg(common, ATH_DBG_EEPROM,
4213 "Invalid 5GHz cal pier index, must be less than %d\n",
4214 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4215 return -1;
4216 }
4217 pCalPier = &(eep->calFreqPier5G[ipier]);
4218 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4219 is2GHz = 0;
4220 } else {
4221 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4222 ath_dbg(common, ATH_DBG_EEPROM,
4223 "Invalid 2GHz cal pier index, must be less than %d\n",
4224 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4225 return -1;
4226 }
4227
4228 pCalPier = &(eep->calFreqPier2G[ipier]);
4229 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4230 is2GHz = 1;
4231 }
4232
4233 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4234 *pcorrection = pCalPierStruct->refPower;
4235 *ptemperature = pCalPierStruct->tempMeas;
4236 *pvoltage = pCalPierStruct->voltMeas;
4237
4238 return 0;
4239}
4240
4241static int ar9003_hw_power_control_override(struct ath_hw *ah,
4242 int frequency,
4243 int *correction,
4244 int *voltage, int *temperature)
4245{
4246 int tempSlope = 0;
4247 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4248 int f[3], t[3];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4249
4250 REG_RMW(ah, AR_PHY_TPC_11_B0,
4251 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4252 AR_PHY_TPC_OLPC_GAIN_DELTA);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4253 if (ah->caps.tx_chainmask & BIT(1))
4254 REG_RMW(ah, AR_PHY_TPC_11_B1,
4255 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4256 AR_PHY_TPC_OLPC_GAIN_DELTA);
4257 if (ah->caps.tx_chainmask & BIT(2))
4258 REG_RMW(ah, AR_PHY_TPC_11_B2,
4259 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4260 AR_PHY_TPC_OLPC_GAIN_DELTA);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4261
4262 /* enable open loop power control on chip */
4263 REG_RMW(ah, AR_PHY_TPC_6_B0,
4264 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4265 AR_PHY_TPC_6_ERROR_EST_MODE);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4266 if (ah->caps.tx_chainmask & BIT(1))
4267 REG_RMW(ah, AR_PHY_TPC_6_B1,
4268 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4269 AR_PHY_TPC_6_ERROR_EST_MODE);
4270 if (ah->caps.tx_chainmask & BIT(2))
4271 REG_RMW(ah, AR_PHY_TPC_6_B2,
4272 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4273 AR_PHY_TPC_6_ERROR_EST_MODE);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4274
4275 /*
4276 * enable temperature compensation
4277 * Need to use register names
4278 */
4279 if (frequency < 4000)
4280 tempSlope = eep->modalHeader2G.tempSlope;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4281 else if (eep->base_ext2.tempSlopeLow != 0) {
4282 t[0] = eep->base_ext2.tempSlopeLow;
4283 f[0] = 5180;
4284 t[1] = eep->modalHeader5G.tempSlope;
4285 f[1] = 5500;
4286 t[2] = eep->base_ext2.tempSlopeHigh;
4287 f[2] = 5785;
4288 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4289 f, t, 3);
4290 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4291 tempSlope = eep->modalHeader5G.tempSlope;
4292
4293 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4294 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4295 temperature[0]);
4296
4297 return 0;
4298}
4299
4300/* Apply the recorded correction values. */
4301static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4302{
4303 int ichain, ipier, npier;
4304 int mode;
4305 int lfrequency[AR9300_MAX_CHAINS],
4306 lcorrection[AR9300_MAX_CHAINS],
4307 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4308 int hfrequency[AR9300_MAX_CHAINS],
4309 hcorrection[AR9300_MAX_CHAINS],
4310 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4311 int fdiff;
4312 int correction[AR9300_MAX_CHAINS],
4313 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4314 int pfrequency, pcorrection, ptemperature, pvoltage;
4315 struct ath_common *common = ath9k_hw_common(ah);
4316
4317 mode = (frequency >= 4000);
4318 if (mode)
4319 npier = AR9300_NUM_5G_CAL_PIERS;
4320 else
4321 npier = AR9300_NUM_2G_CAL_PIERS;
4322
4323 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4324 lfrequency[ichain] = 0;
4325 hfrequency[ichain] = 100000;
4326 }
4327 /* identify best lower and higher frequency calibration measurement */
4328 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4329 for (ipier = 0; ipier < npier; ipier++) {
4330 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4331 &pfrequency, &pcorrection,
4332 &ptemperature, &pvoltage)) {
4333 fdiff = frequency - pfrequency;
4334
4335 /*
4336 * this measurement is higher than
4337 * our desired frequency
4338 */
4339 if (fdiff <= 0) {
4340 if (hfrequency[ichain] <= 0 ||
4341 hfrequency[ichain] >= 100000 ||
4342 fdiff >
4343 (frequency - hfrequency[ichain])) {
4344 /*
4345 * new best higher
4346 * frequency measurement
4347 */
4348 hfrequency[ichain] = pfrequency;
4349 hcorrection[ichain] =
4350 pcorrection;
4351 htemperature[ichain] =
4352 ptemperature;
4353 hvoltage[ichain] = pvoltage;
4354 }
4355 }
4356 if (fdiff >= 0) {
4357 if (lfrequency[ichain] <= 0
4358 || fdiff <
4359 (frequency - lfrequency[ichain])) {
4360 /*
4361 * new best lower
4362 * frequency measurement
4363 */
4364 lfrequency[ichain] = pfrequency;
4365 lcorrection[ichain] =
4366 pcorrection;
4367 ltemperature[ichain] =
4368 ptemperature;
4369 lvoltage[ichain] = pvoltage;
4370 }
4371 }
4372 }
4373 }
4374 }
4375
4376 /* interpolate */
4377 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4378 ath_dbg(common, ATH_DBG_EEPROM,
4379 "ch=%d f=%d low=%d %d h=%d %d\n",
4380 ichain, frequency, lfrequency[ichain],
4381 lcorrection[ichain], hfrequency[ichain],
4382 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4383 /* they're the same, so just pick one */
4384 if (hfrequency[ichain] == lfrequency[ichain]) {
4385 correction[ichain] = lcorrection[ichain];
4386 voltage[ichain] = lvoltage[ichain];
4387 temperature[ichain] = ltemperature[ichain];
4388 }
4389 /* the low frequency is good */
4390 else if (frequency - lfrequency[ichain] < 1000) {
4391 /* so is the high frequency, interpolate */
4392 if (hfrequency[ichain] - frequency < 1000) {
4393
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4394 correction[ichain] = interpolate(frequency,
4395 lfrequency[ichain],
4396 hfrequency[ichain],
4397 lcorrection[ichain],
4398 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4399
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4400 temperature[ichain] = interpolate(frequency,
4401 lfrequency[ichain],
4402 hfrequency[ichain],
4403 ltemperature[ichain],
4404 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4405
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4406 voltage[ichain] = interpolate(frequency,
4407 lfrequency[ichain],
4408 hfrequency[ichain],
4409 lvoltage[ichain],
4410 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4411 }
4412 /* only low is good, use it */
4413 else {
4414 correction[ichain] = lcorrection[ichain];
4415 temperature[ichain] = ltemperature[ichain];
4416 voltage[ichain] = lvoltage[ichain];
4417 }
4418 }
4419 /* only high is good, use it */
4420 else if (hfrequency[ichain] - frequency < 1000) {
4421 correction[ichain] = hcorrection[ichain];
4422 temperature[ichain] = htemperature[ichain];
4423 voltage[ichain] = hvoltage[ichain];
4424 } else { /* nothing is good, presume 0???? */
4425 correction[ichain] = 0;
4426 temperature[ichain] = 0;
4427 voltage[ichain] = 0;
4428 }
4429 }
4430
4431 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4432 temperature);
4433
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4434 ath_dbg(common, ATH_DBG_EEPROM,
4435 "for frequency=%d, calibration correction = %d %d %d\n",
4436 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4437
4438 return 0;
4439}
4440
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4441static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4442 int idx,
4443 int edge,
4444 bool is2GHz)
4445{
4446 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4447 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4448
4449 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4450 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4451 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4452 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4453}
4454
4455static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4456 int idx,
4457 unsigned int edge,
4458 u16 freq,
4459 bool is2GHz)
4460{
4461 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4462 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4463
4464 u8 *ctl_freqbin = is2GHz ?
4465 &eep->ctl_freqbin_2G[idx][0] :
4466 &eep->ctl_freqbin_5G[idx][0];
4467
4468 if (is2GHz) {
4469 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4470 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4471 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4472 } else {
4473 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4474 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4475 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4476 }
4477
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4478 return MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4479}
4480
4481/*
4482 * Find the maximum conformance test limit for the given channel and CTL info
4483 */
4484static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4485 u16 freq, int idx, bool is2GHz)
4486{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4487 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4488 u8 *ctl_freqbin = is2GHz ?
4489 &eep->ctl_freqbin_2G[idx][0] :
4490 &eep->ctl_freqbin_5G[idx][0];
4491 u16 num_edges = is2GHz ?
4492 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4493 unsigned int edge;
4494
4495 /* Get the edge power */
4496 for (edge = 0;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4497 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4498 edge++) {
4499 /*
4500 * If there's an exact channel match or an inband flag set
4501 * on the lower channel use the given rdEdgePower
4502 */
4503 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4504 twiceMaxEdgePower =
4505 ar9003_hw_get_direct_edge_power(eep, idx,
4506 edge, is2GHz);
4507 break;
4508 } else if ((edge > 0) &&
4509 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4510 is2GHz))) {
4511 twiceMaxEdgePower =
4512 ar9003_hw_get_indirect_edge_power(eep, idx,
4513 edge, freq,
4514 is2GHz);
4515 /*
4516 * Leave loop - no more affecting edges possible in
4517 * this monotonic increasing list
4518 */
4519 break;
4520 }
4521 }
4522 return twiceMaxEdgePower;
4523}
4524
4525static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4526 struct ath9k_channel *chan,
4527 u8 *pPwrArray, u16 cfgCtl,
4528 u8 twiceAntennaReduction,
4529 u8 twiceMaxRegulatoryPower,
4530 u16 powerLimit)
4531{
4532 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4533 struct ath_common *common = ath9k_hw_common(ah);
4534 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4535 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4536 static const u16 tpScaleReductionTable[5] = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4537 0, 3, 6, 9, MAX_RATE_POWER
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4538 };
4539 int i;
4540 int16_t twiceLargestAntenna;
4541 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4542 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4543 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4544 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4545 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4546 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4547 CTL_11G_EXT, CTL_2GHT40
4548 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4549 u16 numCtlModes;
4550 const u16 *pCtlMode;
4551 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4552 struct chan_centers centers;
4553 u8 *ctlIndex;
4554 u8 ctlNum;
4555 u16 twiceMinEdgePower;
4556 bool is2ghz = IS_CHAN_2GHZ(chan);
4557
4558 ath9k_hw_get_channel_centers(ah, chan, &centers);
4559
4560 /* Compute TxPower reduction due to Antenna Gain */
4561 if (is2ghz)
4562 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4563 else
4564 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4565
4566 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4567 twiceLargestAntenna, 0);
4568
4569 /*
4570 * scaledPower is the minimum of the user input power level
4571 * and the regulatory allowed power level
4572 */
4573 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4574
4575 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4576 maxRegAllowedPower -=
4577 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4578 }
4579
4580 scaledPower = min(powerLimit, maxRegAllowedPower);
4581
4582 /*
4583 * Reduce scaled Power by number of chains active to get
4584 * to per chain tx power level
4585 */
4586 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4587 case 1:
4588 break;
4589 case 2:
4590 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4591 break;
4592 case 3:
4593 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4594 break;
4595 }
4596
4597 scaledPower = max((u16)0, scaledPower);
4598
4599 /*
4600 * Get target powers from EEPROM - our baseline for TX Power
4601 */
4602 if (is2ghz) {
4603 /* Setup for CTL modes */
4604 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4605 numCtlModes =
4606 ARRAY_SIZE(ctlModesFor11g) -
4607 SUB_NUM_CTL_MODES_AT_2G_40;
4608 pCtlMode = ctlModesFor11g;
4609 if (IS_CHAN_HT40(chan))
4610 /* All 2G CTL's */
4611 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4612 } else {
4613 /* Setup for CTL modes */
4614 /* CTL_11A, CTL_5GHT20 */
4615 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4616 SUB_NUM_CTL_MODES_AT_5G_40;
4617 pCtlMode = ctlModesFor11a;
4618 if (IS_CHAN_HT40(chan))
4619 /* All 5G CTL's */
4620 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4621 }
4622
4623 /*
4624 * For MIMO, need to apply regulatory caps individually across
4625 * dynamically running modes: CCK, OFDM, HT20, HT40
4626 *
4627 * The outer loop walks through each possible applicable runtime mode.
4628 * The inner loop walks through each ctlIndex entry in EEPROM.
4629 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4630 */
4631 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4632 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4633 (pCtlMode[ctlMode] == CTL_2GHT40);
4634 if (isHt40CtlMode)
4635 freq = centers.synth_center;
4636 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4637 freq = centers.ext_center;
4638 else
4639 freq = centers.ctl_center;
4640
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4641 ath_dbg(common, ATH_DBG_REGULATORY,
4642 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4643 ctlMode, numCtlModes, isHt40CtlMode,
4644 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4645
4646 /* walk through each CTL index stored in EEPROM */
4647 if (is2ghz) {
4648 ctlIndex = pEepData->ctlIndex_2G;
4649 ctlNum = AR9300_NUM_CTLS_2G;
4650 } else {
4651 ctlIndex = pEepData->ctlIndex_5G;
4652 ctlNum = AR9300_NUM_CTLS_5G;
4653 }
4654
4655 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4656 ath_dbg(common, ATH_DBG_REGULATORY,
4657 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4658 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4659 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4660
4661 /*
4662 * compare test group from regulatory
4663 * channel list with test mode from pCtlMode
4664 * list
4665 */
4666 if ((((cfgCtl & ~CTL_MODE_M) |
4667 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4668 ctlIndex[i]) ||
4669 (((cfgCtl & ~CTL_MODE_M) |
4670 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4671 ((ctlIndex[i] & CTL_MODE_M) |
4672 SD_NO_CTL))) {
4673 twiceMinEdgePower =
4674 ar9003_hw_get_max_edge_power(pEepData,
4675 freq, i,
4676 is2ghz);
4677
4678 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4679 /*
4680 * Find the minimum of all CTL
4681 * edge powers that apply to
4682 * this channel
4683 */
4684 twiceMaxEdgePower =
4685 min(twiceMaxEdgePower,
4686 twiceMinEdgePower);
4687 else {
4688 /* specific */
4689 twiceMaxEdgePower =
4690 twiceMinEdgePower;
4691 break;
4692 }
4693 }
4694 }
4695
4696 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4697
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4698 ath_dbg(common, ATH_DBG_REGULATORY,
4699 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4700 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4701 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4702
4703 /* Apply ctl mode to correct target power set */
4704 switch (pCtlMode[ctlMode]) {
4705 case CTL_11B:
4706 for (i = ALL_TARGET_LEGACY_1L_5L;
4707 i <= ALL_TARGET_LEGACY_11S; i++)
4708 pPwrArray[i] =
4709 (u8)min((u16)pPwrArray[i],
4710 minCtlPower);
4711 break;
4712 case CTL_11A:
4713 case CTL_11G:
4714 for (i = ALL_TARGET_LEGACY_6_24;
4715 i <= ALL_TARGET_LEGACY_54; i++)
4716 pPwrArray[i] =
4717 (u8)min((u16)pPwrArray[i],
4718 minCtlPower);
4719 break;
4720 case CTL_5GHT20:
4721 case CTL_2GHT20:
4722 for (i = ALL_TARGET_HT20_0_8_16;
4723 i <= ALL_TARGET_HT20_21; i++)
4724 pPwrArray[i] =
4725 (u8)min((u16)pPwrArray[i],
4726 minCtlPower);
4727 pPwrArray[ALL_TARGET_HT20_22] =
4728 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4729 minCtlPower);
4730 pPwrArray[ALL_TARGET_HT20_23] =
4731 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4732 minCtlPower);
4733 break;
4734 case CTL_5GHT40:
4735 case CTL_2GHT40:
4736 for (i = ALL_TARGET_HT40_0_8_16;
4737 i <= ALL_TARGET_HT40_23; i++)
4738 pPwrArray[i] =
4739 (u8)min((u16)pPwrArray[i],
4740 minCtlPower);
4741 break;
4742 default:
4743 break;
4744 }
4745 } /* end ctl mode checking */
4746}
4747
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4748static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4749{
4750 u8 mod_idx = mcs_idx % 8;
4751
4752 if (mod_idx <= 3)
4753 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4754 else
4755 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4756}
4757
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4758static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4759 struct ath9k_channel *chan, u16 cfgCtl,
4760 u8 twiceAntennaReduction,
4761 u8 twiceMaxRegulatoryPower,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4762 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4763{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]4764 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4765 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4766 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4767 struct ar9300_modal_eep_header *modal_hdr;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4768 u8 targetPowerValT2[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4769 u8 target_power_val_t2_eep[ar9300RateSize];
4770 unsigned int i = 0, paprd_scale_factor = 0;
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4771 u8 pwr_idx, min_pwridx = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4772
4773 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4774
4775 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4776 if (IS_CHAN_2GHZ(chan))
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4777 modal_hdr = &eep->modalHeader2G;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4778 else
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4779 modal_hdr = &eep->modalHeader5G;
4780
4781 ah->paprd_ratemask =
4782 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4783 AR9300_PAPRD_RATE_MASK;
4784
4785 ah->paprd_ratemask_ht40 =
4786 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4787 AR9300_PAPRD_RATE_MASK;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4788
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4789 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4790 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4791 ALL_TARGET_HT20_0_8_16;
4792
4793 if (!ah->paprd_table_write_done) {
4794 memcpy(target_power_val_t2_eep, targetPowerValT2,
4795 sizeof(targetPowerValT2));
4796 for (i = 0; i < 24; i++) {
4797 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4798 if (ah->paprd_ratemask & (1 << i)) {
4799 if (targetPowerValT2[pwr_idx] &&
4800 targetPowerValT2[pwr_idx] ==
4801 target_power_val_t2_eep[pwr_idx])
4802 targetPowerValT2[pwr_idx] -=
4803 paprd_scale_factor;
4804 }
4805 }
4806 }
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4807 memcpy(target_power_val_t2_eep, targetPowerValT2,
4808 sizeof(targetPowerValT2));
4809 }
4810
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4811 ar9003_hw_set_power_per_rate_table(ah, chan,
4812 targetPowerValT2, cfgCtl,
4813 twiceAntennaReduction,
4814 twiceMaxRegulatoryPower,
4815 powerLimit);
4816
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4817 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4818 for (i = 0; i < ar9300RateSize; i++) {
4819 if ((ah->paprd_ratemask & (1 << i)) &&
4820 (abs(targetPowerValT2[i] -
4821 target_power_val_t2_eep[i]) >
4822 paprd_scale_factor)) {
4823 ah->paprd_ratemask &= ~(1 << i);
4824 ath_dbg(common, ATH_DBG_EEPROM,
4825 "paprd disabled for mcs %d\n", i);
4826 }
4827 }
4828 }
4829
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4830 regulatory->max_power_level = 0;
4831 for (i = 0; i < ar9300RateSize; i++) {
4832 if (targetPowerValT2[i] > regulatory->max_power_level)
4833 regulatory->max_power_level = targetPowerValT2[i];
4834 }
4835
4836 if (test)
4837 return;
4838
4839 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4840 ath_dbg(common, ATH_DBG_EEPROM,
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4841 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4842 }
4843
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4844 /*
4845 * This is the TX power we send back to driver core,
4846 * and it can use to pass to userspace to display our
4847 * currently configured TX power setting.
4848 *
4849 * Since power is rate dependent, use one of the indices
4850 * from the AR9300_Rates enum to select an entry from
4851 * targetPowerValT2[] to report. Currently returns the
4852 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4853 * as CCK power is less interesting (?).
4854 */
4855 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4856 if (IS_CHAN_HT40(chan))
4857 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4858 else if (IS_CHAN_HT20(chan))
4859 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4860
4861 ah->txpower_limit = targetPowerValT2[i];
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4862 regulatory->max_power_level = targetPowerValT2[i];
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4863
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4864 /* Write target power array to registers */
4865 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4866 ar9003_hw_calibration_apply(ah, chan->channel);
Felix Fietkau1bf38662010-12-13 08:40:54 +0100[diff] [blame]4867
4868 if (IS_CHAN_2GHZ(chan)) {
4869 if (IS_CHAN_HT40(chan))
4870 i = ALL_TARGET_HT40_0_8_16;
4871 else
4872 i = ALL_TARGET_HT20_0_8_16;
4873 } else {
4874 if (IS_CHAN_HT40(chan))
4875 i = ALL_TARGET_HT40_7;
4876 else
4877 i = ALL_TARGET_HT20_7;
4878 }
4879 ah->paprd_target_power = targetPowerValT2[i];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4880}
4881
4882static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4883 u16 i, bool is2GHz)
4884{
4885 return AR_NO_SPUR;
4886}
4887
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]4888s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4889{
4890 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4891
4892 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4893}
4894
4895s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4896{
4897 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4898
4899 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4900}
4901
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]4902u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4903{
4904 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4905
4906 if (is_2ghz)
4907 return eep->modalHeader2G.spurChans;
4908 else
4909 return eep->modalHeader5G.spurChans;
4910}
4911
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]4912unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4913 struct ath9k_channel *chan)
4914{
4915 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4916
4917 if (IS_CHAN_2GHZ(chan))
4918 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
4919 AR9300_PAPRD_SCALE_1);
4920 else {
4921 if (chan->channel >= 5700)
4922 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
4923 AR9300_PAPRD_SCALE_1);
4924 else if (chan->channel >= 5400)
4925 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4926 AR9300_PAPRD_SCALE_2);
4927 else
4928 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4929 AR9300_PAPRD_SCALE_1);
4930 }
4931}
4932
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4933const struct eeprom_ops eep_ar9300_ops = {
4934 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4935 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4936 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4937 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4938 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4939 .set_board_values = ath9k_hw_ar9300_set_board_values,
4940 .set_addac = ath9k_hw_ar9300_set_addac,
4941 .set_txpower = ath9k_hw_ar9300_set_txpower,
4942 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4943};