Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * PHY functions |
| 3 | * |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 4 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
Nick Kossifidis | 33a3182 | 2009-02-09 06:00:34 +0200 | [diff] [blame] | 5 | * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 6 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 7 | * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 8 | * |
| 9 | * Permission to use, copy, modify, and distribute this software for any |
| 10 | * purpose with or without fee is hereby granted, provided that the above |
| 11 | * copyright notice and this permission notice appear in all copies. |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 20 | * |
| 21 | */ |
| 22 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 23 | #define _ATH5K_PHY |
| 24 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 25 | #include <linux/delay.h> |
| 26 | |
| 27 | #include "ath5k.h" |
| 28 | #include "reg.h" |
| 29 | #include "base.h" |
Nick Kossifidis | 33a3182 | 2009-02-09 06:00:34 +0200 | [diff] [blame] | 30 | #include "rfbuffer.h" |
| 31 | #include "rfgain.h" |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * Used to modify RF Banks before writing them to AR5K_RF_BUFFER |
| 35 | */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 36 | static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, |
| 37 | const struct ath5k_rf_reg *rf_regs, |
| 38 | u32 val, u8 reg_id, bool set) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 39 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 40 | const struct ath5k_rf_reg *rfreg = NULL; |
| 41 | u8 offset, bank, num_bits, col, position; |
| 42 | u16 entry; |
| 43 | u32 mask, data, last_bit, bits_shifted, first_bit; |
| 44 | u32 *rfb; |
| 45 | s32 bits_left; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 46 | int i; |
| 47 | |
| 48 | data = 0; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 49 | rfb = ah->ah_rf_banks; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 50 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 51 | for (i = 0; i < ah->ah_rf_regs_count; i++) { |
| 52 | if (rf_regs[i].index == reg_id) { |
| 53 | rfreg = &rf_regs[i]; |
| 54 | break; |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | if (rfb == NULL || rfreg == NULL) { |
| 59 | ATH5K_PRINTF("Rf register not found!\n"); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 60 | /* should not happen */ |
| 61 | return 0; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 62 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 63 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 64 | bank = rfreg->bank; |
| 65 | num_bits = rfreg->field.len; |
| 66 | first_bit = rfreg->field.pos; |
| 67 | col = rfreg->field.col; |
| 68 | |
| 69 | /* first_bit is an offset from bank's |
| 70 | * start. Since we have all banks on |
| 71 | * the same array, we use this offset |
| 72 | * to mark each bank's start */ |
| 73 | offset = ah->ah_offset[bank]; |
| 74 | |
| 75 | /* Boundary check */ |
| 76 | if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 77 | ATH5K_PRINTF("invalid values at offset %u\n", offset); |
| 78 | return 0; |
| 79 | } |
| 80 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 81 | entry = ((first_bit - 1) / 8) + offset; |
| 82 | position = (first_bit - 1) % 8; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 83 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 84 | if (set) |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 85 | data = ath5k_hw_bitswap(val, num_bits); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 86 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 87 | for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; |
| 88 | position = 0, entry++) { |
| 89 | |
| 90 | last_bit = (position + bits_left > 8) ? 8 : |
| 91 | position + bits_left; |
| 92 | |
| 93 | mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << |
| 94 | (col * 8); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 95 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 96 | if (set) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 97 | rfb[entry] &= ~mask; |
| 98 | rfb[entry] |= ((data << position) << (col * 8)) & mask; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 99 | data >>= (8 - position); |
| 100 | } else { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 101 | data |= (((rfb[entry] & mask) >> (col * 8)) >> position) |
| 102 | << bits_shifted; |
| 103 | bits_shifted += last_bit - position; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 104 | } |
| 105 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 106 | bits_left -= 8 - position; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 107 | } |
| 108 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 109 | data = set ? 1 : ath5k_hw_bitswap(data, num_bits); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 110 | |
| 111 | return data; |
| 112 | } |
| 113 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 114 | /**********************\ |
| 115 | * RF Gain optimization * |
| 116 | \**********************/ |
| 117 | |
| 118 | /* |
| 119 | * This code is used to optimize rf gain on different environments |
| 120 | * (temprature mostly) based on feedback from a power detector. |
| 121 | * |
| 122 | * It's only used on RF5111 and RF5112, later RF chips seem to have |
| 123 | * auto adjustment on hw -notice they have a much smaller BANK 7 and |
| 124 | * no gain optimization ladder-. |
| 125 | * |
| 126 | * For more infos check out this patent doc |
| 127 | * http://www.freepatentsonline.com/7400691.html |
| 128 | * |
| 129 | * This paper describes power drops as seen on the receiver due to |
| 130 | * probe packets |
| 131 | * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues |
| 132 | * %20of%20Power%20Control.pdf |
| 133 | * |
| 134 | * And this is the MadWiFi bug entry related to the above |
| 135 | * http://madwifi-project.org/ticket/1659 |
| 136 | * with various measurements and diagrams |
| 137 | * |
| 138 | * TODO: Deal with power drops due to probes by setting an apropriate |
| 139 | * tx power on the probe packets ! Make this part of the calibration process. |
| 140 | */ |
| 141 | |
| 142 | /* Initialize ah_gain durring attach */ |
| 143 | int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) |
| 144 | { |
| 145 | /* Initialize the gain optimization values */ |
| 146 | switch (ah->ah_radio) { |
| 147 | case AR5K_RF5111: |
| 148 | ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; |
| 149 | ah->ah_gain.g_low = 20; |
| 150 | ah->ah_gain.g_high = 35; |
| 151 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 152 | break; |
| 153 | case AR5K_RF5112: |
| 154 | ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; |
| 155 | ah->ah_gain.g_low = 20; |
| 156 | ah->ah_gain.g_high = 85; |
| 157 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 158 | break; |
| 159 | default: |
| 160 | return -EINVAL; |
| 161 | } |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | /* Schedule a gain probe check on the next transmited packet. |
| 167 | * That means our next packet is going to be sent with lower |
| 168 | * tx power and a Peak to Average Power Detector (PAPD) will try |
| 169 | * to measure the gain. |
| 170 | * |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 171 | * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) |
| 172 | * just after we enable the probe so that we don't mess with |
| 173 | * standard traffic ? Maybe it's time to use sw interrupts and |
| 174 | * a probe tasklet !!! |
| 175 | */ |
| 176 | static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) |
| 177 | { |
| 178 | |
| 179 | /* Skip if gain calibration is inactive or |
| 180 | * we already handle a probe request */ |
| 181 | if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) |
| 182 | return; |
| 183 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 184 | /* Send the packet with 2dB below max power as |
| 185 | * patent doc suggest */ |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 186 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 187 | AR5K_PHY_PAPD_PROBE_TXPOWER) | |
| 188 | AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); |
| 189 | |
| 190 | ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; |
| 191 | |
| 192 | } |
| 193 | |
| 194 | /* Calculate gain_F measurement correction |
| 195 | * based on the current step for RF5112 rev. 2 */ |
| 196 | static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 197 | { |
| 198 | u32 mix, step; |
| 199 | u32 *rf; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 200 | const struct ath5k_gain_opt *go; |
| 201 | const struct ath5k_gain_opt_step *g_step; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 202 | const struct ath5k_rf_reg *rf_regs; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 203 | |
| 204 | /* Only RF5112 Rev. 2 supports it */ |
| 205 | if ((ah->ah_radio != AR5K_RF5112) || |
| 206 | (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) |
| 207 | return 0; |
| 208 | |
| 209 | go = &rfgain_opt_5112; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 210 | rf_regs = rf_regs_5112a; |
| 211 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 212 | |
| 213 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 214 | |
| 215 | if (ah->ah_rf_banks == NULL) |
| 216 | return 0; |
| 217 | |
| 218 | rf = ah->ah_rf_banks; |
| 219 | ah->ah_gain.g_f_corr = 0; |
| 220 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 221 | /* No VGA (Variable Gain Amplifier) override, skip */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 222 | if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 223 | return 0; |
| 224 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 225 | /* Mix gain stepping */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 226 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 227 | |
| 228 | /* Mix gain override */ |
| 229 | mix = g_step->gos_param[0]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 230 | |
| 231 | switch (mix) { |
| 232 | case 3: |
| 233 | ah->ah_gain.g_f_corr = step * 2; |
| 234 | break; |
| 235 | case 2: |
| 236 | ah->ah_gain.g_f_corr = (step - 5) * 2; |
| 237 | break; |
| 238 | case 1: |
| 239 | ah->ah_gain.g_f_corr = step; |
| 240 | break; |
| 241 | default: |
| 242 | ah->ah_gain.g_f_corr = 0; |
| 243 | break; |
| 244 | } |
| 245 | |
| 246 | return ah->ah_gain.g_f_corr; |
| 247 | } |
| 248 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 249 | /* Check if current gain_F measurement is in the range of our |
| 250 | * power detector windows. If we get a measurement outside range |
| 251 | * we know it's not accurate (detectors can't measure anything outside |
| 252 | * their detection window) so we must ignore it */ |
| 253 | static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 254 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 255 | const struct ath5k_rf_reg *rf_regs; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 256 | u32 step, mix_ovr, level[4]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 257 | u32 *rf; |
| 258 | |
| 259 | if (ah->ah_rf_banks == NULL) |
| 260 | return false; |
| 261 | |
| 262 | rf = ah->ah_rf_banks; |
| 263 | |
| 264 | if (ah->ah_radio == AR5K_RF5111) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 265 | |
| 266 | rf_regs = rf_regs_5111; |
| 267 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); |
| 268 | |
| 269 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, |
| 270 | false); |
| 271 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 272 | level[0] = 0; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 273 | level[1] = (step == 63) ? 50 : step + 4; |
| 274 | level[2] = (step != 63) ? 64 : level[0]; |
| 275 | level[3] = level[2] + 50 ; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 276 | |
| 277 | ah->ah_gain.g_high = level[3] - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 278 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 279 | ah->ah_gain.g_low = level[0] + |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 280 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 281 | } else { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 282 | |
| 283 | rf_regs = rf_regs_5112; |
| 284 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); |
| 285 | |
| 286 | mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, |
| 287 | false); |
| 288 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 289 | level[0] = level[2] = 0; |
| 290 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 291 | if (mix_ovr == 1) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 292 | level[1] = level[3] = 83; |
| 293 | } else { |
| 294 | level[1] = level[3] = 107; |
| 295 | ah->ah_gain.g_high = 55; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | return (ah->ah_gain.g_current >= level[0] && |
| 300 | ah->ah_gain.g_current <= level[1]) || |
| 301 | (ah->ah_gain.g_current >= level[2] && |
| 302 | ah->ah_gain.g_current <= level[3]); |
| 303 | } |
| 304 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 305 | /* Perform gain_F adjustment by choosing the right set |
| 306 | * of parameters from rf gain optimization ladder */ |
| 307 | static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 308 | { |
| 309 | const struct ath5k_gain_opt *go; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 310 | const struct ath5k_gain_opt_step *g_step; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 311 | int ret = 0; |
| 312 | |
| 313 | switch (ah->ah_radio) { |
| 314 | case AR5K_RF5111: |
| 315 | go = &rfgain_opt_5111; |
| 316 | break; |
| 317 | case AR5K_RF5112: |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 318 | go = &rfgain_opt_5112; |
| 319 | break; |
| 320 | default: |
| 321 | return 0; |
| 322 | } |
| 323 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 324 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 325 | |
| 326 | if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 327 | |
| 328 | /* Reached maximum */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 329 | if (ah->ah_gain.g_step_idx == 0) |
| 330 | return -1; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 331 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 332 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
| 333 | ah->ah_gain.g_target >= ah->ah_gain.g_high && |
| 334 | ah->ah_gain.g_step_idx > 0; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 335 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 336 | ah->ah_gain.g_target -= 2 * |
| 337 | (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 338 | g_step->gos_gain); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 339 | |
| 340 | ret = 1; |
| 341 | goto done; |
| 342 | } |
| 343 | |
| 344 | if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 345 | |
| 346 | /* Reached minimum */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 347 | if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) |
| 348 | return -2; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 349 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 350 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
| 351 | ah->ah_gain.g_target <= ah->ah_gain.g_low && |
| 352 | ah->ah_gain.g_step_idx < go->go_steps_count-1; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 353 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 354 | ah->ah_gain.g_target -= 2 * |
| 355 | (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 356 | g_step->gos_gain); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 357 | |
| 358 | ret = 2; |
| 359 | goto done; |
| 360 | } |
| 361 | |
| 362 | done: |
| 363 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
| 364 | "ret %d, gain step %u, current gain %u, target gain %u\n", |
| 365 | ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, |
| 366 | ah->ah_gain.g_target); |
| 367 | |
| 368 | return ret; |
| 369 | } |
| 370 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 371 | /* Main callback for thermal rf gain calibration engine |
| 372 | * Check for a new gain reading and schedule an adjustment |
| 373 | * if needed. |
| 374 | * |
| 375 | * TODO: Use sw interrupt to schedule reset if gain_F needs |
| 376 | * adjustment */ |
| 377 | enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) |
| 378 | { |
| 379 | u32 data, type; |
| 380 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 381 | |
| 382 | ATH5K_TRACE(ah->ah_sc); |
| 383 | |
| 384 | if (ah->ah_rf_banks == NULL || |
| 385 | ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) |
| 386 | return AR5K_RFGAIN_INACTIVE; |
| 387 | |
| 388 | /* No check requested, either engine is inactive |
| 389 | * or an adjustment is already requested */ |
| 390 | if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) |
| 391 | goto done; |
| 392 | |
| 393 | /* Read the PAPD (Peak to Average Power Detector) |
| 394 | * register */ |
| 395 | data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); |
| 396 | |
| 397 | /* No probe is scheduled, read gain_F measurement */ |
| 398 | if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { |
| 399 | ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; |
| 400 | type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); |
| 401 | |
| 402 | /* If tx packet is CCK correct the gain_F measurement |
| 403 | * by cck ofdm gain delta */ |
| 404 | if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { |
| 405 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) |
| 406 | ah->ah_gain.g_current += |
| 407 | ee->ee_cck_ofdm_gain_delta; |
| 408 | else |
| 409 | ah->ah_gain.g_current += |
| 410 | AR5K_GAIN_CCK_PROBE_CORR; |
| 411 | } |
| 412 | |
| 413 | /* Further correct gain_F measurement for |
| 414 | * RF5112A radios */ |
| 415 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { |
| 416 | ath5k_hw_rf_gainf_corr(ah); |
| 417 | ah->ah_gain.g_current = |
| 418 | ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? |
| 419 | (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : |
| 420 | 0; |
| 421 | } |
| 422 | |
| 423 | /* Check if measurement is ok and if we need |
| 424 | * to adjust gain, schedule a gain adjustment, |
| 425 | * else switch back to the acive state */ |
| 426 | if (ath5k_hw_rf_check_gainf_readback(ah) && |
| 427 | AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && |
| 428 | ath5k_hw_rf_gainf_adjust(ah)) { |
| 429 | ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; |
| 430 | } else { |
| 431 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | done: |
| 436 | return ah->ah_gain.g_state; |
| 437 | } |
| 438 | |
| 439 | /* Write initial rf gain table to set the RF sensitivity |
| 440 | * this one works on all RF chips and has nothing to do |
| 441 | * with gain_F calibration */ |
| 442 | int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) |
| 443 | { |
| 444 | const struct ath5k_ini_rfgain *ath5k_rfg; |
| 445 | unsigned int i, size; |
| 446 | |
| 447 | switch (ah->ah_radio) { |
| 448 | case AR5K_RF5111: |
| 449 | ath5k_rfg = rfgain_5111; |
| 450 | size = ARRAY_SIZE(rfgain_5111); |
| 451 | break; |
| 452 | case AR5K_RF5112: |
| 453 | ath5k_rfg = rfgain_5112; |
| 454 | size = ARRAY_SIZE(rfgain_5112); |
| 455 | break; |
| 456 | case AR5K_RF2413: |
| 457 | ath5k_rfg = rfgain_2413; |
| 458 | size = ARRAY_SIZE(rfgain_2413); |
| 459 | break; |
| 460 | case AR5K_RF2316: |
| 461 | ath5k_rfg = rfgain_2316; |
| 462 | size = ARRAY_SIZE(rfgain_2316); |
| 463 | break; |
| 464 | case AR5K_RF5413: |
| 465 | ath5k_rfg = rfgain_5413; |
| 466 | size = ARRAY_SIZE(rfgain_5413); |
| 467 | break; |
| 468 | case AR5K_RF2317: |
| 469 | case AR5K_RF2425: |
| 470 | ath5k_rfg = rfgain_2425; |
| 471 | size = ARRAY_SIZE(rfgain_2425); |
| 472 | break; |
| 473 | default: |
| 474 | return -EINVAL; |
| 475 | } |
| 476 | |
| 477 | switch (freq) { |
| 478 | case AR5K_INI_RFGAIN_2GHZ: |
| 479 | case AR5K_INI_RFGAIN_5GHZ: |
| 480 | break; |
| 481 | default: |
| 482 | return -EINVAL; |
| 483 | } |
| 484 | |
| 485 | for (i = 0; i < size; i++) { |
| 486 | AR5K_REG_WAIT(i); |
| 487 | ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], |
| 488 | (u32)ath5k_rfg[i].rfg_register); |
| 489 | } |
| 490 | |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | |
| 495 | |
| 496 | /********************\ |
| 497 | * RF Registers setup * |
| 498 | \********************/ |
| 499 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 500 | |
| 501 | /* |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 502 | * Setup RF registers by writing rf buffer on hw |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 503 | */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 504 | int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 505 | unsigned int mode) |
| 506 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 507 | const struct ath5k_rf_reg *rf_regs; |
| 508 | const struct ath5k_ini_rfbuffer *ini_rfb; |
| 509 | const struct ath5k_gain_opt *go = NULL; |
| 510 | const struct ath5k_gain_opt_step *g_step; |
| 511 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 512 | u8 ee_mode = 0; |
| 513 | u32 *rfb; |
| 514 | int i, obdb = -1, bank = -1; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 515 | |
| 516 | switch (ah->ah_radio) { |
| 517 | case AR5K_RF5111: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 518 | rf_regs = rf_regs_5111; |
| 519 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); |
| 520 | ini_rfb = rfb_5111; |
| 521 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); |
| 522 | go = &rfgain_opt_5111; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 523 | break; |
| 524 | case AR5K_RF5112: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 525 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { |
| 526 | rf_regs = rf_regs_5112a; |
| 527 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); |
| 528 | ini_rfb = rfb_5112a; |
| 529 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); |
| 530 | } else { |
| 531 | rf_regs = rf_regs_5112; |
| 532 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); |
| 533 | ini_rfb = rfb_5112; |
| 534 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); |
| 535 | } |
| 536 | go = &rfgain_opt_5112; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 537 | break; |
Nick Kossifidis | f714dd6 | 2008-02-28 14:43:51 -0500 | [diff] [blame] | 538 | case AR5K_RF2413: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 539 | rf_regs = rf_regs_2413; |
| 540 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); |
| 541 | ini_rfb = rfb_2413; |
| 542 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); |
| 543 | break; |
| 544 | case AR5K_RF2316: |
| 545 | rf_regs = rf_regs_2316; |
| 546 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); |
| 547 | ini_rfb = rfb_2316; |
| 548 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); |
| 549 | break; |
| 550 | case AR5K_RF5413: |
| 551 | rf_regs = rf_regs_5413; |
| 552 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); |
| 553 | ini_rfb = rfb_5413; |
| 554 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); |
| 555 | break; |
| 556 | case AR5K_RF2317: |
| 557 | rf_regs = rf_regs_2425; |
| 558 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); |
| 559 | ini_rfb = rfb_2317; |
| 560 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); |
Nick Kossifidis | f714dd6 | 2008-02-28 14:43:51 -0500 | [diff] [blame] | 561 | break; |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 562 | case AR5K_RF2425: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 563 | rf_regs = rf_regs_2425; |
| 564 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); |
| 565 | if (ah->ah_mac_srev < AR5K_SREV_AR2417) { |
| 566 | ini_rfb = rfb_2425; |
| 567 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); |
| 568 | } else { |
| 569 | ini_rfb = rfb_2417; |
| 570 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); |
| 571 | } |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 572 | break; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 573 | default: |
| 574 | return -EINVAL; |
| 575 | } |
| 576 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 577 | /* If it's the first time we set rf buffer, allocate |
| 578 | * ah->ah_rf_banks based on ah->ah_rf_banks_size |
| 579 | * we set above */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 580 | if (ah->ah_rf_banks == NULL) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 581 | ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, |
| 582 | GFP_KERNEL); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 583 | if (ah->ah_rf_banks == NULL) { |
| 584 | ATH5K_ERR(ah->ah_sc, "out of memory\n"); |
| 585 | return -ENOMEM; |
| 586 | } |
| 587 | } |
| 588 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 589 | /* Copy values to modify them */ |
| 590 | rfb = ah->ah_rf_banks; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 591 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 592 | for (i = 0; i < ah->ah_rf_banks_size; i++) { |
| 593 | if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { |
| 594 | ATH5K_ERR(ah->ah_sc, "invalid bank\n"); |
| 595 | return -EINVAL; |
| 596 | } |
| 597 | |
| 598 | /* Bank changed, write down the offset */ |
| 599 | if (bank != ini_rfb[i].rfb_bank) { |
| 600 | bank = ini_rfb[i].rfb_bank; |
| 601 | ah->ah_offset[bank] = i; |
| 602 | } |
| 603 | |
| 604 | rfb[i] = ini_rfb[i].rfb_mode_data[mode]; |
| 605 | } |
| 606 | |
| 607 | /* Set Output and Driver bias current (OB/DB) */ |
| 608 | if (channel->hw_value & CHANNEL_2GHZ) { |
| 609 | |
| 610 | if (channel->hw_value & CHANNEL_CCK) |
| 611 | ee_mode = AR5K_EEPROM_MODE_11B; |
| 612 | else |
| 613 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 614 | |
| 615 | /* For RF511X/RF211X combination we |
| 616 | * use b_OB and b_DB parameters stored |
| 617 | * in eeprom on ee->ee_ob[ee_mode][0] |
| 618 | * |
| 619 | * For all other chips we use OB/DB for 2Ghz |
| 620 | * stored in the b/g modal section just like |
| 621 | * 802.11a on ee->ee_ob[ee_mode][1] */ |
| 622 | if ((ah->ah_radio == AR5K_RF5111) || |
| 623 | (ah->ah_radio == AR5K_RF5112)) |
| 624 | obdb = 0; |
| 625 | else |
| 626 | obdb = 1; |
| 627 | |
| 628 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
| 629 | AR5K_RF_OB_2GHZ, true); |
| 630 | |
| 631 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], |
| 632 | AR5K_RF_DB_2GHZ, true); |
| 633 | |
| 634 | /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ |
| 635 | } else if ((channel->hw_value & CHANNEL_5GHZ) || |
| 636 | (ah->ah_radio == AR5K_RF5111)) { |
| 637 | |
| 638 | /* For 11a, Turbo and XR we need to choose |
| 639 | * OB/DB based on frequency range */ |
| 640 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 641 | obdb = channel->center_freq >= 5725 ? 3 : |
| 642 | (channel->center_freq >= 5500 ? 2 : |
| 643 | (channel->center_freq >= 5260 ? 1 : |
| 644 | (channel->center_freq > 4000 ? 0 : -1))); |
| 645 | |
| 646 | if (obdb < 0) |
| 647 | return -EINVAL; |
| 648 | |
| 649 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
| 650 | AR5K_RF_OB_5GHZ, true); |
| 651 | |
| 652 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], |
| 653 | AR5K_RF_DB_5GHZ, true); |
| 654 | } |
| 655 | |
| 656 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
| 657 | |
| 658 | /* Bank Modifications (chip-specific) */ |
| 659 | if (ah->ah_radio == AR5K_RF5111) { |
| 660 | |
| 661 | /* Set gain_F settings according to current step */ |
| 662 | if (channel->hw_value & CHANNEL_OFDM) { |
| 663 | |
| 664 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, |
| 665 | AR5K_PHY_FRAME_CTL_TX_CLIP, |
| 666 | g_step->gos_param[0]); |
| 667 | |
| 668 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
| 669 | AR5K_RF_PWD_90, true); |
| 670 | |
| 671 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
| 672 | AR5K_RF_PWD_84, true); |
| 673 | |
| 674 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
| 675 | AR5K_RF_RFGAIN_SEL, true); |
| 676 | |
| 677 | /* We programmed gain_F parameters, switch back |
| 678 | * to active state */ |
| 679 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 680 | |
| 681 | } |
| 682 | |
| 683 | /* Bank 6/7 setup */ |
| 684 | |
| 685 | ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], |
| 686 | AR5K_RF_PWD_XPD, true); |
| 687 | |
| 688 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], |
| 689 | AR5K_RF_XPD_GAIN, true); |
| 690 | |
| 691 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
| 692 | AR5K_RF_GAIN_I, true); |
| 693 | |
| 694 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
| 695 | AR5K_RF_PLO_SEL, true); |
| 696 | |
| 697 | /* TODO: Half/quarter channel support */ |
| 698 | } |
| 699 | |
| 700 | if (ah->ah_radio == AR5K_RF5112) { |
| 701 | |
| 702 | /* Set gain_F settings according to current step */ |
| 703 | if (channel->hw_value & CHANNEL_OFDM) { |
| 704 | |
| 705 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], |
| 706 | AR5K_RF_MIXGAIN_OVR, true); |
| 707 | |
| 708 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
| 709 | AR5K_RF_PWD_138, true); |
| 710 | |
| 711 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
| 712 | AR5K_RF_PWD_137, true); |
| 713 | |
| 714 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
| 715 | AR5K_RF_PWD_136, true); |
| 716 | |
| 717 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], |
| 718 | AR5K_RF_PWD_132, true); |
| 719 | |
| 720 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], |
| 721 | AR5K_RF_PWD_131, true); |
| 722 | |
| 723 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], |
| 724 | AR5K_RF_PWD_130, true); |
| 725 | |
| 726 | /* We programmed gain_F parameters, switch back |
| 727 | * to active state */ |
| 728 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 729 | } |
| 730 | |
| 731 | /* Bank 6/7 setup */ |
| 732 | |
| 733 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
| 734 | AR5K_RF_XPD_SEL, true); |
| 735 | |
| 736 | if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { |
| 737 | /* Rev. 1 supports only one xpd */ |
| 738 | ath5k_hw_rfb_op(ah, rf_regs, |
| 739 | ee->ee_x_gain[ee_mode], |
| 740 | AR5K_RF_XPD_GAIN, true); |
| 741 | |
| 742 | } else { |
Nick Kossifidis | d1cb0bd | 2009-08-10 03:27:59 +0300 | [diff] [blame^] | 743 | u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; |
| 744 | if (ee->ee_pd_gains[ee_mode] > 1) { |
| 745 | ath5k_hw_rfb_op(ah, rf_regs, |
| 746 | pdg_curve_to_idx[0], |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 747 | AR5K_RF_PD_GAIN_LO, true); |
Nick Kossifidis | d1cb0bd | 2009-08-10 03:27:59 +0300 | [diff] [blame^] | 748 | ath5k_hw_rfb_op(ah, rf_regs, |
| 749 | pdg_curve_to_idx[1], |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 750 | AR5K_RF_PD_GAIN_HI, true); |
Nick Kossifidis | d1cb0bd | 2009-08-10 03:27:59 +0300 | [diff] [blame^] | 751 | } else { |
| 752 | ath5k_hw_rfb_op(ah, rf_regs, |
| 753 | pdg_curve_to_idx[0], |
| 754 | AR5K_RF_PD_GAIN_LO, true); |
| 755 | ath5k_hw_rfb_op(ah, rf_regs, |
| 756 | pdg_curve_to_idx[0], |
| 757 | AR5K_RF_PD_GAIN_HI, true); |
| 758 | } |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 759 | |
| 760 | /* Lower synth voltage on Rev 2 */ |
| 761 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 762 | AR5K_RF_HIGH_VC_CP, true); |
| 763 | |
| 764 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 765 | AR5K_RF_MID_VC_CP, true); |
| 766 | |
| 767 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 768 | AR5K_RF_LOW_VC_CP, true); |
| 769 | |
| 770 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 771 | AR5K_RF_PUSH_UP, true); |
| 772 | |
| 773 | /* Decrease power consumption on 5213+ BaseBand */ |
| 774 | if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { |
| 775 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 776 | AR5K_RF_PAD2GND, true); |
| 777 | |
| 778 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 779 | AR5K_RF_XB2_LVL, true); |
| 780 | |
| 781 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 782 | AR5K_RF_XB5_LVL, true); |
| 783 | |
| 784 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 785 | AR5K_RF_PWD_167, true); |
| 786 | |
| 787 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 788 | AR5K_RF_PWD_166, true); |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
| 793 | AR5K_RF_GAIN_I, true); |
| 794 | |
| 795 | /* TODO: Half/quarter channel support */ |
| 796 | |
| 797 | } |
| 798 | |
| 799 | if (ah->ah_radio == AR5K_RF5413 && |
| 800 | channel->hw_value & CHANNEL_2GHZ) { |
| 801 | |
| 802 | ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, |
| 803 | true); |
| 804 | |
| 805 | /* Set optimum value for early revisions (on pci-e chips) */ |
| 806 | if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && |
| 807 | ah->ah_mac_srev < AR5K_SREV_AR5413) |
| 808 | ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), |
| 809 | AR5K_RF_PWD_ICLOBUF_2G, true); |
| 810 | |
| 811 | } |
| 812 | |
| 813 | /* Write RF banks on hw */ |
| 814 | for (i = 0; i < ah->ah_rf_banks_size; i++) { |
| 815 | AR5K_REG_WAIT(i); |
| 816 | ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); |
| 817 | } |
| 818 | |
| 819 | return 0; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 820 | } |
| 821 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 822 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 823 | /**************************\ |
| 824 | PHY/RF channel functions |
| 825 | \**************************/ |
| 826 | |
| 827 | /* |
| 828 | * Check if a channel is supported |
| 829 | */ |
| 830 | bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) |
| 831 | { |
| 832 | /* Check if the channel is in our supported range */ |
| 833 | if (flags & CHANNEL_2GHZ) { |
| 834 | if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && |
| 835 | (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) |
| 836 | return true; |
| 837 | } else if (flags & CHANNEL_5GHZ) |
| 838 | if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && |
| 839 | (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) |
| 840 | return true; |
| 841 | |
| 842 | return false; |
| 843 | } |
| 844 | |
| 845 | /* |
| 846 | * Convertion needed for RF5110 |
| 847 | */ |
| 848 | static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) |
| 849 | { |
| 850 | u32 athchan; |
| 851 | |
| 852 | /* |
| 853 | * Convert IEEE channel/MHz to an internal channel value used |
| 854 | * by the AR5210 chipset. This has not been verified with |
| 855 | * newer chipsets like the AR5212A who have a completely |
| 856 | * different RF/PHY part. |
| 857 | */ |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 858 | athchan = (ath5k_hw_bitswap( |
| 859 | (ieee80211_frequency_to_channel( |
| 860 | channel->center_freq) - 24) / 2, 5) |
| 861 | << 1) | (1 << 6) | 0x1; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 862 | return athchan; |
| 863 | } |
| 864 | |
| 865 | /* |
| 866 | * Set channel on RF5110 |
| 867 | */ |
| 868 | static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, |
| 869 | struct ieee80211_channel *channel) |
| 870 | { |
| 871 | u32 data; |
| 872 | |
| 873 | /* |
| 874 | * Set the channel and wait |
| 875 | */ |
| 876 | data = ath5k_hw_rf5110_chan2athchan(channel); |
| 877 | ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); |
| 878 | ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); |
| 879 | mdelay(1); |
| 880 | |
| 881 | return 0; |
| 882 | } |
| 883 | |
| 884 | /* |
| 885 | * Convertion needed for 5111 |
| 886 | */ |
| 887 | static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, |
| 888 | struct ath5k_athchan_2ghz *athchan) |
| 889 | { |
| 890 | int channel; |
| 891 | |
| 892 | /* Cast this value to catch negative channel numbers (>= -19) */ |
| 893 | channel = (int)ieee; |
| 894 | |
| 895 | /* |
| 896 | * Map 2GHz IEEE channel to 5GHz Atheros channel |
| 897 | */ |
| 898 | if (channel <= 13) { |
| 899 | athchan->a2_athchan = 115 + channel; |
| 900 | athchan->a2_flags = 0x46; |
| 901 | } else if (channel == 14) { |
| 902 | athchan->a2_athchan = 124; |
| 903 | athchan->a2_flags = 0x44; |
| 904 | } else if (channel >= 15 && channel <= 26) { |
| 905 | athchan->a2_athchan = ((channel - 14) * 4) + 132; |
| 906 | athchan->a2_flags = 0x46; |
| 907 | } else |
| 908 | return -EINVAL; |
| 909 | |
| 910 | return 0; |
| 911 | } |
| 912 | |
| 913 | /* |
| 914 | * Set channel on 5111 |
| 915 | */ |
| 916 | static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, |
| 917 | struct ieee80211_channel *channel) |
| 918 | { |
| 919 | struct ath5k_athchan_2ghz ath5k_channel_2ghz; |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 920 | unsigned int ath5k_channel = |
| 921 | ieee80211_frequency_to_channel(channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 922 | u32 data0, data1, clock; |
| 923 | int ret; |
| 924 | |
| 925 | /* |
| 926 | * Set the channel on the RF5111 radio |
| 927 | */ |
| 928 | data0 = data1 = 0; |
| 929 | |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 930 | if (channel->hw_value & CHANNEL_2GHZ) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 931 | /* Map 2GHz channel to 5GHz Atheros channel ID */ |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 932 | ret = ath5k_hw_rf5111_chan2athchan( |
| 933 | ieee80211_frequency_to_channel(channel->center_freq), |
| 934 | &ath5k_channel_2ghz); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 935 | if (ret) |
| 936 | return ret; |
| 937 | |
| 938 | ath5k_channel = ath5k_channel_2ghz.a2_athchan; |
| 939 | data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) |
| 940 | << 5) | (1 << 4); |
| 941 | } |
| 942 | |
| 943 | if (ath5k_channel < 145 || !(ath5k_channel & 1)) { |
| 944 | clock = 1; |
| 945 | data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | |
| 946 | (clock << 1) | (1 << 10) | 1; |
| 947 | } else { |
| 948 | clock = 0; |
| 949 | data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) |
| 950 | << 2) | (clock << 1) | (1 << 10) | 1; |
| 951 | } |
| 952 | |
| 953 | ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), |
| 954 | AR5K_RF_BUFFER); |
| 955 | ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), |
| 956 | AR5K_RF_BUFFER_CONTROL_3); |
| 957 | |
| 958 | return 0; |
| 959 | } |
| 960 | |
| 961 | /* |
| 962 | * Set channel on 5112 and newer |
| 963 | */ |
| 964 | static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, |
| 965 | struct ieee80211_channel *channel) |
| 966 | { |
| 967 | u32 data, data0, data1, data2; |
| 968 | u16 c; |
| 969 | |
| 970 | data = data0 = data1 = data2 = 0; |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 971 | c = channel->center_freq; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 972 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 973 | if (c < 4800) { |
| 974 | if (!((c - 2224) % 5)) { |
| 975 | data0 = ((2 * (c - 704)) - 3040) / 10; |
| 976 | data1 = 1; |
| 977 | } else if (!((c - 2192) % 5)) { |
| 978 | data0 = ((2 * (c - 672)) - 3040) / 10; |
| 979 | data1 = 0; |
| 980 | } else |
| 981 | return -EINVAL; |
| 982 | |
| 983 | data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 984 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 985 | if (!(c % 20) && c >= 5120) { |
| 986 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); |
| 987 | data2 = ath5k_hw_bitswap(3, 2); |
| 988 | } else if (!(c % 10)) { |
| 989 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); |
| 990 | data2 = ath5k_hw_bitswap(2, 2); |
| 991 | } else if (!(c % 5)) { |
| 992 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); |
| 993 | data2 = ath5k_hw_bitswap(1, 2); |
| 994 | } else |
| 995 | return -EINVAL; |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 996 | } else { |
| 997 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); |
| 998 | data2 = ath5k_hw_bitswap(0, 2); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 999 | } |
| 1000 | |
| 1001 | data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; |
| 1002 | |
| 1003 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); |
| 1004 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); |
| 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
| 1009 | /* |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1010 | * Set the channel on the RF2425 |
| 1011 | */ |
| 1012 | static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, |
| 1013 | struct ieee80211_channel *channel) |
| 1014 | { |
| 1015 | u32 data, data0, data2; |
| 1016 | u16 c; |
| 1017 | |
| 1018 | data = data0 = data2 = 0; |
| 1019 | c = channel->center_freq; |
| 1020 | |
| 1021 | if (c < 4800) { |
| 1022 | data0 = ath5k_hw_bitswap((c - 2272), 8); |
| 1023 | data2 = 0; |
| 1024 | /* ? 5GHz ? */ |
| 1025 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
| 1026 | if (!(c % 20) && c < 5120) |
| 1027 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); |
| 1028 | else if (!(c % 10)) |
| 1029 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); |
| 1030 | else if (!(c % 5)) |
| 1031 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); |
| 1032 | else |
| 1033 | return -EINVAL; |
| 1034 | data2 = ath5k_hw_bitswap(1, 2); |
| 1035 | } else { |
| 1036 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); |
| 1037 | data2 = ath5k_hw_bitswap(0, 2); |
| 1038 | } |
| 1039 | |
| 1040 | data = (data0 << 4) | data2 << 2 | 0x1001; |
| 1041 | |
| 1042 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); |
| 1043 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); |
| 1044 | |
| 1045 | return 0; |
| 1046 | } |
| 1047 | |
| 1048 | /* |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1049 | * Set a channel on the radio chip |
| 1050 | */ |
| 1051 | int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) |
| 1052 | { |
| 1053 | int ret; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1054 | /* |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1055 | * Check bounds supported by the PHY (we don't care about regultory |
| 1056 | * restrictions at this point). Note: hw_value already has the band |
| 1057 | * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() |
| 1058 | * of the band by that */ |
| 1059 | if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1060 | ATH5K_ERR(ah->ah_sc, |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1061 | "channel frequency (%u MHz) out of supported " |
| 1062 | "band range\n", |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1063 | channel->center_freq); |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1064 | return -EINVAL; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | /* |
| 1068 | * Set the channel and wait |
| 1069 | */ |
| 1070 | switch (ah->ah_radio) { |
| 1071 | case AR5K_RF5110: |
| 1072 | ret = ath5k_hw_rf5110_channel(ah, channel); |
| 1073 | break; |
| 1074 | case AR5K_RF5111: |
| 1075 | ret = ath5k_hw_rf5111_channel(ah, channel); |
| 1076 | break; |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1077 | case AR5K_RF2425: |
| 1078 | ret = ath5k_hw_rf2425_channel(ah, channel); |
| 1079 | break; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1080 | default: |
| 1081 | ret = ath5k_hw_rf5112_channel(ah, channel); |
| 1082 | break; |
| 1083 | } |
| 1084 | |
| 1085 | if (ret) |
| 1086 | return ret; |
| 1087 | |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1088 | /* Set JAPAN setting for channel 14 */ |
| 1089 | if (channel->center_freq == 2484) { |
| 1090 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, |
| 1091 | AR5K_PHY_CCKTXCTL_JAPAN); |
| 1092 | } else { |
| 1093 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, |
| 1094 | AR5K_PHY_CCKTXCTL_WORLD); |
| 1095 | } |
| 1096 | |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 1097 | ah->ah_current_channel = channel; |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1098 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | /*****************\ |
| 1104 | PHY calibration |
| 1105 | \*****************/ |
| 1106 | |
| 1107 | /** |
| 1108 | * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration |
| 1109 | * |
| 1110 | * @ah: struct ath5k_hw pointer we are operating on |
| 1111 | * @freq: the channel frequency, just used for error logging |
| 1112 | * |
| 1113 | * This function performs a noise floor calibration of the PHY and waits for |
| 1114 | * it to complete. Then the noise floor value is compared to some maximum |
| 1115 | * noise floor we consider valid. |
| 1116 | * |
| 1117 | * Note that this is different from what the madwifi HAL does: it reads the |
| 1118 | * noise floor and afterwards initiates the calibration. Since the noise floor |
| 1119 | * calibration can take some time to finish, depending on the current channel |
| 1120 | * use, that avoids the occasional timeout warnings we are seeing now. |
| 1121 | * |
| 1122 | * See the following link for an Atheros patent on noise floor calibration: |
| 1123 | * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ |
| 1124 | * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 |
| 1125 | * |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1126 | * XXX: Since during noise floor calibration antennas are detached according to |
| 1127 | * the patent, we should stop tx queues here. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1128 | */ |
| 1129 | int |
| 1130 | ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) |
| 1131 | { |
| 1132 | int ret; |
| 1133 | unsigned int i; |
| 1134 | s32 noise_floor; |
| 1135 | |
| 1136 | /* |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1137 | * Enable noise floor calibration |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1138 | */ |
| 1139 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 1140 | AR5K_PHY_AGCCTL_NF); |
| 1141 | |
| 1142 | ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
| 1143 | AR5K_PHY_AGCCTL_NF, 0, false); |
| 1144 | if (ret) { |
| 1145 | ATH5K_ERR(ah->ah_sc, |
| 1146 | "noise floor calibration timeout (%uMHz)\n", freq); |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1147 | return -EAGAIN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | /* Wait until the noise floor is calibrated and read the value */ |
| 1151 | for (i = 20; i > 0; i--) { |
| 1152 | mdelay(1); |
| 1153 | noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); |
| 1154 | noise_floor = AR5K_PHY_NF_RVAL(noise_floor); |
| 1155 | if (noise_floor & AR5K_PHY_NF_ACTIVE) { |
| 1156 | noise_floor = AR5K_PHY_NF_AVAL(noise_floor); |
| 1157 | |
| 1158 | if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) |
| 1159 | break; |
| 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
| 1164 | "noise floor %d\n", noise_floor); |
| 1165 | |
| 1166 | if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { |
| 1167 | ATH5K_ERR(ah->ah_sc, |
| 1168 | "noise floor calibration failed (%uMHz)\n", freq); |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1169 | return -EAGAIN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1170 | } |
| 1171 | |
| 1172 | ah->ah_noise_floor = noise_floor; |
| 1173 | |
| 1174 | return 0; |
| 1175 | } |
| 1176 | |
| 1177 | /* |
| 1178 | * Perform a PHY calibration on RF5110 |
| 1179 | * -Fix BPSK/QAM Constellation (I/Q correction) |
| 1180 | * -Calculate Noise Floor |
| 1181 | */ |
| 1182 | static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, |
| 1183 | struct ieee80211_channel *channel) |
| 1184 | { |
| 1185 | u32 phy_sig, phy_agc, phy_sat, beacon; |
| 1186 | int ret; |
| 1187 | |
| 1188 | /* |
| 1189 | * Disable beacons and RX/TX queues, wait |
| 1190 | */ |
| 1191 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, |
| 1192 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); |
| 1193 | beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); |
| 1194 | ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); |
| 1195 | |
Nick Kossifidis | 84e463f | 2008-09-17 03:33:19 +0300 | [diff] [blame] | 1196 | mdelay(2); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1197 | |
| 1198 | /* |
| 1199 | * Set the channel (with AGC turned off) |
| 1200 | */ |
| 1201 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1202 | udelay(10); |
| 1203 | ret = ath5k_hw_channel(ah, channel); |
| 1204 | |
| 1205 | /* |
| 1206 | * Activate PHY and wait |
| 1207 | */ |
| 1208 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); |
| 1209 | mdelay(1); |
| 1210 | |
| 1211 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1212 | |
| 1213 | if (ret) |
| 1214 | return ret; |
| 1215 | |
| 1216 | /* |
| 1217 | * Calibrate the radio chip |
| 1218 | */ |
| 1219 | |
| 1220 | /* Remember normal state */ |
| 1221 | phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); |
| 1222 | phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); |
| 1223 | phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); |
| 1224 | |
| 1225 | /* Update radio registers */ |
| 1226 | ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | |
| 1227 | AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); |
| 1228 | |
| 1229 | ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | |
| 1230 | AR5K_PHY_AGCCOARSE_LO)) | |
| 1231 | AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | |
| 1232 | AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); |
| 1233 | |
| 1234 | ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | |
| 1235 | AR5K_PHY_ADCSAT_THR)) | |
| 1236 | AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | |
| 1237 | AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); |
| 1238 | |
| 1239 | udelay(20); |
| 1240 | |
| 1241 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1242 | udelay(10); |
| 1243 | ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); |
| 1244 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1245 | |
| 1246 | mdelay(1); |
| 1247 | |
| 1248 | /* |
| 1249 | * Enable calibration and wait until completion |
| 1250 | */ |
| 1251 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); |
| 1252 | |
| 1253 | ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
| 1254 | AR5K_PHY_AGCCTL_CAL, 0, false); |
| 1255 | |
| 1256 | /* Reset to normal state */ |
| 1257 | ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); |
| 1258 | ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); |
| 1259 | ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); |
| 1260 | |
| 1261 | if (ret) { |
| 1262 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1263 | channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1264 | return ret; |
| 1265 | } |
| 1266 | |
Felix Fietkau | 8b0162a | 2008-11-03 11:27:38 +0100 | [diff] [blame] | 1267 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1268 | |
| 1269 | /* |
| 1270 | * Re-enable RX/TX and beacons |
| 1271 | */ |
| 1272 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, |
| 1273 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); |
| 1274 | ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); |
| 1275 | |
| 1276 | return 0; |
| 1277 | } |
| 1278 | |
| 1279 | /* |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1280 | * Perform a PHY calibration on RF5111/5112 and newer chips |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1281 | */ |
| 1282 | static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, |
| 1283 | struct ieee80211_channel *channel) |
| 1284 | { |
| 1285 | u32 i_pwr, q_pwr; |
| 1286 | s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1287 | int i; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1288 | ATH5K_TRACE(ah->ah_sc); |
| 1289 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 1290 | if (!ah->ah_calibration || |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1291 | ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1292 | goto done; |
| 1293 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1294 | /* Calibration has finished, get the results and re-run */ |
| 1295 | for (i = 0; i <= 10; i++) { |
| 1296 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); |
| 1297 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); |
| 1298 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); |
| 1299 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1300 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1301 | i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1302 | q_coffd = q_pwr >> 7; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1303 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1304 | /* No correction */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1305 | if (i_coffd == 0 || q_coffd == 0) |
| 1306 | goto done; |
| 1307 | |
| 1308 | i_coff = ((-iq_corr) / i_coffd) & 0x3f; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1309 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1310 | /* Boundary check */ |
| 1311 | if (i_coff > 31) |
| 1312 | i_coff = 31; |
| 1313 | if (i_coff < -32) |
| 1314 | i_coff = -32; |
| 1315 | |
| 1316 | q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; |
| 1317 | |
| 1318 | /* Boundary check */ |
| 1319 | if (q_coff > 15) |
| 1320 | q_coff = 15; |
| 1321 | if (q_coff < -16) |
| 1322 | q_coff = -16; |
| 1323 | |
| 1324 | /* Commit new I/Q value */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1325 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | |
| 1326 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); |
| 1327 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1328 | /* Re-enable calibration -if we don't we'll commit |
| 1329 | * the same values again and again */ |
| 1330 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, |
| 1331 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); |
| 1332 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); |
| 1333 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1334 | done: |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1335 | |
| 1336 | /* TODO: Separate noise floor calibration from I/Q calibration |
| 1337 | * since noise floor calibration interrupts rx path while I/Q |
| 1338 | * calibration doesn't. We don't need to run noise floor calibration |
| 1339 | * as often as I/Q calibration.*/ |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1340 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1341 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 1342 | /* Initiate a gain_F calibration */ |
| 1343 | ath5k_hw_request_rfgain_probe(ah); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1344 | |
| 1345 | return 0; |
| 1346 | } |
| 1347 | |
| 1348 | /* |
| 1349 | * Perform a PHY calibration |
| 1350 | */ |
| 1351 | int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, |
| 1352 | struct ieee80211_channel *channel) |
| 1353 | { |
| 1354 | int ret; |
| 1355 | |
| 1356 | if (ah->ah_radio == AR5K_RF5110) |
| 1357 | ret = ath5k_hw_rf5110_calibrate(ah, channel); |
| 1358 | else |
| 1359 | ret = ath5k_hw_rf511x_calibrate(ah, channel); |
| 1360 | |
| 1361 | return ret; |
| 1362 | } |
| 1363 | |
Nick Kossifidis | 57e6c56 | 2009-04-30 15:55:50 -0400 | [diff] [blame] | 1364 | /***************************\ |
| 1365 | * Spur mitigation functions * |
| 1366 | \***************************/ |
| 1367 | |
| 1368 | bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, |
| 1369 | struct ieee80211_channel *channel) |
| 1370 | { |
| 1371 | u8 refclk_freq; |
| 1372 | |
| 1373 | if ((ah->ah_radio == AR5K_RF5112) || |
| 1374 | (ah->ah_radio == AR5K_RF5413) || |
| 1375 | (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) |
| 1376 | refclk_freq = 40; |
| 1377 | else |
| 1378 | refclk_freq = 32; |
| 1379 | |
| 1380 | if ((channel->center_freq % refclk_freq != 0) && |
| 1381 | ((channel->center_freq % refclk_freq < 10) || |
| 1382 | (channel->center_freq % refclk_freq > 22))) |
| 1383 | return true; |
| 1384 | else |
| 1385 | return false; |
| 1386 | } |
| 1387 | |
| 1388 | void |
| 1389 | ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, |
| 1390 | struct ieee80211_channel *channel) |
| 1391 | { |
| 1392 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 1393 | u32 mag_mask[4] = {0, 0, 0, 0}; |
| 1394 | u32 pilot_mask[2] = {0, 0}; |
| 1395 | /* Note: fbin values are scaled up by 2 */ |
| 1396 | u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; |
| 1397 | s32 spur_delta_phase, spur_freq_sigma_delta; |
| 1398 | s32 spur_offset, num_symbols_x16; |
| 1399 | u8 num_symbol_offsets, i, freq_band; |
| 1400 | |
| 1401 | /* Convert current frequency to fbin value (the same way channels |
| 1402 | * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale |
| 1403 | * up by 2 so we can compare it later */ |
| 1404 | if (channel->hw_value & CHANNEL_2GHZ) { |
| 1405 | chan_fbin = (channel->center_freq - 2300) * 10; |
| 1406 | freq_band = AR5K_EEPROM_BAND_2GHZ; |
| 1407 | } else { |
| 1408 | chan_fbin = (channel->center_freq - 4900) * 10; |
| 1409 | freq_band = AR5K_EEPROM_BAND_5GHZ; |
| 1410 | } |
| 1411 | |
| 1412 | /* Check if any spur_chan_fbin from EEPROM is |
| 1413 | * within our current channel's spur detection range */ |
| 1414 | spur_chan_fbin = AR5K_EEPROM_NO_SPUR; |
| 1415 | spur_detection_window = AR5K_SPUR_CHAN_WIDTH; |
| 1416 | /* XXX: Half/Quarter channels ?*/ |
| 1417 | if (channel->hw_value & CHANNEL_TURBO) |
| 1418 | spur_detection_window *= 2; |
| 1419 | |
| 1420 | for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { |
| 1421 | spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; |
| 1422 | |
| 1423 | /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag |
| 1424 | * so it's zero if we got nothing from EEPROM */ |
| 1425 | if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { |
| 1426 | spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; |
| 1427 | break; |
| 1428 | } |
| 1429 | |
| 1430 | if ((chan_fbin - spur_detection_window <= |
| 1431 | (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && |
| 1432 | (chan_fbin + spur_detection_window >= |
| 1433 | (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { |
| 1434 | spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; |
| 1435 | break; |
| 1436 | } |
| 1437 | } |
| 1438 | |
| 1439 | /* We need to enable spur filter for this channel */ |
| 1440 | if (spur_chan_fbin) { |
| 1441 | spur_offset = spur_chan_fbin - chan_fbin; |
| 1442 | /* |
| 1443 | * Calculate deltas: |
| 1444 | * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 |
| 1445 | * spur_delta_phase -> spur_offset / chip_freq << 11 |
| 1446 | * Note: Both values have 100KHz resolution |
| 1447 | */ |
| 1448 | /* XXX: Half/Quarter rate channels ? */ |
| 1449 | switch (channel->hw_value) { |
| 1450 | case CHANNEL_A: |
| 1451 | /* Both sample_freq and chip_freq are 40MHz */ |
| 1452 | spur_delta_phase = (spur_offset << 17) / 25; |
| 1453 | spur_freq_sigma_delta = (spur_delta_phase >> 10); |
| 1454 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; |
| 1455 | break; |
| 1456 | case CHANNEL_G: |
| 1457 | /* sample_freq -> 40MHz chip_freq -> 44MHz |
| 1458 | * (for b compatibility) */ |
| 1459 | spur_freq_sigma_delta = (spur_offset << 8) / 55; |
| 1460 | spur_delta_phase = (spur_offset << 17) / 25; |
| 1461 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; |
| 1462 | break; |
| 1463 | case CHANNEL_T: |
| 1464 | case CHANNEL_TG: |
| 1465 | /* Both sample_freq and chip_freq are 80MHz */ |
| 1466 | spur_delta_phase = (spur_offset << 16) / 25; |
| 1467 | spur_freq_sigma_delta = (spur_delta_phase >> 10); |
| 1468 | symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; |
| 1469 | break; |
| 1470 | default: |
| 1471 | return; |
| 1472 | } |
| 1473 | |
| 1474 | /* Calculate pilot and magnitude masks */ |
| 1475 | |
| 1476 | /* Scale up spur_offset by 1000 to switch to 100HZ resolution |
| 1477 | * and divide by symbol_width to find how many symbols we have |
| 1478 | * Note: number of symbols is scaled up by 16 */ |
| 1479 | num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; |
| 1480 | |
| 1481 | /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ |
| 1482 | if (!(num_symbols_x16 & 0xF)) |
| 1483 | /* _X_ */ |
| 1484 | num_symbol_offsets = 3; |
| 1485 | else |
| 1486 | /* _xx_ */ |
| 1487 | num_symbol_offsets = 4; |
| 1488 | |
| 1489 | for (i = 0; i < num_symbol_offsets; i++) { |
| 1490 | |
| 1491 | /* Calculate pilot mask */ |
| 1492 | s32 curr_sym_off = |
| 1493 | (num_symbols_x16 / 16) + i + 25; |
| 1494 | |
| 1495 | /* Pilot magnitude mask seems to be a way to |
| 1496 | * declare the boundaries for our detection |
| 1497 | * window or something, it's 2 for the middle |
| 1498 | * value(s) where the symbol is expected to be |
| 1499 | * and 1 on the boundary values */ |
| 1500 | u8 plt_mag_map = |
| 1501 | (i == 0 || i == (num_symbol_offsets - 1)) |
| 1502 | ? 1 : 2; |
| 1503 | |
| 1504 | if (curr_sym_off >= 0 && curr_sym_off <= 32) { |
| 1505 | if (curr_sym_off <= 25) |
| 1506 | pilot_mask[0] |= 1 << curr_sym_off; |
| 1507 | else if (curr_sym_off >= 27) |
| 1508 | pilot_mask[0] |= 1 << (curr_sym_off - 1); |
| 1509 | } else if (curr_sym_off >= 33 && curr_sym_off <= 52) |
| 1510 | pilot_mask[1] |= 1 << (curr_sym_off - 33); |
| 1511 | |
| 1512 | /* Calculate magnitude mask (for viterbi decoder) */ |
| 1513 | if (curr_sym_off >= -1 && curr_sym_off <= 14) |
| 1514 | mag_mask[0] |= |
| 1515 | plt_mag_map << (curr_sym_off + 1) * 2; |
| 1516 | else if (curr_sym_off >= 15 && curr_sym_off <= 30) |
| 1517 | mag_mask[1] |= |
| 1518 | plt_mag_map << (curr_sym_off - 15) * 2; |
| 1519 | else if (curr_sym_off >= 31 && curr_sym_off <= 46) |
| 1520 | mag_mask[2] |= |
| 1521 | plt_mag_map << (curr_sym_off - 31) * 2; |
| 1522 | else if (curr_sym_off >= 46 && curr_sym_off <= 53) |
| 1523 | mag_mask[3] |= |
| 1524 | plt_mag_map << (curr_sym_off - 47) * 2; |
| 1525 | |
| 1526 | } |
| 1527 | |
| 1528 | /* Write settings on hw to enable spur filter */ |
| 1529 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, |
| 1530 | AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); |
| 1531 | /* XXX: Self correlator also ? */ |
| 1532 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, |
| 1533 | AR5K_PHY_IQ_PILOT_MASK_EN | |
| 1534 | AR5K_PHY_IQ_CHAN_MASK_EN | |
| 1535 | AR5K_PHY_IQ_SPUR_FILT_EN); |
| 1536 | |
| 1537 | /* Set delta phase and freq sigma delta */ |
| 1538 | ath5k_hw_reg_write(ah, |
| 1539 | AR5K_REG_SM(spur_delta_phase, |
| 1540 | AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | |
| 1541 | AR5K_REG_SM(spur_freq_sigma_delta, |
| 1542 | AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | |
| 1543 | AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, |
| 1544 | AR5K_PHY_TIMING_11); |
| 1545 | |
| 1546 | /* Write pilot masks */ |
| 1547 | ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); |
| 1548 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, |
| 1549 | AR5K_PHY_TIMING_8_PILOT_MASK_2, |
| 1550 | pilot_mask[1]); |
| 1551 | |
| 1552 | ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); |
| 1553 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, |
| 1554 | AR5K_PHY_TIMING_10_PILOT_MASK_2, |
| 1555 | pilot_mask[1]); |
| 1556 | |
| 1557 | /* Write magnitude masks */ |
| 1558 | ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); |
| 1559 | ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); |
| 1560 | ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); |
| 1561 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, |
| 1562 | AR5K_PHY_BIN_MASK_CTL_MASK_4, |
| 1563 | mag_mask[3]); |
| 1564 | |
| 1565 | ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); |
| 1566 | ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); |
| 1567 | ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); |
| 1568 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, |
| 1569 | AR5K_PHY_BIN_MASK2_4_MASK_4, |
| 1570 | mag_mask[3]); |
| 1571 | |
| 1572 | } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & |
| 1573 | AR5K_PHY_IQ_SPUR_FILT_EN) { |
| 1574 | /* Clean up spur mitigation settings and disable fliter */ |
| 1575 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, |
| 1576 | AR5K_PHY_BIN_MASK_CTL_RATE, 0); |
| 1577 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, |
| 1578 | AR5K_PHY_IQ_PILOT_MASK_EN | |
| 1579 | AR5K_PHY_IQ_CHAN_MASK_EN | |
| 1580 | AR5K_PHY_IQ_SPUR_FILT_EN); |
| 1581 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); |
| 1582 | |
| 1583 | /* Clear pilot masks */ |
| 1584 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); |
| 1585 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, |
| 1586 | AR5K_PHY_TIMING_8_PILOT_MASK_2, |
| 1587 | 0); |
| 1588 | |
| 1589 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); |
| 1590 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, |
| 1591 | AR5K_PHY_TIMING_10_PILOT_MASK_2, |
| 1592 | 0); |
| 1593 | |
| 1594 | /* Clear magnitude masks */ |
| 1595 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); |
| 1596 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); |
| 1597 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); |
| 1598 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, |
| 1599 | AR5K_PHY_BIN_MASK_CTL_MASK_4, |
| 1600 | 0); |
| 1601 | |
| 1602 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); |
| 1603 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); |
| 1604 | ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); |
| 1605 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, |
| 1606 | AR5K_PHY_BIN_MASK2_4_MASK_4, |
| 1607 | 0); |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | /********************\ |
| 1612 | Misc PHY functions |
| 1613 | \********************/ |
| 1614 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1615 | int ath5k_hw_phy_disable(struct ath5k_hw *ah) |
| 1616 | { |
| 1617 | ATH5K_TRACE(ah->ah_sc); |
| 1618 | /*Just a try M.F.*/ |
| 1619 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); |
| 1620 | |
| 1621 | return 0; |
| 1622 | } |
| 1623 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1624 | /* |
| 1625 | * Get the PHY Chip revision |
| 1626 | */ |
| 1627 | u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) |
| 1628 | { |
| 1629 | unsigned int i; |
| 1630 | u32 srev; |
| 1631 | u16 ret; |
| 1632 | |
| 1633 | ATH5K_TRACE(ah->ah_sc); |
| 1634 | |
| 1635 | /* |
| 1636 | * Set the radio chip access register |
| 1637 | */ |
| 1638 | switch (chan) { |
| 1639 | case CHANNEL_2GHZ: |
| 1640 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); |
| 1641 | break; |
| 1642 | case CHANNEL_5GHZ: |
| 1643 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
| 1644 | break; |
| 1645 | default: |
| 1646 | return 0; |
| 1647 | } |
| 1648 | |
| 1649 | mdelay(2); |
| 1650 | |
| 1651 | /* ...wait until PHY is ready and read the selected radio revision */ |
| 1652 | ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); |
| 1653 | |
| 1654 | for (i = 0; i < 8; i++) |
| 1655 | ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); |
| 1656 | |
| 1657 | if (ah->ah_version == AR5K_AR5210) { |
| 1658 | srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; |
| 1659 | ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; |
| 1660 | } else { |
| 1661 | srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; |
| 1662 | ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | |
| 1663 | ((srev & 0x0f) << 4), 8); |
| 1664 | } |
| 1665 | |
| 1666 | /* Reset to the 5GHz mode */ |
| 1667 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
| 1668 | |
| 1669 | return ret; |
| 1670 | } |
| 1671 | |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1672 | /*****************\ |
| 1673 | * Antenna control * |
| 1674 | \*****************/ |
| 1675 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1676 | void /*TODO:Boundary check*/ |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1677 | ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1678 | { |
| 1679 | ATH5K_TRACE(ah->ah_sc); |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1680 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1681 | if (ah->ah_version != AR5K_AR5210) |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1682 | ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1683 | } |
| 1684 | |
| 1685 | unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) |
| 1686 | { |
| 1687 | ATH5K_TRACE(ah->ah_sc); |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1688 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1689 | if (ah->ah_version != AR5K_AR5210) |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1690 | return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1691 | |
| 1692 | return false; /*XXX: What do we return for 5210 ?*/ |
| 1693 | } |
| 1694 | |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1695 | /* |
| 1696 | * Enable/disable fast rx antenna diversity |
| 1697 | */ |
| 1698 | static void |
| 1699 | ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) |
| 1700 | { |
| 1701 | switch (ee_mode) { |
| 1702 | case AR5K_EEPROM_MODE_11G: |
| 1703 | /* XXX: This is set to |
| 1704 | * disabled on initvals !!! */ |
| 1705 | case AR5K_EEPROM_MODE_11A: |
| 1706 | if (enable) |
| 1707 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 1708 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); |
| 1709 | else |
| 1710 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 1711 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); |
| 1712 | break; |
| 1713 | case AR5K_EEPROM_MODE_11B: |
| 1714 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 1715 | AR5K_PHY_AGCCTL_OFDM_DIV_DIS); |
| 1716 | break; |
| 1717 | default: |
| 1718 | return; |
| 1719 | } |
| 1720 | |
| 1721 | if (enable) { |
| 1722 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, |
| 1723 | AR5K_PHY_RESTART_DIV_GC, 0xc); |
| 1724 | |
| 1725 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, |
| 1726 | AR5K_PHY_FAST_ANT_DIV_EN); |
| 1727 | } else { |
| 1728 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, |
| 1729 | AR5K_PHY_RESTART_DIV_GC, 0x8); |
| 1730 | |
| 1731 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, |
| 1732 | AR5K_PHY_FAST_ANT_DIV_EN); |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | /* |
| 1737 | * Set antenna operating mode |
| 1738 | */ |
| 1739 | void |
| 1740 | ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) |
| 1741 | { |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 1742 | struct ieee80211_channel *channel = ah->ah_current_channel; |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1743 | bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; |
| 1744 | bool use_def_for_sg; |
| 1745 | u8 def_ant, tx_ant, ee_mode; |
| 1746 | u32 sta_id1 = 0; |
| 1747 | |
| 1748 | def_ant = ah->ah_def_ant; |
| 1749 | |
| 1750 | ATH5K_TRACE(ah->ah_sc); |
| 1751 | |
| 1752 | switch (channel->hw_value & CHANNEL_MODES) { |
| 1753 | case CHANNEL_A: |
| 1754 | case CHANNEL_T: |
| 1755 | case CHANNEL_XR: |
| 1756 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 1757 | break; |
| 1758 | case CHANNEL_G: |
| 1759 | case CHANNEL_TG: |
| 1760 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 1761 | break; |
| 1762 | case CHANNEL_B: |
| 1763 | ee_mode = AR5K_EEPROM_MODE_11B; |
| 1764 | break; |
| 1765 | default: |
| 1766 | ATH5K_ERR(ah->ah_sc, |
| 1767 | "invalid channel: %d\n", channel->center_freq); |
| 1768 | return; |
| 1769 | } |
| 1770 | |
| 1771 | switch (ant_mode) { |
| 1772 | case AR5K_ANTMODE_DEFAULT: |
| 1773 | tx_ant = 0; |
| 1774 | use_def_for_tx = false; |
| 1775 | update_def_on_tx = false; |
| 1776 | use_def_for_rts = false; |
| 1777 | use_def_for_sg = false; |
| 1778 | fast_div = true; |
| 1779 | break; |
| 1780 | case AR5K_ANTMODE_FIXED_A: |
| 1781 | def_ant = 1; |
| 1782 | tx_ant = 0; |
| 1783 | use_def_for_tx = true; |
| 1784 | update_def_on_tx = false; |
| 1785 | use_def_for_rts = true; |
| 1786 | use_def_for_sg = true; |
| 1787 | fast_div = false; |
| 1788 | break; |
| 1789 | case AR5K_ANTMODE_FIXED_B: |
| 1790 | def_ant = 2; |
| 1791 | tx_ant = 0; |
| 1792 | use_def_for_tx = true; |
| 1793 | update_def_on_tx = false; |
| 1794 | use_def_for_rts = true; |
| 1795 | use_def_for_sg = true; |
| 1796 | fast_div = false; |
| 1797 | break; |
| 1798 | case AR5K_ANTMODE_SINGLE_AP: |
| 1799 | def_ant = 1; /* updated on tx */ |
| 1800 | tx_ant = 0; |
| 1801 | use_def_for_tx = true; |
| 1802 | update_def_on_tx = true; |
| 1803 | use_def_for_rts = true; |
| 1804 | use_def_for_sg = true; |
| 1805 | fast_div = true; |
| 1806 | break; |
| 1807 | case AR5K_ANTMODE_SECTOR_AP: |
| 1808 | tx_ant = 1; /* variable */ |
| 1809 | use_def_for_tx = false; |
| 1810 | update_def_on_tx = false; |
| 1811 | use_def_for_rts = true; |
| 1812 | use_def_for_sg = false; |
| 1813 | fast_div = false; |
| 1814 | break; |
| 1815 | case AR5K_ANTMODE_SECTOR_STA: |
| 1816 | tx_ant = 1; /* variable */ |
| 1817 | use_def_for_tx = true; |
| 1818 | update_def_on_tx = false; |
| 1819 | use_def_for_rts = true; |
| 1820 | use_def_for_sg = false; |
| 1821 | fast_div = true; |
| 1822 | break; |
| 1823 | case AR5K_ANTMODE_DEBUG: |
| 1824 | def_ant = 1; |
| 1825 | tx_ant = 2; |
| 1826 | use_def_for_tx = false; |
| 1827 | update_def_on_tx = false; |
| 1828 | use_def_for_rts = false; |
| 1829 | use_def_for_sg = false; |
| 1830 | fast_div = false; |
| 1831 | break; |
| 1832 | default: |
| 1833 | return; |
| 1834 | } |
| 1835 | |
| 1836 | ah->ah_tx_ant = tx_ant; |
| 1837 | ah->ah_ant_mode = ant_mode; |
| 1838 | |
| 1839 | sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; |
| 1840 | sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; |
| 1841 | sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; |
| 1842 | sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; |
| 1843 | |
| 1844 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); |
| 1845 | |
| 1846 | if (sta_id1) |
| 1847 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); |
| 1848 | |
| 1849 | /* Note: set diversity before default antenna |
| 1850 | * because it won't work correctly */ |
| 1851 | ath5k_hw_set_fast_div(ah, ee_mode, fast_div); |
| 1852 | ath5k_hw_set_def_antenna(ah, def_ant); |
| 1853 | } |
| 1854 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1855 | |
| 1856 | /****************\ |
| 1857 | * TX power setup * |
| 1858 | \****************/ |
| 1859 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1860 | /* |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1861 | * Helper functions |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1862 | */ |
| 1863 | |
| 1864 | /* |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1865 | * Do linear interpolation between two given (x, y) points |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1866 | */ |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1867 | static s16 |
| 1868 | ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, |
| 1869 | s16 y_left, s16 y_right) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1870 | { |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1871 | s16 ratio, result; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1872 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1873 | /* Avoid divide by zero and skip interpolation |
| 1874 | * if we have the same point */ |
| 1875 | if ((x_left == x_right) || (y_left == y_right)) |
| 1876 | return y_left; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1877 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1878 | /* |
| 1879 | * Since we use ints and not fps, we need to scale up in |
| 1880 | * order to get a sane ratio value (or else we 'll eg. get |
| 1881 | * always 1 instead of 1.25, 1.75 etc). We scale up by 100 |
| 1882 | * to have some accuracy both for 0.5 and 0.25 steps. |
| 1883 | */ |
| 1884 | ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1885 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1886 | /* Now scale down to be in range */ |
| 1887 | result = y_left + (ratio * (target - x_left) / 100); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1888 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1889 | return result; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1890 | } |
| 1891 | |
| 1892 | /* |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1893 | * Find vertical boundary (min pwr) for the linear PCDAC curve. |
| 1894 | * |
| 1895 | * Since we have the top of the curve and we draw the line below |
| 1896 | * until we reach 1 (1 pcdac step) we need to know which point |
| 1897 | * (x value) that is so that we don't go below y axis and have negative |
| 1898 | * pcdac values when creating the curve, or fill the table with zeroes. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1899 | */ |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1900 | static s16 |
| 1901 | ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, |
| 1902 | const s16 *pwrL, const s16 *pwrR) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1903 | { |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1904 | s8 tmp; |
| 1905 | s16 min_pwrL, min_pwrR; |
Fabio Rossi | 64cdb0e | 2009-04-01 20:37:50 +0200 | [diff] [blame] | 1906 | s16 pwr_i; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1907 | |
Nick Kossifidis | d1cb0bd | 2009-08-10 03:27:59 +0300 | [diff] [blame^] | 1908 | /* Some vendors write the same pcdac value twice !!! */ |
| 1909 | if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) |
| 1910 | return max(pwrL[0], pwrR[0]); |
Bob Copeland | 9c8b3ed | 2009-05-19 23:37:31 -0400 | [diff] [blame] | 1911 | |
Fabio Rossi | 64cdb0e | 2009-04-01 20:37:50 +0200 | [diff] [blame] | 1912 | if (pwrL[0] == pwrL[1]) |
| 1913 | min_pwrL = pwrL[0]; |
| 1914 | else { |
| 1915 | pwr_i = pwrL[0]; |
| 1916 | do { |
| 1917 | pwr_i--; |
| 1918 | tmp = (s8) ath5k_get_interpolated_value(pwr_i, |
| 1919 | pwrL[0], pwrL[1], |
| 1920 | stepL[0], stepL[1]); |
| 1921 | } while (tmp > 1); |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1922 | |
Fabio Rossi | 64cdb0e | 2009-04-01 20:37:50 +0200 | [diff] [blame] | 1923 | min_pwrL = pwr_i; |
| 1924 | } |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1925 | |
Fabio Rossi | 64cdb0e | 2009-04-01 20:37:50 +0200 | [diff] [blame] | 1926 | if (pwrR[0] == pwrR[1]) |
| 1927 | min_pwrR = pwrR[0]; |
| 1928 | else { |
| 1929 | pwr_i = pwrR[0]; |
| 1930 | do { |
| 1931 | pwr_i--; |
| 1932 | tmp = (s8) ath5k_get_interpolated_value(pwr_i, |
| 1933 | pwrR[0], pwrR[1], |
| 1934 | stepR[0], stepR[1]); |
| 1935 | } while (tmp > 1); |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1936 | |
Fabio Rossi | 64cdb0e | 2009-04-01 20:37:50 +0200 | [diff] [blame] | 1937 | min_pwrR = pwr_i; |
| 1938 | } |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1939 | |
| 1940 | /* Keep the right boundary so that it works for both curves */ |
| 1941 | return max(min_pwrL, min_pwrR); |
| 1942 | } |
| 1943 | |
| 1944 | /* |
| 1945 | * Interpolate (pwr,vpd) points to create a Power to PDADC or a |
| 1946 | * Power to PCDAC curve. |
| 1947 | * |
| 1948 | * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC |
| 1949 | * steps (offsets) on y axis. Power can go up to 31.5dB and max |
| 1950 | * PCDAC/PDADC step for each curve is 64 but we can write more than |
| 1951 | * one curves on hw so we can go up to 128 (which is the max step we |
| 1952 | * can write on the final table). |
| 1953 | * |
| 1954 | * We write y values (PCDAC/PDADC steps) on hw. |
| 1955 | */ |
| 1956 | static void |
| 1957 | ath5k_create_power_curve(s16 pmin, s16 pmax, |
| 1958 | const s16 *pwr, const u8 *vpd, |
| 1959 | u8 num_points, |
| 1960 | u8 *vpd_table, u8 type) |
| 1961 | { |
| 1962 | u8 idx[2] = { 0, 1 }; |
| 1963 | s16 pwr_i = 2*pmin; |
| 1964 | int i; |
| 1965 | |
| 1966 | if (num_points < 2) |
| 1967 | return; |
| 1968 | |
| 1969 | /* We want the whole line, so adjust boundaries |
| 1970 | * to cover the entire power range. Note that |
| 1971 | * power values are already 0.25dB so no need |
| 1972 | * to multiply pwr_i by 2 */ |
| 1973 | if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { |
| 1974 | pwr_i = pmin; |
| 1975 | pmin = 0; |
| 1976 | pmax = 63; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1977 | } |
| 1978 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1979 | /* Find surrounding turning points (TPs) |
| 1980 | * and interpolate between them */ |
| 1981 | for (i = 0; (i <= (u16) (pmax - pmin)) && |
| 1982 | (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { |
| 1983 | |
| 1984 | /* We passed the right TP, move to the next set of TPs |
| 1985 | * if we pass the last TP, extrapolate above using the last |
| 1986 | * two TPs for ratio */ |
| 1987 | if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { |
| 1988 | idx[0]++; |
| 1989 | idx[1]++; |
| 1990 | } |
| 1991 | |
| 1992 | vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, |
| 1993 | pwr[idx[0]], pwr[idx[1]], |
| 1994 | vpd[idx[0]], vpd[idx[1]]); |
| 1995 | |
| 1996 | /* Increase by 0.5dB |
| 1997 | * (0.25 dB units) */ |
| 1998 | pwr_i += 2; |
| 1999 | } |
| 2000 | } |
| 2001 | |
| 2002 | /* |
| 2003 | * Get the surrounding per-channel power calibration piers |
| 2004 | * for a given frequency so that we can interpolate between |
| 2005 | * them and come up with an apropriate dataset for our current |
| 2006 | * channel. |
| 2007 | */ |
| 2008 | static void |
| 2009 | ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, |
| 2010 | struct ieee80211_channel *channel, |
| 2011 | struct ath5k_chan_pcal_info **pcinfo_l, |
| 2012 | struct ath5k_chan_pcal_info **pcinfo_r) |
| 2013 | { |
| 2014 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 2015 | struct ath5k_chan_pcal_info *pcinfo; |
| 2016 | u8 idx_l, idx_r; |
| 2017 | u8 mode, max, i; |
| 2018 | u32 target = channel->center_freq; |
| 2019 | |
| 2020 | idx_l = 0; |
| 2021 | idx_r = 0; |
| 2022 | |
| 2023 | if (!(channel->hw_value & CHANNEL_OFDM)) { |
| 2024 | pcinfo = ee->ee_pwr_cal_b; |
| 2025 | mode = AR5K_EEPROM_MODE_11B; |
| 2026 | } else if (channel->hw_value & CHANNEL_2GHZ) { |
| 2027 | pcinfo = ee->ee_pwr_cal_g; |
| 2028 | mode = AR5K_EEPROM_MODE_11G; |
| 2029 | } else { |
| 2030 | pcinfo = ee->ee_pwr_cal_a; |
| 2031 | mode = AR5K_EEPROM_MODE_11A; |
| 2032 | } |
| 2033 | max = ee->ee_n_piers[mode] - 1; |
| 2034 | |
| 2035 | /* Frequency is below our calibrated |
| 2036 | * range. Use the lowest power curve |
| 2037 | * we have */ |
| 2038 | if (target < pcinfo[0].freq) { |
| 2039 | idx_l = idx_r = 0; |
| 2040 | goto done; |
| 2041 | } |
| 2042 | |
| 2043 | /* Frequency is above our calibrated |
| 2044 | * range. Use the highest power curve |
| 2045 | * we have */ |
| 2046 | if (target > pcinfo[max].freq) { |
| 2047 | idx_l = idx_r = max; |
| 2048 | goto done; |
| 2049 | } |
| 2050 | |
| 2051 | /* Frequency is inside our calibrated |
| 2052 | * channel range. Pick the surrounding |
| 2053 | * calibration piers so that we can |
| 2054 | * interpolate */ |
| 2055 | for (i = 0; i <= max; i++) { |
| 2056 | |
| 2057 | /* Frequency matches one of our calibration |
| 2058 | * piers, no need to interpolate, just use |
| 2059 | * that calibration pier */ |
| 2060 | if (pcinfo[i].freq == target) { |
| 2061 | idx_l = idx_r = i; |
| 2062 | goto done; |
| 2063 | } |
| 2064 | |
| 2065 | /* We found a calibration pier that's above |
| 2066 | * frequency, use this pier and the previous |
| 2067 | * one to interpolate */ |
| 2068 | if (target < pcinfo[i].freq) { |
| 2069 | idx_r = i; |
| 2070 | idx_l = idx_r - 1; |
| 2071 | goto done; |
| 2072 | } |
| 2073 | } |
| 2074 | |
| 2075 | done: |
| 2076 | *pcinfo_l = &pcinfo[idx_l]; |
| 2077 | *pcinfo_r = &pcinfo[idx_r]; |
| 2078 | |
| 2079 | return; |
| 2080 | } |
| 2081 | |
| 2082 | /* |
| 2083 | * Get the surrounding per-rate power calibration data |
| 2084 | * for a given frequency and interpolate between power |
| 2085 | * values to set max target power supported by hw for |
| 2086 | * each rate. |
| 2087 | */ |
| 2088 | static void |
| 2089 | ath5k_get_rate_pcal_data(struct ath5k_hw *ah, |
| 2090 | struct ieee80211_channel *channel, |
| 2091 | struct ath5k_rate_pcal_info *rates) |
| 2092 | { |
| 2093 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 2094 | struct ath5k_rate_pcal_info *rpinfo; |
| 2095 | u8 idx_l, idx_r; |
| 2096 | u8 mode, max, i; |
| 2097 | u32 target = channel->center_freq; |
| 2098 | |
| 2099 | idx_l = 0; |
| 2100 | idx_r = 0; |
| 2101 | |
| 2102 | if (!(channel->hw_value & CHANNEL_OFDM)) { |
| 2103 | rpinfo = ee->ee_rate_tpwr_b; |
| 2104 | mode = AR5K_EEPROM_MODE_11B; |
| 2105 | } else if (channel->hw_value & CHANNEL_2GHZ) { |
| 2106 | rpinfo = ee->ee_rate_tpwr_g; |
| 2107 | mode = AR5K_EEPROM_MODE_11G; |
| 2108 | } else { |
| 2109 | rpinfo = ee->ee_rate_tpwr_a; |
| 2110 | mode = AR5K_EEPROM_MODE_11A; |
| 2111 | } |
| 2112 | max = ee->ee_rate_target_pwr_num[mode] - 1; |
| 2113 | |
| 2114 | /* Get the surrounding calibration |
| 2115 | * piers - same as above */ |
| 2116 | if (target < rpinfo[0].freq) { |
| 2117 | idx_l = idx_r = 0; |
| 2118 | goto done; |
| 2119 | } |
| 2120 | |
| 2121 | if (target > rpinfo[max].freq) { |
| 2122 | idx_l = idx_r = max; |
| 2123 | goto done; |
| 2124 | } |
| 2125 | |
| 2126 | for (i = 0; i <= max; i++) { |
| 2127 | |
| 2128 | if (rpinfo[i].freq == target) { |
| 2129 | idx_l = idx_r = i; |
| 2130 | goto done; |
| 2131 | } |
| 2132 | |
| 2133 | if (target < rpinfo[i].freq) { |
| 2134 | idx_r = i; |
| 2135 | idx_l = idx_r - 1; |
| 2136 | goto done; |
| 2137 | } |
| 2138 | } |
| 2139 | |
| 2140 | done: |
| 2141 | /* Now interpolate power value, based on the frequency */ |
| 2142 | rates->freq = target; |
| 2143 | |
| 2144 | rates->target_power_6to24 = |
| 2145 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, |
| 2146 | rpinfo[idx_r].freq, |
| 2147 | rpinfo[idx_l].target_power_6to24, |
| 2148 | rpinfo[idx_r].target_power_6to24); |
| 2149 | |
| 2150 | rates->target_power_36 = |
| 2151 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, |
| 2152 | rpinfo[idx_r].freq, |
| 2153 | rpinfo[idx_l].target_power_36, |
| 2154 | rpinfo[idx_r].target_power_36); |
| 2155 | |
| 2156 | rates->target_power_48 = |
| 2157 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, |
| 2158 | rpinfo[idx_r].freq, |
| 2159 | rpinfo[idx_l].target_power_48, |
| 2160 | rpinfo[idx_r].target_power_48); |
| 2161 | |
| 2162 | rates->target_power_54 = |
| 2163 | ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, |
| 2164 | rpinfo[idx_r].freq, |
| 2165 | rpinfo[idx_l].target_power_54, |
| 2166 | rpinfo[idx_r].target_power_54); |
| 2167 | } |
| 2168 | |
| 2169 | /* |
| 2170 | * Get the max edge power for this channel if |
| 2171 | * we have such data from EEPROM's Conformance Test |
| 2172 | * Limits (CTL), and limit max power if needed. |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2173 | */ |
| 2174 | static void |
| 2175 | ath5k_get_max_ctl_power(struct ath5k_hw *ah, |
| 2176 | struct ieee80211_channel *channel) |
| 2177 | { |
| 2178 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 2179 | struct ath5k_edge_power *rep = ee->ee_ctl_pwr; |
| 2180 | u8 *ctl_val = ee->ee_ctl; |
| 2181 | s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; |
| 2182 | s16 edge_pwr = 0; |
| 2183 | u8 rep_idx; |
| 2184 | u8 i, ctl_mode; |
| 2185 | u8 ctl_idx = 0xFF; |
| 2186 | u32 target = channel->center_freq; |
| 2187 | |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2188 | ctl_mode = ath_regd_get_band_ctl(&ah->ah_regulatory, channel->band); |
| 2189 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2190 | switch (channel->hw_value & CHANNEL_MODES) { |
| 2191 | case CHANNEL_A: |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2192 | ctl_mode |= AR5K_CTL_11A; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2193 | break; |
| 2194 | case CHANNEL_G: |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2195 | ctl_mode |= AR5K_CTL_11G; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2196 | break; |
| 2197 | case CHANNEL_B: |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2198 | ctl_mode |= AR5K_CTL_11B; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2199 | break; |
| 2200 | case CHANNEL_T: |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2201 | ctl_mode |= AR5K_CTL_TURBO; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2202 | break; |
| 2203 | case CHANNEL_TG: |
Bob Copeland | 6752ee9 | 2009-04-30 15:55:51 -0400 | [diff] [blame] | 2204 | ctl_mode |= AR5K_CTL_TURBOG; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2205 | break; |
| 2206 | case CHANNEL_XR: |
| 2207 | /* Fall through */ |
| 2208 | default: |
| 2209 | return; |
| 2210 | } |
Nick Kossifidis | 903b474 | 2008-02-28 14:50:50 -0500 | [diff] [blame] | 2211 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2212 | for (i = 0; i < ee->ee_ctls; i++) { |
| 2213 | if (ctl_val[i] == ctl_mode) { |
| 2214 | ctl_idx = i; |
| 2215 | break; |
| 2216 | } |
| 2217 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2218 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2219 | /* If we have a CTL dataset available grab it and find the |
| 2220 | * edge power for our frequency */ |
| 2221 | if (ctl_idx == 0xFF) |
| 2222 | return; |
| 2223 | |
| 2224 | /* Edge powers are sorted by frequency from lower |
| 2225 | * to higher. Each CTL corresponds to 8 edge power |
| 2226 | * measurements. */ |
| 2227 | rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; |
| 2228 | |
| 2229 | /* Don't do boundaries check because we |
| 2230 | * might have more that one bands defined |
| 2231 | * for this mode */ |
| 2232 | |
| 2233 | /* Get the edge power that's closer to our |
| 2234 | * frequency */ |
| 2235 | for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { |
| 2236 | rep_idx += i; |
| 2237 | if (target <= rep[rep_idx].freq) |
| 2238 | edge_pwr = (s16) rep[rep_idx].edge; |
| 2239 | } |
| 2240 | |
| 2241 | if (edge_pwr) |
| 2242 | ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); |
| 2243 | } |
| 2244 | |
| 2245 | |
| 2246 | /* |
| 2247 | * Power to PCDAC table functions |
| 2248 | */ |
| 2249 | |
| 2250 | /* |
| 2251 | * Fill Power to PCDAC table on RF5111 |
| 2252 | * |
| 2253 | * No further processing is needed for RF5111, the only thing we have to |
| 2254 | * do is fill the values below and above calibration range since eeprom data |
| 2255 | * may not cover the entire PCDAC table. |
| 2256 | */ |
| 2257 | static void |
| 2258 | ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, |
| 2259 | s16 *table_max) |
| 2260 | { |
| 2261 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
| 2262 | u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; |
| 2263 | u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; |
| 2264 | s16 min_pwr, max_pwr; |
| 2265 | |
| 2266 | /* Get table boundaries */ |
| 2267 | min_pwr = table_min[0]; |
| 2268 | pcdac_0 = pcdac_tmp[0]; |
| 2269 | |
| 2270 | max_pwr = table_max[0]; |
| 2271 | pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; |
| 2272 | |
| 2273 | /* Extrapolate below minimum using pcdac_0 */ |
| 2274 | pcdac_i = 0; |
| 2275 | for (i = 0; i < min_pwr; i++) |
| 2276 | pcdac_out[pcdac_i++] = pcdac_0; |
| 2277 | |
| 2278 | /* Copy values from pcdac_tmp */ |
| 2279 | pwr_idx = min_pwr; |
| 2280 | for (i = 0 ; pwr_idx <= max_pwr && |
| 2281 | pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { |
| 2282 | pcdac_out[pcdac_i++] = pcdac_tmp[i]; |
| 2283 | pwr_idx++; |
| 2284 | } |
| 2285 | |
| 2286 | /* Extrapolate above maximum */ |
| 2287 | while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) |
| 2288 | pcdac_out[pcdac_i++] = pcdac_n; |
| 2289 | |
| 2290 | } |
| 2291 | |
| 2292 | /* |
| 2293 | * Combine available XPD Curves and fill Linear Power to PCDAC table |
| 2294 | * on RF5112 |
| 2295 | * |
| 2296 | * RFX112 can have up to 2 curves (one for low txpower range and one for |
| 2297 | * higher txpower range). We need to put them both on pcdac_out and place |
| 2298 | * them in the correct location. In case we only have one curve available |
| 2299 | * just fit it on pcdac_out (it's supposed to cover the entire range of |
| 2300 | * available pwr levels since it's always the higher power curve). Extrapolate |
| 2301 | * below and above final table if needed. |
| 2302 | */ |
| 2303 | static void |
| 2304 | ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, |
| 2305 | s16 *table_max, u8 pdcurves) |
| 2306 | { |
| 2307 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
| 2308 | u8 *pcdac_low_pwr; |
| 2309 | u8 *pcdac_high_pwr; |
| 2310 | u8 *pcdac_tmp; |
| 2311 | u8 pwr; |
| 2312 | s16 max_pwr_idx; |
| 2313 | s16 min_pwr_idx; |
| 2314 | s16 mid_pwr_idx = 0; |
| 2315 | /* Edge flag turs on the 7nth bit on the PCDAC |
| 2316 | * to delcare the higher power curve (force values |
| 2317 | * to be greater than 64). If we only have one curve |
| 2318 | * we don't need to set this, if we have 2 curves and |
| 2319 | * fill the table backwards this can also be used to |
| 2320 | * switch from higher power curve to lower power curve */ |
| 2321 | u8 edge_flag; |
| 2322 | int i; |
| 2323 | |
| 2324 | /* When we have only one curve available |
| 2325 | * that's the higher power curve. If we have |
| 2326 | * two curves the first is the high power curve |
| 2327 | * and the next is the low power curve. */ |
| 2328 | if (pdcurves > 1) { |
| 2329 | pcdac_low_pwr = ah->ah_txpower.tmpL[1]; |
| 2330 | pcdac_high_pwr = ah->ah_txpower.tmpL[0]; |
| 2331 | mid_pwr_idx = table_max[1] - table_min[1] - 1; |
| 2332 | max_pwr_idx = (table_max[0] - table_min[0]) / 2; |
| 2333 | |
| 2334 | /* If table size goes beyond 31.5dB, keep the |
| 2335 | * upper 31.5dB range when setting tx power. |
| 2336 | * Note: 126 = 31.5 dB in quarter dB steps */ |
| 2337 | if (table_max[0] - table_min[1] > 126) |
| 2338 | min_pwr_idx = table_max[0] - 126; |
| 2339 | else |
| 2340 | min_pwr_idx = table_min[1]; |
| 2341 | |
| 2342 | /* Since we fill table backwards |
| 2343 | * start from high power curve */ |
| 2344 | pcdac_tmp = pcdac_high_pwr; |
| 2345 | |
| 2346 | edge_flag = 0x40; |
| 2347 | #if 0 |
| 2348 | /* If both min and max power limits are in lower |
| 2349 | * power curve's range, only use the low power curve. |
| 2350 | * TODO: min/max levels are related to target |
| 2351 | * power values requested from driver/user |
| 2352 | * XXX: Is this really needed ? */ |
| 2353 | if (min_pwr < table_max[1] && |
| 2354 | max_pwr < table_max[1]) { |
| 2355 | edge_flag = 0; |
| 2356 | pcdac_tmp = pcdac_low_pwr; |
| 2357 | max_pwr_idx = (table_max[1] - table_min[1])/2; |
| 2358 | } |
| 2359 | #endif |
| 2360 | } else { |
| 2361 | pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ |
| 2362 | pcdac_high_pwr = ah->ah_txpower.tmpL[0]; |
| 2363 | min_pwr_idx = table_min[0]; |
| 2364 | max_pwr_idx = (table_max[0] - table_min[0]) / 2; |
| 2365 | pcdac_tmp = pcdac_high_pwr; |
| 2366 | edge_flag = 0; |
| 2367 | } |
| 2368 | |
| 2369 | /* This is used when setting tx power*/ |
| 2370 | ah->ah_txpower.txp_min_idx = min_pwr_idx/2; |
| 2371 | |
| 2372 | /* Fill Power to PCDAC table backwards */ |
| 2373 | pwr = max_pwr_idx; |
| 2374 | for (i = 63; i >= 0; i--) { |
| 2375 | /* Entering lower power range, reset |
| 2376 | * edge flag and set pcdac_tmp to lower |
| 2377 | * power curve.*/ |
| 2378 | if (edge_flag == 0x40 && |
| 2379 | (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { |
| 2380 | edge_flag = 0x00; |
| 2381 | pcdac_tmp = pcdac_low_pwr; |
| 2382 | pwr = mid_pwr_idx/2; |
| 2383 | } |
| 2384 | |
| 2385 | /* Don't go below 1, extrapolate below if we have |
| 2386 | * already swithced to the lower power curve -or |
| 2387 | * we only have one curve and edge_flag is zero |
| 2388 | * anyway */ |
| 2389 | if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { |
| 2390 | while (i >= 0) { |
| 2391 | pcdac_out[i] = pcdac_out[i + 1]; |
| 2392 | i--; |
| 2393 | } |
| 2394 | break; |
| 2395 | } |
| 2396 | |
| 2397 | pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; |
| 2398 | |
| 2399 | /* Extrapolate above if pcdac is greater than |
| 2400 | * 126 -this can happen because we OR pcdac_out |
| 2401 | * value with edge_flag on high power curve */ |
| 2402 | if (pcdac_out[i] > 126) |
| 2403 | pcdac_out[i] = 126; |
| 2404 | |
| 2405 | /* Decrease by a 0.5dB step */ |
| 2406 | pwr--; |
| 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | /* Write PCDAC values on hw */ |
| 2411 | static void |
| 2412 | ath5k_setup_pcdac_table(struct ath5k_hw *ah) |
| 2413 | { |
| 2414 | u8 *pcdac_out = ah->ah_txpower.txp_pd_table; |
| 2415 | int i; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2416 | |
| 2417 | /* |
| 2418 | * Write TX power values |
| 2419 | */ |
| 2420 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { |
| 2421 | ath5k_hw_reg_write(ah, |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2422 | (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | |
| 2423 | (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2424 | AR5K_PHY_PCDAC_TXPOWER(i)); |
| 2425 | } |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2426 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2427 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2428 | |
| 2429 | /* |
| 2430 | * Power to PDADC table functions |
| 2431 | */ |
| 2432 | |
| 2433 | /* |
| 2434 | * Set the gain boundaries and create final Power to PDADC table |
| 2435 | * |
| 2436 | * We can have up to 4 pd curves, we need to do a simmilar process |
| 2437 | * as we do for RF5112. This time we don't have an edge_flag but we |
| 2438 | * set the gain boundaries on a separate register. |
| 2439 | */ |
| 2440 | static void |
| 2441 | ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, |
| 2442 | s16 *pwr_min, s16 *pwr_max, u8 pdcurves) |
| 2443 | { |
| 2444 | u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; |
| 2445 | u8 *pdadc_out = ah->ah_txpower.txp_pd_table; |
| 2446 | u8 *pdadc_tmp; |
| 2447 | s16 pdadc_0; |
| 2448 | u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; |
| 2449 | u8 pd_gain_overlap; |
| 2450 | |
| 2451 | /* Note: Register value is initialized on initvals |
| 2452 | * there is no feedback from hw. |
| 2453 | * XXX: What about pd_gain_overlap from EEPROM ? */ |
| 2454 | pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & |
| 2455 | AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; |
| 2456 | |
| 2457 | /* Create final PDADC table */ |
| 2458 | for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { |
| 2459 | pdadc_tmp = ah->ah_txpower.tmpL[pdg]; |
| 2460 | |
| 2461 | if (pdg == pdcurves - 1) |
| 2462 | /* 2 dB boundary stretch for last |
| 2463 | * (higher power) curve */ |
| 2464 | gain_boundaries[pdg] = pwr_max[pdg] + 4; |
| 2465 | else |
| 2466 | /* Set gain boundary in the middle |
| 2467 | * between this curve and the next one */ |
| 2468 | gain_boundaries[pdg] = |
| 2469 | (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; |
| 2470 | |
| 2471 | /* Sanity check in case our 2 db stretch got out of |
| 2472 | * range. */ |
| 2473 | if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) |
| 2474 | gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; |
| 2475 | |
| 2476 | /* For the first curve (lower power) |
| 2477 | * start from 0 dB */ |
| 2478 | if (pdg == 0) |
| 2479 | pdadc_0 = 0; |
| 2480 | else |
| 2481 | /* For the other curves use the gain overlap */ |
| 2482 | pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - |
| 2483 | pd_gain_overlap; |
| 2484 | |
| 2485 | /* Force each power step to be at least 0.5 dB */ |
| 2486 | if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) |
| 2487 | pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; |
| 2488 | else |
| 2489 | pwr_step = 1; |
| 2490 | |
| 2491 | /* If pdadc_0 is negative, we need to extrapolate |
| 2492 | * below this pdgain by a number of pwr_steps */ |
| 2493 | while ((pdadc_0 < 0) && (pdadc_i < 128)) { |
| 2494 | s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; |
| 2495 | pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; |
| 2496 | pdadc_0++; |
| 2497 | } |
| 2498 | |
| 2499 | /* Set last pwr level, using gain boundaries */ |
| 2500 | pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; |
| 2501 | /* Limit it to be inside pwr range */ |
| 2502 | table_size = pwr_max[pdg] - pwr_min[pdg]; |
| 2503 | max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; |
| 2504 | |
| 2505 | /* Fill pdadc_out table */ |
| 2506 | while (pdadc_0 < max_idx) |
| 2507 | pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; |
| 2508 | |
| 2509 | /* Need to extrapolate above this pdgain? */ |
| 2510 | if (pdadc_n <= max_idx) |
| 2511 | continue; |
| 2512 | |
| 2513 | /* Force each power step to be at least 0.5 dB */ |
| 2514 | if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) |
| 2515 | pwr_step = pdadc_tmp[table_size - 1] - |
| 2516 | pdadc_tmp[table_size - 2]; |
| 2517 | else |
| 2518 | pwr_step = 1; |
| 2519 | |
| 2520 | /* Extrapolate above */ |
| 2521 | while ((pdadc_0 < (s16) pdadc_n) && |
| 2522 | (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { |
| 2523 | s16 tmp = pdadc_tmp[table_size - 1] + |
| 2524 | (pdadc_0 - max_idx) * pwr_step; |
| 2525 | pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; |
| 2526 | pdadc_0++; |
| 2527 | } |
| 2528 | } |
| 2529 | |
| 2530 | while (pdg < AR5K_EEPROM_N_PD_GAINS) { |
| 2531 | gain_boundaries[pdg] = gain_boundaries[pdg - 1]; |
| 2532 | pdg++; |
| 2533 | } |
| 2534 | |
| 2535 | while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { |
| 2536 | pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; |
| 2537 | pdadc_i++; |
| 2538 | } |
| 2539 | |
| 2540 | /* Set gain boundaries */ |
| 2541 | ath5k_hw_reg_write(ah, |
| 2542 | AR5K_REG_SM(pd_gain_overlap, |
| 2543 | AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | |
| 2544 | AR5K_REG_SM(gain_boundaries[0], |
| 2545 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | |
| 2546 | AR5K_REG_SM(gain_boundaries[1], |
| 2547 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | |
| 2548 | AR5K_REG_SM(gain_boundaries[2], |
| 2549 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | |
| 2550 | AR5K_REG_SM(gain_boundaries[3], |
| 2551 | AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), |
| 2552 | AR5K_PHY_TPC_RG5); |
| 2553 | |
| 2554 | /* Used for setting rate power table */ |
| 2555 | ah->ah_txpower.txp_min_idx = pwr_min[0]; |
| 2556 | |
| 2557 | } |
| 2558 | |
| 2559 | /* Write PDADC values on hw */ |
| 2560 | static void |
| 2561 | ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, |
| 2562 | u8 pdcurves, u8 *pdg_to_idx) |
| 2563 | { |
| 2564 | u8 *pdadc_out = ah->ah_txpower.txp_pd_table; |
| 2565 | u32 reg; |
| 2566 | u8 i; |
| 2567 | |
| 2568 | /* Select the right pdgain curves */ |
| 2569 | |
| 2570 | /* Clear current settings */ |
| 2571 | reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); |
| 2572 | reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | |
| 2573 | AR5K_PHY_TPC_RG1_PDGAIN_2 | |
| 2574 | AR5K_PHY_TPC_RG1_PDGAIN_3 | |
| 2575 | AR5K_PHY_TPC_RG1_NUM_PD_GAIN); |
| 2576 | |
| 2577 | /* |
| 2578 | * Use pd_gains curve from eeprom |
| 2579 | * |
| 2580 | * This overrides the default setting from initvals |
| 2581 | * in case some vendors (e.g. Zcomax) don't use the default |
| 2582 | * curves. If we don't honor their settings we 'll get a |
| 2583 | * 5dB (1 * gain overlap ?) drop. |
| 2584 | */ |
| 2585 | reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); |
| 2586 | |
| 2587 | switch (pdcurves) { |
| 2588 | case 3: |
| 2589 | reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); |
| 2590 | /* Fall through */ |
| 2591 | case 2: |
| 2592 | reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); |
| 2593 | /* Fall through */ |
| 2594 | case 1: |
| 2595 | reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); |
| 2596 | break; |
| 2597 | } |
| 2598 | ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); |
| 2599 | |
| 2600 | /* |
| 2601 | * Write TX power values |
| 2602 | */ |
| 2603 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { |
| 2604 | ath5k_hw_reg_write(ah, |
| 2605 | ((pdadc_out[4*i + 0] & 0xff) << 0) | |
| 2606 | ((pdadc_out[4*i + 1] & 0xff) << 8) | |
| 2607 | ((pdadc_out[4*i + 2] & 0xff) << 16) | |
| 2608 | ((pdadc_out[4*i + 3] & 0xff) << 24), |
| 2609 | AR5K_PHY_PDADC_TXPOWER(i)); |
| 2610 | } |
| 2611 | } |
| 2612 | |
| 2613 | |
| 2614 | /* |
| 2615 | * Common code for PCDAC/PDADC tables |
| 2616 | */ |
| 2617 | |
| 2618 | /* |
| 2619 | * This is the main function that uses all of the above |
| 2620 | * to set PCDAC/PDADC table on hw for the current channel. |
| 2621 | * This table is used for tx power calibration on the basband, |
| 2622 | * without it we get weird tx power levels and in some cases |
| 2623 | * distorted spectral mask |
| 2624 | */ |
| 2625 | static int |
| 2626 | ath5k_setup_channel_powertable(struct ath5k_hw *ah, |
| 2627 | struct ieee80211_channel *channel, |
| 2628 | u8 ee_mode, u8 type) |
| 2629 | { |
| 2630 | struct ath5k_pdgain_info *pdg_L, *pdg_R; |
| 2631 | struct ath5k_chan_pcal_info *pcinfo_L; |
| 2632 | struct ath5k_chan_pcal_info *pcinfo_R; |
| 2633 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 2634 | u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; |
| 2635 | s16 table_min[AR5K_EEPROM_N_PD_GAINS]; |
| 2636 | s16 table_max[AR5K_EEPROM_N_PD_GAINS]; |
| 2637 | u8 *tmpL; |
| 2638 | u8 *tmpR; |
| 2639 | u32 target = channel->center_freq; |
| 2640 | int pdg, i; |
| 2641 | |
| 2642 | /* Get surounding freq piers for this channel */ |
| 2643 | ath5k_get_chan_pcal_surrounding_piers(ah, channel, |
| 2644 | &pcinfo_L, |
| 2645 | &pcinfo_R); |
| 2646 | |
| 2647 | /* Loop over pd gain curves on |
| 2648 | * surounding freq piers by index */ |
| 2649 | for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { |
| 2650 | |
| 2651 | /* Fill curves in reverse order |
| 2652 | * from lower power (max gain) |
| 2653 | * to higher power. Use curve -> idx |
| 2654 | * backmaping we did on eeprom init */ |
| 2655 | u8 idx = pdg_curve_to_idx[pdg]; |
| 2656 | |
| 2657 | /* Grab the needed curves by index */ |
| 2658 | pdg_L = &pcinfo_L->pd_curves[idx]; |
| 2659 | pdg_R = &pcinfo_R->pd_curves[idx]; |
| 2660 | |
| 2661 | /* Initialize the temp tables */ |
| 2662 | tmpL = ah->ah_txpower.tmpL[pdg]; |
| 2663 | tmpR = ah->ah_txpower.tmpR[pdg]; |
| 2664 | |
| 2665 | /* Set curve's x boundaries and create |
| 2666 | * curves so that they cover the same |
| 2667 | * range (if we don't do that one table |
| 2668 | * will have values on some range and the |
| 2669 | * other one won't have any so interpolation |
| 2670 | * will fail) */ |
| 2671 | table_min[pdg] = min(pdg_L->pd_pwr[0], |
| 2672 | pdg_R->pd_pwr[0]) / 2; |
| 2673 | |
| 2674 | table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], |
| 2675 | pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; |
| 2676 | |
| 2677 | /* Now create the curves on surrounding channels |
| 2678 | * and interpolate if needed to get the final |
| 2679 | * curve for this gain on this channel */ |
| 2680 | switch (type) { |
| 2681 | case AR5K_PWRTABLE_LINEAR_PCDAC: |
| 2682 | /* Override min/max so that we don't loose |
| 2683 | * accuracy (don't divide by 2) */ |
| 2684 | table_min[pdg] = min(pdg_L->pd_pwr[0], |
| 2685 | pdg_R->pd_pwr[0]); |
| 2686 | |
| 2687 | table_max[pdg] = |
| 2688 | max(pdg_L->pd_pwr[pdg_L->pd_points - 1], |
| 2689 | pdg_R->pd_pwr[pdg_R->pd_points - 1]); |
| 2690 | |
| 2691 | /* Override minimum so that we don't get |
| 2692 | * out of bounds while extrapolating |
| 2693 | * below. Don't do this when we have 2 |
| 2694 | * curves and we are on the high power curve |
| 2695 | * because table_min is ok in this case */ |
| 2696 | if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { |
| 2697 | |
| 2698 | table_min[pdg] = |
| 2699 | ath5k_get_linear_pcdac_min(pdg_L->pd_step, |
| 2700 | pdg_R->pd_step, |
| 2701 | pdg_L->pd_pwr, |
| 2702 | pdg_R->pd_pwr); |
| 2703 | |
| 2704 | /* Don't go too low because we will |
| 2705 | * miss the upper part of the curve. |
| 2706 | * Note: 126 = 31.5dB (max power supported) |
| 2707 | * in 0.25dB units */ |
| 2708 | if (table_max[pdg] - table_min[pdg] > 126) |
| 2709 | table_min[pdg] = table_max[pdg] - 126; |
| 2710 | } |
| 2711 | |
| 2712 | /* Fall through */ |
| 2713 | case AR5K_PWRTABLE_PWR_TO_PCDAC: |
| 2714 | case AR5K_PWRTABLE_PWR_TO_PDADC: |
| 2715 | |
| 2716 | ath5k_create_power_curve(table_min[pdg], |
| 2717 | table_max[pdg], |
| 2718 | pdg_L->pd_pwr, |
| 2719 | pdg_L->pd_step, |
| 2720 | pdg_L->pd_points, tmpL, type); |
| 2721 | |
| 2722 | /* We are in a calibration |
| 2723 | * pier, no need to interpolate |
| 2724 | * between freq piers */ |
| 2725 | if (pcinfo_L == pcinfo_R) |
| 2726 | continue; |
| 2727 | |
| 2728 | ath5k_create_power_curve(table_min[pdg], |
| 2729 | table_max[pdg], |
| 2730 | pdg_R->pd_pwr, |
| 2731 | pdg_R->pd_step, |
| 2732 | pdg_R->pd_points, tmpR, type); |
| 2733 | break; |
| 2734 | default: |
| 2735 | return -EINVAL; |
| 2736 | } |
| 2737 | |
| 2738 | /* Interpolate between curves |
| 2739 | * of surounding freq piers to |
| 2740 | * get the final curve for this |
| 2741 | * pd gain. Re-use tmpL for interpolation |
| 2742 | * output */ |
| 2743 | for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && |
| 2744 | (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { |
| 2745 | tmpL[i] = (u8) ath5k_get_interpolated_value(target, |
| 2746 | (s16) pcinfo_L->freq, |
| 2747 | (s16) pcinfo_R->freq, |
| 2748 | (s16) tmpL[i], |
| 2749 | (s16) tmpR[i]); |
| 2750 | } |
| 2751 | } |
| 2752 | |
| 2753 | /* Now we have a set of curves for this |
| 2754 | * channel on tmpL (x range is table_max - table_min |
| 2755 | * and y values are tmpL[pdg][]) sorted in the same |
| 2756 | * order as EEPROM (because we've used the backmaping). |
| 2757 | * So for RF5112 it's from higher power to lower power |
| 2758 | * and for RF2413 it's from lower power to higher power. |
| 2759 | * For RF5111 we only have one curve. */ |
| 2760 | |
| 2761 | /* Fill min and max power levels for this |
| 2762 | * channel by interpolating the values on |
| 2763 | * surounding channels to complete the dataset */ |
| 2764 | ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, |
| 2765 | (s16) pcinfo_L->freq, |
| 2766 | (s16) pcinfo_R->freq, |
| 2767 | pcinfo_L->min_pwr, pcinfo_R->min_pwr); |
| 2768 | |
| 2769 | ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, |
| 2770 | (s16) pcinfo_L->freq, |
| 2771 | (s16) pcinfo_R->freq, |
| 2772 | pcinfo_L->max_pwr, pcinfo_R->max_pwr); |
| 2773 | |
| 2774 | /* We are ready to go, fill PCDAC/PDADC |
| 2775 | * table and write settings on hardware */ |
| 2776 | switch (type) { |
| 2777 | case AR5K_PWRTABLE_LINEAR_PCDAC: |
| 2778 | /* For RF5112 we can have one or two curves |
| 2779 | * and each curve covers a certain power lvl |
| 2780 | * range so we need to do some more processing */ |
| 2781 | ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, |
| 2782 | ee->ee_pd_gains[ee_mode]); |
| 2783 | |
| 2784 | /* Set txp.offset so that we can |
| 2785 | * match max power value with max |
| 2786 | * table index */ |
| 2787 | ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); |
| 2788 | |
| 2789 | /* Write settings on hw */ |
| 2790 | ath5k_setup_pcdac_table(ah); |
| 2791 | break; |
| 2792 | case AR5K_PWRTABLE_PWR_TO_PCDAC: |
| 2793 | /* We are done for RF5111 since it has only |
| 2794 | * one curve, just fit the curve on the table */ |
| 2795 | ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); |
| 2796 | |
| 2797 | /* No rate powertable adjustment for RF5111 */ |
| 2798 | ah->ah_txpower.txp_min_idx = 0; |
| 2799 | ah->ah_txpower.txp_offset = 0; |
| 2800 | |
| 2801 | /* Write settings on hw */ |
| 2802 | ath5k_setup_pcdac_table(ah); |
| 2803 | break; |
| 2804 | case AR5K_PWRTABLE_PWR_TO_PDADC: |
| 2805 | /* Set PDADC boundaries and fill |
| 2806 | * final PDADC table */ |
| 2807 | ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, |
| 2808 | ee->ee_pd_gains[ee_mode]); |
| 2809 | |
| 2810 | /* Write settings on hw */ |
| 2811 | ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); |
| 2812 | |
| 2813 | /* Set txp.offset, note that table_min |
| 2814 | * can be negative */ |
| 2815 | ah->ah_txpower.txp_offset = table_min[0]; |
| 2816 | break; |
| 2817 | default: |
| 2818 | return -EINVAL; |
| 2819 | } |
| 2820 | |
| 2821 | return 0; |
| 2822 | } |
| 2823 | |
| 2824 | |
| 2825 | /* |
| 2826 | * Per-rate tx power setting |
| 2827 | * |
| 2828 | * This is the code that sets the desired tx power (below |
| 2829 | * maximum) on hw for each rate (we also have TPC that sets |
| 2830 | * power per packet). We do that by providing an index on the |
| 2831 | * PCDAC/PDADC table we set up. |
| 2832 | */ |
| 2833 | |
| 2834 | /* |
| 2835 | * Set rate power table |
| 2836 | * |
| 2837 | * For now we only limit txpower based on maximum tx power |
| 2838 | * supported by hw (what's inside rate_info). We need to limit |
| 2839 | * this even more, based on regulatory domain etc. |
| 2840 | * |
| 2841 | * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) |
| 2842 | * and is indexed as follows: |
| 2843 | * rates[0] - rates[7] -> OFDM rates |
| 2844 | * rates[8] - rates[14] -> CCK rates |
| 2845 | * rates[15] -> XR rates (they all have the same power) |
| 2846 | */ |
| 2847 | static void |
| 2848 | ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, |
| 2849 | struct ath5k_rate_pcal_info *rate_info, |
| 2850 | u8 ee_mode) |
| 2851 | { |
| 2852 | unsigned int i; |
| 2853 | u16 *rates; |
| 2854 | |
| 2855 | /* max_pwr is power level we got from driver/user in 0.5dB |
| 2856 | * units, switch to 0.25dB units so we can compare */ |
| 2857 | max_pwr *= 2; |
| 2858 | max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; |
| 2859 | |
| 2860 | /* apply rate limits */ |
| 2861 | rates = ah->ah_txpower.txp_rates_power_table; |
| 2862 | |
| 2863 | /* OFDM rates 6 to 24Mb/s */ |
| 2864 | for (i = 0; i < 5; i++) |
| 2865 | rates[i] = min(max_pwr, rate_info->target_power_6to24); |
| 2866 | |
| 2867 | /* Rest OFDM rates */ |
| 2868 | rates[5] = min(rates[0], rate_info->target_power_36); |
| 2869 | rates[6] = min(rates[0], rate_info->target_power_48); |
| 2870 | rates[7] = min(rates[0], rate_info->target_power_54); |
| 2871 | |
| 2872 | /* CCK rates */ |
| 2873 | /* 1L */ |
| 2874 | rates[8] = min(rates[0], rate_info->target_power_6to24); |
| 2875 | /* 2L */ |
| 2876 | rates[9] = min(rates[0], rate_info->target_power_36); |
| 2877 | /* 2S */ |
| 2878 | rates[10] = min(rates[0], rate_info->target_power_36); |
| 2879 | /* 5L */ |
| 2880 | rates[11] = min(rates[0], rate_info->target_power_48); |
| 2881 | /* 5S */ |
| 2882 | rates[12] = min(rates[0], rate_info->target_power_48); |
| 2883 | /* 11L */ |
| 2884 | rates[13] = min(rates[0], rate_info->target_power_54); |
| 2885 | /* 11S */ |
| 2886 | rates[14] = min(rates[0], rate_info->target_power_54); |
| 2887 | |
| 2888 | /* XR rates */ |
| 2889 | rates[15] = min(rates[0], rate_info->target_power_6to24); |
| 2890 | |
| 2891 | /* CCK rates have different peak to average ratio |
| 2892 | * so we have to tweak their power so that gainf |
| 2893 | * correction works ok. For this we use OFDM to |
| 2894 | * CCK delta from eeprom */ |
| 2895 | if ((ee_mode == AR5K_EEPROM_MODE_11G) && |
| 2896 | (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) |
| 2897 | for (i = 8; i <= 15; i++) |
| 2898 | rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; |
| 2899 | |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 2900 | /* Now that we have all rates setup use table offset to |
| 2901 | * match the power range set by user with the power indices |
| 2902 | * on PCDAC/PDADC table */ |
| 2903 | for (i = 0; i < 16; i++) { |
| 2904 | rates[i] += ah->ah_txpower.txp_offset; |
| 2905 | /* Don't get out of bounds */ |
| 2906 | if (rates[i] > 63) |
| 2907 | rates[i] = 63; |
| 2908 | } |
| 2909 | |
| 2910 | /* Min/max in 0.25dB units */ |
| 2911 | ah->ah_txpower.txp_min_pwr = 2 * rates[7]; |
| 2912 | ah->ah_txpower.txp_max_pwr = 2 * rates[0]; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 2913 | ah->ah_txpower.txp_ofdm = rates[7]; |
| 2914 | } |
| 2915 | |
| 2916 | |
| 2917 | /* |
| 2918 | * Set transmition power |
| 2919 | */ |
| 2920 | int |
| 2921 | ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
| 2922 | u8 ee_mode, u8 txpower) |
| 2923 | { |
| 2924 | struct ath5k_rate_pcal_info rate_info; |
| 2925 | u8 type; |
| 2926 | int ret; |
| 2927 | |
| 2928 | ATH5K_TRACE(ah->ah_sc); |
| 2929 | if (txpower > AR5K_TUNE_MAX_TXPOWER) { |
| 2930 | ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); |
| 2931 | return -EINVAL; |
| 2932 | } |
| 2933 | if (txpower == 0) |
| 2934 | txpower = AR5K_TUNE_DEFAULT_TXPOWER; |
| 2935 | |
| 2936 | /* Reset TX power values */ |
| 2937 | memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); |
| 2938 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; |
| 2939 | ah->ah_txpower.txp_min_pwr = 0; |
| 2940 | ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; |
| 2941 | |
| 2942 | /* Initialize TX power table */ |
| 2943 | switch (ah->ah_radio) { |
| 2944 | case AR5K_RF5111: |
| 2945 | type = AR5K_PWRTABLE_PWR_TO_PCDAC; |
| 2946 | break; |
| 2947 | case AR5K_RF5112: |
| 2948 | type = AR5K_PWRTABLE_LINEAR_PCDAC; |
| 2949 | break; |
| 2950 | case AR5K_RF2413: |
| 2951 | case AR5K_RF5413: |
| 2952 | case AR5K_RF2316: |
| 2953 | case AR5K_RF2317: |
| 2954 | case AR5K_RF2425: |
| 2955 | type = AR5K_PWRTABLE_PWR_TO_PDADC; |
| 2956 | break; |
| 2957 | default: |
| 2958 | return -EINVAL; |
| 2959 | } |
| 2960 | |
| 2961 | /* FIXME: Only on channel/mode change */ |
| 2962 | ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); |
| 2963 | if (ret) |
| 2964 | return ret; |
| 2965 | |
| 2966 | /* Limit max power if we have a CTL available */ |
| 2967 | ath5k_get_max_ctl_power(ah, channel); |
| 2968 | |
| 2969 | /* FIXME: Tx power limit for this regdomain |
| 2970 | * XXX: Mac80211/CRDA will do that anyway ? */ |
| 2971 | |
| 2972 | /* FIXME: Antenna reduction stuff */ |
| 2973 | |
| 2974 | /* FIXME: Limit power on turbo modes */ |
| 2975 | |
| 2976 | /* FIXME: TPC scale reduction */ |
| 2977 | |
| 2978 | /* Get surounding channels for per-rate power table |
| 2979 | * calibration */ |
| 2980 | ath5k_get_rate_pcal_data(ah, channel, &rate_info); |
| 2981 | |
| 2982 | /* Setup rate power table */ |
| 2983 | ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); |
| 2984 | |
| 2985 | /* Write rate power table on hw */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2986 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | |
| 2987 | AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | |
| 2988 | AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); |
| 2989 | |
| 2990 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | |
| 2991 | AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | |
| 2992 | AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); |
| 2993 | |
| 2994 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | |
| 2995 | AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | |
| 2996 | AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); |
| 2997 | |
| 2998 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | |
| 2999 | AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | |
| 3000 | AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); |
| 3001 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 3002 | /* FIXME: TPC support */ |
| 3003 | if (ah->ah_txpower.txp_tpc) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3004 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | |
| 3005 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 3006 | |
| 3007 | ath5k_hw_reg_write(ah, |
| 3008 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | |
| 3009 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | |
| 3010 | AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), |
| 3011 | AR5K_TPC); |
| 3012 | } else { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3013 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | |
| 3014 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 3015 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3016 | |
| 3017 | return 0; |
| 3018 | } |
| 3019 | |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 3020 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3021 | { |
| 3022 | /*Just a try M.F.*/ |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 3023 | struct ieee80211_channel *channel = ah->ah_current_channel; |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 3024 | u8 ee_mode; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3025 | |
| 3026 | ATH5K_TRACE(ah->ah_sc); |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 3027 | |
| 3028 | switch (channel->hw_value & CHANNEL_MODES) { |
| 3029 | case CHANNEL_A: |
| 3030 | case CHANNEL_T: |
| 3031 | case CHANNEL_XR: |
| 3032 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 3033 | break; |
| 3034 | case CHANNEL_G: |
| 3035 | case CHANNEL_TG: |
| 3036 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 3037 | break; |
| 3038 | case CHANNEL_B: |
| 3039 | ee_mode = AR5K_EEPROM_MODE_11B; |
| 3040 | break; |
| 3041 | default: |
| 3042 | ATH5K_ERR(ah->ah_sc, |
| 3043 | "invalid channel: %d\n", channel->center_freq); |
| 3044 | return -EINVAL; |
| 3045 | } |
| 3046 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3047 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 3048 | "changing txpower to %d\n", txpower); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3049 | |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 3050 | return ath5k_hw_txpower(ah, channel, ee_mode, txpower); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3051 | } |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 3052 | |
| 3053 | #undef _ATH5K_PHY |