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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
AnilKumar Ch571ccb22012-10-15 18:05:39 +05302/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
AnilKumar Ch571ccb22012-10-15 18:05:39 +05304 */
5
6/*
7 * AM335x Starter Kit
8 * http://www.ti.com/tool/tmdssk3358
9 */
10
11/dts-v1/;
12
Florian Vaussardeb33ef662013-06-03 16:12:22 +020013#include "am33xx.dtsi"
Laurent Pincharteb9bdef2013-07-18 00:54:24 +020014#include <dt-bindings/pwm/pwm.h>
Eliad Peller99f84ca2015-03-18 18:38:29 +020015#include <dt-bindings/interrupt-controller/irq.h>
AnilKumar Ch571ccb22012-10-15 18:05:39 +053016
17/ {
18 model = "TI AM335x EVM-SK";
19 compatible = "ti,am335x-evmsk", "ti,am33xx";
20
21 cpus {
22 cpu@0 {
23 cpu0-supply = <&vdd1_reg>;
24 };
25 };
26
Javier Martinez Canillas278cb792016-08-31 12:35:30 +020027 memory@80000000 {
AnilKumar Ch571ccb22012-10-15 18:05:39 +053028 device_type = "memory";
29 reg = <0x80000000 0x10000000>; /* 256 MB */
30 };
31
Lokesh Vutlab7639732017-01-18 09:33:23 +053032 chosen {
33 stdout-path = &uart0;
34 };
35
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -040036 vbat: fixedregulator0 {
AnilKumar Ch571ccb22012-10-15 18:05:39 +053037 compatible = "regulator-fixed";
38 regulator-name = "vbat";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 regulator-boot-on;
42 };
43
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -040044 lis3_reg: fixedregulator1 {
AnilKumar Ch571ccb22012-10-15 18:05:39 +053045 compatible = "regulator-fixed";
46 regulator-name = "lis3_reg";
47 regulator-boot-on;
48 };
AnilKumar Ch29b0b8432012-11-06 19:18:36 +053049
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -040050 wl12xx_vmmc: fixedregulator2 {
Imre Kaloz90f4f012014-03-03 10:02:56 +010051 pinctrl-names = "default";
52 pinctrl-0 = <&wl12xx_gpio>;
53 compatible = "regulator-fixed";
54 regulator-name = "vwl1271";
55 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <1800000>;
57 gpio = <&gpio1 29 0>;
58 startup-delay-us = <70000>;
59 enable-active-high;
60 };
61
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -040062 vtt_fixed: fixedregulator3 {
Dave Gerlach12f03232014-05-05 14:58:29 -050063 compatible = "regulator-fixed";
64 regulator-name = "vtt";
65 regulator-min-microvolt = <1500000>;
66 regulator-max-microvolt = <1500000>;
67 gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
68 regulator-always-on;
69 regulator-boot-on;
70 enable-active-high;
71 };
72
Peter Ujfalusi66913702019-03-15 12:59:17 +020073 /* TPS79518 */
74 v1_8d_reg: fixedregulator-v1_8d {
75 compatible = "regulator-fixed";
76 regulator-name = "v1_8d";
77 vin-supply = <&vbat>;
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <1800000>;
80 };
81
82 /* TPS78633 */
83 v3_3d_reg: fixedregulator-v3_3d {
84 compatible = "regulator-fixed";
85 regulator-name = "v3_3d";
86 vin-supply = <&vbat>;
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 };
90
AnilKumar Ch29b0b8432012-11-06 19:18:36 +053091 leds {
Vaibhav Hiremathb8f70c32013-03-26 15:42:15 +053092 pinctrl-names = "default";
93 pinctrl-0 = <&user_leds_s0>;
94
AnilKumar Ch29b0b8432012-11-06 19:18:36 +053095 compatible = "gpio-leds";
96
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040097 led1 {
AnilKumar Ch29b0b8432012-11-06 19:18:36 +053098 label = "evmsk:green:usr0";
Florian Vaussarde94233c2013-06-03 16:12:23 +020099 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530100 default-state = "off";
101 };
102
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400103 led2 {
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530104 label = "evmsk:green:usr1";
Florian Vaussarde94233c2013-06-03 16:12:23 +0200105 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530106 default-state = "off";
107 };
108
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400109 led3 {
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530110 label = "evmsk:green:mmc0";
Florian Vaussarde94233c2013-06-03 16:12:23 +0200111 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530112 linux,default-trigger = "mmc0";
113 default-state = "off";
114 };
115
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400116 led4 {
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530117 label = "evmsk:green:heartbeat";
Florian Vaussarde94233c2013-06-03 16:12:23 +0200118 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
AnilKumar Ch29b0b8432012-11-06 19:18:36 +0530119 linux,default-trigger = "heartbeat";
120 default-state = "off";
121 };
122 };
AnilKumar Ch00834b72012-11-06 19:18:38 +0530123
Javier Martinez Canillas57a78a82016-08-01 12:47:01 -0400124 gpio_buttons: gpio_buttons0 {
AnilKumar Ch00834b72012-11-06 19:18:38 +0530125 compatible = "gpio-keys";
126 #address-cells = <1>;
127 #size-cells = <0>;
128
Javier Martinez Canillas57a78a82016-08-01 12:47:01 -0400129 switch1 {
AnilKumar Ch00834b72012-11-06 19:18:38 +0530130 label = "button0";
131 linux,code = <0x100>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200132 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
AnilKumar Ch00834b72012-11-06 19:18:38 +0530133 };
134
Javier Martinez Canillas57a78a82016-08-01 12:47:01 -0400135 switch2 {
AnilKumar Ch00834b72012-11-06 19:18:38 +0530136 label = "button1";
137 linux,code = <0x101>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200138 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
AnilKumar Ch00834b72012-11-06 19:18:38 +0530139 };
140
Javier Martinez Canillas57a78a82016-08-01 12:47:01 -0400141 switch3 {
AnilKumar Ch00834b72012-11-06 19:18:38 +0530142 label = "button2";
143 linux,code = <0x102>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200144 gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
Sudeep Holla3efda002015-10-21 11:10:06 +0100145 wakeup-source;
AnilKumar Ch00834b72012-11-06 19:18:38 +0530146 };
147
Javier Martinez Canillas57a78a82016-08-01 12:47:01 -0400148 switch4 {
AnilKumar Ch00834b72012-11-06 19:18:38 +0530149 label = "button3";
150 linux,code = <0x103>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200151 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
AnilKumar Ch00834b72012-11-06 19:18:38 +0530152 };
153 };
Philip Avinash1632fbd2013-06-06 15:52:39 +0200154
Peter Ujfalusi2a9fb4a2018-05-08 13:04:33 +0300155 lcd_bl: backlight {
Philip Avinash1632fbd2013-06-06 15:52:39 +0200156 compatible = "pwm-backlight";
Laurent Pincharteb9bdef2013-07-18 00:54:24 +0200157 pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
Philip Avinash1632fbd2013-06-06 15:52:39 +0200158 brightness-levels = <0 58 61 66 75 90 125 170 255>;
159 default-brightness-level = <8>;
160 };
Peter Ujfalusib4529852013-10-20 20:04:11 +0300161
162 sound {
Peter Ujfalusib3c616e2015-07-02 17:06:31 +0300163 compatible = "simple-audio-card";
164 simple-audio-card,name = "AM335x-EVMSK";
165 simple-audio-card,widgets =
166 "Headphone", "Headphone Jack";
167 simple-audio-card,routing =
168 "Headphone Jack", "HPLOUT",
169 "Headphone Jack", "HPROUT";
170 simple-audio-card,format = "dsp_b";
171 simple-audio-card,bitclock-master = <&sound_master>;
172 simple-audio-card,frame-master = <&sound_master>;
173 simple-audio-card,bitclock-inversion;
174
175 simple-audio-card,cpu {
176 sound-dai = <&mcasp1>;
177 };
178
179 sound_master: simple-audio-card,codec {
180 sound-dai = <&tlv320aic3106>;
181 system-clock-frequency = <24000000>;
182 };
Peter Ujfalusib4529852013-10-20 20:04:11 +0300183 };
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500184
185 panel {
186 compatible = "ti,tilcdc,panel";
187 pinctrl-names = "default", "sleep";
188 pinctrl-0 = <&lcd_pins_default>;
189 pinctrl-1 = <&lcd_pins_sleep>;
Peter Ujfalusi2a9fb4a2018-05-08 13:04:33 +0300190 backlight = <&lcd_bl>;
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500191 status = "okay";
192 panel-info {
Jyri Sarha5dffb6842016-09-16 14:50:12 +0300193 ac-bias = <255>;
194 ac-bias-intrpt = <0>;
195 dma-burst-sz = <16>;
196 bpp = <32>;
197 fdd = <0x80>;
198 sync-edge = <0>;
199 sync-ctrl = <1>;
200 raster-order = <0>;
201 fifo-th = <0>;
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500202 };
203 display-timings {
204 480x272 {
Jyri Sarha5dffb6842016-09-16 14:50:12 +0300205 hactive = <480>;
206 vactive = <272>;
207 hback-porch = <43>;
208 hfront-porch = <8>;
209 hsync-len = <4>;
210 vback-porch = <12>;
211 vfront-porch = <4>;
212 vsync-len = <10>;
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500213 clock-frequency = <9000000>;
Jyri Sarha5dffb6842016-09-16 14:50:12 +0300214 hsync-active = <0>;
215 vsync-active = <0>;
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500216 };
217 };
218 };
AnilKumar Ch571ccb22012-10-15 18:05:39 +0530219};
220
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200221&am33xx_pinmux {
222 pinctrl-names = "default";
223 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
224
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500225 lcd_pins_default: lcd_pins_default {
226 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200227 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */
228 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */
229 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */
230 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */
231 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */
232 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */
233 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */
234 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */
235 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
236 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
237 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
238 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
239 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
240 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
241 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
242 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
243 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
244 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
245 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
246 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
247 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
248 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
249 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
250 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
251 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
252 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
253 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
254 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500255 >;
256 };
257
258 lcd_pins_sleep: lcd_pins_sleep {
259 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200260 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */
261 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */
262 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */
263 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */
264 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */
265 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */
266 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */
267 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */
268 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
269 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
270 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
271 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
272 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
273 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
274 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
275 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
276 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
277 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
278 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
279 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
280 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
281 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
282 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
283 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
284 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
285 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
286 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
287 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500288 >;
289 };
290
291
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200292 user_leds_s0: user_leds_s0 {
293 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200294 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */
295 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */
296 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */
297 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200298 >;
299 };
300
301 gpio_keys_s0: gpio_keys_s0 {
302 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200303 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
304 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
305 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */
306 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200307 >;
308 };
309
310 i2c0_pins: pinmux_i2c0_pins {
311 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200312 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
313 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200314 >;
315 };
316
317 uart0_pins: pinmux_uart0_pins {
318 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200319 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
320 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200321 >;
322 };
323
324 clkout2_pin: pinmux_clkout2_pin {
325 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200326 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200327 >;
328 };
329
330 ecap2_pins: backlight_pins {
331 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200332 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200333 >;
334 };
335
336 cpsw_default: cpsw_default {
337 pinctrl-single,pins = <
338 /* Slave 1 */
Christina Quast1f757e02019-04-09 18:03:45 +0200339 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
340 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
341 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
342 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
343 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
344 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
345 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
346 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
347 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
348 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
349 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
350 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200351
352 /* Slave 2 */
Christina Quast1f757e02019-04-09 18:03:45 +0200353 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
354 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
355 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
356 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
357 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
358 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
359 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
360 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
361 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
362 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
363 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
364 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200365 >;
366 };
367
368 cpsw_sleep: cpsw_sleep {
369 pinctrl-single,pins = <
370 /* Slave 1 reset value */
Christina Quast1f757e02019-04-09 18:03:45 +0200371 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
372 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
373 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
374 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
375 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
376 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
377 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
378 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
379 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
380 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
381 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
382 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200383
384 /* Slave 2 reset value*/
Christina Quast1f757e02019-04-09 18:03:45 +0200385 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
386 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
387 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
388 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
389 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
390 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
391 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
392 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
393 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
394 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
395 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
396 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200397 >;
398 };
399
400 davinci_mdio_default: davinci_mdio_default {
401 pinctrl-single,pins = <
402 /* MDIO */
Christina Quast1f757e02019-04-09 18:03:45 +0200403 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
404 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200405 >;
406 };
407
408 davinci_mdio_sleep: davinci_mdio_sleep {
409 pinctrl-single,pins = <
410 /* MDIO reset value */
Christina Quast1f757e02019-04-09 18:03:45 +0200411 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
412 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200413 >;
414 };
Peter Ujfalusib4529852013-10-20 20:04:11 +0300415
Peter Ujfalusi29ea5ef2013-12-23 11:28:35 +0200416 mmc1_pins: pinmux_mmc1_pins {
417 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200418 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
419 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
420 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
421 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
422 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
423 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
424 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
425 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
Peter Ujfalusi29ea5ef2013-12-23 11:28:35 +0200426 >;
427 };
428
Peter Ujfalusib4529852013-10-20 20:04:11 +0300429 mcasp1_pins: mcasp1_pins {
430 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200431 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
432 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
433 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
434 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
Peter Ujfalusib4529852013-10-20 20:04:11 +0300435 >;
436 };
Imre Kaloz90f4f012014-03-03 10:02:56 +0100437
Peter Ujfalusied8830f2015-07-02 17:06:30 +0300438 mcasp1_pins_sleep: mcasp1_pins_sleep {
439 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200440 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
441 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
442 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
443 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
Peter Ujfalusied8830f2015-07-02 17:06:30 +0300444 >;
445 };
446
Imre Kaloz90f4f012014-03-03 10:02:56 +0100447 mmc2_pins: pinmux_mmc2_pins {
448 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200449 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
450 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
451 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
452 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
453 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
454 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
455 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
Imre Kaloz90f4f012014-03-03 10:02:56 +0100456 >;
457 };
458
459 wl12xx_gpio: pinmux_wl12xx_gpio {
460 pinctrl-single,pins = <
Christina Quast1f757e02019-04-09 18:03:45 +0200461 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
Imre Kaloz90f4f012014-03-03 10:02:56 +0100462 >;
463 };
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200464};
465
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200466&uart0 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&uart0_pins>;
469
470 status = "okay";
471};
472
473&i2c0 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&i2c0_pins>;
476
477 status = "okay";
478 clock-frequency = <400000>;
479
480 tps: tps@2d {
481 reg = <0x2d>;
482 };
483
484 lis331dlh: lis331dlh@18 {
485 compatible = "st,lis331dlh", "st,lis3lv02d";
486 reg = <0x18>;
487 Vdd-supply = <&lis3_reg>;
488 Vdd_IO-supply = <&lis3_reg>;
489
490 st,click-single-x;
491 st,click-single-y;
492 st,click-single-z;
493 st,click-thresh-x = <10>;
494 st,click-thresh-y = <10>;
495 st,click-thresh-z = <10>;
496 st,irq1-click;
497 st,irq2-click;
498 st,wakeup-x-lo;
499 st,wakeup-x-hi;
500 st,wakeup-y-lo;
501 st,wakeup-y-hi;
502 st,wakeup-z-lo;
503 st,wakeup-z-hi;
504 st,min-limit-x = <120>;
505 st,min-limit-y = <120>;
506 st,min-limit-z = <140>;
507 st,max-limit-x = <550>;
508 st,max-limit-y = <550>;
509 st,max-limit-z = <750>;
510 };
Peter Ujfalusib4529852013-10-20 20:04:11 +0300511
512 tlv320aic3106: tlv320aic3106@1b {
Peter Ujfalusib3c616e2015-07-02 17:06:31 +0300513 #sound-dai-cells = <0>;
Peter Ujfalusib4529852013-10-20 20:04:11 +0300514 compatible = "ti,tlv320aic3106";
515 reg = <0x1b>;
516 status = "okay";
517
518 /* Regulators */
Peter Ujfalusi66913702019-03-15 12:59:17 +0200519 AVDD-supply = <&v3_3d_reg>;
520 IOVDD-supply = <&v3_3d_reg>;
521 DRVDD-supply = <&v3_3d_reg>;
522 DVDD-supply = <&v1_8d_reg>;
Peter Ujfalusib4529852013-10-20 20:04:11 +0300523 };
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200524};
525
526&usb {
527 status = "okay";
Guido Martínez0f686d22014-04-28 17:54:34 -0300528};
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200529
Guido Martínez0f686d22014-04-28 17:54:34 -0300530&usb_ctrl_mod {
531 status = "okay";
532};
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200533
Guido Martínez0f686d22014-04-28 17:54:34 -0300534&usb0_phy {
535 status = "okay";
536};
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200537
Guido Martínez0f686d22014-04-28 17:54:34 -0300538&usb1_phy {
539 status = "okay";
540};
Yegor Yefremoveda1a4b2014-02-28 08:19:04 +0100541
Guido Martínez0f686d22014-04-28 17:54:34 -0300542&usb0 {
543 status = "okay";
544};
Yegor Yefremoveda1a4b2014-02-28 08:19:04 +0100545
Guido Martínez0f686d22014-04-28 17:54:34 -0300546&usb1 {
547 status = "okay";
548 dr_mode = "host";
549};
Yegor Yefremovcae2a9e2014-03-10 16:26:57 +0100550
Guido Martínez0f686d22014-04-28 17:54:34 -0300551&cppi41dma {
552 status = "okay";
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200553};
554
555&epwmss2 {
556 status = "okay";
557
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -0800558 ecap2: ecap@100 {
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200559 status = "okay";
560 pinctrl-names = "default";
561 pinctrl-0 = <&ecap2_pins>;
562 };
563};
564
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200565#include "tps65910.dtsi"
AnilKumar Ch571ccb22012-10-15 18:05:39 +0530566
567&tps {
568 vcc1-supply = <&vbat>;
569 vcc2-supply = <&vbat>;
570 vcc3-supply = <&vbat>;
571 vcc4-supply = <&vbat>;
572 vcc5-supply = <&vbat>;
573 vcc6-supply = <&vbat>;
574 vcc7-supply = <&vbat>;
575 vccio-supply = <&vbat>;
576
577 regulators {
578 vrtc_reg: regulator@0 {
579 regulator-always-on;
580 };
581
582 vio_reg: regulator@1 {
583 regulator-always-on;
584 };
585
586 vdd1_reg: regulator@2 {
587 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
588 regulator-name = "vdd_mpu";
589 regulator-min-microvolt = <912500>;
Dave Gerlachfb515b82016-05-18 18:36:26 -0500590 regulator-max-microvolt = <1351500>;
AnilKumar Ch571ccb22012-10-15 18:05:39 +0530591 regulator-boot-on;
592 regulator-always-on;
593 };
594
595 vdd2_reg: regulator@3 {
596 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
597 regulator-name = "vdd_core";
598 regulator-min-microvolt = <912500>;
599 regulator-max-microvolt = <1150000>;
600 regulator-boot-on;
601 regulator-always-on;
602 };
603
604 vdd3_reg: regulator@4 {
605 regulator-always-on;
606 };
607
608 vdig1_reg: regulator@5 {
609 regulator-always-on;
610 };
611
612 vdig2_reg: regulator@6 {
613 regulator-always-on;
614 };
615
616 vpll_reg: regulator@7 {
617 regulator-always-on;
618 };
619
620 vdac_reg: regulator@8 {
621 regulator-always-on;
622 };
623
624 vaux1_reg: regulator@9 {
625 regulator-always-on;
626 };
627
628 vaux2_reg: regulator@10 {
629 regulator-always-on;
630 };
631
632 vaux33_reg: regulator@11 {
633 regulator-always-on;
634 };
635
636 vmmc_reg: regulator@12 {
Matt Porter55b44522013-09-10 14:24:39 -0500637 regulator-min-microvolt = <1800000>;
638 regulator-max-microvolt = <3300000>;
AnilKumar Ch571ccb22012-10-15 18:05:39 +0530639 regulator-always-on;
640 };
641 };
642};
Mugunthan V N94a924c2013-06-07 17:02:53 +0530643
644&mac {
645 pinctrl-names = "default", "sleep";
646 pinctrl-0 = <&cpsw_default>;
647 pinctrl-1 = <&cpsw_sleep>;
Yegor Yefremov18c49af2014-03-05 08:29:19 +0100648 dual_emac = <1>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200649 status = "okay";
Mugunthan V N94a924c2013-06-07 17:02:53 +0530650};
651
652&davinci_mdio {
653 pinctrl-names = "default", "sleep";
654 pinctrl-0 = <&davinci_mdio_default>;
655 pinctrl-1 = <&davinci_mdio_sleep>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200656 status = "okay";
Grygorii Strashko53c2c222018-09-08 19:05:05 -0500657
658 ethphy0: ethernet-phy@0 {
659 reg = <0>;
660 };
661
662 ethphy1: ethernet-phy@1 {
663 reg = <1>;
664 };
Mugunthan V N94a924c2013-06-07 17:02:53 +0530665};
Linus Torvalds496322b2013-07-09 18:24:39 -0700666
Mugunthan V Nf6655d62013-06-03 20:10:09 +0000667&cpsw_emac0 {
Grygorii Strashko53c2c222018-09-08 19:05:05 -0500668 phy-handle = <&ethphy0>;
Peter Ujfalusi759c9622019-02-19 08:46:32 -0800669 phy-mode = "rgmii-id";
Yegor Yefremov18c49af2014-03-05 08:29:19 +0100670 dual_emac_res_vlan = <1>;
Mugunthan V Nf6655d62013-06-03 20:10:09 +0000671};
672
673&cpsw_emac1 {
Grygorii Strashko53c2c222018-09-08 19:05:05 -0500674 phy-handle = <&ethphy1>;
Peter Ujfalusi759c9622019-02-19 08:46:32 -0800675 phy-mode = "rgmii-id";
Yegor Yefremov18c49af2014-03-05 08:29:19 +0100676 dual_emac_res_vlan = <2>;
Mugunthan V Nf6655d62013-06-03 20:10:09 +0000677};
Matt Porter55b44522013-09-10 14:24:39 -0500678
679&mmc1 {
680 status = "okay";
681 vmmc-supply = <&vmmc_reg>;
Balaji T K0d8d40f2013-09-27 17:05:10 +0530682 bus-width = <4>;
Peter Ujfalusi29ea5ef2013-12-23 11:28:35 +0200683 pinctrl-names = "default";
684 pinctrl-0 = <&mmc1_pins>;
Mugunthan V Nc7ce74b2015-10-12 14:37:10 +0530685 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Matt Porter55b44522013-09-10 14:24:39 -0500686};
Mark A. Greerf8302e12013-08-23 14:12:35 -0700687
688&sham {
689 status = "okay";
690};
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700691
692&aes {
693 status = "okay";
694};
Rajendra Nayak6046adb2013-10-09 15:42:01 +0530695
696&gpio0 {
697 ti,no-reset-on-init;
698};
Peter Ujfalusib4529852013-10-20 20:04:11 +0300699
Imre Kaloz90f4f012014-03-03 10:02:56 +0100700&mmc2 {
701 status = "okay";
702 vmmc-supply = <&wl12xx_vmmc>;
703 ti,non-removable;
704 bus-width = <4>;
705 cap-power-off-card;
Reizer, Eyal9bcf53f2017-03-26 08:53:10 +0000706 keep-power-in-suspend;
Imre Kaloz90f4f012014-03-03 10:02:56 +0100707 pinctrl-names = "default";
708 pinctrl-0 = <&mmc2_pins>;
Eliad Peller99f84ca2015-03-18 18:38:29 +0200709
710 #address-cells = <1>;
711 #size-cells = <0>;
712 wlcore: wlcore@2 {
713 compatible = "ti,wl1271";
714 reg = <2>;
Romain Izardf25bf742015-05-20 10:00:10 -0700715 interrupt-parent = <&gpio0>;
Tony Lindgren572cf7d2018-07-02 23:57:20 -0700716 interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */
Eliad Peller99f84ca2015-03-18 18:38:29 +0200717 ref-clock-frequency = <38400000>;
718 };
Imre Kaloz90f4f012014-03-03 10:02:56 +0100719};
720
Peter Ujfalusib4529852013-10-20 20:04:11 +0300721&mcasp1 {
Peter Ujfalusib3c616e2015-07-02 17:06:31 +0300722 #sound-dai-cells = <0>;
Peter Ujfalusied8830f2015-07-02 17:06:30 +0300723 pinctrl-names = "default", "sleep";
Peter Ujfalusic8b518a2015-07-02 17:06:29 +0300724 pinctrl-0 = <&mcasp1_pins>;
Peter Ujfalusied8830f2015-07-02 17:06:30 +0300725 pinctrl-1 = <&mcasp1_pins_sleep>;
Peter Ujfalusib4529852013-10-20 20:04:11 +0300726
Peter Ujfalusic8b518a2015-07-02 17:06:29 +0300727 status = "okay";
Peter Ujfalusib4529852013-10-20 20:04:11 +0300728
Peter Ujfalusic8b518a2015-07-02 17:06:29 +0300729 op-mode = <0>; /* MCASP_IIS_MODE */
730 tdm-slots = <2>;
731 /* 4 serializers */
732 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
733 0 0 1 2
734 >;
735 tx-num-evt = <32>;
736 rx-num-evt = <32>;
Peter Ujfalusib4529852013-10-20 20:04:11 +0300737};
Linus Torvalds4937e2a2013-11-15 16:43:53 -0800738
Felipe Balbi2c027b72013-11-10 23:58:31 -0800739&tscadc {
740 status = "okay";
741 tsc {
742 ti,wires = <4>;
743 ti,x-plate-resistance = <200>;
744 ti,coordinate-readouts = <5>;
745 ti,wire-config = <0x00 0x11 0x22 0x33>;
746 };
747};
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500748
749&lcdc {
Jyri Sarha5dffb6842016-09-16 14:50:12 +0300750 status = "okay";
Jyri Sarha3dc46742016-09-16 14:50:13 +0300751
752 blue-and-red-wiring = "crossed";
Darren Etheridgeb675d1e2014-07-01 16:00:20 -0500753};
Keerthy3fb5c892016-10-27 11:18:08 +0530754
755&rtc {
Tero Kristo69fd70c2018-08-31 18:14:49 +0300756 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Keerthy3fb5c892016-10-27 11:18:08 +0530757 clock-names = "ext-clk", "int-clk";
758};