blob: 77c0736d3c9e98103fcd862a60e2cfdc2c498e33 [file] [log] [blame]
Jeeja KPd255b092015-07-21 23:53:56 +05301/*
2 * skl-message.c - HDA DSP interface for FW registration, Pipe and Module
3 * configurations
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
7 * Jeeja KP <jeeja.kp@intel.com>
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl.h"
27#include "../common/sst-dsp.h"
28#include "../common/sst-dsp-priv.h"
Jeeja KP23db4722015-08-01 19:40:41 +053029#include "skl-topology.h"
30#include "skl-tplg-interface.h"
Jeeja KPd255b092015-07-21 23:53:56 +053031
32static int skl_alloc_dma_buf(struct device *dev,
33 struct snd_dma_buffer *dmab, size_t size)
34{
35 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
36 struct hdac_bus *bus = ebus_to_hbus(ebus);
37
38 if (!bus)
39 return -ENODEV;
40
41 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, size, dmab);
42}
43
44static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab)
45{
46 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
47 struct hdac_bus *bus = ebus_to_hbus(ebus);
48
49 if (!bus)
50 return -ENODEV;
51
52 bus->io_ops->dma_free_pages(bus, dmab);
53
54 return 0;
55}
56
57int skl_init_dsp(struct skl *skl)
58{
59 void __iomem *mmio_base;
60 struct hdac_ext_bus *ebus = &skl->ebus;
61 struct hdac_bus *bus = ebus_to_hbus(ebus);
62 int irq = bus->irq;
63 struct skl_dsp_loader_ops loader_ops;
64 int ret;
65
66 loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
67 loader_ops.free_dma_buf = skl_free_dma_buf;
68
69 /* enable ppcap interrupt */
70 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
71 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
72
73 /* read the BAR of the ADSP MMIO */
74 mmio_base = pci_ioremap_bar(skl->pci, 4);
75 if (mmio_base == NULL) {
76 dev_err(bus->dev, "ioremap error\n");
77 return -ENXIO;
78 }
79
80 ret = skl_sst_dsp_init(bus->dev, mmio_base, irq,
81 loader_ops, &skl->skl_sst);
82
83 dev_dbg(bus->dev, "dsp registration status=%d\n", ret);
84
85 return ret;
86}
87
88void skl_free_dsp(struct skl *skl)
89{
90 struct hdac_ext_bus *ebus = &skl->ebus;
91 struct hdac_bus *bus = ebus_to_hbus(ebus);
92 struct skl_sst *ctx = skl->skl_sst;
93
94 /* disable ppcap interrupt */
95 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
96
97 skl_sst_dsp_cleanup(bus->dev, ctx);
98 if (ctx->dsp->addr.lpe)
99 iounmap(ctx->dsp->addr.lpe);
100}
101
102int skl_suspend_dsp(struct skl *skl)
103{
104 struct skl_sst *ctx = skl->skl_sst;
105 int ret;
106
107 /* if ppcap is not supported return 0 */
108 if (!skl->ebus.ppcap)
109 return 0;
110
111 ret = skl_dsp_sleep(ctx->dsp);
112 if (ret < 0)
113 return ret;
114
115 /* disable ppcap interrupt */
116 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
117 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false);
118
119 return 0;
120}
121
122int skl_resume_dsp(struct skl *skl)
123{
124 struct skl_sst *ctx = skl->skl_sst;
125
126 /* if ppcap is not supported return 0 */
127 if (!skl->ebus.ppcap)
128 return 0;
129
130 /* enable ppcap interrupt */
131 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
132 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
133
134 return skl_dsp_wake(ctx->dsp);
135}
Jeeja KP23db4722015-08-01 19:40:41 +0530136
137enum skl_bitdepth skl_get_bit_depth(int params)
138{
139 switch (params) {
140 case 8:
141 return SKL_DEPTH_8BIT;
142
143 case 16:
144 return SKL_DEPTH_16BIT;
145
146 case 24:
147 return SKL_DEPTH_24BIT;
148
149 case 32:
150 return SKL_DEPTH_32BIT;
151
152 default:
153 return SKL_DEPTH_INVALID;
154
155 }
156}
157
158static u32 skl_create_channel_map(enum skl_ch_cfg ch_cfg)
159{
160 u32 config;
161
162 switch (ch_cfg) {
163 case SKL_CH_CFG_MONO:
164 config = (0xFFFFFFF0 | SKL_CHANNEL_LEFT);
165 break;
166
167 case SKL_CH_CFG_STEREO:
168 config = (0xFFFFFF00 | SKL_CHANNEL_LEFT
169 | (SKL_CHANNEL_RIGHT << 4));
170 break;
171
172 case SKL_CH_CFG_2_1:
173 config = (0xFFFFF000 | SKL_CHANNEL_LEFT
174 | (SKL_CHANNEL_RIGHT << 4)
175 | (SKL_CHANNEL_LFE << 8));
176 break;
177
178 case SKL_CH_CFG_3_0:
179 config = (0xFFFFF000 | SKL_CHANNEL_LEFT
180 | (SKL_CHANNEL_CENTER << 4)
181 | (SKL_CHANNEL_RIGHT << 8));
182 break;
183
184 case SKL_CH_CFG_3_1:
185 config = (0xFFFF0000 | SKL_CHANNEL_LEFT
186 | (SKL_CHANNEL_CENTER << 4)
187 | (SKL_CHANNEL_RIGHT << 8)
188 | (SKL_CHANNEL_LFE << 12));
189 break;
190
191 case SKL_CH_CFG_QUATRO:
192 config = (0xFFFF0000 | SKL_CHANNEL_LEFT
193 | (SKL_CHANNEL_RIGHT << 4)
194 | (SKL_CHANNEL_LEFT_SURROUND << 8)
195 | (SKL_CHANNEL_RIGHT_SURROUND << 12));
196 break;
197
198 case SKL_CH_CFG_4_0:
199 config = (0xFFFF0000 | SKL_CHANNEL_LEFT
200 | (SKL_CHANNEL_CENTER << 4)
201 | (SKL_CHANNEL_RIGHT << 8)
202 | (SKL_CHANNEL_CENTER_SURROUND << 12));
203 break;
204
205 case SKL_CH_CFG_5_0:
206 config = (0xFFF00000 | SKL_CHANNEL_LEFT
207 | (SKL_CHANNEL_CENTER << 4)
208 | (SKL_CHANNEL_RIGHT << 8)
209 | (SKL_CHANNEL_LEFT_SURROUND << 12)
210 | (SKL_CHANNEL_RIGHT_SURROUND << 16));
211 break;
212
213 case SKL_CH_CFG_5_1:
214 config = (0xFF000000 | SKL_CHANNEL_CENTER
215 | (SKL_CHANNEL_LEFT << 4)
216 | (SKL_CHANNEL_RIGHT << 8)
217 | (SKL_CHANNEL_LEFT_SURROUND << 12)
218 | (SKL_CHANNEL_RIGHT_SURROUND << 16)
219 | (SKL_CHANNEL_LFE << 20));
220 break;
221
222 case SKL_CH_CFG_DUAL_MONO:
223 config = (0xFFFFFF00 | SKL_CHANNEL_LEFT
224 | (SKL_CHANNEL_LEFT << 4));
225 break;
226
227 case SKL_CH_CFG_I2S_DUAL_STEREO_0:
228 config = (0xFFFFFF00 | SKL_CHANNEL_LEFT
229 | (SKL_CHANNEL_RIGHT << 4));
230 break;
231
232 case SKL_CH_CFG_I2S_DUAL_STEREO_1:
233 config = (0xFFFF00FF | (SKL_CHANNEL_LEFT << 8)
234 | (SKL_CHANNEL_RIGHT << 12));
235 break;
236
237 default:
238 config = 0xFFFFFFFF;
239 break;
240
241 }
242
243 return config;
244}
245
246/*
247 * Each module in DSP expects a base module configuration, which consists of
248 * PCM format information, which we calculate in driver and resource values
249 * which are read from widget information passed through topology binary
250 * This is send when we create a module with INIT_INSTANCE IPC msg
251 */
252static void skl_set_base_module_format(struct skl_sst *ctx,
253 struct skl_module_cfg *mconfig,
254 struct skl_base_cfg *base_cfg)
255{
256 struct skl_module_fmt *format = &mconfig->in_fmt;
257
258 base_cfg->audio_fmt.number_of_channels = (u8)format->channels;
259
260 base_cfg->audio_fmt.s_freq = format->s_freq;
261 base_cfg->audio_fmt.bit_depth = format->bit_depth;
262 base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth;
263 base_cfg->audio_fmt.ch_cfg = format->ch_cfg;
264
265 dev_dbg(ctx->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n",
266 format->bit_depth, format->valid_bit_depth,
267 format->ch_cfg);
268
269 base_cfg->audio_fmt.channel_map = skl_create_channel_map(
270 base_cfg->audio_fmt.ch_cfg);
271
272 base_cfg->audio_fmt.interleaving = SKL_INTERLEAVING_PER_CHANNEL;
273
274 base_cfg->cps = mconfig->mcps;
275 base_cfg->ibs = mconfig->ibs;
276 base_cfg->obs = mconfig->obs;
277}
278
279/*
280 * Copies copier capabilities into copier module and updates copier module
281 * config size.
282 */
283static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
284 struct skl_cpr_cfg *cpr_mconfig)
285{
286 if (mconfig->formats_config.caps_size == 0)
287 return;
288
289 memcpy(cpr_mconfig->gtw_cfg.config_data,
290 mconfig->formats_config.caps,
291 mconfig->formats_config.caps_size);
292
293 cpr_mconfig->gtw_cfg.config_length =
294 (mconfig->formats_config.caps_size) / 4;
295}
296
297/*
298 * Calculate the gatewat settings required for copier module, type of
299 * gateway and index of gateway to use
300 */
301static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx,
302 struct skl_module_cfg *mconfig,
303 struct skl_cpr_cfg *cpr_mconfig)
304{
305 union skl_connector_node_id node_id = {0};
Jeeja KPd7b18812015-10-22 23:22:38 +0530306 union skl_ssp_dma_node ssp_node = {0};
Jeeja KP23db4722015-08-01 19:40:41 +0530307 struct skl_pipe_params *params = mconfig->pipe->p_params;
308
309 switch (mconfig->dev_type) {
310 case SKL_DEVICE_BT:
311 node_id.node.dma_type =
312 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
313 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
314 SKL_DMA_I2S_LINK_INPUT_CLASS;
315 node_id.node.vindex = params->host_dma_id +
316 (mconfig->vbus_id << 3);
317 break;
318
319 case SKL_DEVICE_I2S:
320 node_id.node.dma_type =
321 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
322 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
323 SKL_DMA_I2S_LINK_INPUT_CLASS;
Jeeja KPd7b18812015-10-22 23:22:38 +0530324 ssp_node.dma_node.time_slot_index = mconfig->time_slot;
325 ssp_node.dma_node.i2s_instance = mconfig->vbus_id;
326 node_id.node.vindex = ssp_node.val;
Jeeja KP23db4722015-08-01 19:40:41 +0530327 break;
328
329 case SKL_DEVICE_DMIC:
330 node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS;
331 node_id.node.vindex = mconfig->vbus_id +
332 (mconfig->time_slot);
333 break;
334
335 case SKL_DEVICE_HDALINK:
336 node_id.node.dma_type =
337 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
338 SKL_DMA_HDA_LINK_OUTPUT_CLASS :
339 SKL_DMA_HDA_LINK_INPUT_CLASS;
340 node_id.node.vindex = params->link_dma_id;
341 break;
342
343 default:
344 node_id.node.dma_type =
345 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
346 SKL_DMA_HDA_HOST_OUTPUT_CLASS :
347 SKL_DMA_HDA_HOST_INPUT_CLASS;
348 node_id.node.vindex = params->host_dma_id;
349 break;
350 }
351
352 cpr_mconfig->gtw_cfg.node_id = node_id.val;
353
354 if (SKL_CONN_SOURCE == mconfig->hw_conn_type)
355 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->obs;
356 else
357 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->ibs;
358
359 cpr_mconfig->cpr_feature_mask = 0;
360 cpr_mconfig->gtw_cfg.config_length = 0;
361
362 skl_copy_copier_caps(mconfig, cpr_mconfig);
363}
364
365static void skl_setup_out_format(struct skl_sst *ctx,
366 struct skl_module_cfg *mconfig,
367 struct skl_audio_data_format *out_fmt)
368{
369 struct skl_module_fmt *format = &mconfig->out_fmt;
370
371 out_fmt->number_of_channels = (u8)format->channels;
372 out_fmt->s_freq = format->s_freq;
373 out_fmt->bit_depth = format->bit_depth;
374 out_fmt->valid_bit_depth = format->valid_bit_depth;
375 out_fmt->ch_cfg = format->ch_cfg;
376
377 out_fmt->channel_map = skl_create_channel_map(out_fmt->ch_cfg);
378 out_fmt->interleaving = SKL_INTERLEAVING_PER_CHANNEL;
379
380 dev_dbg(ctx->dev, "copier out format chan=%d fre=%d bitdepth=%d\n",
381 out_fmt->number_of_channels, format->s_freq, format->bit_depth);
382}
383
384/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530385 * DSP needs SRC module for frequency conversion, SRC takes base module
386 * configuration and the target frequency as extra parameter passed as src
387 * config
388 */
389static void skl_set_src_format(struct skl_sst *ctx,
390 struct skl_module_cfg *mconfig,
391 struct skl_src_module_cfg *src_mconfig)
392{
393 struct skl_module_fmt *fmt = &mconfig->out_fmt;
394
395 skl_set_base_module_format(ctx, mconfig,
396 (struct skl_base_cfg *)src_mconfig);
397
398 src_mconfig->src_cfg = fmt->s_freq;
399}
400
401/*
402 * DSP needs updown module to do channel conversion. updown module take base
403 * module configuration and channel configuration
404 * It also take coefficients and now we have defaults applied here
405 */
406static void skl_set_updown_mixer_format(struct skl_sst *ctx,
407 struct skl_module_cfg *mconfig,
408 struct skl_up_down_mixer_cfg *mixer_mconfig)
409{
410 struct skl_module_fmt *fmt = &mconfig->out_fmt;
411 int i = 0;
412
413 skl_set_base_module_format(ctx, mconfig,
414 (struct skl_base_cfg *)mixer_mconfig);
415 mixer_mconfig->out_ch_cfg = fmt->ch_cfg;
416
417 /* Select F/W default coefficient */
418 mixer_mconfig->coeff_sel = 0x0;
419
420 /* User coeff, don't care since we are selecting F/W defaults */
421 for (i = 0; i < UP_DOWN_MIXER_MAX_COEFF; i++)
422 mixer_mconfig->coeff[i] = 0xDEADBEEF;
423}
424
425/*
Jeeja KP23db4722015-08-01 19:40:41 +0530426 * 'copier' is DSP internal module which copies data from Host DMA (HDA host
427 * dma) or link (hda link, SSP, PDM)
428 * Here we calculate the copier module parameters, like PCM format, output
429 * format, gateway settings
430 * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg
431 */
432static void skl_set_copier_format(struct skl_sst *ctx,
433 struct skl_module_cfg *mconfig,
434 struct skl_cpr_cfg *cpr_mconfig)
435{
436 struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt;
437 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig;
438
439 skl_set_base_module_format(ctx, mconfig, base_cfg);
440
441 skl_setup_out_format(ctx, mconfig, out_fmt);
442 skl_setup_cpr_gateway_cfg(ctx, mconfig, cpr_mconfig);
443}
444
445static u16 skl_get_module_param_size(struct skl_sst *ctx,
446 struct skl_module_cfg *mconfig)
447{
448 u16 param_size;
449
450 switch (mconfig->m_type) {
451 case SKL_MODULE_TYPE_COPIER:
452 param_size = sizeof(struct skl_cpr_cfg);
453 param_size += mconfig->formats_config.caps_size;
454 return param_size;
455
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530456 case SKL_MODULE_TYPE_SRCINT:
457 return sizeof(struct skl_src_module_cfg);
458
459 case SKL_MODULE_TYPE_UPDWMIX:
460 return sizeof(struct skl_up_down_mixer_cfg);
461
Jeeja KP23db4722015-08-01 19:40:41 +0530462 default:
463 /*
464 * return only base cfg when no specific module type is
465 * specified
466 */
467 return sizeof(struct skl_base_cfg);
468 }
469
470 return 0;
471}
472
473/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530474 * DSP firmware supports various modules like copier, SRC, updown etc.
475 * These modules required various parameters to be calculated and sent for
476 * the module initialization to DSP. By default a generic module needs only
477 * base module format configuration
Jeeja KP23db4722015-08-01 19:40:41 +0530478 */
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530479
Jeeja KP23db4722015-08-01 19:40:41 +0530480static int skl_set_module_format(struct skl_sst *ctx,
481 struct skl_module_cfg *module_config,
482 u16 *module_config_size,
483 void **param_data)
484{
485 u16 param_size;
486
487 param_size = skl_get_module_param_size(ctx, module_config);
488
489 *param_data = kzalloc(param_size, GFP_KERNEL);
490 if (NULL == *param_data)
491 return -ENOMEM;
492
493 *module_config_size = param_size;
494
495 switch (module_config->m_type) {
496 case SKL_MODULE_TYPE_COPIER:
497 skl_set_copier_format(ctx, module_config, *param_data);
498 break;
499
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530500 case SKL_MODULE_TYPE_SRCINT:
501 skl_set_src_format(ctx, module_config, *param_data);
502 break;
503
504 case SKL_MODULE_TYPE_UPDWMIX:
505 skl_set_updown_mixer_format(ctx, module_config, *param_data);
506 break;
507
Jeeja KP23db4722015-08-01 19:40:41 +0530508 default:
509 skl_set_base_module_format(ctx, module_config, *param_data);
510 break;
511
512 }
513
514 dev_dbg(ctx->dev, "Module type=%d config size: %d bytes\n",
515 module_config->id.module_id, param_size);
516 print_hex_dump(KERN_DEBUG, "Module params:", DUMP_PREFIX_OFFSET, 8, 4,
517 *param_data, param_size, false);
518 return 0;
519}
520
521static int skl_get_queue_index(struct skl_module_pin *mpin,
522 struct skl_module_inst_id id, int max)
523{
524 int i;
525
526 for (i = 0; i < max; i++) {
527 if (mpin[i].id.module_id == id.module_id &&
528 mpin[i].id.instance_id == id.instance_id)
529 return i;
530 }
531
532 return -EINVAL;
533}
534
535/*
536 * Allocates queue for each module.
537 * if dynamic, the pin_index is allocated 0 to max_pin.
538 * In static, the pin_index is fixed based on module_id and instance id
539 */
540static int skl_alloc_queue(struct skl_module_pin *mpin,
541 struct skl_module_inst_id id, int max)
542{
543 int i;
544
545 /*
546 * if pin in dynamic, find first free pin
547 * otherwise find match module and instance id pin as topology will
548 * ensure a unique pin is assigned to this so no need to
549 * allocate/free
550 */
551 for (i = 0; i < max; i++) {
552 if (mpin[i].is_dynamic) {
553 if (!mpin[i].in_use) {
554 mpin[i].in_use = true;
555 mpin[i].id.module_id = id.module_id;
556 mpin[i].id.instance_id = id.instance_id;
557 return i;
558 }
559 } else {
560 if (mpin[i].id.module_id == id.module_id &&
561 mpin[i].id.instance_id == id.instance_id)
562 return i;
563 }
564 }
565
566 return -EINVAL;
567}
568
569static void skl_free_queue(struct skl_module_pin *mpin, int q_index)
570{
571 if (mpin[q_index].is_dynamic) {
572 mpin[q_index].in_use = false;
573 mpin[q_index].id.module_id = 0;
574 mpin[q_index].id.instance_id = 0;
575 }
576}
Jeeja KPbeb73b22015-08-01 19:40:43 +0530577
578/*
579 * A module needs to be instanataited in DSP. A mdoule is present in a
580 * collection of module referred as a PIPE.
581 * We first calculate the module format, based on module type and then
582 * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper
583 */
584int skl_init_module(struct skl_sst *ctx,
585 struct skl_module_cfg *mconfig, char *param)
586{
587 u16 module_config_size = 0;
588 void *param_data = NULL;
589 int ret;
590 struct skl_ipc_init_instance_msg msg;
591
592 dev_dbg(ctx->dev, "%s: module_id = %d instance=%d\n", __func__,
593 mconfig->id.module_id, mconfig->id.instance_id);
594
595 if (mconfig->pipe->state != SKL_PIPE_CREATED) {
596 dev_err(ctx->dev, "Pipe not created state= %d pipe_id= %d\n",
597 mconfig->pipe->state, mconfig->pipe->ppl_id);
598 return -EIO;
599 }
600
601 ret = skl_set_module_format(ctx, mconfig,
602 &module_config_size, &param_data);
603 if (ret < 0) {
604 dev_err(ctx->dev, "Failed to set module format ret=%d\n", ret);
605 return ret;
606 }
607
608 msg.module_id = mconfig->id.module_id;
609 msg.instance_id = mconfig->id.instance_id;
610 msg.ppl_instance_id = mconfig->pipe->ppl_id;
611 msg.param_data_size = module_config_size;
612 msg.core_id = mconfig->core_id;
613
614 ret = skl_ipc_init_instance(&ctx->ipc, &msg, param_data);
615 if (ret < 0) {
616 dev_err(ctx->dev, "Failed to init instance ret=%d\n", ret);
617 kfree(param_data);
618 return ret;
619 }
620 mconfig->m_state = SKL_MODULE_INIT_DONE;
621
622 return ret;
623}
624
625static void skl_dump_bind_info(struct skl_sst *ctx, struct skl_module_cfg
626 *src_module, struct skl_module_cfg *dst_module)
627{
628 dev_dbg(ctx->dev, "%s: src module_id = %d src_instance=%d\n",
629 __func__, src_module->id.module_id, src_module->id.instance_id);
630 dev_dbg(ctx->dev, "%s: dst_module=%d dst_instacne=%d\n", __func__,
631 dst_module->id.module_id, dst_module->id.instance_id);
632
633 dev_dbg(ctx->dev, "src_module state = %d dst module state = %d\n",
634 src_module->m_state, dst_module->m_state);
635}
636
637/*
638 * On module freeup, we need to unbind the module with modules
639 * it is already bind.
640 * Find the pin allocated and unbind then using bind_unbind IPC
641 */
642int skl_unbind_modules(struct skl_sst *ctx,
643 struct skl_module_cfg *src_mcfg,
644 struct skl_module_cfg *dst_mcfg)
645{
646 int ret;
647 struct skl_ipc_bind_unbind_msg msg;
648 struct skl_module_inst_id src_id = src_mcfg->id;
649 struct skl_module_inst_id dst_id = dst_mcfg->id;
650 int in_max = dst_mcfg->max_in_queue;
651 int out_max = src_mcfg->max_out_queue;
652 int src_index, dst_index;
653
654 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
655
656 if (src_mcfg->m_state != SKL_MODULE_BIND_DONE)
657 return 0;
658
659 /*
660 * if intra module unbind, check if both modules are BIND,
661 * then send unbind
662 */
663 if ((src_mcfg->pipe->ppl_id != dst_mcfg->pipe->ppl_id) &&
664 dst_mcfg->m_state != SKL_MODULE_BIND_DONE)
665 return 0;
666 else if (src_mcfg->m_state < SKL_MODULE_INIT_DONE &&
667 dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
668 return 0;
669
670 /* get src queue index */
671 src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max);
672 if (src_index < 0)
673 return -EINVAL;
674
675 msg.src_queue = src_mcfg->m_out_pin[src_index].pin_index;
676
677 /* get dst queue index */
678 dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max);
679 if (dst_index < 0)
680 return -EINVAL;
681
682 msg.dst_queue = dst_mcfg->m_in_pin[dst_index].pin_index;
683
684 msg.module_id = src_mcfg->id.module_id;
685 msg.instance_id = src_mcfg->id.instance_id;
686 msg.dst_module_id = dst_mcfg->id.module_id;
687 msg.dst_instance_id = dst_mcfg->id.instance_id;
688 msg.bind = false;
689
690 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
691 if (!ret) {
692 src_mcfg->m_state = SKL_MODULE_UNINIT;
693 /* free queue only if unbind is success */
694 skl_free_queue(src_mcfg->m_out_pin, src_index);
695 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
696 }
697
698 return ret;
699}
700
701/*
702 * Once a module is instantiated it need to be 'bind' with other modules in
703 * the pipeline. For binding we need to find the module pins which are bind
704 * together
705 * This function finds the pins and then sends bund_unbind IPC message to
706 * DSP using IPC helper
707 */
708int skl_bind_modules(struct skl_sst *ctx,
709 struct skl_module_cfg *src_mcfg,
710 struct skl_module_cfg *dst_mcfg)
711{
712 int ret;
713 struct skl_ipc_bind_unbind_msg msg;
714 struct skl_module_inst_id src_id = src_mcfg->id;
715 struct skl_module_inst_id dst_id = dst_mcfg->id;
716 int in_max = dst_mcfg->max_in_queue;
717 int out_max = src_mcfg->max_out_queue;
718 int src_index, dst_index;
719
720 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
721
722 if (src_mcfg->m_state < SKL_MODULE_INIT_DONE &&
723 dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
724 return 0;
725
726 src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_id, out_max);
727 if (src_index < 0)
728 return -EINVAL;
729
730 msg.src_queue = src_mcfg->m_out_pin[src_index].pin_index;
731 dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_id, in_max);
732 if (dst_index < 0) {
733 skl_free_queue(src_mcfg->m_out_pin, src_index);
734 return -EINVAL;
735 }
736
737 msg.dst_queue = dst_mcfg->m_in_pin[dst_index].pin_index;
738
739 dev_dbg(ctx->dev, "src queue = %d dst queue =%d\n",
740 msg.src_queue, msg.dst_queue);
741
742 msg.module_id = src_mcfg->id.module_id;
743 msg.instance_id = src_mcfg->id.instance_id;
744 msg.dst_module_id = dst_mcfg->id.module_id;
745 msg.dst_instance_id = dst_mcfg->id.instance_id;
746 msg.bind = true;
747
748 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
749
750 if (!ret) {
751 src_mcfg->m_state = SKL_MODULE_BIND_DONE;
752 } else {
753 /* error case , if IPC fails, clear the queue index */
754 skl_free_queue(src_mcfg->m_out_pin, src_index);
755 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
756 }
757
758 return ret;
759}
Jeeja KPc9b1e832015-08-01 19:40:44 +0530760
761static int skl_set_pipe_state(struct skl_sst *ctx, struct skl_pipe *pipe,
762 enum skl_ipc_pipeline_state state)
763{
764 dev_dbg(ctx->dev, "%s: pipe_satate = %d\n", __func__, state);
765
766 return skl_ipc_set_pipeline_state(&ctx->ipc, pipe->ppl_id, state);
767}
768
769/*
770 * A pipeline is a collection of modules. Before a module in instantiated a
771 * pipeline needs to be created for it.
772 * This function creates pipeline, by sending create pipeline IPC messages
773 * to FW
774 */
775int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe)
776{
777 int ret;
778
779 dev_dbg(ctx->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id);
780
781 ret = skl_ipc_create_pipeline(&ctx->ipc, pipe->memory_pages,
782 pipe->pipe_priority, pipe->ppl_id);
783 if (ret < 0) {
784 dev_err(ctx->dev, "Failed to create pipeline\n");
785 return ret;
786 }
787
788 pipe->state = SKL_PIPE_CREATED;
789
790 return 0;
791}
792
793/*
794 * A pipeline needs to be deleted on cleanup. If a pipeline is running, then
795 * pause the pipeline first and then delete it
796 * The pipe delete is done by sending delete pipeline IPC. DSP will stop the
797 * DMA engines and releases resources
798 */
799int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
800{
801 int ret;
802
803 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
804
805 /* If pipe is not started, do not try to stop the pipe in FW. */
806 if (pipe->state > SKL_PIPE_STARTED) {
807 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
808 if (ret < 0) {
809 dev_err(ctx->dev, "Failed to stop pipeline\n");
810 return ret;
811 }
812
813 pipe->state = SKL_PIPE_PAUSED;
814 } else {
815 /* If pipe was not created in FW, do not try to delete it */
816 if (pipe->state < SKL_PIPE_CREATED)
817 return 0;
818
819 ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id);
820 if (ret < 0)
821 dev_err(ctx->dev, "Failed to delete pipeline\n");
822 }
823
824 return ret;
825}
826
827/*
828 * A pipeline is also a scheduling entity in DSP which can be run, stopped
829 * For processing data the pipe need to be run by sending IPC set pipe state
830 * to DSP
831 */
832int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
833{
834 int ret;
835
836 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
837
838 /* If pipe was not created in FW, do not try to pause or delete */
839 if (pipe->state < SKL_PIPE_CREATED)
840 return 0;
841
842 /* Pipe has to be paused before it is started */
843 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
844 if (ret < 0) {
845 dev_err(ctx->dev, "Failed to pause pipe\n");
846 return ret;
847 }
848
849 pipe->state = SKL_PIPE_PAUSED;
850
851 ret = skl_set_pipe_state(ctx, pipe, PPL_RUNNING);
852 if (ret < 0) {
853 dev_err(ctx->dev, "Failed to start pipe\n");
854 return ret;
855 }
856
857 pipe->state = SKL_PIPE_STARTED;
858
859 return 0;
860}
861
862/*
863 * Stop the pipeline by sending set pipe state IPC
864 * DSP doesnt implement stop so we always send pause message
865 */
866int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
867{
868 int ret;
869
870 dev_dbg(ctx->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id);
871
872 /* If pipe was not created in FW, do not try to pause or delete */
873 if (pipe->state < SKL_PIPE_PAUSED)
874 return 0;
875
876 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
877 if (ret < 0) {
878 dev_dbg(ctx->dev, "Failed to stop pipe\n");
879 return ret;
880 }
881
882 pipe->state = SKL_PIPE_CREATED;
883
884 return 0;
885}