blob: 507263a2d22606155321ef31a7a848ee7db4cc04 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020052#include <linux/dcbnl.h>
Jiri Pirkoc4745502016-02-26 17:32:26 +010053#include <net/devlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020054#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
251static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
252{
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
260static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
261 bool enable)
262{
263 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
264 char svpe_pl[MLXSW_REG_SVPE_LEN];
265
266 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
267 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
268}
269
270int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
271 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
272 u16 vid)
273{
274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
275 char svfa_pl[MLXSW_REG_SVFA_LEN];
276
277 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
278 fid, vid);
279 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
280}
281
282static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
283 u16 vid, bool learn_enable)
284{
285 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
286 char *spvmlr_pl;
287 int err;
288
289 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
290 if (!spvmlr_pl)
291 return -ENOMEM;
292 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
293 learn_enable);
294 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
295 kfree(spvmlr_pl);
296 return err;
297}
298
299static int
300mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
301{
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
303 char sspr_pl[MLXSW_REG_SSPR_LEN];
304
305 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
306 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
307}
308
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200309static int __mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
310 u8 local_port, u8 *p_module,
311 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200312{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200313 char pmlp_pl[MLXSW_REG_PMLP_LEN];
314 int err;
315
Ido Schimmel558c2d52016-02-26 17:32:29 +0100316 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200317 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
318 if (err)
319 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100320 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
321 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200322 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200323 return 0;
324}
325
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200326static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
327 u8 local_port, u8 *p_module,
328 u8 *p_width)
329{
330 u8 lane;
331
332 return __mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, p_module,
333 p_width, &lane);
334}
335
Ido Schimmel18f1e702016-02-26 17:32:31 +0100336static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
337 u8 module, u8 width, u8 lane)
338{
339 char pmlp_pl[MLXSW_REG_PMLP_LEN];
340 int i;
341
342 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
343 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
344 for (i = 0; i < width; i++) {
345 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
346 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
347 }
348
349 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
350}
351
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100352static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
353{
354 char pmlp_pl[MLXSW_REG_PMLP_LEN];
355
356 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
357 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
358 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
359}
360
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200361static int mlxsw_sp_port_open(struct net_device *dev)
362{
363 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
364 int err;
365
366 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
367 if (err)
368 return err;
369 netif_start_queue(dev);
370 return 0;
371}
372
373static int mlxsw_sp_port_stop(struct net_device *dev)
374{
375 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
376
377 netif_stop_queue(dev);
378 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
379}
380
381static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
382 struct net_device *dev)
383{
384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
385 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
386 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
387 const struct mlxsw_tx_info tx_info = {
388 .local_port = mlxsw_sp_port->local_port,
389 .is_emad = false,
390 };
391 u64 len;
392 int err;
393
394 if (mlxsw_core_skb_transmit_busy(mlxsw_sp, &tx_info))
395 return NETDEV_TX_BUSY;
396
397 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
398 struct sk_buff *skb_orig = skb;
399
400 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
401 if (!skb) {
402 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
403 dev_kfree_skb_any(skb_orig);
404 return NETDEV_TX_OK;
405 }
406 }
407
408 if (eth_skb_pad(skb)) {
409 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
410 return NETDEV_TX_OK;
411 }
412
413 mlxsw_sp_txhdr_construct(skb, &tx_info);
414 len = skb->len;
415 /* Due to a race we might fail here because of a full queue. In that
416 * unlikely case we simply drop the packet.
417 */
418 err = mlxsw_core_skb_transmit(mlxsw_sp, skb, &tx_info);
419
420 if (!err) {
421 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
422 u64_stats_update_begin(&pcpu_stats->syncp);
423 pcpu_stats->tx_packets++;
424 pcpu_stats->tx_bytes += len;
425 u64_stats_update_end(&pcpu_stats->syncp);
426 } else {
427 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
428 dev_kfree_skb_any(skb);
429 }
430 return NETDEV_TX_OK;
431}
432
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100433static void mlxsw_sp_set_rx_mode(struct net_device *dev)
434{
435}
436
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200437static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
438{
439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
440 struct sockaddr *addr = p;
441 int err;
442
443 if (!is_valid_ether_addr(addr->sa_data))
444 return -EADDRNOTAVAIL;
445
446 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
447 if (err)
448 return err;
449 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
450 return 0;
451}
452
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200453static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200454 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200455{
456 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
457
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200458 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
459 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200460
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200461 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200462 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200463 pg_size + delay, pg_size);
464 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200465 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200466}
467
468int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200469 u8 *prio_tc, bool pause_en,
470 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200471{
472 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200473 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
474 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200475 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200476 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200477
478 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
479 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
480 if (err)
481 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200482
483 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
484 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200485 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200486
487 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
488 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200489 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200490 configure = true;
491 break;
492 }
493 }
494
495 if (!configure)
496 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200497 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200498 }
499
Ido Schimmelff6551e2016-04-06 17:10:03 +0200500 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
501}
502
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200503static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200504 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200505{
506 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
507 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200508 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200509 u8 *prio_tc;
510
511 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200512 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200513
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200514 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200515 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200516}
517
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200518static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
519{
520 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200521 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200522 int err;
523
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200524 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200525 if (err)
526 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200527 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
528 if (err)
529 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200530 dev->mtu = mtu;
531 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200532
533err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200534 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200535 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200536}
537
538static struct rtnl_link_stats64 *
539mlxsw_sp_port_get_stats64(struct net_device *dev,
540 struct rtnl_link_stats64 *stats)
541{
542 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
543 struct mlxsw_sp_port_pcpu_stats *p;
544 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
545 u32 tx_dropped = 0;
546 unsigned int start;
547 int i;
548
549 for_each_possible_cpu(i) {
550 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
551 do {
552 start = u64_stats_fetch_begin_irq(&p->syncp);
553 rx_packets = p->rx_packets;
554 rx_bytes = p->rx_bytes;
555 tx_packets = p->tx_packets;
556 tx_bytes = p->tx_bytes;
557 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
558
559 stats->rx_packets += rx_packets;
560 stats->rx_bytes += rx_bytes;
561 stats->tx_packets += tx_packets;
562 stats->tx_bytes += tx_bytes;
563 /* tx_dropped is u32, updated without syncp protection. */
564 tx_dropped += p->tx_dropped;
565 }
566 stats->tx_dropped = tx_dropped;
567 return stats;
568}
569
570int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
571 u16 vid_end, bool is_member, bool untagged)
572{
573 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
574 char *spvm_pl;
575 int err;
576
577 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
578 if (!spvm_pl)
579 return -ENOMEM;
580
581 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
582 vid_end, is_member, untagged);
583 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
584 kfree(spvm_pl);
585 return err;
586}
587
588static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
589{
590 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
591 u16 vid, last_visited_vid;
592 int err;
593
594 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
595 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
596 vid);
597 if (err) {
598 last_visited_vid = vid;
599 goto err_port_vid_to_fid_set;
600 }
601 }
602
603 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
604 if (err) {
605 last_visited_vid = VLAN_N_VID;
606 goto err_port_vid_to_fid_set;
607 }
608
609 return 0;
610
611err_port_vid_to_fid_set:
612 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
613 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
614 vid);
615 return err;
616}
617
618static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
619{
620 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
621 u16 vid;
622 int err;
623
624 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
625 if (err)
626 return err;
627
628 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
629 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
630 vid, vid);
631 if (err)
632 return err;
633 }
634
635 return 0;
636}
637
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100638static struct mlxsw_sp_vfid *
639mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
640{
641 struct mlxsw_sp_vfid *vfid;
642
643 list_for_each_entry(vfid, &mlxsw_sp->port_vfids.list, list) {
644 if (vfid->vid == vid)
645 return vfid;
646 }
647
648 return NULL;
649}
650
651static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
652{
653 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
654 MLXSW_SP_VFID_PORT_MAX);
655}
656
657static int __mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp, u16 vfid)
658{
659 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
660 char sfmr_pl[MLXSW_REG_SFMR_LEN];
661
662 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, 0);
663 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
664}
665
666static void __mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp, u16 vfid)
667{
668 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
669 char sfmr_pl[MLXSW_REG_SFMR_LEN];
670
671 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, fid, 0);
672 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
673}
674
675static struct mlxsw_sp_vfid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
676 u16 vid)
677{
678 struct device *dev = mlxsw_sp->bus_info->dev;
679 struct mlxsw_sp_vfid *vfid;
680 u16 n_vfid;
681 int err;
682
683 n_vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
684 if (n_vfid == MLXSW_SP_VFID_PORT_MAX) {
685 dev_err(dev, "No available vFIDs\n");
686 return ERR_PTR(-ERANGE);
687 }
688
689 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
690 if (err) {
691 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
692 return ERR_PTR(err);
693 }
694
695 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
696 if (!vfid)
697 goto err_allocate_vfid;
698
699 vfid->vfid = n_vfid;
700 vfid->vid = vid;
701
702 list_add(&vfid->list, &mlxsw_sp->port_vfids.list);
703 set_bit(n_vfid, mlxsw_sp->port_vfids.mapped);
704
705 return vfid;
706
707err_allocate_vfid:
708 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
709 return ERR_PTR(-ENOMEM);
710}
711
712static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
713 struct mlxsw_sp_vfid *vfid)
714{
715 clear_bit(vfid->vfid, mlxsw_sp->port_vfids.mapped);
716 list_del(&vfid->list);
717
718 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
719
720 kfree(vfid);
721}
722
723static struct mlxsw_sp_port *
724mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
725 struct mlxsw_sp_vfid *vfid)
726{
727 struct mlxsw_sp_port *mlxsw_sp_vport;
728
729 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
730 if (!mlxsw_sp_vport)
731 return NULL;
732
733 /* dev will be set correctly after the VLAN device is linked
734 * with the real device. In case of bridge SELF invocation, dev
735 * will remain as is.
736 */
737 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
738 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
739 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
740 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100741 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
742 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100743 mlxsw_sp_vport->vport.vfid = vfid;
744 mlxsw_sp_vport->vport.vid = vfid->vid;
745
746 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
747
748 return mlxsw_sp_vport;
749}
750
751static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
752{
753 list_del(&mlxsw_sp_vport->vport.list);
754 kfree(mlxsw_sp_vport);
755}
756
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200757int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
758 u16 vid)
759{
760 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
761 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100762 struct mlxsw_sp_port *mlxsw_sp_vport;
763 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200764 int err;
765
766 /* VLAN 0 is added to HW filter when device goes up, but it is
767 * reserved in our case, so simply return.
768 */
769 if (!vid)
770 return 0;
771
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100772 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200773 netdev_warn(dev, "VID=%d already configured\n", vid);
774 return 0;
775 }
776
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100777 vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
778 if (!vfid) {
779 vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
780 if (IS_ERR(vfid)) {
781 netdev_err(dev, "Failed to create vFID for VID=%d\n",
782 vid);
783 return PTR_ERR(vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200784 }
785 }
786
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100787 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vfid);
788 if (!mlxsw_sp_vport) {
789 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
790 err = -ENOMEM;
791 goto err_port_vport_create;
792 }
793
794 if (!vfid->nr_vports) {
795 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100796 true, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100797 if (err) {
798 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
799 vfid->vfid);
800 goto err_vport_flood_set;
801 }
802 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200803
804 /* When adding the first VLAN interface on a bridged port we need to
805 * transition all the active 802.1Q bridge VLANs to use explicit
806 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
807 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100808 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200809 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
810 if (err) {
811 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100812 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200813 }
814 }
815
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100816 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200817 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100818 true,
819 mlxsw_sp_vfid_to_fid(vfid->vfid),
820 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821 if (err) {
822 netdev_err(dev, "Failed to map {Port, VID=%d} to vFID=%d\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100823 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200824 goto err_port_vid_to_fid_set;
825 }
826
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100827 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200828 if (err) {
829 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
830 goto err_port_vid_learning_set;
831 }
832
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100833 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200834 if (err) {
835 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
836 vid);
837 goto err_port_add_vid;
838 }
839
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100840 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200841 MLXSW_REG_SPMS_STATE_FORWARDING);
842 if (err) {
843 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
844 goto err_port_stp_state_set;
845 }
846
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100847 vfid->nr_vports++;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848
849 return 0;
850
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200851err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100852 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200853err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100854 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200855err_port_vid_learning_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100856 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200857 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100858 mlxsw_sp_vfid_to_fid(vfid->vfid), vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200859err_port_vid_to_fid_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100860 if (list_is_singular(&mlxsw_sp_port->vports_list))
861 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
862err_port_vp_mode_trans:
863 if (!vfid->nr_vports)
Ido Schimmel19ae6122015-12-15 16:03:39 +0100864 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
865 false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100866err_vport_flood_set:
867 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
868err_port_vport_create:
869 if (!vfid->nr_vports)
870 mlxsw_sp_vfid_destroy(mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871 return err;
872}
873
874int mlxsw_sp_port_kill_vid(struct net_device *dev,
875 __be16 __always_unused proto, u16 vid)
876{
877 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100878 struct mlxsw_sp_port *mlxsw_sp_vport;
879 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200880 int err;
881
882 /* VLAN 0 is removed from HW filter when device goes down, but
883 * it is reserved in our case, so simply return.
884 */
885 if (!vid)
886 return 0;
887
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100888 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
889 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 netdev_warn(dev, "VID=%d does not exist\n", vid);
891 return 0;
892 }
893
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100894 vfid = mlxsw_sp_vport->vport.vfid;
895
896 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897 MLXSW_REG_SPMS_STATE_DISCARDING);
898 if (err) {
899 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
900 return err;
901 }
902
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100903 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200904 if (err) {
905 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
906 vid);
907 return err;
908 }
909
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100910 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200911 if (err) {
912 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
913 return err;
914 }
915
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100916 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200917 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100918 false,
919 mlxsw_sp_vfid_to_fid(vfid->vfid),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200920 vid);
921 if (err) {
922 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to vFID=%d mapping\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100923 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200924 return err;
925 }
926
927 /* When removing the last VLAN interface on a bridged port we need to
928 * transition all active 802.1Q bridge VLANs to use VID to FID
929 * mappings and set port's mode to VLAN mode.
930 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100931 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200932 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
933 if (err) {
934 netdev_err(dev, "Failed to set to VLAN mode\n");
935 return err;
936 }
937 }
938
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100939 vfid->nr_vports--;
940 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
941
942 /* Destroy the vFID if no vPorts are assigned to it anymore. */
943 if (!vfid->nr_vports)
944 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200945
946 return 0;
947}
948
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200949static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
950 size_t len)
951{
952 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
953 u8 module, width, lane;
954 int err;
955
956 err = __mlxsw_sp_port_module_info_get(mlxsw_sp_port->mlxsw_sp,
957 mlxsw_sp_port->local_port,
958 &module, &width, &lane);
959 if (err) {
960 netdev_err(dev, "Failed to retrieve module information\n");
961 return err;
962 }
963
964 if (!mlxsw_sp_port->split)
965 err = snprintf(name, len, "p%d", module + 1);
966 else
967 err = snprintf(name, len, "p%ds%d", module + 1,
968 lane / width);
969
970 if (err >= len)
971 return -EINVAL;
972
973 return 0;
974}
975
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200976static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
977 .ndo_open = mlxsw_sp_port_open,
978 .ndo_stop = mlxsw_sp_port_stop,
979 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100980 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200981 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
982 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
983 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
984 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
985 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
986 .ndo_fdb_add = switchdev_port_fdb_add,
987 .ndo_fdb_del = switchdev_port_fdb_del,
988 .ndo_fdb_dump = switchdev_port_fdb_dump,
989 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
990 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
991 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200992 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200993};
994
995static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
996 struct ethtool_drvinfo *drvinfo)
997{
998 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
999 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1000
1001 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1002 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1003 sizeof(drvinfo->version));
1004 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1005 "%d.%d.%d",
1006 mlxsw_sp->bus_info->fw_rev.major,
1007 mlxsw_sp->bus_info->fw_rev.minor,
1008 mlxsw_sp->bus_info->fw_rev.subminor);
1009 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1010 sizeof(drvinfo->bus_info));
1011}
1012
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001013static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1014 struct ethtool_pauseparam *pause)
1015{
1016 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1017
1018 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1019 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1020}
1021
1022static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1023 struct ethtool_pauseparam *pause)
1024{
1025 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1026
1027 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1028 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1029 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1030
1031 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1032 pfcc_pl);
1033}
1034
1035static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1036 struct ethtool_pauseparam *pause)
1037{
1038 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1039 bool pause_en = pause->tx_pause || pause->rx_pause;
1040 int err;
1041
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001042 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1043 netdev_err(dev, "PFC already enabled on port\n");
1044 return -EINVAL;
1045 }
1046
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001047 if (pause->autoneg) {
1048 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1049 return -EINVAL;
1050 }
1051
1052 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1053 if (err) {
1054 netdev_err(dev, "Failed to configure port's headroom\n");
1055 return err;
1056 }
1057
1058 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1059 if (err) {
1060 netdev_err(dev, "Failed to set PAUSE parameters\n");
1061 goto err_port_pause_configure;
1062 }
1063
1064 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1065 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1066
1067 return 0;
1068
1069err_port_pause_configure:
1070 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1071 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1072 return err;
1073}
1074
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001075struct mlxsw_sp_port_hw_stats {
1076 char str[ETH_GSTRING_LEN];
1077 u64 (*getter)(char *payload);
1078};
1079
1080static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1081 {
1082 .str = "a_frames_transmitted_ok",
1083 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1084 },
1085 {
1086 .str = "a_frames_received_ok",
1087 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1088 },
1089 {
1090 .str = "a_frame_check_sequence_errors",
1091 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1092 },
1093 {
1094 .str = "a_alignment_errors",
1095 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1096 },
1097 {
1098 .str = "a_octets_transmitted_ok",
1099 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1100 },
1101 {
1102 .str = "a_octets_received_ok",
1103 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1104 },
1105 {
1106 .str = "a_multicast_frames_xmitted_ok",
1107 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1108 },
1109 {
1110 .str = "a_broadcast_frames_xmitted_ok",
1111 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1112 },
1113 {
1114 .str = "a_multicast_frames_received_ok",
1115 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1116 },
1117 {
1118 .str = "a_broadcast_frames_received_ok",
1119 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1120 },
1121 {
1122 .str = "a_in_range_length_errors",
1123 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1124 },
1125 {
1126 .str = "a_out_of_range_length_field",
1127 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1128 },
1129 {
1130 .str = "a_frame_too_long_errors",
1131 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1132 },
1133 {
1134 .str = "a_symbol_error_during_carrier",
1135 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1136 },
1137 {
1138 .str = "a_mac_control_frames_transmitted",
1139 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1140 },
1141 {
1142 .str = "a_mac_control_frames_received",
1143 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1144 },
1145 {
1146 .str = "a_unsupported_opcodes_received",
1147 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1148 },
1149 {
1150 .str = "a_pause_mac_ctrl_frames_received",
1151 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1152 },
1153 {
1154 .str = "a_pause_mac_ctrl_frames_xmitted",
1155 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1156 },
1157};
1158
1159#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1160
1161static void mlxsw_sp_port_get_strings(struct net_device *dev,
1162 u32 stringset, u8 *data)
1163{
1164 u8 *p = data;
1165 int i;
1166
1167 switch (stringset) {
1168 case ETH_SS_STATS:
1169 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1170 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1171 ETH_GSTRING_LEN);
1172 p += ETH_GSTRING_LEN;
1173 }
1174 break;
1175 }
1176}
1177
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001178static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1179 enum ethtool_phys_id_state state)
1180{
1181 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1182 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1183 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1184 bool active;
1185
1186 switch (state) {
1187 case ETHTOOL_ID_ACTIVE:
1188 active = true;
1189 break;
1190 case ETHTOOL_ID_INACTIVE:
1191 active = false;
1192 break;
1193 default:
1194 return -EOPNOTSUPP;
1195 }
1196
1197 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1198 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1199}
1200
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001201static void mlxsw_sp_port_get_stats(struct net_device *dev,
1202 struct ethtool_stats *stats, u64 *data)
1203{
1204 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1206 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1207 int i;
1208 int err;
1209
Ido Schimmel34dba0a2016-04-06 17:10:15 +02001210 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1211 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001212 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1213 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1214 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1215}
1216
1217static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1218{
1219 switch (sset) {
1220 case ETH_SS_STATS:
1221 return MLXSW_SP_PORT_HW_STATS_LEN;
1222 default:
1223 return -EOPNOTSUPP;
1224 }
1225}
1226
1227struct mlxsw_sp_port_link_mode {
1228 u32 mask;
1229 u32 supported;
1230 u32 advertised;
1231 u32 speed;
1232};
1233
1234static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1235 {
1236 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1237 .supported = SUPPORTED_100baseT_Full,
1238 .advertised = ADVERTISED_100baseT_Full,
1239 .speed = 100,
1240 },
1241 {
1242 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1243 .speed = 100,
1244 },
1245 {
1246 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1247 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1248 .supported = SUPPORTED_1000baseKX_Full,
1249 .advertised = ADVERTISED_1000baseKX_Full,
1250 .speed = 1000,
1251 },
1252 {
1253 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1254 .supported = SUPPORTED_10000baseT_Full,
1255 .advertised = ADVERTISED_10000baseT_Full,
1256 .speed = 10000,
1257 },
1258 {
1259 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1260 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1261 .supported = SUPPORTED_10000baseKX4_Full,
1262 .advertised = ADVERTISED_10000baseKX4_Full,
1263 .speed = 10000,
1264 },
1265 {
1266 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1267 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1268 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1269 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1270 .supported = SUPPORTED_10000baseKR_Full,
1271 .advertised = ADVERTISED_10000baseKR_Full,
1272 .speed = 10000,
1273 },
1274 {
1275 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1276 .supported = SUPPORTED_20000baseKR2_Full,
1277 .advertised = ADVERTISED_20000baseKR2_Full,
1278 .speed = 20000,
1279 },
1280 {
1281 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1282 .supported = SUPPORTED_40000baseCR4_Full,
1283 .advertised = ADVERTISED_40000baseCR4_Full,
1284 .speed = 40000,
1285 },
1286 {
1287 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1288 .supported = SUPPORTED_40000baseKR4_Full,
1289 .advertised = ADVERTISED_40000baseKR4_Full,
1290 .speed = 40000,
1291 },
1292 {
1293 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1294 .supported = SUPPORTED_40000baseSR4_Full,
1295 .advertised = ADVERTISED_40000baseSR4_Full,
1296 .speed = 40000,
1297 },
1298 {
1299 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1300 .supported = SUPPORTED_40000baseLR4_Full,
1301 .advertised = ADVERTISED_40000baseLR4_Full,
1302 .speed = 40000,
1303 },
1304 {
1305 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1306 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1307 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1308 .speed = 25000,
1309 },
1310 {
1311 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1312 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1313 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1314 .speed = 50000,
1315 },
1316 {
1317 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1318 .supported = SUPPORTED_56000baseKR4_Full,
1319 .advertised = ADVERTISED_56000baseKR4_Full,
1320 .speed = 56000,
1321 },
1322 {
1323 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1324 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1325 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1327 .speed = 100000,
1328 },
1329};
1330
1331#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1332
1333static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1334{
1335 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1336 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1337 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1338 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1339 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1340 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1341 return SUPPORTED_FIBRE;
1342
1343 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1344 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1345 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1346 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1348 return SUPPORTED_Backplane;
1349 return 0;
1350}
1351
1352static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1353{
1354 u32 modes = 0;
1355 int i;
1356
1357 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1358 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1359 modes |= mlxsw_sp_port_link_mode[i].supported;
1360 }
1361 return modes;
1362}
1363
1364static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1365{
1366 u32 modes = 0;
1367 int i;
1368
1369 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1370 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1371 modes |= mlxsw_sp_port_link_mode[i].advertised;
1372 }
1373 return modes;
1374}
1375
1376static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1377 struct ethtool_cmd *cmd)
1378{
1379 u32 speed = SPEED_UNKNOWN;
1380 u8 duplex = DUPLEX_UNKNOWN;
1381 int i;
1382
1383 if (!carrier_ok)
1384 goto out;
1385
1386 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1387 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1388 speed = mlxsw_sp_port_link_mode[i].speed;
1389 duplex = DUPLEX_FULL;
1390 break;
1391 }
1392 }
1393out:
1394 ethtool_cmd_speed_set(cmd, speed);
1395 cmd->duplex = duplex;
1396}
1397
1398static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1399{
1400 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1401 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1402 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1403 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1404 return PORT_FIBRE;
1405
1406 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1407 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1408 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1409 return PORT_DA;
1410
1411 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1412 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1413 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1414 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1415 return PORT_NONE;
1416
1417 return PORT_OTHER;
1418}
1419
1420static int mlxsw_sp_port_get_settings(struct net_device *dev,
1421 struct ethtool_cmd *cmd)
1422{
1423 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1424 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1425 char ptys_pl[MLXSW_REG_PTYS_LEN];
1426 u32 eth_proto_cap;
1427 u32 eth_proto_admin;
1428 u32 eth_proto_oper;
1429 int err;
1430
1431 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1432 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1433 if (err) {
1434 netdev_err(dev, "Failed to get proto");
1435 return err;
1436 }
1437 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1438 &eth_proto_admin, &eth_proto_oper);
1439
1440 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1441 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1442 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1443 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1444 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1445 eth_proto_oper, cmd);
1446
1447 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1448 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1449 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1450
1451 cmd->transceiver = XCVR_INTERNAL;
1452 return 0;
1453}
1454
1455static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1456{
1457 u32 ptys_proto = 0;
1458 int i;
1459
1460 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1461 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1462 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1463 }
1464 return ptys_proto;
1465}
1466
1467static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1468{
1469 u32 ptys_proto = 0;
1470 int i;
1471
1472 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1473 if (speed == mlxsw_sp_port_link_mode[i].speed)
1474 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1475 }
1476 return ptys_proto;
1477}
1478
Ido Schimmel18f1e702016-02-26 17:32:31 +01001479static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1480{
1481 u32 ptys_proto = 0;
1482 int i;
1483
1484 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1485 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1486 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1487 }
1488 return ptys_proto;
1489}
1490
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001491static int mlxsw_sp_port_set_settings(struct net_device *dev,
1492 struct ethtool_cmd *cmd)
1493{
1494 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1495 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1496 char ptys_pl[MLXSW_REG_PTYS_LEN];
1497 u32 speed;
1498 u32 eth_proto_new;
1499 u32 eth_proto_cap;
1500 u32 eth_proto_admin;
1501 bool is_up;
1502 int err;
1503
1504 speed = ethtool_cmd_speed(cmd);
1505
1506 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1507 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1508 mlxsw_sp_to_ptys_speed(speed);
1509
1510 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1511 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1512 if (err) {
1513 netdev_err(dev, "Failed to get proto");
1514 return err;
1515 }
1516 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1517
1518 eth_proto_new = eth_proto_new & eth_proto_cap;
1519 if (!eth_proto_new) {
1520 netdev_err(dev, "Not supported proto admin requested");
1521 return -EINVAL;
1522 }
1523 if (eth_proto_new == eth_proto_admin)
1524 return 0;
1525
1526 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1527 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1528 if (err) {
1529 netdev_err(dev, "Failed to set proto admin");
1530 return err;
1531 }
1532
1533 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1534 if (err) {
1535 netdev_err(dev, "Failed to get oper status");
1536 return err;
1537 }
1538 if (!is_up)
1539 return 0;
1540
1541 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1542 if (err) {
1543 netdev_err(dev, "Failed to set admin status");
1544 return err;
1545 }
1546
1547 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1548 if (err) {
1549 netdev_err(dev, "Failed to set admin status");
1550 return err;
1551 }
1552
1553 return 0;
1554}
1555
1556static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1557 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1558 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001559 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1560 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001561 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001562 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001563 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1564 .get_sset_count = mlxsw_sp_port_get_sset_count,
1565 .get_settings = mlxsw_sp_port_get_settings,
1566 .set_settings = mlxsw_sp_port_set_settings,
1567};
1568
Ido Schimmel18f1e702016-02-26 17:32:31 +01001569static int
1570mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1571{
1572 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1573 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1574 char ptys_pl[MLXSW_REG_PTYS_LEN];
1575 u32 eth_proto_admin;
1576
1577 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1578 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1579 eth_proto_admin);
1580 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1581}
1582
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001583int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1584 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1585 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001586{
1587 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1588 char qeec_pl[MLXSW_REG_QEEC_LEN];
1589
1590 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1591 next_index);
1592 mlxsw_reg_qeec_de_set(qeec_pl, true);
1593 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1594 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1595 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1596}
1597
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001598int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1599 enum mlxsw_reg_qeec_hr hr, u8 index,
1600 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001601{
1602 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1603 char qeec_pl[MLXSW_REG_QEEC_LEN];
1604
1605 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1606 next_index);
1607 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1608 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1609 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1610}
1611
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001612int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1613 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001614{
1615 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1616 char qtct_pl[MLXSW_REG_QTCT_LEN];
1617
1618 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1619 tclass);
1620 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1621}
1622
1623static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1624{
1625 int err, i;
1626
1627 /* Setup the elements hierarcy, so that each TC is linked to
1628 * one subgroup, which are all member in the same group.
1629 */
1630 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1631 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1632 0);
1633 if (err)
1634 return err;
1635 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1636 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1637 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1638 0, false, 0);
1639 if (err)
1640 return err;
1641 }
1642 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1643 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1644 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1645 false, 0);
1646 if (err)
1647 return err;
1648 }
1649
1650 /* Make sure the max shaper is disabled in all hierarcies that
1651 * support it.
1652 */
1653 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1654 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1655 MLXSW_REG_QEEC_MAS_DIS);
1656 if (err)
1657 return err;
1658 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1659 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1660 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1661 i, 0,
1662 MLXSW_REG_QEEC_MAS_DIS);
1663 if (err)
1664 return err;
1665 }
1666 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1667 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1668 MLXSW_REG_QEEC_HIERARCY_TC,
1669 i, i,
1670 MLXSW_REG_QEEC_MAS_DIS);
1671 if (err)
1672 return err;
1673 }
1674
1675 /* Map all priorities to traffic class 0. */
1676 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1677 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1678 if (err)
1679 return err;
1680 }
1681
1682 return 0;
1683}
1684
Ido Schimmel18f1e702016-02-26 17:32:31 +01001685static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1686 bool split, u8 module, u8 width)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001687{
Jiri Pirkoc4745502016-02-26 17:32:26 +01001688 struct devlink *devlink = priv_to_devlink(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001689 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirkoc4745502016-02-26 17:32:26 +01001690 struct devlink_port *devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001691 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001692 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001693 int err;
1694
1695 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1696 if (!dev)
1697 return -ENOMEM;
1698 mlxsw_sp_port = netdev_priv(dev);
1699 mlxsw_sp_port->dev = dev;
1700 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1701 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001702 mlxsw_sp_port->split = split;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001703 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1704 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1705 if (!mlxsw_sp_port->active_vlans) {
1706 err = -ENOMEM;
1707 goto err_port_active_vlans_alloc;
1708 }
Elad Razfc1273a2016-01-06 13:01:11 +01001709 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1710 if (!mlxsw_sp_port->untagged_vlans) {
1711 err = -ENOMEM;
1712 goto err_port_untagged_vlans_alloc;
1713 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001714 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001715
1716 mlxsw_sp_port->pcpu_stats =
1717 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1718 if (!mlxsw_sp_port->pcpu_stats) {
1719 err = -ENOMEM;
1720 goto err_alloc_stats;
1721 }
1722
1723 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1724 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1725
1726 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1727 if (err) {
1728 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1729 mlxsw_sp_port->local_port);
1730 goto err_dev_addr_init;
1731 }
1732
1733 netif_carrier_off(dev);
1734
1735 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1736 NETIF_F_HW_VLAN_CTAG_FILTER;
1737
1738 /* Each packet needs to have a Tx header (metadata) on top all other
1739 * headers.
1740 */
1741 dev->hard_header_len += MLXSW_TXHDR_LEN;
1742
Jiri Pirkoc4745502016-02-26 17:32:26 +01001743 devlink_port = &mlxsw_sp_port->devlink_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001744 if (mlxsw_sp_port->split)
1745 devlink_port_split_set(devlink_port, module);
Jiri Pirkoc4745502016-02-26 17:32:26 +01001746 err = devlink_port_register(devlink, devlink_port, local_port);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register devlink port\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_devlink_port_register;
1751 }
1752
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001753 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_system_port_mapping_set;
1758 }
1759
1760 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_swid_set;
1765 }
1766
Ido Schimmel18f1e702016-02-26 17:32:31 +01001767 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_speed_by_width_set;
1772 }
1773
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001774 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1775 if (err) {
1776 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1777 mlxsw_sp_port->local_port);
1778 goto err_port_mtu_set;
1779 }
1780
1781 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1782 if (err)
1783 goto err_port_admin_status_set;
1784
1785 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1786 if (err) {
1787 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1788 mlxsw_sp_port->local_port);
1789 goto err_port_buffers_init;
1790 }
1791
Ido Schimmel90183b92016-04-06 17:10:08 +02001792 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1793 if (err) {
1794 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1795 mlxsw_sp_port->local_port);
1796 goto err_port_ets_init;
1797 }
1798
Ido Schimmelf00817d2016-04-06 17:10:09 +02001799 /* ETS and buffers must be initialized before DCB. */
1800 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1801 if (err) {
1802 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1803 mlxsw_sp_port->local_port);
1804 goto err_port_dcb_init;
1805 }
1806
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001807 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1808 err = register_netdev(dev);
1809 if (err) {
1810 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1811 mlxsw_sp_port->local_port);
1812 goto err_register_netdev;
1813 }
1814
Jiri Pirkoc4745502016-02-26 17:32:26 +01001815 devlink_port_type_eth_set(devlink_port, dev);
1816
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001817 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1818 if (err)
1819 goto err_port_vlan_init;
1820
1821 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1822 return 0;
1823
1824err_port_vlan_init:
1825 unregister_netdev(dev);
1826err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001827err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001828err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001829err_port_buffers_init:
1830err_port_admin_status_set:
1831err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001832err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001833err_port_swid_set:
1834err_port_system_port_mapping_set:
Jiri Pirkoc4745502016-02-26 17:32:26 +01001835 devlink_port_unregister(&mlxsw_sp_port->devlink_port);
1836err_devlink_port_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001837err_dev_addr_init:
1838 free_percpu(mlxsw_sp_port->pcpu_stats);
1839err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001840 kfree(mlxsw_sp_port->untagged_vlans);
1841err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001842 kfree(mlxsw_sp_port->active_vlans);
1843err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001844 free_netdev(dev);
1845 return err;
1846}
1847
Ido Schimmel18f1e702016-02-26 17:32:31 +01001848static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1849 bool split, u8 module, u8 width, u8 lane)
1850{
1851 int err;
1852
1853 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1854 lane);
1855 if (err)
1856 return err;
1857
1858 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split, module,
1859 width);
1860 if (err)
1861 goto err_port_create;
1862
1863 return 0;
1864
1865err_port_create:
1866 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port);
1867 return err;
1868}
1869
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001870static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001871{
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001872 struct net_device *dev = mlxsw_sp_port->dev;
1873 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001874
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001875 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1876 &mlxsw_sp_port->vports_list, vport.list) {
1877 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1878
1879 /* vPorts created for VLAN devices should already be gone
1880 * by now, since we unregistered the port netdev.
1881 */
1882 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1883 mlxsw_sp_port_kill_vid(dev, 0, vid);
1884 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001885}
1886
1887static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1888{
1889 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
Jiri Pirkoc4745502016-02-26 17:32:26 +01001890 struct devlink_port *devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001891
1892 if (!mlxsw_sp_port)
1893 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001894 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirkoc4745502016-02-26 17:32:26 +01001895 devlink_port = &mlxsw_sp_port->devlink_port;
1896 devlink_port_type_clear(devlink_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001897 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001898 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Jiri Pirkoc4745502016-02-26 17:32:26 +01001899 devlink_port_unregister(devlink_port);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001900 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001901 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001902 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1903 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001904 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001905 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001906 kfree(mlxsw_sp_port->active_vlans);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001907 free_netdev(mlxsw_sp_port->dev);
1908}
1909
1910static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1911{
1912 int i;
1913
1914 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1915 mlxsw_sp_port_remove(mlxsw_sp, i);
1916 kfree(mlxsw_sp->ports);
1917}
1918
1919static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1920{
1921 size_t alloc_size;
Ido Schimmel558c2d52016-02-26 17:32:29 +01001922 u8 module, width;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001923 int i;
1924 int err;
1925
1926 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1927 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1928 if (!mlxsw_sp->ports)
1929 return -ENOMEM;
1930
1931 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001932 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1933 &width);
1934 if (err)
1935 goto err_port_module_info_get;
1936 if (!width)
1937 continue;
1938 mlxsw_sp->port_to_module[i] = module;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001939 err = __mlxsw_sp_port_create(mlxsw_sp, i, false, module, width);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001940 if (err)
1941 goto err_port_create;
1942 }
1943 return 0;
1944
1945err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001946err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001947 for (i--; i >= 1; i--)
1948 mlxsw_sp_port_remove(mlxsw_sp, i);
1949 kfree(mlxsw_sp->ports);
1950 return err;
1951}
1952
Ido Schimmel18f1e702016-02-26 17:32:31 +01001953static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1954{
1955 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1956
1957 return local_port - offset;
1958}
1959
1960static int mlxsw_sp_port_split(void *priv, u8 local_port, unsigned int count)
1961{
1962 struct mlxsw_sp *mlxsw_sp = priv;
1963 struct mlxsw_sp_port *mlxsw_sp_port;
1964 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1965 u8 module, cur_width, base_port;
1966 int i;
1967 int err;
1968
1969 mlxsw_sp_port = mlxsw_sp->ports[local_port];
1970 if (!mlxsw_sp_port) {
1971 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1972 local_port);
1973 return -EINVAL;
1974 }
1975
1976 if (count != 2 && count != 4) {
1977 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
1978 return -EINVAL;
1979 }
1980
1981 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
1982 &cur_width);
1983 if (err) {
1984 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
1985 return err;
1986 }
1987
1988 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
1989 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
1990 return -EINVAL;
1991 }
1992
1993 /* Make sure we have enough slave (even) ports for the split. */
1994 if (count == 2) {
1995 base_port = local_port;
1996 if (mlxsw_sp->ports[base_port + 1]) {
1997 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1998 return -EINVAL;
1999 }
2000 } else {
2001 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2002 if (mlxsw_sp->ports[base_port + 1] ||
2003 mlxsw_sp->ports[base_port + 3]) {
2004 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2005 return -EINVAL;
2006 }
2007 }
2008
2009 for (i = 0; i < count; i++)
2010 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2011
2012 for (i = 0; i < count; i++) {
2013 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
2014 module, width, i * width);
2015 if (err) {
2016 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split port\n");
2017 goto err_port_create;
2018 }
2019 }
2020
2021 return 0;
2022
2023err_port_create:
2024 for (i--; i >= 0; i--)
2025 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2026 for (i = 0; i < count / 2; i++) {
2027 module = mlxsw_sp->port_to_module[base_port + i * 2];
2028 mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
2029 module, MLXSW_PORT_MODULE_MAX_WIDTH, 0);
2030 }
2031 return err;
2032}
2033
2034static int mlxsw_sp_port_unsplit(void *priv, u8 local_port)
2035{
2036 struct mlxsw_sp *mlxsw_sp = priv;
2037 struct mlxsw_sp_port *mlxsw_sp_port;
2038 u8 module, cur_width, base_port;
2039 unsigned int count;
2040 int i;
2041 int err;
2042
2043 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2044 if (!mlxsw_sp_port) {
2045 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2046 local_port);
2047 return -EINVAL;
2048 }
2049
2050 if (!mlxsw_sp_port->split) {
2051 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2052 return -EINVAL;
2053 }
2054
2055 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
2056 &cur_width);
2057 if (err) {
2058 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
2059 return err;
2060 }
2061 count = cur_width == 1 ? 4 : 2;
2062
2063 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2064
2065 /* Determine which ports to remove. */
2066 if (count == 2 && local_port >= base_port + 2)
2067 base_port = base_port + 2;
2068
2069 for (i = 0; i < count; i++)
2070 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2071
2072 for (i = 0; i < count / 2; i++) {
2073 module = mlxsw_sp->port_to_module[base_port + i * 2];
2074 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
2075 module, MLXSW_PORT_MODULE_MAX_WIDTH,
2076 0);
2077 if (err)
2078 dev_err(mlxsw_sp->bus_info->dev, "Failed to reinstantiate port\n");
2079 }
2080
2081 return 0;
2082}
2083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002084static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2085 char *pude_pl, void *priv)
2086{
2087 struct mlxsw_sp *mlxsw_sp = priv;
2088 struct mlxsw_sp_port *mlxsw_sp_port;
2089 enum mlxsw_reg_pude_oper_status status;
2090 u8 local_port;
2091
2092 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2093 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2094 if (!mlxsw_sp_port) {
2095 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2096 local_port);
2097 return;
2098 }
2099
2100 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2101 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2102 netdev_info(mlxsw_sp_port->dev, "link up\n");
2103 netif_carrier_on(mlxsw_sp_port->dev);
2104 } else {
2105 netdev_info(mlxsw_sp_port->dev, "link down\n");
2106 netif_carrier_off(mlxsw_sp_port->dev);
2107 }
2108}
2109
2110static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2111 .func = mlxsw_sp_pude_event_func,
2112 .trap_id = MLXSW_TRAP_ID_PUDE,
2113};
2114
2115static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2116 enum mlxsw_event_trap_id trap_id)
2117{
2118 struct mlxsw_event_listener *el;
2119 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2120 int err;
2121
2122 switch (trap_id) {
2123 case MLXSW_TRAP_ID_PUDE:
2124 el = &mlxsw_sp_pude_event;
2125 break;
2126 }
2127 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2128 if (err)
2129 return err;
2130
2131 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2132 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2133 if (err)
2134 goto err_event_trap_set;
2135
2136 return 0;
2137
2138err_event_trap_set:
2139 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2140 return err;
2141}
2142
2143static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2144 enum mlxsw_event_trap_id trap_id)
2145{
2146 struct mlxsw_event_listener *el;
2147
2148 switch (trap_id) {
2149 case MLXSW_TRAP_ID_PUDE:
2150 el = &mlxsw_sp_pude_event;
2151 break;
2152 }
2153 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2154}
2155
2156static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2157 void *priv)
2158{
2159 struct mlxsw_sp *mlxsw_sp = priv;
2160 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2161 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2162
2163 if (unlikely(!mlxsw_sp_port)) {
2164 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2165 local_port);
2166 return;
2167 }
2168
2169 skb->dev = mlxsw_sp_port->dev;
2170
2171 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2172 u64_stats_update_begin(&pcpu_stats->syncp);
2173 pcpu_stats->rx_packets++;
2174 pcpu_stats->rx_bytes += skb->len;
2175 u64_stats_update_end(&pcpu_stats->syncp);
2176
2177 skb->protocol = eth_type_trans(skb, skb->dev);
2178 netif_receive_skb(skb);
2179}
2180
2181static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2182 {
2183 .func = mlxsw_sp_rx_listener_func,
2184 .local_port = MLXSW_PORT_DONT_CARE,
2185 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2186 },
2187 /* Traps for specific L2 packet types, not trapped as FDB MC */
2188 {
2189 .func = mlxsw_sp_rx_listener_func,
2190 .local_port = MLXSW_PORT_DONT_CARE,
2191 .trap_id = MLXSW_TRAP_ID_STP,
2192 },
2193 {
2194 .func = mlxsw_sp_rx_listener_func,
2195 .local_port = MLXSW_PORT_DONT_CARE,
2196 .trap_id = MLXSW_TRAP_ID_LACP,
2197 },
2198 {
2199 .func = mlxsw_sp_rx_listener_func,
2200 .local_port = MLXSW_PORT_DONT_CARE,
2201 .trap_id = MLXSW_TRAP_ID_EAPOL,
2202 },
2203 {
2204 .func = mlxsw_sp_rx_listener_func,
2205 .local_port = MLXSW_PORT_DONT_CARE,
2206 .trap_id = MLXSW_TRAP_ID_LLDP,
2207 },
2208 {
2209 .func = mlxsw_sp_rx_listener_func,
2210 .local_port = MLXSW_PORT_DONT_CARE,
2211 .trap_id = MLXSW_TRAP_ID_MMRP,
2212 },
2213 {
2214 .func = mlxsw_sp_rx_listener_func,
2215 .local_port = MLXSW_PORT_DONT_CARE,
2216 .trap_id = MLXSW_TRAP_ID_MVRP,
2217 },
2218 {
2219 .func = mlxsw_sp_rx_listener_func,
2220 .local_port = MLXSW_PORT_DONT_CARE,
2221 .trap_id = MLXSW_TRAP_ID_RPVST,
2222 },
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_DHCP,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2252 },
2253};
2254
2255static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2256{
2257 char htgt_pl[MLXSW_REG_HTGT_LEN];
2258 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2259 int i;
2260 int err;
2261
2262 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2263 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2264 if (err)
2265 return err;
2266
2267 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2268 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2269 if (err)
2270 return err;
2271
2272 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2273 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2274 &mlxsw_sp_rx_listener[i],
2275 mlxsw_sp);
2276 if (err)
2277 goto err_rx_listener_register;
2278
2279 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2280 mlxsw_sp_rx_listener[i].trap_id);
2281 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2282 if (err)
2283 goto err_rx_trap_set;
2284 }
2285 return 0;
2286
2287err_rx_trap_set:
2288 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2289 &mlxsw_sp_rx_listener[i],
2290 mlxsw_sp);
2291err_rx_listener_register:
2292 for (i--; i >= 0; i--) {
2293 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2294 mlxsw_sp_rx_listener[i].trap_id);
2295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2296
2297 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2298 &mlxsw_sp_rx_listener[i],
2299 mlxsw_sp);
2300 }
2301 return err;
2302}
2303
2304static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2305{
2306 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2307 int i;
2308
2309 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2310 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2311 mlxsw_sp_rx_listener[i].trap_id);
2312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2313
2314 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2315 &mlxsw_sp_rx_listener[i],
2316 mlxsw_sp);
2317 }
2318}
2319
2320static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2321 enum mlxsw_reg_sfgc_type type,
2322 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2323{
2324 enum mlxsw_flood_table_type table_type;
2325 enum mlxsw_sp_flood_table flood_table;
2326 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2327
Ido Schimmel19ae6122015-12-15 16:03:39 +01002328 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002329 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002330 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002331 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002332
2333 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2334 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2335 else
2336 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002337
2338 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2339 flood_table);
2340 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2341}
2342
2343static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2344{
2345 int type, err;
2346
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002347 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2348 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2349 continue;
2350
2351 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2352 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2353 if (err)
2354 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002355
2356 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2357 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2358 if (err)
2359 return err;
2360 }
2361
2362 return 0;
2363}
2364
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002365static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2366{
2367 char slcr_pl[MLXSW_REG_SLCR_LEN];
2368
2369 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2370 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2371 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2372 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2373 MLXSW_REG_SLCR_LAG_HASH_SIP |
2374 MLXSW_REG_SLCR_LAG_HASH_DIP |
2375 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2376 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2377 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2378 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2379}
2380
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002381static int mlxsw_sp_init(void *priv, struct mlxsw_core *mlxsw_core,
2382 const struct mlxsw_bus_info *mlxsw_bus_info)
2383{
2384 struct mlxsw_sp *mlxsw_sp = priv;
2385 int err;
2386
2387 mlxsw_sp->core = mlxsw_core;
2388 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002389 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002390 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002391 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002392
2393 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2394 if (err) {
2395 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2396 return err;
2397 }
2398
2399 err = mlxsw_sp_ports_create(mlxsw_sp);
2400 if (err) {
2401 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002402 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002403 }
2404
2405 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2406 if (err) {
2407 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2408 goto err_event_register;
2409 }
2410
2411 err = mlxsw_sp_traps_init(mlxsw_sp);
2412 if (err) {
2413 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2414 goto err_rx_listener_register;
2415 }
2416
2417 err = mlxsw_sp_flood_init(mlxsw_sp);
2418 if (err) {
2419 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2420 goto err_flood_init;
2421 }
2422
2423 err = mlxsw_sp_buffers_init(mlxsw_sp);
2424 if (err) {
2425 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2426 goto err_buffers_init;
2427 }
2428
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002429 err = mlxsw_sp_lag_init(mlxsw_sp);
2430 if (err) {
2431 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2432 goto err_lag_init;
2433 }
2434
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2436 if (err) {
2437 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2438 goto err_switchdev_init;
2439 }
2440
2441 return 0;
2442
2443err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002444err_lag_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445err_buffers_init:
2446err_flood_init:
2447 mlxsw_sp_traps_fini(mlxsw_sp);
2448err_rx_listener_register:
2449 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2450err_event_register:
2451 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002452 return err;
2453}
2454
2455static void mlxsw_sp_fini(void *priv)
2456{
2457 struct mlxsw_sp *mlxsw_sp = priv;
2458
2459 mlxsw_sp_switchdev_fini(mlxsw_sp);
2460 mlxsw_sp_traps_fini(mlxsw_sp);
2461 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2462 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002463}
2464
2465static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2466 .used_max_vepa_channels = 1,
2467 .max_vepa_channels = 0,
2468 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002469 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002470 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002471 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002472 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002473 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002474 .used_max_pgt = 1,
2475 .max_pgt = 0,
2476 .used_max_system_port = 1,
2477 .max_system_port = 64,
2478 .used_max_vlan_groups = 1,
2479 .max_vlan_groups = 127,
2480 .used_max_regions = 1,
2481 .max_regions = 400,
2482 .used_flood_tables = 1,
2483 .used_flood_mode = 1,
2484 .flood_mode = 3,
2485 .max_fid_offset_flood_tables = 2,
2486 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002487 .max_fid_flood_tables = 2,
2488 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002489 .used_max_ib_mc = 1,
2490 .max_ib_mc = 0,
2491 .used_max_pkey = 1,
2492 .max_pkey = 0,
2493 .swid_config = {
2494 {
2495 .used_type = 1,
2496 .type = MLXSW_PORT_SWID_TYPE_ETH,
2497 }
2498 },
2499};
2500
2501static struct mlxsw_driver mlxsw_sp_driver = {
2502 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2503 .owner = THIS_MODULE,
2504 .priv_size = sizeof(struct mlxsw_sp),
2505 .init = mlxsw_sp_init,
2506 .fini = mlxsw_sp_fini,
Ido Schimmel18f1e702016-02-26 17:32:31 +01002507 .port_split = mlxsw_sp_port_split,
2508 .port_unsplit = mlxsw_sp_port_unsplit,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002509 .txhdr_construct = mlxsw_sp_txhdr_construct,
2510 .txhdr_len = MLXSW_TXHDR_LEN,
2511 .profile = &mlxsw_sp_config_profile,
2512};
2513
Ido Schimmel039c49a2016-01-27 15:20:18 +01002514static int
2515mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2516{
2517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2518 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2519
2520 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2521 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2522
2523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2524}
2525
2526static int
2527mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2528 u16 fid)
2529{
2530 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2531 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2532
2533 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2534 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2535 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2536 mlxsw_sp_port->local_port);
2537
2538 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2539}
2540
2541static int
2542mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2543{
2544 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2545 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2546
2547 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2548 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2549
2550 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2551}
2552
2553static int
2554mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2555 u16 fid)
2556{
2557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2558 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2559
2560 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2561 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2562 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2563
2564 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2565}
2566
2567static int
2568__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2569{
2570 int err, last_err = 0;
2571 u16 vid;
2572
2573 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2574 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2575 if (err)
2576 last_err = err;
2577 }
2578
2579 return last_err;
2580}
2581
2582static int
2583__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2584{
2585 int err, last_err = 0;
2586 u16 vid;
2587
2588 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2589 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2590 if (err)
2591 last_err = err;
2592 }
2593
2594 return last_err;
2595}
2596
2597static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2598{
2599 if (!list_empty(&mlxsw_sp_port->vports_list))
2600 if (mlxsw_sp_port->lagged)
2601 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2602 else
2603 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2604 else
2605 if (mlxsw_sp_port->lagged)
2606 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2607 else
2608 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2609}
2610
2611static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2612{
2613 u16 vfid = mlxsw_sp_vport_vfid_get(mlxsw_sp_vport);
2614 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
2615
2616 if (mlxsw_sp_vport->lagged)
2617 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2618 fid);
2619 else
2620 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2621}
2622
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002623static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2624{
2625 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2626}
2627
2628static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port)
2629{
2630 struct net_device *dev = mlxsw_sp_port->dev;
2631 int err;
2632
2633 /* When port is not bridged untagged packets are tagged with
2634 * PVID=VID=1, thereby creating an implicit VLAN interface in
2635 * the device. Remove it and let bridge code take care of its
2636 * own VLANs.
2637 */
2638 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002639 if (err)
2640 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002641
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002642 mlxsw_sp_port->learning = 1;
2643 mlxsw_sp_port->learning_sync = 1;
2644 mlxsw_sp_port->uc_flood = 1;
2645 mlxsw_sp_port->bridged = 1;
2646
2647 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002648}
2649
Ido Schimmel039c49a2016-01-27 15:20:18 +01002650static int mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2651 bool flush_fdb)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002652{
2653 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002654
Ido Schimmel039c49a2016-01-27 15:20:18 +01002655 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2656 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2657
Ido Schimmel28a01d22016-02-18 11:30:02 +01002658 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2659
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002660 mlxsw_sp_port->learning = 0;
2661 mlxsw_sp_port->learning_sync = 0;
2662 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002663 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002664
2665 /* Add implicit VLAN interface in the device, so that untagged
2666 * packets will be classified to the default vFID.
2667 */
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002668 return mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002669}
2670
2671static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2672 struct net_device *br_dev)
2673{
2674 return !mlxsw_sp->master_bridge.dev ||
2675 mlxsw_sp->master_bridge.dev == br_dev;
2676}
2677
2678static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2679 struct net_device *br_dev)
2680{
2681 mlxsw_sp->master_bridge.dev = br_dev;
2682 mlxsw_sp->master_bridge.ref_count++;
2683}
2684
2685static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp,
2686 struct net_device *br_dev)
2687{
2688 if (--mlxsw_sp->master_bridge.ref_count == 0)
2689 mlxsw_sp->master_bridge.dev = NULL;
2690}
2691
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002692static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002693{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002694 char sldr_pl[MLXSW_REG_SLDR_LEN];
2695
2696 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2697 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2698}
2699
2700static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2701{
2702 char sldr_pl[MLXSW_REG_SLDR_LEN];
2703
2704 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2705 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2706}
2707
2708static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2709 u16 lag_id, u8 port_index)
2710{
2711 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2712 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2713
2714 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2715 lag_id, port_index);
2716 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2717}
2718
2719static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2720 u16 lag_id)
2721{
2722 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2723 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2724
2725 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2726 lag_id);
2727 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2728}
2729
2730static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2731 u16 lag_id)
2732{
2733 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2735
2736 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2737 lag_id);
2738 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2739}
2740
2741static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2742 u16 lag_id)
2743{
2744 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2745 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2746
2747 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2748 lag_id);
2749 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2750}
2751
2752static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2753 struct net_device *lag_dev,
2754 u16 *p_lag_id)
2755{
2756 struct mlxsw_sp_upper *lag;
2757 int free_lag_id = -1;
2758 int i;
2759
2760 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2761 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2762 if (lag->ref_count) {
2763 if (lag->dev == lag_dev) {
2764 *p_lag_id = i;
2765 return 0;
2766 }
2767 } else if (free_lag_id < 0) {
2768 free_lag_id = i;
2769 }
2770 }
2771 if (free_lag_id < 0)
2772 return -EBUSY;
2773 *p_lag_id = free_lag_id;
2774 return 0;
2775}
2776
2777static bool
2778mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2779 struct net_device *lag_dev,
2780 struct netdev_lag_upper_info *lag_upper_info)
2781{
2782 u16 lag_id;
2783
2784 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2785 return false;
2786 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2787 return false;
2788 return true;
2789}
2790
2791static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2792 u16 lag_id, u8 *p_port_index)
2793{
2794 int i;
2795
2796 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2797 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2798 *p_port_index = i;
2799 return 0;
2800 }
2801 }
2802 return -EBUSY;
2803}
2804
2805static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2806 struct net_device *lag_dev)
2807{
2808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2809 struct mlxsw_sp_upper *lag;
2810 u16 lag_id;
2811 u8 port_index;
2812 int err;
2813
2814 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2815 if (err)
2816 return err;
2817 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2818 if (!lag->ref_count) {
2819 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2820 if (err)
2821 return err;
2822 lag->dev = lag_dev;
2823 }
2824
2825 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2826 if (err)
2827 return err;
2828 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2829 if (err)
2830 goto err_col_port_add;
2831 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2832 if (err)
2833 goto err_col_port_enable;
2834
2835 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2836 mlxsw_sp_port->local_port);
2837 mlxsw_sp_port->lag_id = lag_id;
2838 mlxsw_sp_port->lagged = 1;
2839 lag->ref_count++;
2840 return 0;
2841
2842err_col_port_add:
2843 if (!lag->ref_count)
2844 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2845err_col_port_enable:
2846 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2847 return err;
2848}
2849
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002850static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01002851 struct net_device *br_dev,
2852 bool flush_fdb);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002853
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002854static int mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2855 struct net_device *lag_dev)
2856{
2857 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002858 struct mlxsw_sp_port *mlxsw_sp_vport;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002859 struct mlxsw_sp_upper *lag;
2860 u16 lag_id = mlxsw_sp_port->lag_id;
2861 int err;
2862
2863 if (!mlxsw_sp_port->lagged)
2864 return 0;
2865 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2866 WARN_ON(lag->ref_count == 0);
2867
2868 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2869 if (err)
2870 return err;
Dan Carpenter82a06422015-12-09 13:33:51 +03002871 err = mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002872 if (err)
2873 return err;
2874
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002875 /* In case we leave a LAG device that has bridges built on top,
2876 * then their teardown sequence is never issued and we need to
2877 * invoke the necessary cleanup routines ourselves.
2878 */
2879 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2880 vport.list) {
2881 struct net_device *br_dev;
2882
2883 if (!mlxsw_sp_vport->bridged)
2884 continue;
2885
2886 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002887 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002888 }
2889
2890 if (mlxsw_sp_port->bridged) {
2891 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002892 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
Ido Schimmel912b1c82016-03-07 15:15:29 +01002893 mlxsw_sp_master_bridge_dec(mlxsw_sp, NULL);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002894 }
2895
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002896 if (lag->ref_count == 1) {
Ido Schimmel039c49a2016-01-27 15:20:18 +01002897 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2898 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002899 err = mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2900 if (err)
2901 return err;
2902 }
2903
2904 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2905 mlxsw_sp_port->local_port);
2906 mlxsw_sp_port->lagged = 0;
2907 lag->ref_count--;
2908 return 0;
2909}
2910
Jiri Pirko74581202015-12-03 12:12:30 +01002911static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2912 u16 lag_id)
2913{
2914 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2915 char sldr_pl[MLXSW_REG_SLDR_LEN];
2916
2917 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2918 mlxsw_sp_port->local_port);
2919 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2920}
2921
2922static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2923 u16 lag_id)
2924{
2925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2926 char sldr_pl[MLXSW_REG_SLDR_LEN];
2927
2928 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2929 mlxsw_sp_port->local_port);
2930 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2931}
2932
2933static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2934 bool lag_tx_enabled)
2935{
2936 if (lag_tx_enabled)
2937 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2938 mlxsw_sp_port->lag_id);
2939 else
2940 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2941 mlxsw_sp_port->lag_id);
2942}
2943
2944static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2945 struct netdev_lag_lower_state_info *info)
2946{
2947 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2948}
2949
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002950static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2951 struct net_device *vlan_dev)
2952{
2953 struct mlxsw_sp_port *mlxsw_sp_vport;
2954 u16 vid = vlan_dev_vlan_id(vlan_dev);
2955
2956 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2957 if (!mlxsw_sp_vport) {
2958 WARN_ON(!mlxsw_sp_vport);
2959 return -EINVAL;
2960 }
2961
2962 mlxsw_sp_vport->dev = vlan_dev;
2963
2964 return 0;
2965}
2966
2967static int mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2968 struct net_device *vlan_dev)
2969{
2970 struct mlxsw_sp_port *mlxsw_sp_vport;
2971 u16 vid = vlan_dev_vlan_id(vlan_dev);
2972
2973 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2974 if (!mlxsw_sp_vport) {
2975 WARN_ON(!mlxsw_sp_vport);
2976 return -EINVAL;
2977 }
2978
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002979 /* When removing a VLAN device while still bridged we should first
2980 * remove it from the bridge, as we receive the bridge's notification
2981 * when the vPort is already gone.
2982 */
2983 if (mlxsw_sp_vport->bridged) {
2984 struct net_device *br_dev;
2985
2986 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002987 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002988 }
2989
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002990 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
2991
2992 return 0;
2993}
2994
Jiri Pirko74581202015-12-03 12:12:30 +01002995static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2996 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002997{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002998 struct netdev_notifier_changeupper_info *info;
2999 struct mlxsw_sp_port *mlxsw_sp_port;
3000 struct net_device *upper_dev;
3001 struct mlxsw_sp *mlxsw_sp;
3002 int err;
3003
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003004 mlxsw_sp_port = netdev_priv(dev);
3005 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3006 info = ptr;
3007
3008 switch (event) {
3009 case NETDEV_PRECHANGEUPPER:
3010 upper_dev = info->upper_dev;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003011 if (!info->master || !info->linking)
3012 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003013 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003014 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003015 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
3016 return NOTIFY_BAD;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003017 if (netif_is_lag_master(upper_dev) &&
3018 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3019 info->upper_info))
3020 return NOTIFY_BAD;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003021 break;
3022 case NETDEV_CHANGEUPPER:
3023 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003024 if (is_vlan_dev(upper_dev)) {
3025 if (info->linking) {
3026 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3027 upper_dev);
3028 if (err) {
3029 netdev_err(dev, "Failed to link VLAN device\n");
3030 return NOTIFY_BAD;
3031 }
3032 } else {
3033 err = mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3034 upper_dev);
3035 if (err) {
3036 netdev_err(dev, "Failed to unlink VLAN device\n");
3037 return NOTIFY_BAD;
3038 }
3039 }
3040 } else if (netif_is_bridge_master(upper_dev)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003041 if (info->linking) {
3042 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port);
Ido Schimmel78124072016-01-04 10:42:24 +01003043 if (err) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003044 netdev_err(dev, "Failed to join bridge\n");
Ido Schimmel78124072016-01-04 10:42:24 +01003045 return NOTIFY_BAD;
3046 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003047 mlxsw_sp_master_bridge_inc(mlxsw_sp, upper_dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003048 } else {
Ido Schimmel039c49a2016-01-27 15:20:18 +01003049 err = mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
3050 true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003051 mlxsw_sp_master_bridge_dec(mlxsw_sp, upper_dev);
Ido Schimmel78124072016-01-04 10:42:24 +01003052 if (err) {
3053 netdev_err(dev, "Failed to leave bridge\n");
3054 return NOTIFY_BAD;
3055 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003056 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003057 } else if (netif_is_lag_master(upper_dev)) {
3058 if (info->linking) {
3059 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3060 upper_dev);
3061 if (err) {
3062 netdev_err(dev, "Failed to join link aggregation\n");
3063 return NOTIFY_BAD;
3064 }
3065 } else {
3066 err = mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3067 upper_dev);
3068 if (err) {
3069 netdev_err(dev, "Failed to leave link aggregation\n");
3070 return NOTIFY_BAD;
3071 }
3072 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003073 }
3074 break;
3075 }
3076
3077 return NOTIFY_DONE;
3078}
3079
Jiri Pirko74581202015-12-03 12:12:30 +01003080static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3081 unsigned long event, void *ptr)
3082{
3083 struct netdev_notifier_changelowerstate_info *info;
3084 struct mlxsw_sp_port *mlxsw_sp_port;
3085 int err;
3086
3087 mlxsw_sp_port = netdev_priv(dev);
3088 info = ptr;
3089
3090 switch (event) {
3091 case NETDEV_CHANGELOWERSTATE:
3092 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3093 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3094 info->lower_state_info);
3095 if (err)
3096 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3097 }
3098 break;
3099 }
3100
3101 return NOTIFY_DONE;
3102}
3103
3104static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3105 unsigned long event, void *ptr)
3106{
3107 switch (event) {
3108 case NETDEV_PRECHANGEUPPER:
3109 case NETDEV_CHANGEUPPER:
3110 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3111 case NETDEV_CHANGELOWERSTATE:
3112 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3113 }
3114
3115 return NOTIFY_DONE;
3116}
3117
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003118static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3119 unsigned long event, void *ptr)
3120{
3121 struct net_device *dev;
3122 struct list_head *iter;
3123 int ret;
3124
3125 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3126 if (mlxsw_sp_port_dev_check(dev)) {
3127 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3128 if (ret == NOTIFY_BAD)
3129 return ret;
3130 }
3131 }
3132
3133 return NOTIFY_DONE;
3134}
3135
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003136static struct mlxsw_sp_vfid *
3137mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3138 const struct net_device *br_dev)
3139{
3140 struct mlxsw_sp_vfid *vfid;
3141
3142 list_for_each_entry(vfid, &mlxsw_sp->br_vfids.list, list) {
3143 if (vfid->br_dev == br_dev)
3144 return vfid;
3145 }
3146
3147 return NULL;
3148}
3149
3150static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3151{
3152 return vfid - MLXSW_SP_VFID_PORT_MAX;
3153}
3154
3155static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3156{
3157 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3158}
3159
3160static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3161{
3162 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3163 MLXSW_SP_VFID_BR_MAX);
3164}
3165
3166static struct mlxsw_sp_vfid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3167 struct net_device *br_dev)
3168{
3169 struct device *dev = mlxsw_sp->bus_info->dev;
3170 struct mlxsw_sp_vfid *vfid;
3171 u16 n_vfid;
3172 int err;
3173
3174 n_vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3175 if (n_vfid == MLXSW_SP_VFID_MAX) {
3176 dev_err(dev, "No available vFIDs\n");
3177 return ERR_PTR(-ERANGE);
3178 }
3179
3180 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
3181 if (err) {
3182 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
3183 return ERR_PTR(err);
3184 }
3185
3186 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
3187 if (!vfid)
3188 goto err_allocate_vfid;
3189
3190 vfid->vfid = n_vfid;
3191 vfid->br_dev = br_dev;
3192
3193 list_add(&vfid->list, &mlxsw_sp->br_vfids.list);
3194 set_bit(mlxsw_sp_vfid_to_br_vfid(n_vfid), mlxsw_sp->br_vfids.mapped);
3195
3196 return vfid;
3197
3198err_allocate_vfid:
3199 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
3200 return ERR_PTR(-ENOMEM);
3201}
3202
3203static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3204 struct mlxsw_sp_vfid *vfid)
3205{
3206 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid->vfid);
3207
3208 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3209 list_del(&vfid->list);
3210
3211 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
3212
3213 kfree(vfid);
3214}
3215
3216static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003217 struct net_device *br_dev,
3218 bool flush_fdb)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003219{
3220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3221 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3222 struct net_device *dev = mlxsw_sp_vport->dev;
3223 struct mlxsw_sp_vfid *vfid, *new_vfid;
3224 int err;
3225
3226 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3227 if (!vfid) {
3228 WARN_ON(!vfid);
3229 return -EINVAL;
3230 }
3231
3232 /* We need a vFID to go back to after leaving the bridge's vFID. */
3233 new_vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3234 if (!new_vfid) {
3235 new_vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3236 if (IS_ERR(new_vfid)) {
3237 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3238 vid);
3239 return PTR_ERR(new_vfid);
3240 }
3241 }
3242
3243 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3244 * one for the new vFID.
3245 */
3246 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3247 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3248 false,
3249 mlxsw_sp_vfid_to_fid(vfid->vfid),
3250 vid);
3251 if (err) {
3252 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3253 vfid->vfid);
3254 goto err_port_vid_to_fid_invalidate;
3255 }
3256
3257 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3258 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3259 true,
3260 mlxsw_sp_vfid_to_fid(new_vfid->vfid),
3261 vid);
3262 if (err) {
3263 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3264 new_vfid->vfid);
3265 goto err_port_vid_to_fid_validate;
3266 }
3267
3268 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3269 if (err) {
3270 netdev_err(dev, "Failed to disable learning\n");
3271 goto err_port_vid_learning_set;
3272 }
3273
3274 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
3275 false);
3276 if (err) {
3277 netdev_err(dev, "Failed clear to clear flooding\n");
3278 goto err_vport_flood_set;
3279 }
3280
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003281 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3282 MLXSW_REG_SPMS_STATE_FORWARDING);
3283 if (err) {
3284 netdev_err(dev, "Failed to set STP state\n");
3285 goto err_port_stp_state_set;
3286 }
3287
Ido Schimmel039c49a2016-01-27 15:20:18 +01003288 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3289 netdev_err(dev, "Failed to flush FDB\n");
3290
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003291 /* Switch between the vFIDs and destroy the old one if needed. */
3292 new_vfid->nr_vports++;
3293 mlxsw_sp_vport->vport.vfid = new_vfid;
3294 vfid->nr_vports--;
3295 if (!vfid->nr_vports)
3296 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3297
3298 mlxsw_sp_vport->learning = 0;
3299 mlxsw_sp_vport->learning_sync = 0;
3300 mlxsw_sp_vport->uc_flood = 0;
3301 mlxsw_sp_vport->bridged = 0;
3302
3303 return 0;
3304
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003305err_port_stp_state_set:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003306err_vport_flood_set:
3307err_port_vid_learning_set:
3308err_port_vid_to_fid_validate:
3309err_port_vid_to_fid_invalidate:
3310 /* Rollback vFID only if new. */
3311 if (!new_vfid->nr_vports)
3312 mlxsw_sp_vfid_destroy(mlxsw_sp, new_vfid);
3313 return err;
3314}
3315
3316static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3317 struct net_device *br_dev)
3318{
3319 struct mlxsw_sp_vfid *old_vfid = mlxsw_sp_vport->vport.vfid;
3320 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3321 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3322 struct net_device *dev = mlxsw_sp_vport->dev;
3323 struct mlxsw_sp_vfid *vfid;
3324 int err;
3325
3326 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3327 if (!vfid) {
3328 vfid = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3329 if (IS_ERR(vfid)) {
3330 netdev_err(dev, "Failed to create bridge vFID\n");
3331 return PTR_ERR(vfid);
3332 }
3333 }
3334
3335 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, true, false);
3336 if (err) {
3337 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
3338 vfid->vfid);
3339 goto err_port_flood_set;
3340 }
3341
3342 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3343 if (err) {
3344 netdev_err(dev, "Failed to enable learning\n");
3345 goto err_port_vid_learning_set;
3346 }
3347
3348 /* We need to invalidate existing {Port, VID} to vFID mapping and
3349 * create a new one for the bridge's vFID.
3350 */
3351 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3352 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3353 false,
3354 mlxsw_sp_vfid_to_fid(old_vfid->vfid),
3355 vid);
3356 if (err) {
3357 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3358 old_vfid->vfid);
3359 goto err_port_vid_to_fid_invalidate;
3360 }
3361
3362 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3363 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3364 true,
3365 mlxsw_sp_vfid_to_fid(vfid->vfid),
3366 vid);
3367 if (err) {
3368 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3369 vfid->vfid);
3370 goto err_port_vid_to_fid_validate;
3371 }
3372
3373 /* Switch between the vFIDs and destroy the old one if needed. */
3374 vfid->nr_vports++;
3375 mlxsw_sp_vport->vport.vfid = vfid;
3376 old_vfid->nr_vports--;
3377 if (!old_vfid->nr_vports)
3378 mlxsw_sp_vfid_destroy(mlxsw_sp, old_vfid);
3379
3380 mlxsw_sp_vport->learning = 1;
3381 mlxsw_sp_vport->learning_sync = 1;
3382 mlxsw_sp_vport->uc_flood = 1;
3383 mlxsw_sp_vport->bridged = 1;
3384
3385 return 0;
3386
3387err_port_vid_to_fid_validate:
3388 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3389 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
3390 mlxsw_sp_vfid_to_fid(old_vfid->vfid), vid);
3391err_port_vid_to_fid_invalidate:
3392 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3393err_port_vid_learning_set:
3394 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false, false);
3395err_port_flood_set:
3396 if (!vfid->nr_vports)
3397 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3398 return err;
3399}
3400
3401static bool
3402mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3403 const struct net_device *br_dev)
3404{
3405 struct mlxsw_sp_port *mlxsw_sp_vport;
3406
3407 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3408 vport.list) {
3409 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3410 return false;
3411 }
3412
3413 return true;
3414}
3415
3416static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3417 unsigned long event, void *ptr,
3418 u16 vid)
3419{
3420 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3421 struct netdev_notifier_changeupper_info *info = ptr;
3422 struct mlxsw_sp_port *mlxsw_sp_vport;
3423 struct net_device *upper_dev;
3424 int err;
3425
3426 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3427
3428 switch (event) {
3429 case NETDEV_PRECHANGEUPPER:
3430 upper_dev = info->upper_dev;
3431 if (!info->master || !info->linking)
3432 break;
3433 if (!netif_is_bridge_master(upper_dev))
3434 return NOTIFY_BAD;
3435 /* We can't have multiple VLAN interfaces configured on
3436 * the same port and being members in the same bridge.
3437 */
3438 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3439 upper_dev))
3440 return NOTIFY_BAD;
3441 break;
3442 case NETDEV_CHANGEUPPER:
3443 upper_dev = info->upper_dev;
3444 if (!info->master)
3445 break;
3446 if (info->linking) {
3447 if (!mlxsw_sp_vport) {
3448 WARN_ON(!mlxsw_sp_vport);
3449 return NOTIFY_BAD;
3450 }
3451 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3452 upper_dev);
3453 if (err) {
3454 netdev_err(dev, "Failed to join bridge\n");
3455 return NOTIFY_BAD;
3456 }
3457 } else {
3458 /* We ignore bridge's unlinking notifications if vPort
3459 * is gone, since we already left the bridge when the
3460 * VLAN device was unlinked from the real device.
3461 */
3462 if (!mlxsw_sp_vport)
3463 return NOTIFY_DONE;
3464 err = mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003465 upper_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003466 if (err) {
3467 netdev_err(dev, "Failed to leave bridge\n");
3468 return NOTIFY_BAD;
3469 }
3470 }
3471 }
3472
3473 return NOTIFY_DONE;
3474}
3475
Ido Schimmel272c4472015-12-15 16:03:47 +01003476static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3477 unsigned long event, void *ptr,
3478 u16 vid)
3479{
3480 struct net_device *dev;
3481 struct list_head *iter;
3482 int ret;
3483
3484 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3485 if (mlxsw_sp_port_dev_check(dev)) {
3486 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3487 vid);
3488 if (ret == NOTIFY_BAD)
3489 return ret;
3490 }
3491 }
3492
3493 return NOTIFY_DONE;
3494}
3495
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003496static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3497 unsigned long event, void *ptr)
3498{
3499 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3500 u16 vid = vlan_dev_vlan_id(vlan_dev);
3501
Ido Schimmel272c4472015-12-15 16:03:47 +01003502 if (mlxsw_sp_port_dev_check(real_dev))
3503 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3504 vid);
3505 else if (netif_is_lag_master(real_dev))
3506 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3507 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003508
Ido Schimmel272c4472015-12-15 16:03:47 +01003509 return NOTIFY_DONE;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003510}
3511
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003512static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3513 unsigned long event, void *ptr)
3514{
3515 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3516
3517 if (mlxsw_sp_port_dev_check(dev))
3518 return mlxsw_sp_netdevice_port_event(dev, event, ptr);
3519
3520 if (netif_is_lag_master(dev))
3521 return mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3522
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003523 if (is_vlan_dev(dev))
3524 return mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3525
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003526 return NOTIFY_DONE;
3527}
3528
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003529static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3530 .notifier_call = mlxsw_sp_netdevice_event,
3531};
3532
3533static int __init mlxsw_sp_module_init(void)
3534{
3535 int err;
3536
3537 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3538 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3539 if (err)
3540 goto err_core_driver_register;
3541 return 0;
3542
3543err_core_driver_register:
3544 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3545 return err;
3546}
3547
3548static void __exit mlxsw_sp_module_exit(void)
3549{
3550 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3551 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3552}
3553
3554module_init(mlxsw_sp_module_init);
3555module_exit(mlxsw_sp_module_exit);
3556
3557MODULE_LICENSE("Dual BSD/GPL");
3558MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3559MODULE_DESCRIPTION("Mellanox Spectrum driver");
3560MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);