blob: 9206cc02c8a883df978199c167a11292ac121293 [file] [log] [blame]
Zhi Wang28c4c6c2016-05-01 05:22:47 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
Zhi Wange4734052016-05-01 07:42:16 -040022 *
23 * Authors:
24 * Zhi Wang <zhi.a.wang@intel.com>
25 *
26 * Contributors:
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
33 *
Zhi Wang28c4c6c2016-05-01 05:22:47 -040034 */
35
36#ifndef _GVT_SCHEDULER_H_
37#define _GVT_SCHEDULER_H_
38
39struct intel_gvt_workload_scheduler {
Zhi Wange4734052016-05-01 07:42:16 -040040 struct intel_vgpu *current_vgpu;
41 struct intel_vgpu *next_vgpu;
42 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
43 bool need_reschedule;
44
45 wait_queue_head_t workload_complete_wq;
46 struct task_struct *thread[I915_NUM_ENGINES];
47 wait_queue_head_t waitq[I915_NUM_ENGINES];
Zhi Wang28c4c6c2016-05-01 05:22:47 -040048};
49
50struct intel_vgpu_workload {
51 struct intel_vgpu *vgpu;
52 int ring_id;
53 struct drm_i915_gem_request *req;
54 /* if this workload has been dispatched to i915? */
55 bool dispatched;
56 int status;
57
58 struct intel_vgpu_mm *shadow_mm;
59
60 /* different submission model may need different handler */
61 int (*prepare)(struct intel_vgpu_workload *);
62 int (*complete)(struct intel_vgpu_workload *);
63 struct list_head list;
64
65 /* execlist context information */
66 struct execlist_ctx_descriptor_format ctx_desc;
67 struct execlist_ring_context *ring_context;
68 unsigned long rb_head, rb_tail, rb_ctl, rb_start;
Zhi Wange4734052016-05-01 07:42:16 -040069 bool restore_inhibit;
Zhi Wang28c4c6c2016-05-01 05:22:47 -040070 struct intel_vgpu_elsp_dwords elsp_dwords;
71 bool emulate_schedule_in;
72 atomic_t shadow_ctx_active;
73 wait_queue_head_t shadow_ctx_status_wq;
74 u64 ring_context_gpa;
75};
76
77#define workload_q_head(vgpu, ring_id) \
78 (&(vgpu->workload_q_head[ring_id]))
79
Zhi Wange4734052016-05-01 07:42:16 -040080#define queue_workload(workload) do { \
Zhi Wang28c4c6c2016-05-01 05:22:47 -040081 list_add_tail(&workload->list, \
Zhi Wange4734052016-05-01 07:42:16 -040082 workload_q_head(workload->vgpu, workload->ring_id)); \
83 wake_up(&workload->vgpu->gvt-> \
84 scheduler.waitq[workload->ring_id]); \
85} while (0)
86
87int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
88
89void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
90
91void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
92
93int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
94
95void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
Zhi Wang28c4c6c2016-05-01 05:22:47 -040096
97#endif