blob: cd293d27677e6ae57601c5bd58c5d151ae16c5ef [file] [log] [blame]
Johannes Berg8ca151b2013-01-24 14:25:36 +01001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
Emmanuel Grumbach51368bf2013-12-30 13:15:54 +02008 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
Avraham Sternee9219b2015-03-23 15:09:27 +02009 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
Johannes Berg8ca151b2013-01-24 14:25:36 +010010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
Emmanuel Grumbach410dc5a2013-02-18 09:22:28 +020026 * in the file called COPYING.
Johannes Berg8ca151b2013-01-24 14:25:36 +010027 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
Emmanuel Grumbach51368bf2013-12-30 13:15:54 +020034 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
Avraham Sternee9219b2015-03-23 15:09:27 +020035 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
Johannes Berg8ca151b2013-01-24 14:25:36 +010036 * All rights reserved.
37 *
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39 * modification, are permitted provided that the following conditions
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41 *
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43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
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46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
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50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65
66#ifndef __fw_api_h__
67#define __fw_api_h__
68
69#include "fw-api-rs.h"
70#include "fw-api-tx.h"
71#include "fw-api-sta.h"
72#include "fw-api-mac.h"
73#include "fw-api-power.h"
74#include "fw-api-d3.h"
Emmanuel Grumbach5b7ff612014-03-11 19:27:45 +020075#include "fw-api-coex.h"
Haim Dreyfusse820c2d2014-04-06 11:19:09 +030076#include "fw-api-scan.h"
Johannes Bergd19ac582015-01-14 15:54:18 +010077#include "fw-api-stats.h"
Gregory Greenmance792912015-06-02 18:06:16 +030078#include "fw-api-tof.h"
Johannes Berg8ca151b2013-01-24 14:25:36 +010079
Eytan Lifshitz19e737c2013-09-09 13:30:15 +020080/* Tx queue numbers */
Johannes Berg8ca151b2013-01-24 14:25:36 +010081enum {
82 IWL_MVM_OFFCHANNEL_QUEUE = 8,
83 IWL_MVM_CMD_QUEUE = 9,
Johannes Berg8ca151b2013-01-24 14:25:36 +010084};
85
Johannes Bergb2d81db2014-08-01 20:48:25 +020086enum iwl_mvm_tx_fifo {
87 IWL_MVM_TX_FIFO_BK = 0,
88 IWL_MVM_TX_FIFO_BE,
89 IWL_MVM_TX_FIFO_VI,
90 IWL_MVM_TX_FIFO_VO,
91 IWL_MVM_TX_FIFO_MCAST = 5,
92 IWL_MVM_TX_FIFO_CMD = 7,
93};
Eytan Lifshitz19e737c2013-09-09 13:30:15 +020094
Johannes Berg8ca151b2013-01-24 14:25:36 +010095#define IWL_MVM_STATION_COUNT 16
96
Arik Nemtsovcf7b4912014-05-15 11:44:40 +030097#define IWL_MVM_TDLS_STA_COUNT 4
98
Johannes Berg8ca151b2013-01-24 14:25:36 +010099/* commands */
100enum {
101 MVM_ALIVE = 0x1,
102 REPLY_ERROR = 0x2,
Emmanuel Grumbache5046012015-08-17 10:45:50 +0300103 ECHO_CMD = 0x3,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100104
105 INIT_COMPLETE_NOTIF = 0x4,
106
107 /* PHY context commands */
108 PHY_CONTEXT_CMD = 0x8,
109 DBG_CFG = 0x9,
Emmanuel Grumbachb9fae2d2014-02-17 11:24:10 +0200110 ANTENNA_COUPLING_NOTIFICATION = 0xa,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100111
David Spinadeld2496222014-05-20 12:46:37 +0300112 /* UMAC scan commands */
Avraham Sternee9219b2015-03-23 15:09:27 +0200113 SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
David Spinadeld2496222014-05-20 12:46:37 +0300114 SCAN_CFG_CMD = 0xc,
115 SCAN_REQ_UMAC = 0xd,
116 SCAN_ABORT_UMAC = 0xe,
117 SCAN_COMPLETE_UMAC = 0xf,
118
Johannes Berg8ca151b2013-01-24 14:25:36 +0100119 /* station table */
Max Stepanov5a258aa2013-04-07 09:11:21 +0300120 ADD_STA_KEY = 0x17,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100121 ADD_STA = 0x18,
122 REMOVE_STA = 0x19,
123
Matti Gottliebe1120182015-07-19 11:15:07 +0300124 /* paging get item */
125 FW_GET_ITEM_CMD = 0x1a,
126
Johannes Berg8ca151b2013-01-24 14:25:36 +0100127 /* TX */
128 TX_CMD = 0x1c,
129 TXPATH_FLUSH = 0x1e,
130 MGMT_MCAST_KEY = 0x1f,
131
Avri Altman3edf8ff2014-07-30 11:41:01 +0300132 /* scheduler config */
133 SCD_QUEUE_CFG = 0x1d,
134
Johannes Berg8ca151b2013-01-24 14:25:36 +0100135 /* global key */
136 WEP_KEY = 0x20,
137
Liad Kaufman04fd2c22014-12-15 17:54:16 +0200138 /* Memory */
139 SHARED_MEM_CFG = 0x25,
140
Arik Nemtsov77c5d7e2014-09-11 13:10:08 +0300141 /* TDLS */
142 TDLS_CHANNEL_SWITCH_CMD = 0x27,
143 TDLS_CHANNEL_SWITCH_NOTIFICATION = 0xaa,
Arik Nemtsov307e4722014-09-15 18:48:59 +0300144 TDLS_CONFIG_CMD = 0xa7,
Arik Nemtsov77c5d7e2014-09-11 13:10:08 +0300145
Johannes Berg8ca151b2013-01-24 14:25:36 +0100146 /* MAC and Binding commands */
147 MAC_CONTEXT_CMD = 0x28,
148 TIME_EVENT_CMD = 0x29, /* both CMD and response */
149 TIME_EVENT_NOTIFICATION = 0x2a,
150 BINDING_CONTEXT_CMD = 0x2b,
151 TIME_QUOTA_CMD = 0x2c,
Johannes Berg4ac6cb52013-08-08 09:30:13 +0200152 NON_QOS_TX_COUNTER_CMD = 0x2d,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100153
154 LQ_CMD = 0x4e,
155
Matti Gottlieba6c4fb42015-07-15 16:19:29 +0300156 /* paging block to FW cpu2 */
157 FW_PAGING_BLOCK_CMD = 0x4f,
158
Johannes Berg8ca151b2013-01-24 14:25:36 +0100159 /* Scan offload */
160 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
161 SCAN_OFFLOAD_ABORT_CMD = 0x52,
Ariej Marjieh720befbf2014-07-07 09:04:58 +0300162 HOT_SPOT_CMD = 0x53,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100163 SCAN_OFFLOAD_COMPLETE = 0x6D,
164 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
165 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
David Spinadel35a000b2013-08-28 09:29:43 +0300166 MATCH_FOUND_NOTIFICATION = 0xd9,
David Spinadelfb98be52014-05-04 12:51:10 +0300167 SCAN_ITERATION_COMPLETE = 0xe7,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100168
169 /* Phy */
170 PHY_CONFIGURATION_CMD = 0x6a,
171 CALIB_RES_NOTIF_PHY_DB = 0x6b,
172 /* PHY_DB_CMD = 0x6c, */
173
Gregory Greenmance792912015-06-02 18:06:16 +0300174 /* ToF - 802.11mc FTM */
175 TOF_CMD = 0x10,
176 TOF_NOTIFICATION = 0x11,
177
Alexander Bondare811ada2013-03-10 15:29:44 +0200178 /* Power - legacy power table command */
Johannes Berg8ca151b2013-01-24 14:25:36 +0100179 POWER_TABLE_CMD = 0x77,
Alexander Bondar175a70b2013-04-14 20:59:37 +0300180 PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
Emmanuel Grumbach9180ac52014-09-23 23:02:41 +0300181 LTR_CONFIG = 0xee,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100182
Eytan Lifshitz9ee718a2013-05-19 19:14:41 +0300183 /* Thermal Throttling*/
184 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
185
Matti Gottlieb0becb372015-05-31 09:18:30 +0300186 /* Set/Get DC2DC frequency tune */
187 DC2DC_CONFIG_CMD = 0x83,
188
Johannes Berg8ca151b2013-01-24 14:25:36 +0100189 /* NVM */
190 NVM_ACCESS_CMD = 0x88,
191
192 SET_CALIB_DEFAULT_CMD = 0x8e,
193
Ilan Peer571765c2013-03-05 15:26:03 +0200194 BEACON_NOTIFICATION = 0x90,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100195 BEACON_TEMPLATE_CMD = 0x91,
196 TX_ANT_CONFIGURATION_CMD = 0x98,
Johannes Berg91a8bcd2015-01-14 18:12:41 +0100197 STATISTICS_CMD = 0x9c,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100198 STATISTICS_NOTIFICATION = 0x9d,
Johannes Berg3e56ead2013-02-15 22:23:18 +0100199 EOSP_NOTIFICATION = 0x9e,
Matti Gottlieb88f2fd72013-07-09 15:25:46 +0300200 REDUCE_TX_POWER_CMD = 0x9f,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100201
202 /* RF-KILL commands and notifications */
203 CARD_STATE_CMD = 0xa0,
204 CARD_STATE_NOTIFICATION = 0xa1,
205
Hila Gonend64048e2013-03-13 18:00:03 +0200206 MISSED_BEACONS_NOTIFICATION = 0xa2,
207
Alexander Bondare811ada2013-03-10 15:29:44 +0200208 /* Power - new power table command */
209 MAC_PM_POWER_TABLE = 0xa9,
210
Chaya Rachel Ivgy30269c12014-11-15 21:08:29 +0200211 MFUART_LOAD_NOTIFICATION = 0xb1,
212
Johannes Berg8ca151b2013-01-24 14:25:36 +0100213 REPLY_RX_PHY_CMD = 0xc0,
214 REPLY_RX_MPDU_CMD = 0xc1,
215 BA_NOTIF = 0xc5,
216
Arik Nemtsovdcaf9f52014-03-04 19:54:12 +0200217 /* Location Aware Regulatory */
218 MCC_UPDATE_CMD = 0xc8,
Arik Nemtsov88931cc2014-03-05 12:26:15 +0200219 MCC_CHUB_UPDATE_CMD = 0xc9,
Arik Nemtsovdcaf9f52014-03-04 19:54:12 +0200220
Matti Gottlieba2d79c52014-08-25 14:41:23 +0300221 MARKER_CMD = 0xcb,
222
Emmanuel Grumbachfb3ceb82013-01-14 15:04:01 +0200223 /* BT Coex */
224 BT_COEX_PRIO_TABLE = 0xcc,
225 BT_COEX_PROT_ENV = 0xcd,
226 BT_PROFILE_NOTIFICATION = 0xce,
Emmanuel Grumbach430a3bb2014-04-02 09:55:16 +0300227 BT_CONFIG = 0x9b,
228 BT_COEX_UPDATE_SW_BOOST = 0x5a,
229 BT_COEX_UPDATE_CORUN_LUT = 0x5b,
230 BT_COEX_UPDATE_REDUCED_TXP = 0x5c,
Emmanuel Grumbachdac94da2013-06-18 07:35:27 +0300231 BT_COEX_CI = 0x5d,
Emmanuel Grumbachfb3ceb82013-01-14 15:04:01 +0200232
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +0200233 REPLY_SF_CFG_CMD = 0xd1,
Hila Gonen7df15b12012-12-12 11:16:19 +0200234 REPLY_BEACON_FILTERING_CMD = 0xd2,
235
Luciano Coelhoa0a09242014-09-04 12:29:15 +0300236 /* DTS measurements */
237 CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
238 DTS_MEASUREMENT_NOTIFICATION = 0xdd,
239
Johannes Berg8ca151b2013-01-24 14:25:36 +0100240 REPLY_DEBUG_CMD = 0xf0,
241 DEBUG_LOG_MSG = 0xf7,
242
Eliad Pellerc87163b2014-01-08 10:11:11 +0200243 BCAST_FILTER_CMD = 0xcf,
Emmanuel Grumbach51b6b9e2013-05-02 15:01:24 +0300244 MCAST_FILTER_CMD = 0xd0,
245
Johannes Berg8ca151b2013-01-24 14:25:36 +0100246 /* D3 commands/notifications */
247 D3_CONFIG_CMD = 0xd3,
248 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
249 OFFLOADS_QUERY_CMD = 0xd5,
250 REMOTE_WAKE_CONFIG_CMD = 0xd6,
Arik Nemtsov98ee7782013-10-02 16:58:09 +0300251 D0I3_END_CMD = 0xed,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100252
253 /* for WoWLAN in particular */
254 WOWLAN_PATTERNS = 0xe0,
255 WOWLAN_CONFIGURATION = 0xe1,
256 WOWLAN_TSC_RSC_PARAM = 0xe2,
257 WOWLAN_TKIP_PARAM = 0xe3,
258 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
259 WOWLAN_GET_STATUSES = 0xe5,
260 WOWLAN_TX_POWER_PER_DB = 0xe6,
261
262 /* and for NetDetect */
Luciano Coelhob04998f2014-11-20 15:58:34 +0200263 SCAN_OFFLOAD_PROFILES_QUERY_CMD = 0x56,
264 SCAN_OFFLOAD_HOTSPOTS_CONFIG_CMD = 0x58,
265 SCAN_OFFLOAD_HOTSPOTS_QUERY_CMD = 0x59,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100266
267 REPLY_MAX = 0xff,
268};
269
270/**
271 * struct iwl_cmd_response - generic response struct for most commands
272 * @status: status of the command asked, changes for each one
273 */
274struct iwl_cmd_response {
275 __le32 status;
276};
277
278/*
279 * struct iwl_tx_ant_cfg_cmd
280 * @valid: valid antenna configuration
281 */
282struct iwl_tx_ant_cfg_cmd {
283 __le32 valid;
284} __packed;
285
286/*
287 * Calibration control struct.
288 * Sent as part of the phy configuration command.
289 * @flow_trigger: bitmap for which calibrations to perform according to
290 * flow triggers.
291 * @event_trigger: bitmap for which calibrations to perform according to
292 * event triggers.
293 */
294struct iwl_calib_ctrl {
295 __le32 flow_trigger;
296 __le32 event_trigger;
297} __packed;
298
299/* This enum defines the bitmap of various calibrations to enable in both
300 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
301 */
302enum iwl_calib_cfg {
303 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
304 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
305 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
306 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
307 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
308 IWL_CALIB_CFG_DC_IDX = BIT(5),
309 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
310 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
311 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
312 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
313 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
314 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
315 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
316 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
317 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
318 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
319 IWL_CALIB_CFG_DAC_IDX = BIT(16),
320 IWL_CALIB_CFG_ABS_IDX = BIT(17),
321 IWL_CALIB_CFG_AGC_IDX = BIT(18),
322};
323
324/*
325 * Phy configuration command.
326 */
327struct iwl_phy_cfg_cmd {
328 __le32 phy_cfg;
329 struct iwl_calib_ctrl calib_control;
330} __packed;
331
332#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
333#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
334#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
335#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
336#define PHY_CFG_TX_CHAIN_A BIT(8)
337#define PHY_CFG_TX_CHAIN_B BIT(9)
338#define PHY_CFG_TX_CHAIN_C BIT(10)
339#define PHY_CFG_RX_CHAIN_A BIT(12)
340#define PHY_CFG_RX_CHAIN_B BIT(13)
341#define PHY_CFG_RX_CHAIN_C BIT(14)
342
343
344/* Target of the NVM_ACCESS_CMD */
345enum {
346 NVM_ACCESS_TARGET_CACHE = 0,
347 NVM_ACCESS_TARGET_OTP = 1,
348 NVM_ACCESS_TARGET_EEPROM = 2,
349};
350
Emmanuel Grumbachb9545b42013-03-06 11:34:44 +0200351/* Section types for NVM_ACCESS_CMD */
Johannes Berg8ca151b2013-01-24 14:25:36 +0100352enum {
Eran Hararyae2b21b2014-01-09 08:08:24 +0200353 NVM_SECTION_TYPE_SW = 1,
Eran Harary77db0a32014-02-04 14:21:38 +0200354 NVM_SECTION_TYPE_REGULATORY = 3,
Eran Hararyae2b21b2014-01-09 08:08:24 +0200355 NVM_SECTION_TYPE_CALIBRATION = 4,
356 NVM_SECTION_TYPE_PRODUCTION = 5,
Eran Harary77db0a32014-02-04 14:21:38 +0200357 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
Eran Hararyce500072014-12-01 17:53:53 +0200358 NVM_SECTION_TYPE_PHY_SKU = 12,
359 NVM_MAX_NUM_SECTIONS = 13,
Johannes Berg8ca151b2013-01-24 14:25:36 +0100360};
361
362/**
363 * struct iwl_nvm_access_cmd_ver2 - Request the device to send an NVM section
364 * @op_code: 0 - read, 1 - write
365 * @target: NVM_ACCESS_TARGET_*
366 * @type: NVM_SECTION_TYPE_*
367 * @offset: offset in bytes into the section
368 * @length: in bytes, to read/write
369 * @data: if write operation, the data to write. On read its empty
370 */
Emmanuel Grumbachb9545b42013-03-06 11:34:44 +0200371struct iwl_nvm_access_cmd {
Johannes Berg8ca151b2013-01-24 14:25:36 +0100372 u8 op_code;
373 u8 target;
374 __le16 type;
375 __le16 offset;
376 __le16 length;
377 u8 data[];
378} __packed; /* NVM_ACCESS_CMD_API_S_VER_2 */
379
Matti Gottlieba6c4fb42015-07-15 16:19:29 +0300380#define NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
381
382/*
383 * struct iwl_fw_paging_cmd - paging layout
384 *
385 * (FW_PAGING_BLOCK_CMD = 0x4f)
386 *
387 * Send to FW the paging layout in the driver.
388 *
389 * @flags: various flags for the command
390 * @block_size: the block size in powers of 2
391 * @block_num: number of blocks specified in the command.
392 * @device_phy_addr: virtual addresses from device side
393*/
394struct iwl_fw_paging_cmd {
395 __le32 flags;
396 __le32 block_size;
397 __le32 block_num;
398 __le32 device_phy_addr[NUM_OF_FW_PAGING_BLOCKS];
399} __packed; /* FW_PAGING_BLOCK_CMD_API_S_VER_1 */
400
Matti Gottliebe1120182015-07-19 11:15:07 +0300401/*
402 * Fw items ID's
403 *
404 * @IWL_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload
405 * download
406 */
407enum iwl_fw_item_id {
408 IWL_FW_ITEM_ID_PAGING = 3,
409};
410
411/*
412 * struct iwl_fw_get_item_cmd - get an item from the fw
413 */
414struct iwl_fw_get_item_cmd {
415 __le32 item_id;
416} __packed; /* FW_GET_ITEM_CMD_API_S_VER_1 */
417
418struct iwl_fw_get_item_resp {
419 __le32 item_id;
420 __le32 item_byte_cnt;
421 __le32 item_val;
422} __packed; /* FW_GET_ITEM_RSP_S_VER_1 */
423
Johannes Berg8ca151b2013-01-24 14:25:36 +0100424/**
425 * struct iwl_nvm_access_resp_ver2 - response to NVM_ACCESS_CMD
426 * @offset: offset in bytes into the section
427 * @length: in bytes, either how much was written or read
428 * @type: NVM_SECTION_TYPE_*
429 * @status: 0 for success, fail otherwise
430 * @data: if read operation, the data returned. Empty on write.
431 */
Emmanuel Grumbachb9545b42013-03-06 11:34:44 +0200432struct iwl_nvm_access_resp {
Johannes Berg8ca151b2013-01-24 14:25:36 +0100433 __le16 offset;
434 __le16 length;
435 __le16 type;
436 __le16 status;
437 u8 data[];
438} __packed; /* NVM_ACCESS_CMD_RESP_API_S_VER_2 */
439
440/* MVM_ALIVE 0x1 */
441
442/* alive response is_valid values */
443#define ALIVE_RESP_UCODE_OK BIT(0)
444#define ALIVE_RESP_RFKILL BIT(1)
445
446/* alive response ver_type values */
447enum {
448 FW_TYPE_HW = 0,
449 FW_TYPE_PROT = 1,
450 FW_TYPE_AP = 2,
451 FW_TYPE_WOWLAN = 3,
452 FW_TYPE_TIMING = 4,
453 FW_TYPE_WIPAN = 5
454};
455
456/* alive response ver_subtype values */
457enum {
458 FW_SUBTYPE_FULL_FEATURE = 0,
459 FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
460 FW_SUBTYPE_REDUCED = 2,
461 FW_SUBTYPE_ALIVE_ONLY = 3,
462 FW_SUBTYPE_WOWLAN = 4,
463 FW_SUBTYPE_AP_SUBTYPE = 5,
464 FW_SUBTYPE_WIPAN = 6,
465 FW_SUBTYPE_INITIALIZE = 9
466};
467
468#define IWL_ALIVE_STATUS_ERR 0xDEAD
469#define IWL_ALIVE_STATUS_OK 0xCAFE
470
471#define IWL_ALIVE_FLG_RFKILL BIT(0)
472
Emmanuel Grumbach7e1223b2015-02-03 20:11:48 +0200473struct mvm_alive_resp_ver1 {
Johannes Berg8ca151b2013-01-24 14:25:36 +0100474 __le16 status;
475 __le16 flags;
476 u8 ucode_minor;
477 u8 ucode_major;
478 __le16 id;
479 u8 api_minor;
480 u8 api_major;
481 u8 ver_subtype;
482 u8 ver_type;
483 u8 mac;
484 u8 opt;
485 __le16 reserved2;
486 __le32 timestamp;
487 __le32 error_event_table_ptr; /* SRAM address for error log */
488 __le32 log_event_table_ptr; /* SRAM address for event log */
489 __le32 cpu_register_ptr;
490 __le32 dbgm_config_ptr;
491 __le32 alive_counter_ptr;
492 __le32 scd_base_ptr; /* SRAM address for SCD */
493} __packed; /* ALIVE_RES_API_S_VER_1 */
494
Eran Harary01a9ca52014-02-03 09:29:57 +0200495struct mvm_alive_resp_ver2 {
496 __le16 status;
497 __le16 flags;
498 u8 ucode_minor;
499 u8 ucode_major;
500 __le16 id;
501 u8 api_minor;
502 u8 api_major;
503 u8 ver_subtype;
504 u8 ver_type;
505 u8 mac;
506 u8 opt;
507 __le16 reserved2;
508 __le32 timestamp;
509 __le32 error_event_table_ptr; /* SRAM address for error log */
510 __le32 log_event_table_ptr; /* SRAM address for LMAC event log */
511 __le32 cpu_register_ptr;
512 __le32 dbgm_config_ptr;
513 __le32 alive_counter_ptr;
514 __le32 scd_base_ptr; /* SRAM address for SCD */
515 __le32 st_fwrd_addr; /* pointer to Store and forward */
516 __le32 st_fwrd_size;
517 u8 umac_minor; /* UMAC version: minor */
518 u8 umac_major; /* UMAC version: major */
519 __le16 umac_id; /* UMAC version: id */
520 __le32 error_info_addr; /* SRAM address for UMAC error log */
521 __le32 dbg_print_buff_addr;
522} __packed; /* ALIVE_RES_API_S_VER_2 */
523
Emmanuel Grumbach7e1223b2015-02-03 20:11:48 +0200524struct mvm_alive_resp {
525 __le16 status;
526 __le16 flags;
527 __le32 ucode_minor;
528 __le32 ucode_major;
529 u8 ver_subtype;
530 u8 ver_type;
531 u8 mac;
532 u8 opt;
533 __le32 timestamp;
534 __le32 error_event_table_ptr; /* SRAM address for error log */
535 __le32 log_event_table_ptr; /* SRAM address for LMAC event log */
536 __le32 cpu_register_ptr;
537 __le32 dbgm_config_ptr;
538 __le32 alive_counter_ptr;
539 __le32 scd_base_ptr; /* SRAM address for SCD */
540 __le32 st_fwrd_addr; /* pointer to Store and forward */
541 __le32 st_fwrd_size;
542 __le32 umac_minor; /* UMAC version: minor */
543 __le32 umac_major; /* UMAC version: major */
544 __le32 error_info_addr; /* SRAM address for UMAC error log */
545 __le32 dbg_print_buff_addr;
546} __packed; /* ALIVE_RES_API_S_VER_3 */
547
Johannes Berg8ca151b2013-01-24 14:25:36 +0100548/* Error response/notification */
549enum {
550 FW_ERR_UNKNOWN_CMD = 0x0,
551 FW_ERR_INVALID_CMD_PARAM = 0x1,
552 FW_ERR_SERVICE = 0x2,
553 FW_ERR_ARC_MEMORY = 0x3,
554 FW_ERR_ARC_CODE = 0x4,
555 FW_ERR_WATCH_DOG = 0x5,
556 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
557 FW_ERR_WEP_KEY_SIZE = 0x11,
558 FW_ERR_OBSOLETE_FUNC = 0x12,
559 FW_ERR_UNEXPECTED = 0xFE,
560 FW_ERR_FATAL = 0xFF
561};
562
563/**
564 * struct iwl_error_resp - FW error indication
565 * ( REPLY_ERROR = 0x2 )
566 * @error_type: one of FW_ERR_*
567 * @cmd_id: the command ID for which the error occured
568 * @bad_cmd_seq_num: sequence number of the erroneous command
569 * @error_service: which service created the error, applicable only if
570 * error_type = 2, otherwise 0
571 * @timestamp: TSF in usecs.
572 */
573struct iwl_error_resp {
574 __le32 error_type;
575 u8 cmd_id;
576 u8 reserved1;
577 __le16 bad_cmd_seq_num;
578 __le32 error_service;
579 __le64 timestamp;
580} __packed;
581
582
583/* Common PHY, MAC and Bindings definitions */
584
585#define MAX_MACS_IN_BINDING (3)
586#define MAX_BINDINGS (4)
587#define AUX_BINDING_INDEX (3)
588#define MAX_PHYS (4)
589
590/* Used to extract ID and color from the context dword */
591#define FW_CTXT_ID_POS (0)
592#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
593#define FW_CTXT_COLOR_POS (8)
594#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
595#define FW_CTXT_INVALID (0xffffffff)
596
597#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
598 (_color << FW_CTXT_COLOR_POS))
599
600/* Possible actions on PHYs, MACs and Bindings */
601enum {
602 FW_CTXT_ACTION_STUB = 0,
603 FW_CTXT_ACTION_ADD,
604 FW_CTXT_ACTION_MODIFY,
605 FW_CTXT_ACTION_REMOVE,
606 FW_CTXT_ACTION_NUM
607}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
608
609/* Time Events */
610
611/* Time Event types, according to MAC type */
612enum iwl_time_event_type {
613 /* BSS Station Events */
614 TE_BSS_STA_AGGRESSIVE_ASSOC,
615 TE_BSS_STA_ASSOC,
616 TE_BSS_EAP_DHCP_PROT,
617 TE_BSS_QUIET_PERIOD,
618
619 /* P2P Device Events */
620 TE_P2P_DEVICE_DISCOVERABLE,
621 TE_P2P_DEVICE_LISTEN,
622 TE_P2P_DEVICE_ACTION_SCAN,
623 TE_P2P_DEVICE_FULL_SCAN,
624
625 /* P2P Client Events */
626 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
627 TE_P2P_CLIENT_ASSOC,
628 TE_P2P_CLIENT_QUIET_PERIOD,
629
630 /* P2P GO Events */
631 TE_P2P_GO_ASSOC_PROT,
632 TE_P2P_GO_REPETITIVE_NOA,
633 TE_P2P_GO_CT_WINDOW,
634
635 /* WiDi Sync Events */
636 TE_WIDI_TX_SYNC,
637
Andrei Otcheretianski7f0a7c62014-05-04 11:48:12 +0300638 /* Channel Switch NoA */
Luciano Coelhof991e172014-08-26 16:14:10 +0300639 TE_CHANNEL_SWITCH_PERIOD,
Andrei Otcheretianski7f0a7c62014-05-04 11:48:12 +0300640
Johannes Berg8ca151b2013-01-24 14:25:36 +0100641 TE_MAX
642}; /* MAC_EVENT_TYPE_API_E_VER_1 */
643
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300644
645
646/* Time event - defines for command API v1 */
Johannes Berg8ca151b2013-01-24 14:25:36 +0100647
648/*
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300649 * @TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
650 * @TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
651 * the first fragment is scheduled.
652 * @TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
653 * the first 2 fragments are scheduled.
654 * @TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
655 * number of fragments are valid.
Johannes Berg8ca151b2013-01-24 14:25:36 +0100656 *
657 * Other than the constant defined above, specifying a fragmentation value 'x'
658 * means that the event can be fragmented but only the first 'x' will be
659 * scheduled.
660 */
661enum {
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300662 TE_V1_FRAG_NONE = 0,
663 TE_V1_FRAG_SINGLE = 1,
664 TE_V1_FRAG_DUAL = 2,
665 TE_V1_FRAG_ENDLESS = 0xffffffff
Johannes Berg8ca151b2013-01-24 14:25:36 +0100666};
667
Johannes Berg8ca151b2013-01-24 14:25:36 +0100668/* If a Time Event can be fragmented, this is the max number of fragments */
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300669#define TE_V1_FRAG_MAX_MSK 0x0fffffff
670/* Repeat the time event endlessly (until removed) */
671#define TE_V1_REPEAT_ENDLESS 0xffffffff
672/* If a Time Event has bounded repetitions, this is the maximal value */
673#define TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
674
675/* Time Event dependencies: none, on another TE, or in a specific time */
676enum {
677 TE_V1_INDEPENDENT = 0,
678 TE_V1_DEP_OTHER = BIT(0),
679 TE_V1_DEP_TSF = BIT(1),
680 TE_V1_EVENT_SOCIOPATHIC = BIT(2),
681}; /* MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
682
683/*
684 * @TE_V1_NOTIF_NONE: no notifications
685 * @TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
686 * @TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
687 * @TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
688 * @TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
689 * @TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
690 * @TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
691 * @TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
692 * @TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
693 *
694 * Supported Time event notifications configuration.
695 * A notification (both event and fragment) includes a status indicating weather
696 * the FW was able to schedule the event or not. For fragment start/end
697 * notification the status is always success. There is no start/end fragment
698 * notification for monolithic events.
699 */
700enum {
701 TE_V1_NOTIF_NONE = 0,
702 TE_V1_NOTIF_HOST_EVENT_START = BIT(0),
703 TE_V1_NOTIF_HOST_EVENT_END = BIT(1),
704 TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2),
705 TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3),
706 TE_V1_NOTIF_HOST_FRAG_START = BIT(4),
707 TE_V1_NOTIF_HOST_FRAG_END = BIT(5),
708 TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6),
709 TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7),
710}; /* MAC_EVENT_ACTION_API_E_VER_2 */
711
Emmanuel Grumbacha373f672014-03-30 08:40:46 +0300712/* Time event - defines for command API */
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300713
714/*
715 * @TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
716 * @TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
717 * the first fragment is scheduled.
718 * @TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
719 * the first 2 fragments are scheduled.
720 * @TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
721 * number of fragments are valid.
722 *
723 * Other than the constant defined above, specifying a fragmentation value 'x'
724 * means that the event can be fragmented but only the first 'x' will be
725 * scheduled.
726 */
727enum {
728 TE_V2_FRAG_NONE = 0,
729 TE_V2_FRAG_SINGLE = 1,
730 TE_V2_FRAG_DUAL = 2,
731 TE_V2_FRAG_MAX = 0xfe,
732 TE_V2_FRAG_ENDLESS = 0xff
733};
734
735/* Repeat the time event endlessly (until removed) */
736#define TE_V2_REPEAT_ENDLESS 0xff
737/* If a Time Event has bounded repetitions, this is the maximal value */
738#define TE_V2_REPEAT_MAX 0xfe
739
740#define TE_V2_PLACEMENT_POS 12
741#define TE_V2_ABSENCE_POS 15
742
Emmanuel Grumbacha373f672014-03-30 08:40:46 +0300743/* Time event policy values
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300744 * A notification (both event and fragment) includes a status indicating weather
745 * the FW was able to schedule the event or not. For fragment start/end
746 * notification the status is always success. There is no start/end fragment
747 * notification for monolithic events.
748 *
749 * @TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
750 * @TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
751 * @TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
752 * @TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
753 * @TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
754 * @TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
755 * @TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
756 * @TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
757 * @TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
758 * @TE_V2_DEP_OTHER: depends on another time event
759 * @TE_V2_DEP_TSF: depends on a specific time
760 * @TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
761 * @TE_V2_ABSENCE: are we present or absent during the Time Event.
762 */
763enum {
764 TE_V2_DEFAULT_POLICY = 0x0,
765
766 /* notifications (event start/stop, fragment start/stop) */
767 TE_V2_NOTIF_HOST_EVENT_START = BIT(0),
768 TE_V2_NOTIF_HOST_EVENT_END = BIT(1),
769 TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2),
770 TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3),
771
772 TE_V2_NOTIF_HOST_FRAG_START = BIT(4),
773 TE_V2_NOTIF_HOST_FRAG_END = BIT(5),
774 TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6),
775 TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7),
Emmanuel Grumbach1f6bf072014-02-16 15:36:00 +0200776 T2_V2_START_IMMEDIATELY = BIT(11),
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300777
778 TE_V2_NOTIF_MSK = 0xff,
779
780 /* placement characteristics */
781 TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS),
782 TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1),
783 TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2),
784
785 /* are we present or absent during the Time Event. */
786 TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS),
787};
788
789/**
Emmanuel Grumbacha373f672014-03-30 08:40:46 +0300790 * struct iwl_time_event_cmd_api - configuring Time Events
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300791 * with struct MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
792 * with version 1. determined by IWL_UCODE_TLV_FLAGS)
793 * ( TIME_EVENT_CMD = 0x29 )
794 * @id_and_color: ID and color of the relevant MAC
795 * @action: action to perform, one of FW_CTXT_ACTION_*
796 * @id: this field has two meanings, depending on the action:
797 * If the action is ADD, then it means the type of event to add.
798 * For all other actions it is the unique event ID assigned when the
799 * event was added by the FW.
800 * @apply_time: When to start the Time Event (in GP2)
801 * @max_delay: maximum delay to event's start (apply time), in TU
802 * @depends_on: the unique ID of the event we depend on (if any)
803 * @interval: interval between repetitions, in TU
804 * @duration: duration of event in TU
805 * @repeat: how many repetitions to do, can be TE_REPEAT_ENDLESS
806 * @max_frags: maximal number of fragments the Time Event can be divided to
807 * @policy: defines whether uCode shall notify the host or other uCode modules
808 * on event and/or fragment start and/or end
809 * using one of TE_INDEPENDENT, TE_DEP_OTHER, TE_DEP_TSF
810 * TE_EVENT_SOCIOPATHIC
811 * using TE_ABSENCE and using TE_NOTIF_*
812 */
Emmanuel Grumbacha373f672014-03-30 08:40:46 +0300813struct iwl_time_event_cmd {
Eytan Lifshitzf8f03c32013-08-07 19:36:42 +0300814 /* COMMON_INDEX_HDR_API_S_VER_1 */
815 __le32 id_and_color;
816 __le32 action;
817 __le32 id;
818 /* MAC_TIME_EVENT_DATA_API_S_VER_2 */
819 __le32 apply_time;
820 __le32 max_delay;
821 __le32 depends_on;
822 __le32 interval;
823 __le32 duration;
824 u8 repeat;
825 u8 max_frags;
826 __le16 policy;
827} __packed; /* MAC_TIME_EVENT_CMD_API_S_VER_2 */
828
Johannes Berg8ca151b2013-01-24 14:25:36 +0100829/**
830 * struct iwl_time_event_resp - response structure to iwl_time_event_cmd
831 * @status: bit 0 indicates success, all others specify errors
832 * @id: the Time Event type
833 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
834 * @id_and_color: ID and color of the relevant MAC
835 */
836struct iwl_time_event_resp {
837 __le32 status;
838 __le32 id;
839 __le32 unique_id;
840 __le32 id_and_color;
841} __packed; /* MAC_TIME_EVENT_RSP_API_S_VER_1 */
842
843/**
844 * struct iwl_time_event_notif - notifications of time event start/stop
845 * ( TIME_EVENT_NOTIFICATION = 0x2a )
846 * @timestamp: action timestamp in GP2
847 * @session_id: session's unique id
848 * @unique_id: unique id of the Time Event itself
849 * @id_and_color: ID and color of the relevant MAC
850 * @action: one of TE_NOTIF_START or TE_NOTIF_END
851 * @status: true if scheduled, false otherwise (not executed)
852 */
853struct iwl_time_event_notif {
854 __le32 timestamp;
855 __le32 session_id;
856 __le32 unique_id;
857 __le32 id_and_color;
858 __le32 action;
859 __le32 status;
860} __packed; /* MAC_TIME_EVENT_NTFY_API_S_VER_1 */
861
862
863/* Bindings and Time Quota */
864
865/**
866 * struct iwl_binding_cmd - configuring bindings
867 * ( BINDING_CONTEXT_CMD = 0x2b )
868 * @id_and_color: ID and color of the relevant Binding
869 * @action: action to perform, one of FW_CTXT_ACTION_*
870 * @macs: array of MAC id and colors which belong to the binding
871 * @phy: PHY id and color which belongs to the binding
872 */
873struct iwl_binding_cmd {
874 /* COMMON_INDEX_HDR_API_S_VER_1 */
875 __le32 id_and_color;
876 __le32 action;
877 /* BINDING_DATA_API_S_VER_1 */
878 __le32 macs[MAX_MACS_IN_BINDING];
879 __le32 phy;
880} __packed; /* BINDING_CMD_API_S_VER_1 */
881
Ilan Peer35adfd62013-02-04 13:16:24 +0200882/* The maximal number of fragments in the FW's schedule session */
883#define IWL_MVM_MAX_QUOTA 128
884
Johannes Berg8ca151b2013-01-24 14:25:36 +0100885/**
886 * struct iwl_time_quota_data - configuration of time quota per binding
887 * @id_and_color: ID and color of the relevant Binding
888 * @quota: absolute time quota in TU. The scheduler will try to divide the
889 * remainig quota (after Time Events) according to this quota.
890 * @max_duration: max uninterrupted context duration in TU
891 */
892struct iwl_time_quota_data {
893 __le32 id_and_color;
894 __le32 quota;
895 __le32 max_duration;
896} __packed; /* TIME_QUOTA_DATA_API_S_VER_1 */
897
898/**
899 * struct iwl_time_quota_cmd - configuration of time quota between bindings
900 * ( TIME_QUOTA_CMD = 0x2c )
901 * @quotas: allocations per binding
902 */
903struct iwl_time_quota_cmd {
904 struct iwl_time_quota_data quotas[MAX_BINDINGS];
905} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
906
907
908/* PHY context */
909
910/* Supported bands */
911#define PHY_BAND_5 (0)
912#define PHY_BAND_24 (1)
913
914/* Supported channel width, vary if there is VHT support */
915#define PHY_VHT_CHANNEL_MODE20 (0x0)
916#define PHY_VHT_CHANNEL_MODE40 (0x1)
917#define PHY_VHT_CHANNEL_MODE80 (0x2)
918#define PHY_VHT_CHANNEL_MODE160 (0x3)
919
920/*
921 * Control channel position:
922 * For legacy set bit means upper channel, otherwise lower.
923 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
924 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
925 * center_freq
926 * |
927 * 40Mhz |_______|_______|
928 * 80Mhz |_______|_______|_______|_______|
929 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
930 * code 011 010 001 000 | 100 101 110 111
931 */
932#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
933#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
934#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
935#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
936#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
937#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
938#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
939#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
940
941/*
942 * @band: PHY_BAND_*
943 * @channel: channel number
944 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
945 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
946 */
947struct iwl_fw_channel_info {
948 u8 band;
949 u8 channel;
950 u8 width;
951 u8 ctrl_pos;
952} __packed;
953
954#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
955#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
956 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
957#define PHY_RX_CHAIN_VALID_POS (1)
958#define PHY_RX_CHAIN_VALID_MSK \
959 (0x7 << PHY_RX_CHAIN_VALID_POS)
960#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
961#define PHY_RX_CHAIN_FORCE_SEL_MSK \
962 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
963#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
964#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
965 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
966#define PHY_RX_CHAIN_CNT_POS (10)
967#define PHY_RX_CHAIN_CNT_MSK \
968 (0x3 << PHY_RX_CHAIN_CNT_POS)
969#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
970#define PHY_RX_CHAIN_MIMO_CNT_MSK \
971 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
972#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
973#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
974 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
975
976/* TODO: fix the value, make it depend on firmware at runtime? */
977#define NUM_PHY_CTX 3
978
979/* TODO: complete missing documentation */
980/**
981 * struct iwl_phy_context_cmd - config of the PHY context
982 * ( PHY_CONTEXT_CMD = 0x8 )
983 * @id_and_color: ID and color of the relevant Binding
984 * @action: action to perform, one of FW_CTXT_ACTION_*
985 * @apply_time: 0 means immediate apply and context switch.
986 * other value means apply new params after X usecs
987 * @tx_param_color: ???
988 * @channel_info:
989 * @txchain_info: ???
990 * @rxchain_info: ???
991 * @acquisition_data: ???
992 * @dsp_cfg_flags: set to 0
993 */
994struct iwl_phy_context_cmd {
995 /* COMMON_INDEX_HDR_API_S_VER_1 */
996 __le32 id_and_color;
997 __le32 action;
998 /* PHY_CONTEXT_DATA_API_S_VER_1 */
999 __le32 apply_time;
1000 __le32 tx_param_color;
1001 struct iwl_fw_channel_info ci;
1002 __le32 txchain_info;
1003 __le32 rxchain_info;
1004 __le32 acquisition_data;
1005 __le32 dsp_cfg_flags;
1006} __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
1007
Ariej Marjieh720befbf2014-07-07 09:04:58 +03001008/*
1009 * Aux ROC command
1010 *
1011 * Command requests the firmware to create a time event for a certain duration
1012 * and remain on the given channel. This is done by using the Aux framework in
1013 * the FW.
1014 * The command was first used for Hot Spot issues - but can be used regardless
1015 * to Hot Spot.
1016 *
1017 * ( HOT_SPOT_CMD 0x53 )
1018 *
1019 * @id_and_color: ID and color of the MAC
1020 * @action: action to perform, one of FW_CTXT_ACTION_*
1021 * @event_unique_id: If the action FW_CTXT_ACTION_REMOVE then the
1022 * event_unique_id should be the id of the time event assigned by ucode.
1023 * Otherwise ignore the event_unique_id.
1024 * @sta_id_and_color: station id and color, resumed during "Remain On Channel"
1025 * activity.
1026 * @channel_info: channel info
1027 * @node_addr: Our MAC Address
1028 * @reserved: reserved for alignment
1029 * @apply_time: GP2 value to start (should always be the current GP2 value)
1030 * @apply_time_max_delay: Maximum apply time delay value in TU. Defines max
1031 * time by which start of the event is allowed to be postponed.
1032 * @duration: event duration in TU To calculate event duration:
1033 * timeEventDuration = min(duration, remainingQuota)
1034 */
1035struct iwl_hs20_roc_req {
1036 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */
1037 __le32 id_and_color;
1038 __le32 action;
1039 __le32 event_unique_id;
1040 __le32 sta_id_and_color;
1041 struct iwl_fw_channel_info channel_info;
1042 u8 node_addr[ETH_ALEN];
1043 __le16 reserved;
1044 __le32 apply_time;
1045 __le32 apply_time_max_delay;
1046 __le32 duration;
1047} __packed; /* HOT_SPOT_CMD_API_S_VER_1 */
1048
1049/*
1050 * values for AUX ROC result values
1051 */
1052enum iwl_mvm_hot_spot {
1053 HOT_SPOT_RSP_STATUS_OK,
1054 HOT_SPOT_RSP_STATUS_TOO_MANY_EVENTS,
1055 HOT_SPOT_MAX_NUM_OF_SESSIONS,
1056};
1057
1058/*
1059 * Aux ROC command response
1060 *
1061 * In response to iwl_hs20_roc_req the FW sends this command to notify the
1062 * driver the uid of the timevent.
1063 *
1064 * ( HOT_SPOT_CMD 0x53 )
1065 *
1066 * @event_unique_id: Unique ID of time event assigned by ucode
1067 * @status: Return status 0 is success, all the rest used for specific errors
1068 */
1069struct iwl_hs20_roc_res {
1070 __le32 event_unique_id;
1071 __le32 status;
1072} __packed; /* HOT_SPOT_RSP_API_S_VER_1 */
1073
Johannes Berg8ca151b2013-01-24 14:25:36 +01001074#define IWL_RX_INFO_PHY_CNT 8
Avri Altmana2d7b872013-07-09 01:42:17 +03001075#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
1076#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
1077#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
1078#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
1079#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
1080#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
1081#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
1082
Johannes Berg8ca151b2013-01-24 14:25:36 +01001083#define IWL_RX_INFO_AGC_IDX 1
1084#define IWL_RX_INFO_RSSI_AB_IDX 2
Emmanuel Grumbach8101a7f2013-02-28 11:54:28 +02001085#define IWL_OFDM_AGC_A_MSK 0x0000007f
1086#define IWL_OFDM_AGC_A_POS 0
1087#define IWL_OFDM_AGC_B_MSK 0x00003f80
1088#define IWL_OFDM_AGC_B_POS 7
1089#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
1090#define IWL_OFDM_AGC_CODE_POS 20
Johannes Berg8ca151b2013-01-24 14:25:36 +01001091#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
Johannes Berg8ca151b2013-01-24 14:25:36 +01001092#define IWL_OFDM_RSSI_A_POS 0
Emmanuel Grumbach8101a7f2013-02-28 11:54:28 +02001093#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
1094#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
Johannes Berg8ca151b2013-01-24 14:25:36 +01001095#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
Johannes Berg8ca151b2013-01-24 14:25:36 +01001096#define IWL_OFDM_RSSI_B_POS 16
Emmanuel Grumbach8101a7f2013-02-28 11:54:28 +02001097#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
1098#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
Johannes Berg8ca151b2013-01-24 14:25:36 +01001099
1100/**
1101 * struct iwl_rx_phy_info - phy info
1102 * (REPLY_RX_PHY_CMD = 0xc0)
1103 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
1104 * @cfg_phy_cnt: configurable DSP phy data byte count
1105 * @stat_id: configurable DSP phy data set ID
1106 * @reserved1:
1107 * @system_timestamp: GP2 at on air rise
1108 * @timestamp: TSF at on air rise
1109 * @beacon_time_stamp: beacon at on-air rise
1110 * @phy_flags: general phy flags: band, modulation, ...
1111 * @channel: channel number
1112 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
1113 * @rate_n_flags: RATE_MCS_*
1114 * @byte_count: frame's byte-count
1115 * @frame_time: frame's time on the air, based on byte count and frame rate
1116 * calculation
Emmanuel Grumbach6bfcb7e2013-03-03 10:19:45 +02001117 * @mac_active_msk: what MACs were active when the frame was received
Johannes Berg8ca151b2013-01-24 14:25:36 +01001118 *
1119 * Before each Rx, the device sends this data. It contains PHY information
1120 * about the reception of the packet.
1121 */
1122struct iwl_rx_phy_info {
1123 u8 non_cfg_phy_cnt;
1124 u8 cfg_phy_cnt;
1125 u8 stat_id;
1126 u8 reserved1;
1127 __le32 system_timestamp;
1128 __le64 timestamp;
1129 __le32 beacon_time_stamp;
1130 __le16 phy_flags;
1131 __le16 channel;
1132 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
1133 __le32 rate_n_flags;
1134 __le32 byte_count;
Emmanuel Grumbach6bfcb7e2013-03-03 10:19:45 +02001135 __le16 mac_active_msk;
Johannes Berg8ca151b2013-01-24 14:25:36 +01001136 __le16 frame_time;
1137} __packed;
1138
Avri Altman93190fb2014-12-27 09:09:47 +02001139/*
1140 * TCP offload Rx assist info
1141 *
1142 * bits 0:3 - reserved
1143 * bits 4:7 - MIC CRC length
1144 * bits 8:12 - MAC header length
1145 * bit 13 - Padding indication
1146 * bit 14 - A-AMSDU indication
1147 * bit 15 - Offload enabled
1148 */
1149enum iwl_csum_rx_assist_info {
1150 CSUM_RXA_RESERVED_MASK = 0x000f,
1151 CSUM_RXA_MICSIZE_MASK = 0x00f0,
1152 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
1153 CSUM_RXA_PADD = BIT(13),
1154 CSUM_RXA_AMSDU = BIT(14),
1155 CSUM_RXA_ENA = BIT(15)
1156};
1157
1158/**
1159 * struct iwl_rx_mpdu_res_start - phy info
1160 * @assist: see CSUM_RX_ASSIST_ above
1161 */
Johannes Berg8ca151b2013-01-24 14:25:36 +01001162struct iwl_rx_mpdu_res_start {
1163 __le16 byte_count;
Avri Altman93190fb2014-12-27 09:09:47 +02001164 __le16 assist;
1165} __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
Johannes Berg8ca151b2013-01-24 14:25:36 +01001166
1167/**
1168 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
1169 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
1170 * @RX_RES_PHY_FLAGS_MOD_CCK:
1171 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
1172 * @RX_RES_PHY_FLAGS_NARROW_BAND:
1173 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
1174 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
1175 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
1176 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
1177 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
1178 */
1179enum iwl_rx_phy_flags {
1180 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
1181 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
1182 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
1183 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
1184 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
1185 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
1186 RX_RES_PHY_FLAGS_AGG = BIT(7),
1187 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
1188 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
1189 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
1190};
1191
1192/**
1193 * enum iwl_mvm_rx_status - written by fw for each Rx packet
1194 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
1195 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
1196 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
1197 * @RX_MPDU_RES_STATUS_KEY_VALID:
1198 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
1199 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
1200 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
1201 * in the driver.
1202 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
1203 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
1204 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
1205 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
1206 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
1207 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
1208 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
1209 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
1210 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
1211 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
1212 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
1213 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
1214 * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
1215 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
1216 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
1217 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
Avri Altman93190fb2014-12-27 09:09:47 +02001218 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
1219 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
Johannes Berg8ca151b2013-01-24 14:25:36 +01001220 * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
1221 * @RX_MPDU_RES_STATUS_STA_ID_MSK:
1222 * @RX_MPDU_RES_STATUS_RRF_KILL:
1223 * @RX_MPDU_RES_STATUS_FILTERING_MSK:
1224 * @RX_MPDU_RES_STATUS2_FILTERING_MSK:
1225 */
1226enum iwl_mvm_rx_status {
1227 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
1228 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
1229 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
1230 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
1231 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
1232 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
1233 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
1234 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
1235 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
1236 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
1237 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
1238 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
1239 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
Max Stepanove36e5432013-08-27 19:56:13 +03001240 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
Johannes Berg8ca151b2013-01-24 14:25:36 +01001241 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
1242 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
1243 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
1244 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
1245 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
1246 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
1247 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
1248 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
Avri Altman93190fb2014-12-27 09:09:47 +02001249 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16),
1250 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17),
Johannes Berg8ca151b2013-01-24 14:25:36 +01001251 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
1252 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
1253 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
1254 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
1255 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
1256};
1257
1258/**
1259 * struct iwl_radio_version_notif - information on the radio version
1260 * ( RADIO_VERSION_NOTIFICATION = 0x68 )
1261 * @radio_flavor:
1262 * @radio_step:
1263 * @radio_dash:
1264 */
1265struct iwl_radio_version_notif {
1266 __le32 radio_flavor;
1267 __le32 radio_step;
1268 __le32 radio_dash;
1269} __packed; /* RADIO_VERSION_NOTOFICATION_S_VER_1 */
1270
1271enum iwl_card_state_flags {
1272 CARD_ENABLED = 0x00,
1273 HW_CARD_DISABLED = 0x01,
1274 SW_CARD_DISABLED = 0x02,
1275 CT_KILL_CARD_DISABLED = 0x04,
1276 HALT_CARD_DISABLED = 0x08,
1277 CARD_DISABLED_MSK = 0x0f,
1278 CARD_IS_RX_ON = 0x10,
1279};
1280
1281/**
1282 * struct iwl_radio_version_notif - information on the radio version
1283 * ( CARD_STATE_NOTIFICATION = 0xa1 )
1284 * @flags: %iwl_card_state_flags
1285 */
1286struct iwl_card_state_notif {
1287 __le32 flags;
1288} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
1289
1290/**
Hila Gonend64048e2013-03-13 18:00:03 +02001291 * struct iwl_missed_beacons_notif - information on missed beacons
1292 * ( MISSED_BEACONS_NOTIFICATION = 0xa2 )
1293 * @mac_id: interface ID
1294 * @consec_missed_beacons_since_last_rx: number of consecutive missed
1295 * beacons since last RX.
1296 * @consec_missed_beacons: number of consecutive missed beacons
1297 * @num_expected_beacons:
1298 * @num_recvd_beacons:
1299 */
1300struct iwl_missed_beacons_notif {
1301 __le32 mac_id;
1302 __le32 consec_missed_beacons_since_last_rx;
1303 __le32 consec_missed_beacons;
1304 __le32 num_expected_beacons;
1305 __le32 num_recvd_beacons;
1306} __packed; /* MISSED_BEACON_NTFY_API_S_VER_3 */
1307
1308/**
Chaya Rachel Ivgy30269c12014-11-15 21:08:29 +02001309 * struct iwl_mfuart_load_notif - mfuart image version & status
1310 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
1311 * @installed_ver: installed image version
1312 * @external_ver: external image version
1313 * @status: MFUART loading status
1314 * @duration: MFUART loading time
1315*/
1316struct iwl_mfuart_load_notif {
1317 __le32 installed_ver;
1318 __le32 external_ver;
1319 __le32 status;
1320 __le32 duration;
1321} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
1322
1323/**
Johannes Berg8ca151b2013-01-24 14:25:36 +01001324 * struct iwl_set_calib_default_cmd - set default value for calibration.
1325 * ( SET_CALIB_DEFAULT_CMD = 0x8e )
1326 * @calib_index: the calibration to set value for
1327 * @length: of data
1328 * @data: the value to set for the calibration result
1329 */
1330struct iwl_set_calib_default_cmd {
1331 __le16 calib_index;
1332 __le16 length;
1333 u8 data[0];
1334} __packed; /* PHY_CALIB_OVERRIDE_VALUES_S */
1335
Emmanuel Grumbach51b6b9e2013-05-02 15:01:24 +03001336#define MAX_PORT_ID_NUM 2
Eliad Pellere59647e2013-11-28 14:08:50 +02001337#define MAX_MCAST_FILTERING_ADDRESSES 256
Emmanuel Grumbach51b6b9e2013-05-02 15:01:24 +03001338
1339/**
1340 * struct iwl_mcast_filter_cmd - configure multicast filter.
1341 * @filter_own: Set 1 to filter out multicast packets sent by station itself
1342 * @port_id: Multicast MAC addresses array specifier. This is a strange way
1343 * to identify network interface adopted in host-device IF.
1344 * It is used by FW as index in array of addresses. This array has
1345 * MAX_PORT_ID_NUM members.
1346 * @count: Number of MAC addresses in the array
1347 * @pass_all: Set 1 to pass all multicast packets.
1348 * @bssid: current association BSSID.
1349 * @addr_list: Place holder for array of MAC addresses.
1350 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
1351 */
1352struct iwl_mcast_filter_cmd {
1353 u8 filter_own;
1354 u8 port_id;
1355 u8 count;
1356 u8 pass_all;
1357 u8 bssid[6];
1358 u8 reserved[2];
1359 u8 addr_list[0];
1360} __packed; /* MCAST_FILTERING_CMD_API_S_VER_1 */
1361
Eliad Pellerc87163b2014-01-08 10:11:11 +02001362#define MAX_BCAST_FILTERS 8
1363#define MAX_BCAST_FILTER_ATTRS 2
1364
1365/**
1366 * enum iwl_mvm_bcast_filter_attr_offset - written by fw for each Rx packet
1367 * @BCAST_FILTER_OFFSET_PAYLOAD_START: offset is from payload start.
1368 * @BCAST_FILTER_OFFSET_IP_END: offset is from ip header end (i.e.
1369 * start of ip payload).
1370 */
1371enum iwl_mvm_bcast_filter_attr_offset {
1372 BCAST_FILTER_OFFSET_PAYLOAD_START = 0,
1373 BCAST_FILTER_OFFSET_IP_END = 1,
1374};
1375
1376/**
1377 * struct iwl_fw_bcast_filter_attr - broadcast filter attribute
1378 * @offset_type: &enum iwl_mvm_bcast_filter_attr_offset.
1379 * @offset: starting offset of this pattern.
1380 * @val: value to match - big endian (MSB is the first
1381 * byte to match from offset pos).
1382 * @mask: mask to match (big endian).
1383 */
1384struct iwl_fw_bcast_filter_attr {
1385 u8 offset_type;
1386 u8 offset;
1387 __le16 reserved1;
1388 __be32 val;
1389 __be32 mask;
1390} __packed; /* BCAST_FILTER_ATT_S_VER_1 */
1391
1392/**
1393 * enum iwl_mvm_bcast_filter_frame_type - filter frame type
1394 * @BCAST_FILTER_FRAME_TYPE_ALL: consider all frames.
1395 * @BCAST_FILTER_FRAME_TYPE_IPV4: consider only ipv4 frames
1396 */
1397enum iwl_mvm_bcast_filter_frame_type {
1398 BCAST_FILTER_FRAME_TYPE_ALL = 0,
1399 BCAST_FILTER_FRAME_TYPE_IPV4 = 1,
1400};
1401
1402/**
1403 * struct iwl_fw_bcast_filter - broadcast filter
1404 * @discard: discard frame (1) or let it pass (0).
1405 * @frame_type: &enum iwl_mvm_bcast_filter_frame_type.
1406 * @num_attrs: number of valid attributes in this filter.
1407 * @attrs: attributes of this filter. a filter is considered matched
1408 * only when all its attributes are matched (i.e. AND relationship)
1409 */
1410struct iwl_fw_bcast_filter {
1411 u8 discard;
1412 u8 frame_type;
1413 u8 num_attrs;
1414 u8 reserved1;
1415 struct iwl_fw_bcast_filter_attr attrs[MAX_BCAST_FILTER_ATTRS];
1416} __packed; /* BCAST_FILTER_S_VER_1 */
1417
1418/**
1419 * struct iwl_fw_bcast_mac - per-mac broadcast filtering configuration.
1420 * @default_discard: default action for this mac (discard (1) / pass (0)).
1421 * @attached_filters: bitmap of relevant filters for this mac.
1422 */
1423struct iwl_fw_bcast_mac {
1424 u8 default_discard;
1425 u8 reserved1;
1426 __le16 attached_filters;
1427} __packed; /* BCAST_MAC_CONTEXT_S_VER_1 */
1428
1429/**
1430 * struct iwl_bcast_filter_cmd - broadcast filtering configuration
1431 * @disable: enable (0) / disable (1)
1432 * @max_bcast_filters: max number of filters (MAX_BCAST_FILTERS)
1433 * @max_macs: max number of macs (NUM_MAC_INDEX_DRIVER)
1434 * @filters: broadcast filters
1435 * @macs: broadcast filtering configuration per-mac
1436 */
1437struct iwl_bcast_filter_cmd {
1438 u8 disable;
1439 u8 max_bcast_filters;
1440 u8 max_macs;
1441 u8 reserved1;
1442 struct iwl_fw_bcast_filter filters[MAX_BCAST_FILTERS];
1443 struct iwl_fw_bcast_mac macs[NUM_MAC_INDEX_DRIVER];
1444} __packed; /* BCAST_FILTERING_HCMD_API_S_VER_1 */
1445
Matti Gottlieba2d79c52014-08-25 14:41:23 +03001446/*
1447 * enum iwl_mvm_marker_id - maker ids
1448 *
1449 * The ids for different type of markers to insert into the usniffer logs
1450 */
1451enum iwl_mvm_marker_id {
1452 MARKER_ID_TX_FRAME_LATENCY = 1,
1453}; /* MARKER_ID_API_E_VER_1 */
1454
1455/**
1456 * struct iwl_mvm_marker - mark info into the usniffer logs
1457 *
1458 * (MARKER_CMD = 0xcb)
1459 *
1460 * Mark the UTC time stamp into the usniffer logs together with additional
1461 * metadata, so the usniffer output can be parsed.
1462 * In the command response the ucode will return the GP2 time.
1463 *
1464 * @dw_len: The amount of dwords following this byte including this byte.
1465 * @marker_id: A unique marker id (iwl_mvm_marker_id).
1466 * @reserved: reserved.
1467 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
1468 * @metadata: additional meta data that will be written to the unsiffer log
1469 */
1470struct iwl_mvm_marker {
1471 u8 dwLen;
1472 u8 markerId;
1473 __le16 reserved;
1474 __le64 timestamp;
1475 __le32 metadata[0];
1476} __packed; /* MARKER_API_S_VER_1 */
1477
Matti Gottlieb0becb372015-05-31 09:18:30 +03001478/*
1479 * enum iwl_dc2dc_config_id - flag ids
1480 *
1481 * Ids of dc2dc configuration flags
1482 */
1483enum iwl_dc2dc_config_id {
1484 DCDC_LOW_POWER_MODE_MSK_SET = 0x1, /* not used */
1485 DCDC_FREQ_TUNE_SET = 0x2,
1486}; /* MARKER_ID_API_E_VER_1 */
1487
1488/**
1489 * struct iwl_dc2dc_config_cmd - configure dc2dc values
1490 *
1491 * (DC2DC_CONFIG_CMD = 0x83)
1492 *
1493 * Set/Get & configure dc2dc values.
1494 * The command always returns the current dc2dc values.
1495 *
1496 * @flags: set/get dc2dc
1497 * @enable_low_power_mode: not used.
1498 * @dc2dc_freq_tune0: frequency divider - digital domain
1499 * @dc2dc_freq_tune1: frequency divider - analog domain
1500 */
1501struct iwl_dc2dc_config_cmd {
1502 __le32 flags;
1503 __le32 enable_low_power_mode; /* not used */
1504 __le32 dc2dc_freq_tune0;
1505 __le32 dc2dc_freq_tune1;
1506} __packed; /* DC2DC_CONFIG_CMD_API_S_VER_1 */
1507
1508/**
1509 * struct iwl_dc2dc_config_resp - response for iwl_dc2dc_config_cmd
1510 *
1511 * Current dc2dc values returned by the FW.
1512 *
1513 * @dc2dc_freq_tune0: frequency divider - digital domain
1514 * @dc2dc_freq_tune1: frequency divider - analog domain
1515 */
1516struct iwl_dc2dc_config_resp {
1517 __le32 dc2dc_freq_tune0;
1518 __le32 dc2dc_freq_tune1;
1519} __packed; /* DC2DC_CONFIG_RESP_API_S_VER_1 */
1520
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001521/***********************************
1522 * Smart Fifo API
1523 ***********************************/
1524/* Smart Fifo state */
1525enum iwl_sf_state {
1526 SF_LONG_DELAY_ON = 0, /* should never be called by driver */
1527 SF_FULL_ON,
1528 SF_UNINIT,
1529 SF_INIT_OFF,
1530 SF_HW_NUM_STATES
1531};
1532
1533/* Smart Fifo possible scenario */
1534enum iwl_sf_scenario {
1535 SF_SCENARIO_SINGLE_UNICAST,
1536 SF_SCENARIO_AGG_UNICAST,
1537 SF_SCENARIO_MULTICAST,
1538 SF_SCENARIO_BA_RESP,
1539 SF_SCENARIO_TX_RESP,
1540 SF_NUM_SCENARIO
1541};
1542
1543#define SF_TRANSIENT_STATES_NUMBER 2 /* SF_LONG_DELAY_ON and SF_FULL_ON */
1544#define SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
1545
1546/* smart FIFO default values */
Emmanuel Grumbachb4c82ad2014-12-01 16:44:09 +02001547#define SF_W_MARK_SISO 6144
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001548#define SF_W_MARK_MIMO2 8192
1549#define SF_W_MARK_MIMO3 6144
1550#define SF_W_MARK_LEGACY 4096
1551#define SF_W_MARK_SCAN 4096
1552
Eran Hararyf4a3ee42015-02-08 13:58:50 +02001553/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
1554#define SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
1555#define SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1556#define SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
1557#define SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1558#define SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
1559#define SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1560#define SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
1561#define SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
1562#define SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
1563#define SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
1564
1565/* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001566#define SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1567#define SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1568#define SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1569#define SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1570#define SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
1571#define SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
1572#define SF_BA_IDLE_TIMER 320 /* 300 uSec */
1573#define SF_BA_AGING_TIMER 2016 /* 2 mSec */
1574#define SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
1575#define SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
1576
1577#define SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
1578
Eran Harary161bdb72014-07-27 08:03:06 +03001579#define SF_CFG_DUMMY_NOTIF_OFF BIT(16)
1580
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001581/**
1582 * Smart Fifo configuration command.
Emmanuel Grumbach86974bf2014-07-31 14:32:37 +03001583 * @state: smart fifo state, types listed in enum %iwl_sf_sate.
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001584 * @watermark: Minimum allowed availabe free space in RXF for transient state.
1585 * @long_delay_timeouts: aging and idle timer values for each scenario
1586 * in long delay state.
1587 * @full_on_timeouts: timer values for each scenario in full on state.
1588 */
1589struct iwl_sf_cfg_cmd {
Emmanuel Grumbach86974bf2014-07-31 14:32:37 +03001590 __le32 state;
Lilach Edelstein1f3b0ff2013-10-06 13:03:32 +02001591 __le32 watermark[SF_TRANSIENT_STATES_NUMBER];
1592 __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1593 __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1594} __packed; /* SF_CFG_API_S_VER_2 */
1595
Eran Harary8ba2d7a2015-02-08 11:41:43 +02001596/***********************************
1597 * Location Aware Regulatory (LAR) API - MCC updates
1598 ***********************************/
1599
1600/**
1601 * struct iwl_mcc_update_cmd - Request the device to update geographic
1602 * regulatory profile according to the given MCC (Mobile Country Code).
1603 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
1604 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
1605 * MCC in the cmd response will be the relevant MCC in the NVM.
1606 * @mcc: given mobile country code
1607 * @source_id: the source from where we got the MCC, see iwl_mcc_source
1608 * @reserved: reserved for alignment
1609 */
1610struct iwl_mcc_update_cmd {
1611 __le16 mcc;
1612 u8 source_id;
1613 u8 reserved;
1614} __packed; /* LAR_UPDATE_MCC_CMD_API_S */
1615
1616/**
1617 * iwl_mcc_update_resp - response to MCC_UPDATE_CMD.
1618 * Contains the new channel control profile map, if changed, and the new MCC
1619 * (mobile country code).
1620 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
Jonathan Doron47c8b152014-11-27 16:55:25 +02001621 * @status: see &enum iwl_mcc_update_status
Eran Harary8ba2d7a2015-02-08 11:41:43 +02001622 * @mcc: the new applied MCC
1623 * @cap: capabilities for all channels which matches the MCC
1624 * @source_id: the MCC source, see iwl_mcc_source
1625 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
1626 * channels, depending on platform)
1627 * @channels: channel control data map, DWORD for each channel. Only the first
1628 * 16bits are used.
1629 */
1630struct iwl_mcc_update_resp {
1631 __le32 status;
1632 __le16 mcc;
1633 u8 cap;
1634 u8 source_id;
1635 __le32 n_channels;
1636 __le32 channels[0];
1637} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S */
1638
1639/**
1640 * struct iwl_mcc_chub_notif - chub notifies of mcc change
1641 * (MCC_CHUB_UPDATE_CMD = 0xc9)
1642 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
1643 * the cellular and connectivity cores that gets updates of the mcc, and
1644 * notifies the ucode directly of any mcc change.
1645 * The ucode requests the driver to request the device to update geographic
1646 * regulatory profile according to the given MCC (Mobile Country Code).
1647 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
1648 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
1649 * MCC in the cmd response will be the relevant MCC in the NVM.
1650 * @mcc: given mobile country code
1651 * @source_id: identity of the change originator, see iwl_mcc_source
1652 * @reserved1: reserved for alignment
1653 */
1654struct iwl_mcc_chub_notif {
1655 u16 mcc;
1656 u8 source_id;
1657 u8 reserved1;
1658} __packed; /* LAR_MCC_NOTIFY_S */
1659
1660enum iwl_mcc_update_status {
1661 MCC_RESP_NEW_CHAN_PROFILE,
1662 MCC_RESP_SAME_CHAN_PROFILE,
1663 MCC_RESP_INVALID,
1664 MCC_RESP_NVM_DISABLED,
1665 MCC_RESP_ILLEGAL,
1666 MCC_RESP_LOW_PRIORITY,
1667};
1668
1669enum iwl_mcc_source {
1670 MCC_SOURCE_OLD_FW = 0,
1671 MCC_SOURCE_ME = 1,
1672 MCC_SOURCE_BIOS = 2,
1673 MCC_SOURCE_3G_LTE_HOST = 3,
1674 MCC_SOURCE_3G_LTE_DEVICE = 4,
1675 MCC_SOURCE_WIFI = 5,
1676 MCC_SOURCE_RESERVED = 6,
1677 MCC_SOURCE_DEFAULT = 7,
1678 MCC_SOURCE_UNINITIALIZED = 8,
1679 MCC_SOURCE_GET_CURRENT = 0x10
1680};
1681
Luciano Coelhoa0a09242014-09-04 12:29:15 +03001682/* DTS measurements */
1683
1684enum iwl_dts_measurement_flags {
1685 DTS_TRIGGER_CMD_FLAGS_TEMP = BIT(0),
1686 DTS_TRIGGER_CMD_FLAGS_VOLT = BIT(1),
1687};
1688
1689/**
1690 * iwl_dts_measurement_cmd - request DTS temperature and/or voltage measurements
1691 *
1692 * @flags: indicates which measurements we want as specified in &enum
1693 * iwl_dts_measurement_flags
1694 */
1695struct iwl_dts_measurement_cmd {
1696 __le32 flags;
1697} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_CMD_S */
1698
1699/**
1700 * iwl_dts_measurement_notif - notification received with the measurements
1701 *
1702 * @temp: the measured temperature
1703 * @voltage: the measured voltage
1704 */
1705struct iwl_dts_measurement_notif {
1706 __le32 temp;
1707 __le32 voltage;
1708} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S */
1709
Arik Nemtsov77c5d7e2014-09-11 13:10:08 +03001710/***********************************
1711 * TDLS API
1712 ***********************************/
1713
1714/* Type of TDLS request */
1715enum iwl_tdls_channel_switch_type {
1716 TDLS_SEND_CHAN_SW_REQ = 0,
1717 TDLS_SEND_CHAN_SW_RESP_AND_MOVE_CH,
1718 TDLS_MOVE_CH,
1719}; /* TDLS_STA_CHANNEL_SWITCH_CMD_TYPE_API_E_VER_1 */
1720
1721/**
1722 * Switch timing sub-element in a TDLS channel-switch command
1723 * @frame_timestamp: GP2 timestamp of channel-switch request/response packet
1724 * received from peer
1725 * @max_offchan_duration: What amount of microseconds out of a DTIM is given
1726 * to the TDLS off-channel communication. For instance if the DTIM is
1727 * 200TU and the TDLS peer is to be given 25% of the time, the value
1728 * given will be 50TU, or 50 * 1024 if translated into microseconds.
1729 * @switch_time: switch time the peer sent in its channel switch timing IE
1730 * @switch_timout: switch timeout the peer sent in its channel switch timing IE
1731 */
1732struct iwl_tdls_channel_switch_timing {
1733 __le32 frame_timestamp; /* GP2 time of peer packet Rx */
1734 __le32 max_offchan_duration; /* given in micro-seconds */
1735 __le32 switch_time; /* given in micro-seconds */
1736 __le32 switch_timeout; /* given in micro-seconds */
1737} __packed; /* TDLS_STA_CHANNEL_SWITCH_TIMING_DATA_API_S_VER_1 */
1738
1739#define IWL_TDLS_CH_SW_FRAME_MAX_SIZE 200
1740
1741/**
1742 * TDLS channel switch frame template
1743 *
1744 * A template representing a TDLS channel-switch request or response frame
1745 *
1746 * @switch_time_offset: offset to the channel switch timing IE in the template
1747 * @tx_cmd: Tx parameters for the frame
1748 * @data: frame data
1749 */
1750struct iwl_tdls_channel_switch_frame {
1751 __le32 switch_time_offset;
1752 struct iwl_tx_cmd tx_cmd;
1753 u8 data[IWL_TDLS_CH_SW_FRAME_MAX_SIZE];
1754} __packed; /* TDLS_STA_CHANNEL_SWITCH_FRAME_API_S_VER_1 */
1755
1756/**
1757 * TDLS channel switch command
1758 *
1759 * The command is sent to initiate a channel switch and also in response to
1760 * incoming TDLS channel-switch request/response packets from remote peers.
1761 *
1762 * @switch_type: see &enum iwl_tdls_channel_switch_type
1763 * @peer_sta_id: station id of TDLS peer
1764 * @ci: channel we switch to
1765 * @timing: timing related data for command
1766 * @frame: channel-switch request/response template, depending to switch_type
1767 */
1768struct iwl_tdls_channel_switch_cmd {
1769 u8 switch_type;
1770 __le32 peer_sta_id;
1771 struct iwl_fw_channel_info ci;
1772 struct iwl_tdls_channel_switch_timing timing;
1773 struct iwl_tdls_channel_switch_frame frame;
1774} __packed; /* TDLS_STA_CHANNEL_SWITCH_CMD_API_S_VER_1 */
1775
1776/**
1777 * TDLS channel switch start notification
1778 *
1779 * @status: non-zero on success
1780 * @offchannel_duration: duration given in microseconds
1781 * @sta_id: peer currently performing the channel-switch with
1782 */
1783struct iwl_tdls_channel_switch_notif {
1784 __le32 status;
1785 __le32 offchannel_duration;
1786 __le32 sta_id;
1787} __packed; /* TDLS_STA_CHANNEL_SWITCH_NTFY_API_S_VER_1 */
1788
Arik Nemtsov307e4722014-09-15 18:48:59 +03001789/**
1790 * TDLS station info
1791 *
1792 * @sta_id: station id of the TDLS peer
1793 * @tx_to_peer_tid: TID reserved vs. the peer for FW based Tx
1794 * @tx_to_peer_ssn: initial SSN the FW should use for Tx on its TID vs the peer
1795 * @is_initiator: 1 if the peer is the TDLS link initiator, 0 otherwise
1796 */
1797struct iwl_tdls_sta_info {
1798 u8 sta_id;
1799 u8 tx_to_peer_tid;
1800 __le16 tx_to_peer_ssn;
1801 __le32 is_initiator;
1802} __packed; /* TDLS_STA_INFO_VER_1 */
1803
1804/**
1805 * TDLS basic config command
1806 *
1807 * @id_and_color: MAC id and color being configured
1808 * @tdls_peer_count: amount of currently connected TDLS peers
1809 * @tx_to_ap_tid: TID reverved vs. the AP for FW based Tx
1810 * @tx_to_ap_ssn: initial SSN the FW should use for Tx on its TID vs. the AP
1811 * @sta_info: per-station info. Only the first tdls_peer_count entries are set
1812 * @pti_req_data_offset: offset of network-level data for the PTI template
1813 * @pti_req_tx_cmd: Tx parameters for PTI request template
1814 * @pti_req_template: PTI request template data
1815 */
1816struct iwl_tdls_config_cmd {
1817 __le32 id_and_color; /* mac id and color */
1818 u8 tdls_peer_count;
1819 u8 tx_to_ap_tid;
1820 __le16 tx_to_ap_ssn;
1821 struct iwl_tdls_sta_info sta_info[IWL_MVM_TDLS_STA_COUNT];
1822
1823 __le32 pti_req_data_offset;
1824 struct iwl_tx_cmd pti_req_tx_cmd;
1825 u8 pti_req_template[0];
1826} __packed; /* TDLS_CONFIG_CMD_API_S_VER_1 */
1827
1828/**
1829 * TDLS per-station config information from FW
1830 *
1831 * @sta_id: station id of the TDLS peer
1832 * @tx_to_peer_last_seq: last sequence number used by FW during FW-based Tx to
1833 * the peer
1834 */
1835struct iwl_tdls_config_sta_info_res {
1836 __le16 sta_id;
1837 __le16 tx_to_peer_last_seq;
1838} __packed; /* TDLS_STA_INFO_RSP_VER_1 */
1839
1840/**
1841 * TDLS config information from FW
1842 *
1843 * @tx_to_ap_last_seq: last sequence number used by FW during FW-based Tx to AP
1844 * @sta_info: per-station TDLS config information
1845 */
1846struct iwl_tdls_config_res {
1847 __le32 tx_to_ap_last_seq;
1848 struct iwl_tdls_config_sta_info_res sta_info[IWL_MVM_TDLS_STA_COUNT];
1849} __packed; /* TDLS_CONFIG_RSP_API_S_VER_1 */
1850
Liad Kaufman04fd2c22014-12-15 17:54:16 +02001851#define TX_FIFO_MAX_NUM 8
1852#define RX_FIFO_MAX_NUM 2
1853
1854/**
1855 * Shared memory configuration information from the FW
1856 *
1857 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
1858 * accessible)
1859 * @shared_mem_size: shared memory size
1860 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
1861 * 0x0 as accessible only via DBGM RDAT)
1862 * @sample_buff_size: internal sample buff size
1863 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
1864 * 8000 HW set to 0x0 as not accessible)
1865 * @txfifo_size: size of TXF0 ... TXF7
1866 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
1867 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
1868 * when paging is not supported this should be 0
1869 * @page_buff_size: size of %page_buff_addr
1870 */
1871struct iwl_shared_mem_cfg {
1872 __le32 shared_mem_addr;
1873 __le32 shared_mem_size;
1874 __le32 sample_buff_addr;
1875 __le32 sample_buff_size;
1876 __le32 txfifo_addr;
1877 __le32 txfifo_size[TX_FIFO_MAX_NUM];
1878 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
1879 __le32 page_buff_addr;
1880 __le32 page_buff_size;
1881} __packed; /* SHARED_MEM_ALLOC_API_S_VER_1 */
1882
Johannes Berg8ca151b2013-01-24 14:25:36 +01001883#endif /* __fw_api_h__ */