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Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -07001/*
2 * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
Enric Balletbo i Serra7c128022018-06-06 17:54:06 +020011#include <dt-bindings/pwm/pwm.h>
Enric Balletbo i Serra98435322018-06-06 17:54:10 +020012#include <dt-bindings/interrupt-controller/irq.h>
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070013
14/ {
15 model = "Toby Churchill SL50 Series";
16 compatible = "tcl,am335x-sl50", "ti,am33xx";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&dcdc2_reg>;
21 };
22 };
23
Javier Martinez Canillas278cb792016-08-31 12:35:30 +020024 memory@80000000 {
Javier Martinez Canillas35852c62016-08-31 12:35:15 +020025 device_type = "memory";
26 reg = <0x80000000 0x20000000>; /* 512 MB */
27 };
28
Enric Balletbo i Serra01c37be42016-01-16 11:51:12 +010029 chosen {
30 stdout-path = &uart0;
31 };
32
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070033 leds {
34 compatible = "gpio-leds";
35 pinctrl-names = "default";
36 pinctrl-0 = <&led_pins>;
37
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040038 led0 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070039 label = "sl50:green:usr0";
40 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
41 default-state = "off";
42 };
43
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040044 led1 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070045 label = "sl50:red:usr1";
46 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
47 default-state = "off";
48 };
49
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040050 led2 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070051 label = "sl50:green:usr2";
52 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
53 default-state = "off";
54 };
55
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040056 led3 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070057 label = "sl50:red:usr3";
58 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
59 default-state = "off";
60 };
61 };
62
63 backlight0: disp0 {
64 compatible = "pwm-backlight";
Enric Balletbo i Serra7c128022018-06-06 17:54:06 +020065 pinctrl-names = "default";
66 pinctrl-0 = <&backlight0_pins>;
67 pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>;
68 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
69 10 11 12 13 14 15 16 17 18 19
70 20 21 22 23 24 25 26 27 28 29
71 30 31 32 33 34 35 36 37 38 39
72 40 41 42 43 44 45 46 47 48 49
73 50 51 52 53 54 55 56 57 58 59
74 60 61 62 63 64 65 66 67 68 69
75 70 71 72 73 74 75 76 77 78 79
76 80 81 82 83 84 85 86 87 88 89
77 90 91 92 93 94 95 96 97 98 99
78 100>;
79 default-brightness-level = <50>;
80 enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
81 power-supply = <&vdd_sys_reg>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070082 };
83
84 backlight1: disp1 {
85 compatible = "pwm-backlight";
Enric Balletbo i Serra7c128022018-06-06 17:54:06 +020086 pinctrl-names = "default";
87 pinctrl-0 = <&backlight1_pins>;
88 pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>;
89 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
90 10 11 12 13 14 15 16 17 18 19
91 20 21 22 23 24 25 26 27 28 29
92 30 31 32 33 34 35 36 37 38 39
93 40 41 42 43 44 45 46 47 48 49
94 50 51 52 53 54 55 56 57 58 59
95 60 61 62 63 64 65 66 67 68 69
96 70 71 72 73 74 75 76 77 78 79
97 80 81 82 83 84 85 86 87 88 89
98 90 91 92 93 94 95 96 97 98 99
99 100>;
100 default-brightness-level = <50>;
101 enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
102 power-supply = <&vdd_sys_reg>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700103 };
104
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100105 clocks {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 /* audio external oscillator */
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200111 audio_mclk_fixed: oscillator@0 {
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <24576000>; /* 24.576MHz */
115 };
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200116
117 audio_mclk: audio_mclk_gate@0 {
118 compatible = "gpio-gate-clock";
119 #clock-cells = <0>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&audio_mclk_pins>;
122 clocks = <&audio_mclk_fixed>;
123 enable-gpios = <&gpio1 27 0>;
124 };
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100125 };
126
Enric Balletbo i Serra79932e72018-06-06 17:54:08 +0200127 panel: lcd_panel {
128 compatible = "ti,tilcdc,panel";
129 pinctrl-names = "default";
130 pinctrl-0 = <&lcd_pins>;
131
132 panel-info {
133 ac-bias = <255>;
134 ac-bias-intrpt = <0>;
135 dma-burst-sz = <16>;
136 bpp = <16>;
137 fdd = <0x80>;
138 tft-alt-mode = <0>;
139 mono-8bit-mode = <0>;
140 sync-edge = <0>;
141 sync-ctrl = <1>;
142 raster-order = <0>;
143 fifo-th = <0>;
144 };
145
146 display-timings {
147 native-mode = <&timing0>;
148 timing0: 960x128 {
149 clock-frequency = <18000000>;
150 hactive = <960>;
151 vactive = <272>;
152
153 hback-porch = <40>;
154 hfront-porch = <16>;
155 hsync-len = <24>;
156 hsync-active = <0>;
157
158 vback-porch = <3>;
159 vfront-porch = <8>;
160 vsync-len = <4>;
161 vsync-active = <0>;
162 };
163 };
164 };
165
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700166 sound {
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200167 compatible = "audio-graph-card";
168 label = "sound-card";
169 pinctrl-names = "default";
170 pinctrl-0 = <&audio_pa_pins>;
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100171
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200172 widgets = "Headphone", "Headphone Jack",
173 "Speaker", "Speaker External",
174 "Line", "Line In",
175 "Microphone", "Microphone Jack";
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100176
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200177 routing = "Headphone Jack", "HPLOUT",
178 "Headphone Jack", "HPROUT",
179 "Amplifier", "MONO_LOUT",
180 "Speaker External", "Amplifier",
181 "LINE1R", "Line In",
182 "LINE1L", "Line In",
183 "MIC3L", "Microphone Jack",
184 "MIC3R", "Microphone Jack",
185 "Microphone Jack", "Mic Bias";
186
187 dais = <&cpu_port>;
188
189 pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700190 };
191
192 emmc_pwrseq: pwrseq@0 {
193 compatible = "mmc-pwrseq-emmc";
194 pinctrl-names = "default";
195 pinctrl-0 = <&emmc_pwrseq_pins>;
196 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
197 };
198
Enric Balletbo i Serra7c128022018-06-06 17:54:06 +0200199 vdd_sys_reg: regulator@0 {
200 compatible = "regulator-fixed";
201 regulator-name = "vdd_sys_reg";
202 regulator-min-microvolt = <5000000>;
203 regulator-max-microvolt = <5000000>;
204 regulator-always-on;
205 };
206
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -0400207 vmmcsd_fixed: fixedregulator0 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700208 compatible = "regulator-fixed";
209 regulator-name = "vmmcsd_fixed";
210 regulator-min-microvolt = <3300000>;
211 regulator-max-microvolt = <3300000>;
212 };
213};
214
215&am33xx_pinmux {
216 pinctrl-names = "default";
217 pinctrl-0 = <&lwb_pins>;
218
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200219 audio_pins: pinmux_audio_pins {
220 pinctrl-single,pins = <
221 AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
222 AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
223 AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
224 AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
225 AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */
226 >;
227 };
228
229 audio_pa_pins: pinmux_audio_pa_pins {
230 pinctrl-single,pins = <
231 AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */
232 >;
233 };
234
235 audio_mclk_pins: pinmux_audio_mclk_pins {
236 pinctrl-single,pins = <
237 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
238 >;
239 };
240
Enric Balletbo i Serra7c128022018-06-06 17:54:06 +0200241 backlight0_pins: pinmux_backlight0_pins {
242 pinctrl-single,pins = <
243 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
244 >;
245 };
246
247 backlight1_pins: pinmux_backlight1_pins {
248 pinctrl-single,pins = <
249 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */
250 >;
251 };
252
Enric Balletbo i Serra79932e72018-06-06 17:54:08 +0200253 lcd_pins: pinmux_lcd_pins {
254 pinctrl-single,pins = <
255 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
256 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
257 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
258 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
259 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
260 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
261 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
262 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
263 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
264 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
265 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
266 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
267 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
268 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
269 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
270 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
271 AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
272 AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
273 AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
274 AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
275 >;
276 };
277
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700278 led_pins: pinmux_led_pins {
279 pinctrl-single,pins = <
280 AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
281 AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */
282 AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */
283 AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */
284 >;
285 };
286
287 uart0_pins: pinmux_uart0_pins {
288 pinctrl-single,pins = <
289 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
290 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
291 >;
292 };
293
Enric Balletbo i Serrae9c7beb2017-01-16 17:57:32 +0100294 uart1_pins: pinmux_uart1_pins {
295 pinctrl-single,pins = <
296 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
297 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
298 >;
299 };
300
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700301 uart4_pins: pinmux_uart4_pins {
302 pinctrl-single,pins = <
303 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */
304 AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */
305 >;
306 };
307
308 i2c0_pins: pinmux_i2c0_pins {
309 pinctrl-single,pins = <
310 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
311 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
312 >;
313 };
314
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700315 i2c2_pins: pinmux_i2c2_pins {
316 pinctrl-single,pins = <
317 AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
318 AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
319 >;
320 };
321
322 cpsw_default: cpsw_default {
323 pinctrl-single,pins = <
324 /* Slave 1 */
325 AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
326 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
327 AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
328 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
329 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
330 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
331 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
332 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
333 AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
334 AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
335 AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
336 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
337 AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
338 >;
339 };
340
341 cpsw_sleep: cpsw_sleep {
342 pinctrl-single,pins = <
343 /* Slave 1 reset value */
344 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
345 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
346 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
347 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
348 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
349 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
350 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
351 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
352 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
353 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
354 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
355 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
356 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
357 >;
358 };
359
360 davinci_mdio_default: davinci_mdio_default {
361 pinctrl-single,pins = <
362 /* MDIO */
363 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
364 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
Enric Balletbo i Serra25d2ee92018-06-06 17:54:07 +0200365 /* Ethernet */
366 AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700367 >;
368 };
369
370 davinci_mdio_sleep: davinci_mdio_sleep {
371 pinctrl-single,pins = <
372 /* MDIO reset value */
373 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
374 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
375 >;
376 };
377
378 mmc1_pins: pinmux_mmc1_pins {
379 pinctrl-single,pins = <
Enric Balletbo i Serra56b74ed2017-05-22 11:01:52 +0200380 AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700381 >;
382 };
383
384 emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
385 pinctrl-single,pins = <
386 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */
387 >;
388 };
389
390 emmc_pins: pinmux_emmc_pins {
391 pinctrl-single,pins = <
392 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
393 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
394 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
395 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
396 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
397 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
398 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
399 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
400 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
401 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
402 >;
403 };
404
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700405 ehrpwm1_pins: pinmux_ehrpwm1a_pins {
406 pinctrl-single,pins = <
407 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */
408 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */
409 >;
410 };
411
Enric Balletbo i Serra98435322018-06-06 17:54:10 +0200412 rtc0_irq_pins: pinmux_rtc0_irq_pins {
413 pinctrl-single,pins = <
414 AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad9.gpio0_23 */
415 >;
416 };
417
Enric Balletbo i Serraf37f9112017-01-16 17:57:33 +0100418 spi0_pins: pinmux_spi0_pins {
419 pinctrl-single,pins = <
420 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */
421 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */
422 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */
423 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
424 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
425 >;
426 };
427
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700428 lwb_pins: pinmux_lwb_pins {
429 pinctrl-single,pins = <
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700430 AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */
431 AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700432 AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700433 /* PDI Bus - Battery system */
434 AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */
435 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */
436 >;
437 };
438};
439
440&i2c0 {
441 status = "okay";
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c0_pins>;
444
445 clock-frequency = <400000>;
446
447 tps: tps@24 {
448 reg = <0x24>;
449 };
450
Enric Balletbo i Serra98435322018-06-06 17:54:10 +0200451 rtc0: rtc@68 {
452 compatible = "dallas,ds1339";
453 pinctrl-names = "default";
454 pinctrl-0 = <&rtc0_irq_pins>;
455 interrupt-parent = <&gpio0>;
456 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */
457 wakeup-source;
458 trickle-resistor-ohms = <2000>;
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100459 reg = <0x68>;
460 };
461
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700462 eeprom: eeprom@50 {
Javier Martinez Canillas05e7d622017-05-23 15:34:31 +0200463 compatible = "atmel,24c256";
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700464 reg = <0x50>;
465 };
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100466
Enric Balletbo i Serra4340f9d2017-01-16 17:57:35 +0100467 gpio_exp: mcp23017@20 {
468 compatible = "microchip,mcp23017";
469 reg = <0x20>;
470 };
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100471
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700472};
473
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700474&i2c2 {
475 status = "okay";
476 pinctrl-names = "default";
477 pinctrl-0 = <&i2c2_pins>;
478
479 clock-frequency = <400000>;
480
481 audio_codec: tlv320aic3106@1b {
482 status = "okay";
483 compatible = "ti,tlv320aic3106";
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200484 #sound-dai-cells = <0>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700485 reg = <0x1b>;
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200486 ai3x-micbias-vg = <2>; /* 2.5V */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700487
488 AVDD-supply = <&ldo4_reg>;
489 IOVDD-supply = <&ldo4_reg>;
490 DRVDD-supply = <&ldo4_reg>;
491 DVDD-supply = <&ldo3_reg>;
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200492
493 codec_port: port {
494 codec_endpoint: endpoint {
495 remote-endpoint = <&cpu_endpoint>;
496 clocks = <&audio_mclk>;
497 };
498 };
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700499 };
Enric Balletbo i Serra885658f2017-01-16 17:57:36 +0100500
501 /* Ambient Light Sensor */
502 als: isl29023@44 {
503 compatible = "isil,isl29023";
504 reg = <0x44>;
505 };
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700506};
507
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100508&rtc {
509 status = "disabled";
510};
511
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700512&usb {
513 status = "okay";
514};
515
516&usb_ctrl_mod {
517 status = "okay";
518};
519
520&usb0_phy {
521 status = "okay";
522};
523
524&usb1_phy {
525 status = "okay";
526};
527
528&usb0 {
529 status = "okay";
Enric Balletbo i Serraf9d1dec2018-06-06 17:54:09 +0200530 dr_mode = "otg";
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700531};
532
533&usb1 {
534 status = "okay";
535 dr_mode = "host";
536};
537
538&cppi41dma {
539 status = "okay";
540};
541
542&mmc1 {
543 status = "okay";
544 pinctrl-names = "default";
545 pinctrl-0 = <&mmc1_pins>;
546 bus-width = <4>;
Enric Balletbo i Serra56b74ed2017-05-22 11:01:52 +0200547 cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700548 vmmc-supply = <&vmmcsd_fixed>;
549};
550
551&mmc2 {
552 status = "okay";
553 pinctrl-names = "default";
554 pinctrl-0 = <&emmc_pins>;
555 bus-width = <8>;
556 vmmc-supply = <&vmmcsd_fixed>;
557 mmc-pwrseq = <&emmc_pwrseq>;
558};
559
560&mcasp0 {
561 status = "okay";
562 pinctrl-names = "default";
563 pinctrl-0 = <&audio_pins>;
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200564 #sound-dai-cells = <0>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700565 op-mode = <0>; /* MCASP_ISS_MODE */
566 tdm-slots = <2>;
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200567 /* 4 serializers */
568 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
569 0 0 1 2
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700570 >;
Enric Balletbo i Serrae5f89db2018-06-06 17:54:11 +0200571 tx-num-evt = <32>;
572 rx-num-evt = <32>;
573
574 cpu_port: port {
575 cpu_endpoint: endpoint {
576 remote-endpoint = <&codec_endpoint>;
577
578 dai-format = "dsp_b";
579 bitclock-master = <&codec_port>;
580 frame-master = <&codec_port>;
581 bitclock-inversion;
582 clocks = <&audio_mclk>;
583 };
584 };
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700585};
586
587&uart0 {
588 status = "okay";
589 pinctrl-names = "default";
590 pinctrl-0 = <&uart0_pins>;
591};
592
Enric Balletbo i Serrae9c7beb2017-01-16 17:57:32 +0100593&uart1 {
594 status = "okay";
595 pinctrl-names = "default";
596 pinctrl-0 = <&uart1_pins>;
597};
598
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700599&uart4 {
600 status = "okay";
601 pinctrl-names = "default";
602 pinctrl-0 = <&uart4_pins>;
603};
604
Enric Balletbo i Serraf37f9112017-01-16 17:57:33 +0100605&spi0 {
606 status = "okay";
607 pinctrl-names = "default";
608 pinctrl-0 = <&spi0_pins>;
609
610 flash: n25q032@1 {
611 #address-cells = <1>;
612 #size-cells = <1>;
613 compatible = "micron,n25q032";
614 reg = <1>;
615 spi-max-frequency = <5000000>;
616 };
617};
618
Peter Ujfalusie327b3f2016-02-19 16:12:19 +0200619#include "tps65217.dtsi"
620
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700621&tps {
622 ti,pmic-shutdown-controller;
623
624 interrupt-parent = <&intc>;
625 interrupts = <7>; /* NNMI */
626
627 regulators {
628 dcdc1_reg: regulator@0 {
629 /* VDDS_DDR */
630 regulator-min-microvolt = <1500000>;
631 regulator-max-microvolt = <1500000>;
632 regulator-always-on;
633 };
634
635 dcdc2_reg: regulator@1 {
636 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
637 regulator-name = "vdd_mpu";
638 regulator-min-microvolt = <925000>;
639 regulator-max-microvolt = <1325000>;
640 regulator-boot-on;
641 regulator-always-on;
642 };
643
644 dcdc3_reg: regulator@2 {
645 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
646 regulator-name = "vdd_core";
647 regulator-min-microvolt = <925000>;
648 regulator-max-microvolt = <1150000>;
649 regulator-boot-on;
650 regulator-always-on;
651 };
652
653 ldo1_reg: regulator@3 {
654 /* VRTC / VIO / VDDS*/
655 regulator-always-on;
656 regulator-min-microvolt = <1800000>;
657 regulator-max-microvolt = <1800000>;
658 };
659
660 ldo2_reg: regulator@4 {
661 /* VDD_3V3AUX */
662 regulator-always-on;
663 regulator-min-microvolt = <3300000>;
664 regulator-max-microvolt = <3300000>;
665 };
666
667 ldo3_reg: regulator@5 {
668 /* VDD_1V8 */
669 regulator-min-microvolt = <1800000>;
670 regulator-max-microvolt = <1800000>;
671 regulator-always-on;
672 };
673
674 ldo4_reg: regulator@6 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700675 /* VDD_3V3A */
676 regulator-min-microvolt = <3300000>;
677 regulator-max-microvolt = <3300000>;
678 regulator-always-on;
679 };
680 };
681};
682
683&cpsw_emac0 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700684 phy-mode = "mii";
Enric Balletbo i Serra25d2ee92018-06-06 17:54:07 +0200685 phy-handle = <&ethphy0>;
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700686};
687
688&mac {
689 status = "okay";
690 pinctrl-names = "default", "sleep";
691 pinctrl-0 = <&cpsw_default>;
692 pinctrl-1 = <&cpsw_sleep>;
693};
694
695&davinci_mdio {
696 status = "okay";
697 pinctrl-names = "default", "sleep";
698 pinctrl-0 = <&davinci_mdio_default>;
699 pinctrl-1 = <&davinci_mdio_sleep>;
Enric Balletbo i Serra25d2ee92018-06-06 17:54:07 +0200700 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
701 reset-delay-us = <100>; /* PHY datasheet states 100us min */
702
703 ethphy0: ethernet-phy@0 {
704 reg = <0>;
705 };
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700706};
707
708&sham {
709 status = "okay";
710};
711
712&aes {
713 status = "okay";
714};
715
716&epwmss1 {
717 status = "okay";
718};
719
720&ehrpwm1 {
721 status = "okay";
722 pinctrl-names = "default";
723 pinctrl-0 = <&ehrpwm1_pins>;
724};
Enric Balletbo i Serra79932e72018-06-06 17:54:08 +0200725
726&lcdc {
727 status = "okay";
728};