blob: 8b9c8c0695df9902ab97e79702b3b8e2201c2c8b [file] [log] [blame]
Stefan Agnera67970a2016-06-26 01:47:53 -07001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "imx7s.dtsi"
Andrey Smirnova816d572017-05-15 07:53:04 -070045#include <dt-bindings/reset/imx7-reset.h>
Stefan Agnera67970a2016-06-26 01:47:53 -070046
47/ {
48 cpus {
Stefan Agnerf5bd51b2016-08-11 17:11:06 -070049 cpu0: cpu@0 {
50 operating-points = <
51 /* KHz uV */
52 996000 1075000
53 792000 975000
54 >;
Stefan Agner1c4e2a12016-08-11 17:11:07 -070055 clock-frequency = <996000000>;
Stefan Agnerf5bd51b2016-08-11 17:11:06 -070056 };
57
Stefan Agnera67970a2016-06-26 01:47:53 -070058 cpu1: cpu@1 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <1>;
Stefan Agner1c4e2a12016-08-11 17:11:07 -070062 clock-frequency = <996000000>;
Stefan Agnera67970a2016-06-26 01:47:53 -070063 };
64 };
65
Stefan Agner974a3ab2016-07-25 23:42:35 -070066 soc {
67 etm@3007d000 {
68 compatible = "arm,coresight-etm3x", "arm,primecell";
69 reg = <0x3007d000 0x1000>;
Stefan Agnera67970a2016-06-26 01:47:53 -070070
Stefan Agner974a3ab2016-07-25 23:42:35 -070071 /*
72 * System will hang if added nosmp in kernel command line
73 * without arm,primecell-periphid because amba bus try to
74 * read id and core1 power off at this time.
75 */
76 arm,primecell-periphid = <0xbb956>;
77 cpu = <&cpu1>;
78 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
79 clock-names = "apb_pclk";
Stefan Agnera67970a2016-06-26 01:47:53 -070080
Stefan Agner974a3ab2016-07-25 23:42:35 -070081 port {
82 etm1_out_port: endpoint {
83 remote-endpoint = <&ca_funnel_in_port1>;
84 };
Stefan Agnera67970a2016-06-26 01:47:53 -070085 };
86 };
87 };
88};
89
90&aips3 {
91 usbotg2: usb@30b20000 {
92 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
93 reg = <0x30b20000 0x200>;
94 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&clks IMX7D_USB_CTRL_CLK>;
96 fsl,usbphy = <&usbphynop2>;
97 fsl,usbmisc = <&usbmisc2 0>;
98 phy-clkgate-delay-us = <400>;
99 status = "disabled";
100 };
101
102 usbmisc2: usbmisc@30b20200 {
103 #index-cells = <1>;
104 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
105 reg = <0x30b20200 0x200>;
106 };
107
108 usbphynop2: usbphynop2 {
109 compatible = "usb-nop-xceiv";
110 clocks = <&clks IMX7D_USB_PHY2_CLK>;
111 clock-names = "main_clk";
112 };
113
114 fec2: ethernet@30bf0000 {
115 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
116 reg = <0x30bf0000 0x10000>;
Troy Kiskye94a2302017-11-03 10:29:58 -0700117 interrupt-names = "int0", "int1", "int2", "pps";
118 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
Stefan Agnera67970a2016-06-26 01:47:53 -0700120 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
Troy Kiskye94a2302017-11-03 10:29:58 -0700121 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
Stefan Agnera67970a2016-06-26 01:47:53 -0700122 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
123 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
124 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
125 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
126 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
127 clock-names = "ipg", "ahb", "ptp",
128 "enet_clk_ref", "enet_out";
129 fsl,num-tx-queues=<3>;
130 fsl,num-rx-queues=<3>;
131 status = "disabled";
132 };
Andrey Smirnova816d572017-05-15 07:53:04 -0700133
134 pcie: pcie@0x33800000 {
135 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
136 reg = <0x33800000 0x4000>,
137 <0x4ff00000 0x80000>;
138 reg-names = "dbi", "config";
139 #address-cells = <3>;
140 #size-cells = <2>;
141 device_type = "pci";
142 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
143 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
144 num-lanes = <1>;
145 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "msi";
147 #interrupt-cells = <1>;
148 interrupt-map-mask = <0 0 0 0x7>;
Andrey Smirnov1c86c9d2017-10-09 11:43:44 -0700149 interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Andrey Smirnova816d572017-05-15 07:53:04 -0700153 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
154 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
155 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
156 clock-names = "pcie", "pcie_bus", "pcie_phy";
157 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
158 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
159 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
160 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
161
162 fsl,max-link-speed = <2>;
163 power-domains = <&pgc_pcie_phy>;
164 resets = <&src IMX7_RESET_PCIEPHY>,
165 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
166 reset-names = "pciephy", "apps";
167 status = "disabled";
168 };
Stefan Agnera67970a2016-06-26 01:47:53 -0700169};
170
171&ca_funnel_ports {
172 port@1 {
173 reg = <1>;
174 ca_funnel_in_port1: endpoint {
175 slave-mode;
176 remote-endpoint = <&etm1_out_port>;
177 };
178 };
179};