blob: 435a2b6e55a1e1e81a7ed4f908fcf0eb0a287c35 [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -05001/*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8540ADS";
Kumar Gala52094872007-02-17 16:04:23 -060015 compatible = "MPC8540ADS", "MPC85xxADS";
Andy Fleming2654d632006-08-18 18:04:34 -050016 #address-cells = <1>;
17 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050018
19 cpus {
Andy Fleming2654d632006-08-18 18:04:34 -050020 #address-cells = <1>;
21 #size-cells = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -050022
23 PowerPC,8540@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
Andy Fleming2654d632006-08-18 18:04:34 -050033 };
34 };
35
36 memory {
37 device_type = "memory";
Andy Fleming2654d632006-08-18 18:04:34 -050038 reg = <00000000 08000000>; // 128M at 0x0
39 };
40
41 soc8540@e0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050044 device_type = "soc";
45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00100000>; // CCSRBAR 1M
47 bus-frequency = <0>;
48
Dave Jiang50cf6702007-05-10 10:03:05 -070049 memory-controller@2000 {
50 compatible = "fsl,8540-memory-controller";
51 reg = <2000 1000>;
52 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050053 interrupts = <12 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -070054 };
55
56 l2-cache-controller@20000 {
57 compatible = "fsl,8540-l2-cache-controller";
58 reg = <20000 1000>;
59 cache-line-size = <20>; // 32 bytes
60 cache-size = <40000>; // L2, 256K
61 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050062 interrupts = <10 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -070063 };
64
Andy Fleming2654d632006-08-18 18:04:34 -050065 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -060066 #address-cells = <1>;
67 #size-cells = <0>;
68 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -050069 compatible = "fsl-i2c";
70 reg = <3000 100>;
Kumar Galab533f8a2007-07-03 02:35:35 -050071 interrupts = <2b 2>;
Kumar Gala52094872007-02-17 16:04:23 -060072 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -050073 dfsrr;
74 };
75
76 mdio@24520 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 device_type = "mdio";
80 compatible = "gianfar";
81 reg = <24520 20>;
Kumar Gala52094872007-02-17 16:04:23 -060082 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050084 interrupts = <5 1>;
Andy Fleming2654d632006-08-18 18:04:34 -050085 reg = <0>;
86 device_type = "ethernet-phy";
87 };
Kumar Gala52094872007-02-17 16:04:23 -060088 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050090 interrupts = <5 1>;
Andy Fleming2654d632006-08-18 18:04:34 -050091 reg = <1>;
92 device_type = "ethernet-phy";
93 };
Kumar Gala52094872007-02-17 16:04:23 -060094 phy3: ethernet-phy@3 {
95 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050096 interrupts = <7 1>;
Andy Flemingaa74a302006-08-21 14:29:28 -050097 reg = <3>;
Andy Fleming2654d632006-08-18 18:04:34 -050098 device_type = "ethernet-phy";
99 };
100 };
101
102 ethernet@24000 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 device_type = "network";
106 model = "TSEC";
107 compatible = "gianfar";
108 reg = <24000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500109 /*
110 * address is deprecated and will be removed
111 * in 2.6.25. Only recent versions of
112 * U-Boot support local-mac-address, however.
113 */
114 address = [ 00 00 00 00 00 00 ];
115 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500116 interrupts = <1d 2 1e 2 22 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600117 interrupt-parent = <&mpic>;
118 phy-handle = <&phy0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500119 };
120
121 ethernet@25000 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 device_type = "network";
125 model = "TSEC";
126 compatible = "gianfar";
127 reg = <25000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500128 /*
129 * address is deprecated and will be removed
130 * in 2.6.25. Only recent versions of
131 * U-Boot support local-mac-address, however.
132 */
133 address = [ 00 00 00 00 00 00 ];
134 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500135 interrupts = <23 2 24 2 28 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600136 interrupt-parent = <&mpic>;
137 phy-handle = <&phy1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500138 };
139
140 ethernet@26000 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 device_type = "network";
Andy Flemingaa74a302006-08-21 14:29:28 -0500144 model = "FEC";
Andy Fleming2654d632006-08-18 18:04:34 -0500145 compatible = "gianfar";
146 reg = <26000 1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500147 /*
148 * address is deprecated and will be removed
149 * in 2.6.25. Only recent versions of
150 * U-Boot support local-mac-address, however.
151 */
152 address = [ 00 00 00 00 00 00 ];
153 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500154 interrupts = <29 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600155 interrupt-parent = <&mpic>;
156 phy-handle = <&phy3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500157 };
158
159 serial@4500 {
160 device_type = "serial";
161 compatible = "ns16550";
162 reg = <4500 100>; // reg base, size
163 clock-frequency = <0>; // should we fill in in uboot?
Kumar Galab533f8a2007-07-03 02:35:35 -0500164 interrupts = <2a 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600165 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500166 };
167
168 serial@4600 {
169 device_type = "serial";
170 compatible = "ns16550";
171 reg = <4600 100>; // reg base, size
172 clock-frequency = <0>; // should we fill in in uboot?
Kumar Galab533f8a2007-07-03 02:35:35 -0500173 interrupts = <2a 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600174 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500175 };
Kumar Gala52094872007-02-17 16:04:23 -0600176 mpic: pic@40000 {
Andy Fleming2654d632006-08-18 18:04:34 -0500177 clock-frequency = <0>;
178 interrupt-controller;
179 #address-cells = <0>;
180 #interrupt-cells = <2>;
181 reg = <40000 40000>;
Andy Fleming2654d632006-08-18 18:04:34 -0500182 compatible = "chrp,open-pic";
183 device_type = "open-pic";
Andy Flemingaa74a302006-08-21 14:29:28 -0500184 big-endian;
Andy Fleming2654d632006-08-18 18:04:34 -0500185 };
186 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500187
188 pci@e0008000 {
189 interrupt-map-mask = <f800 0 0 7>;
190 interrupt-map = <
191
192 /* IDSEL 0x02 */
193 1000 0 0 1 &mpic 1 1
194 1000 0 0 2 &mpic 2 1
195 1000 0 0 3 &mpic 3 1
196 1000 0 0 4 &mpic 4 1
197
198 /* IDSEL 0x03 */
199 1800 0 0 1 &mpic 4 1
200 1800 0 0 2 &mpic 1 1
201 1800 0 0 3 &mpic 2 1
202 1800 0 0 4 &mpic 3 1
203
204 /* IDSEL 0x04 */
205 2000 0 0 1 &mpic 3 1
206 2000 0 0 2 &mpic 4 1
207 2000 0 0 3 &mpic 1 1
208 2000 0 0 4 &mpic 2 1
209
210 /* IDSEL 0x05 */
211 2800 0 0 1 &mpic 2 1
212 2800 0 0 2 &mpic 3 1
213 2800 0 0 3 &mpic 4 1
214 2800 0 0 4 &mpic 1 1
215
216 /* IDSEL 0x0c */
217 6000 0 0 1 &mpic 1 1
218 6000 0 0 2 &mpic 2 1
219 6000 0 0 3 &mpic 3 1
220 6000 0 0 4 &mpic 4 1
221
222 /* IDSEL 0x0d */
223 6800 0 0 1 &mpic 4 1
224 6800 0 0 2 &mpic 1 1
225 6800 0 0 3 &mpic 2 1
226 6800 0 0 4 &mpic 3 1
227
228 /* IDSEL 0x0e */
229 7000 0 0 1 &mpic 3 1
230 7000 0 0 2 &mpic 4 1
231 7000 0 0 3 &mpic 1 1
232 7000 0 0 4 &mpic 2 1
233
234 /* IDSEL 0x0f */
235 7800 0 0 1 &mpic 2 1
236 7800 0 0 2 &mpic 3 1
237 7800 0 0 3 &mpic 4 1
238 7800 0 0 4 &mpic 1 1
239
240 /* IDSEL 0x12 */
241 9000 0 0 1 &mpic 1 1
242 9000 0 0 2 &mpic 2 1
243 9000 0 0 3 &mpic 3 1
244 9000 0 0 4 &mpic 4 1
245
246 /* IDSEL 0x13 */
247 9800 0 0 1 &mpic 4 1
248 9800 0 0 2 &mpic 1 1
249 9800 0 0 3 &mpic 2 1
250 9800 0 0 4 &mpic 3 1
251
252 /* IDSEL 0x14 */
253 a000 0 0 1 &mpic 3 1
254 a000 0 0 2 &mpic 4 1
255 a000 0 0 3 &mpic 1 1
256 a000 0 0 4 &mpic 2 1
257
258 /* IDSEL 0x15 */
259 a800 0 0 1 &mpic 2 1
260 a800 0 0 2 &mpic 3 1
261 a800 0 0 3 &mpic 4 1
262 a800 0 0 4 &mpic 1 1>;
263 interrupt-parent = <&mpic>;
264 interrupts = <18 2>;
265 bus-range = <0 0>;
266 ranges = <02000000 0 80000000 80000000 0 20000000
267 01000000 0 00000000 e2000000 0 00100000>;
268 clock-frequency = <3f940aa>;
269 #interrupt-cells = <1>;
270 #size-cells = <2>;
271 #address-cells = <3>;
272 reg = <e0008000 1000>;
273 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
274 device_type = "pci";
275 };
Andy Fleming2654d632006-08-18 18:04:34 -0500276};