blob: 6d88a63232299960df5bc7c315bbc80b4c98f8ac [file] [log] [blame]
Archit Tanejae1ef4d22010-09-15 18:47:29 +05301/*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
21#include <linux/types.h>
22#include <linux/err.h>
23#include <linux/slab.h>
24
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030025#include <video/omapdss.h>
Archit Tanejae1ef4d22010-09-15 18:47:29 +053026#include <plat/cpu.h>
27
Archit Taneja067a57e2011-03-02 11:57:25 +053028#include "dss.h"
Archit Tanejae1ef4d22010-09-15 18:47:29 +053029#include "dss_features.h"
30
31/* Defines a generic omap register field */
32struct dss_reg_field {
Archit Tanejae1ef4d22010-09-15 18:47:29 +053033 u8 start, end;
34};
35
Taneja, Archit31ef8232011-03-14 23:28:22 -050036struct dss_param_range {
37 int min, max;
38};
39
Archit Tanejae1ef4d22010-09-15 18:47:29 +053040struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const u32 has_feature;
45
46 const int num_mgrs;
47 const int num_ovls;
48 const enum omap_display_type *supported_displays;
49 const enum omap_color_mode *supported_color_modes;
Taneja, Archit235e7db2011-03-14 23:28:21 -050050 const char * const *clksrc_names;
Taneja, Archit31ef8232011-03-14 23:28:22 -050051 const struct dss_param_range *dss_params;
Archit Tanejae1ef4d22010-09-15 18:47:29 +053052};
53
54/* This struct is assigned to one of the below during initialization */
Tomi Valkeinenea290332011-04-20 10:09:36 +030055static const struct omap_dss_features *omap_current_dss_features;
Archit Tanejae1ef4d22010-09-15 18:47:29 +053056
57static const struct dss_reg_field omap2_dss_reg_fields[] = {
Taneja, Archit49641112011-03-14 23:28:23 -050058 [FEAT_REG_FIRHINC] = { 11, 0 },
59 [FEAT_REG_FIRVINC] = { 27, 16 },
60 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
61 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
62 [FEAT_REG_FIFOSIZE] = { 8, 0 },
63 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
64 [FEAT_REG_VERTICALACCU] = { 25, 16 },
65 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
66 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
67 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
68 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
69 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
Archit Tanejae1ef4d22010-09-15 18:47:29 +053070};
71
72static const struct dss_reg_field omap3_dss_reg_fields[] = {
Taneja, Archit49641112011-03-14 23:28:23 -050073 [FEAT_REG_FIRHINC] = { 12, 0 },
74 [FEAT_REG_FIRVINC] = { 28, 16 },
75 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
76 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
77 [FEAT_REG_FIFOSIZE] = { 10, 0 },
78 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
79 [FEAT_REG_VERTICALACCU] = { 25, 16 },
80 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
81 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
82 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
83 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
84 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
Archit Taneja87a74842011-03-02 11:19:50 +053085};
86
87static const struct dss_reg_field omap4_dss_reg_fields[] = {
Taneja, Archit49641112011-03-14 23:28:23 -050088 [FEAT_REG_FIRHINC] = { 12, 0 },
89 [FEAT_REG_FIRVINC] = { 28, 16 },
90 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
91 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
92 [FEAT_REG_FIFOSIZE] = { 15, 0 },
93 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
94 [FEAT_REG_VERTICALACCU] = { 26, 16 },
95 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
96 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
97 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
98 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
99 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530100};
101
102static const enum omap_display_type omap2_dss_supported_displays[] = {
103 /* OMAP_DSS_CHANNEL_LCD */
Tomi Valkeinenf8df01f2011-02-24 14:21:25 +0200104 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530105
106 /* OMAP_DSS_CHANNEL_DIGIT */
107 OMAP_DISPLAY_TYPE_VENC,
108};
109
Tomi Valkeinen4e777dd2011-02-24 14:20:31 +0200110static const enum omap_display_type omap3430_dss_supported_displays[] = {
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530111 /* OMAP_DSS_CHANNEL_LCD */
112 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
113 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
114
115 /* OMAP_DSS_CHANNEL_DIGIT */
116 OMAP_DISPLAY_TYPE_VENC,
117};
118
Tomi Valkeinen4e777dd2011-02-24 14:20:31 +0200119static const enum omap_display_type omap3630_dss_supported_displays[] = {
120 /* OMAP_DSS_CHANNEL_LCD */
121 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
122 OMAP_DISPLAY_TYPE_DSI,
123
124 /* OMAP_DSS_CHANNEL_DIGIT */
125 OMAP_DISPLAY_TYPE_VENC,
126};
127
Archit Tanejad50cd032010-12-02 11:27:08 +0000128static const enum omap_display_type omap4_dss_supported_displays[] = {
129 /* OMAP_DSS_CHANNEL_LCD */
130 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
131
132 /* OMAP_DSS_CHANNEL_DIGIT */
Mythri P Kb1196012011-03-08 17:15:54 +0530133 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
Archit Tanejad50cd032010-12-02 11:27:08 +0000134
135 /* OMAP_DSS_CHANNEL_LCD2 */
136 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
137 OMAP_DISPLAY_TYPE_DSI,
138};
139
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530140static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
141 /* OMAP_DSS_GFX */
142 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
143 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
144 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
145 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
146
147 /* OMAP_DSS_VIDEO1 */
148 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
149 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
150 OMAP_DSS_COLOR_UYVY,
151
152 /* OMAP_DSS_VIDEO2 */
153 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
154 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
155 OMAP_DSS_COLOR_UYVY,
156};
157
158static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
159 /* OMAP_DSS_GFX */
160 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
161 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
162 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
163 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
164 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
165 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
166
167 /* OMAP_DSS_VIDEO1 */
168 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
169 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
170 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
171
172 /* OMAP_DSS_VIDEO2 */
173 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
174 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
175 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
176 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
177 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
178};
179
Amber Jainf20e4222011-05-19 19:47:50 +0530180static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
181 /* OMAP_DSS_GFX */
182 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
183 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
184 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
185 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
186 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
187 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
188 OMAP_DSS_COLOR_ARGB16_1555,
189
190 /* OMAP_DSS_VIDEO1 */
191 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
192 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
193 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
194 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
195 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
196 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
197 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
198 OMAP_DSS_COLOR_RGBX32,
199
200 /* OMAP_DSS_VIDEO2 */
201 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
202 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
203 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
204 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
205 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
206 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
207 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
208 OMAP_DSS_COLOR_RGBX32,
209};
210
Taneja, Archit235e7db2011-03-14 23:28:21 -0500211static const char * const omap2_dss_clk_source_names[] = {
Archit Taneja89a35e52011-04-12 13:52:23 +0530212 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
213 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
214 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
Archit Taneja067a57e2011-03-02 11:57:25 +0530215};
216
Taneja, Archit235e7db2011-03-14 23:28:21 -0500217static const char * const omap3_dss_clk_source_names[] = {
Archit Taneja89a35e52011-04-12 13:52:23 +0530218 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
219 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
220 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
Archit Taneja067a57e2011-03-02 11:57:25 +0530221};
222
Taneja, Archit235e7db2011-03-14 23:28:21 -0500223static const char * const omap4_dss_clk_source_names[] = {
Archit Taneja89a35e52011-04-12 13:52:23 +0530224 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
225 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
226 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
Archit Taneja5a8b5722011-05-12 17:26:29 +0530227 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
228 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
Taneja, Architea751592011-03-08 05:50:35 -0600229};
230
Taneja, Archit31ef8232011-03-14 23:28:22 -0500231static const struct dss_param_range omap2_dss_param_range[] = {
Taneja, Archit49641112011-03-14 23:28:23 -0500232 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
233 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
234 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
235 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
236 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
237 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
238 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
Taneja, Archit31ef8232011-03-14 23:28:22 -0500239};
240
241static const struct dss_param_range omap3_dss_param_range[] = {
Taneja, Archit49641112011-03-14 23:28:23 -0500242 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
243 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
244 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
245 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
246 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
247 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
248 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
Taneja, Archit31ef8232011-03-14 23:28:22 -0500249};
250
251static const struct dss_param_range omap4_dss_param_range[] = {
Taneja, Archit49641112011-03-14 23:28:23 -0500252 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
253 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
254 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
255 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
256 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
257 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
258 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
Taneja, Archit31ef8232011-03-14 23:28:22 -0500259};
260
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530261/* OMAP2 DSS Features */
Tomi Valkeinenea290332011-04-20 10:09:36 +0300262static const struct omap_dss_features omap2_dss_features = {
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530263 .reg_fields = omap2_dss_reg_fields,
264 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
265
Archit Tanejad50cd032010-12-02 11:27:08 +0000266 .has_feature =
267 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
Archit Taneja87a74842011-03-02 11:19:50 +0530268 FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
269 FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
Archit Tanejad50cd032010-12-02 11:27:08 +0000270
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530271 .num_mgrs = 2,
272 .num_ovls = 3,
273 .supported_displays = omap2_dss_supported_displays,
274 .supported_color_modes = omap2_dss_supported_color_modes,
Archit Taneja067a57e2011-03-02 11:57:25 +0530275 .clksrc_names = omap2_dss_clk_source_names,
Taneja, Archit31ef8232011-03-14 23:28:22 -0500276 .dss_params = omap2_dss_param_range,
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530277};
278
279/* OMAP3 DSS Features */
Tomi Valkeinenea290332011-04-20 10:09:36 +0300280static const struct omap_dss_features omap3430_dss_features = {
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530281 .reg_fields = omap3_dss_reg_fields,
282 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
283
Archit Tanejad50cd032010-12-02 11:27:08 +0000284 .has_feature =
285 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
286 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
Archit Taneja87a74842011-03-02 11:19:50 +0530287 FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
Archit Taneja9613c022011-03-22 06:33:36 -0500288 FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
Tomi Valkeinen293ef192011-04-15 15:07:33 +0300289 FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC,
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530290
291 .num_mgrs = 2,
292 .num_ovls = 3,
Tomi Valkeinen4e777dd2011-02-24 14:20:31 +0200293 .supported_displays = omap3430_dss_supported_displays,
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530294 .supported_color_modes = omap3_dss_supported_color_modes,
Archit Taneja067a57e2011-03-02 11:57:25 +0530295 .clksrc_names = omap3_dss_clk_source_names,
Taneja, Archit31ef8232011-03-14 23:28:22 -0500296 .dss_params = omap3_dss_param_range,
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530297};
298
Tomi Valkeinenea290332011-04-20 10:09:36 +0300299static const struct omap_dss_features omap3630_dss_features = {
Samreen8fbde102010-11-04 12:28:41 +0100300 .reg_fields = omap3_dss_reg_fields,
301 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
302
Archit Tanejad50cd032010-12-02 11:27:08 +0000303 .has_feature =
304 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
305 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
Archit Taneja87a74842011-03-02 11:19:50 +0530306 FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
307 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
Archit Taneja9613c022011-03-22 06:33:36 -0500308 FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
Tomi Valkeinen95861362011-04-14 11:42:22 +0300309 FEAT_DSI_PLL_FREQSEL,
Samreen8fbde102010-11-04 12:28:41 +0100310
311 .num_mgrs = 2,
312 .num_ovls = 3,
Tomi Valkeinen4e777dd2011-02-24 14:20:31 +0200313 .supported_displays = omap3630_dss_supported_displays,
Samreen8fbde102010-11-04 12:28:41 +0100314 .supported_color_modes = omap3_dss_supported_color_modes,
Archit Taneja067a57e2011-03-02 11:57:25 +0530315 .clksrc_names = omap3_dss_clk_source_names,
Taneja, Archit31ef8232011-03-14 23:28:22 -0500316 .dss_params = omap3_dss_param_range,
Samreen8fbde102010-11-04 12:28:41 +0100317};
318
Archit Tanejad50cd032010-12-02 11:27:08 +0000319/* OMAP4 DSS Features */
Ricardo Neri6ff70842011-05-18 22:23:33 -0500320/* For OMAP4430 ES 1.0 revision */
321static const struct omap_dss_features omap4430_es1_0_dss_features = {
322 .reg_fields = omap4_dss_reg_fields,
323 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
324
325 .has_feature =
326 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
327 FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
328 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
329 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
330 FEAT_DSI_GNQ,
331
332 .num_mgrs = 3,
333 .num_ovls = 3,
334 .supported_displays = omap4_dss_supported_displays,
Amber Jainf20e4222011-05-19 19:47:50 +0530335 .supported_color_modes = omap4_dss_supported_color_modes,
Ricardo Neri6ff70842011-05-18 22:23:33 -0500336 .clksrc_names = omap4_dss_clk_source_names,
337 .dss_params = omap4_dss_param_range,
338};
339
340/* For all the other OMAP4 versions */
Tomi Valkeinenea290332011-04-20 10:09:36 +0300341static const struct omap_dss_features omap4_dss_features = {
Archit Taneja87a74842011-03-02 11:19:50 +0530342 .reg_fields = omap4_dss_reg_fields,
343 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
Archit Tanejad50cd032010-12-02 11:27:08 +0000344
345 .has_feature =
346 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
Murthy, Raghuveer5c6366e2011-03-03 09:27:58 -0600347 FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
Archit Taneja9613c022011-03-22 06:33:36 -0500348 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
Archit Taneja75d72472011-05-16 15:17:08 +0530349 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
Ricardo Neri72e91ac2011-05-18 22:27:56 -0500350 FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE,
Archit Tanejad50cd032010-12-02 11:27:08 +0000351
352 .num_mgrs = 3,
353 .num_ovls = 3,
354 .supported_displays = omap4_dss_supported_displays,
Amber Jainf20e4222011-05-19 19:47:50 +0530355 .supported_color_modes = omap4_dss_supported_color_modes,
Taneja, Architea751592011-03-08 05:50:35 -0600356 .clksrc_names = omap4_dss_clk_source_names,
Taneja, Archit31ef8232011-03-14 23:28:22 -0500357 .dss_params = omap4_dss_param_range,
Archit Tanejad50cd032010-12-02 11:27:08 +0000358};
359
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530360/* Functions returning values related to a DSS feature */
361int dss_feat_get_num_mgrs(void)
362{
363 return omap_current_dss_features->num_mgrs;
364}
365
366int dss_feat_get_num_ovls(void)
367{
368 return omap_current_dss_features->num_ovls;
369}
370
Taneja, Archit31ef8232011-03-14 23:28:22 -0500371unsigned long dss_feat_get_param_min(enum dss_range_param param)
Archit Taneja819d8072011-03-01 11:54:00 +0530372{
Taneja, Archit31ef8232011-03-14 23:28:22 -0500373 return omap_current_dss_features->dss_params[param].min;
374}
375
376unsigned long dss_feat_get_param_max(enum dss_range_param param)
377{
378 return omap_current_dss_features->dss_params[param].max;
Archit Taneja819d8072011-03-01 11:54:00 +0530379}
380
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530381enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
382{
383 return omap_current_dss_features->supported_displays[channel];
384}
385
386enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
387{
388 return omap_current_dss_features->supported_color_modes[plane];
389}
390
Archit Taneja8dad2ab2010-11-25 17:58:10 +0530391bool dss_feat_color_mode_supported(enum omap_plane plane,
392 enum omap_color_mode color_mode)
393{
394 return omap_current_dss_features->supported_color_modes[plane] &
395 color_mode;
396}
397
Archit Taneja89a35e52011-04-12 13:52:23 +0530398const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
Archit Taneja067a57e2011-03-02 11:57:25 +0530399{
Taneja, Archit235e7db2011-03-14 23:28:21 -0500400 return omap_current_dss_features->clksrc_names[id];
Archit Taneja067a57e2011-03-02 11:57:25 +0530401}
402
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530403/* DSS has_feature check */
404bool dss_has_feature(enum dss_feat_id id)
405{
406 return omap_current_dss_features->has_feature & id;
407}
408
409void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
410{
411 if (id >= omap_current_dss_features->num_reg_fields)
412 BUG();
413
414 *start = omap_current_dss_features->reg_fields[id].start;
415 *end = omap_current_dss_features->reg_fields[id].end;
416}
417
418void dss_features_init(void)
419{
420 if (cpu_is_omap24xx())
421 omap_current_dss_features = &omap2_dss_features;
Samreen8fbde102010-11-04 12:28:41 +0100422 else if (cpu_is_omap3630())
423 omap_current_dss_features = &omap3630_dss_features;
424 else if (cpu_is_omap34xx())
425 omap_current_dss_features = &omap3430_dss_features;
Ricardo Neri6ff70842011-05-18 22:23:33 -0500426 else if (omap_rev() == OMAP4430_REV_ES1_0)
427 omap_current_dss_features = &omap4430_es1_0_dss_features;
428 else if (cpu_is_omap44xx())
Archit Tanejad50cd032010-12-02 11:27:08 +0000429 omap_current_dss_features = &omap4_dss_features;
Ricardo Neri6ff70842011-05-18 22:23:33 -0500430 else
431 DSSWARN("Unsupported OMAP version");
Archit Tanejae1ef4d22010-09-15 18:47:29 +0530432}