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gerrit-public.fairphone.software / kernel / msm-5.4 / f317e689cba38b1d5cf9dd5763e7f91ed5168d63 / . / arch / arm / boot / dts / stih415-clock.dtsi
blob: 3016e537b2e3565d5408ac3db605f6e07a51a21f [file] [log] [blame]
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100[diff] [blame]1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +0200[diff] [blame^]8
9#include <dt-bindings/clock/stih415-clks.h>
10
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100[diff] [blame]11/ {
12 clocks {
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +0200[diff] [blame^]13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges;
16
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100[diff] [blame]17 /*
18 * Fixed 30MHz oscillator input to SoC
19 */
Gabriel FERNANDEZed3593f2014-05-20 15:22:00 +0200[diff] [blame]20 clk_sysin: clk-sysin {
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100[diff] [blame]21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 };
25
26 /*
27 * ARM Peripheral clock for timers
28 */
29 arm_periph_clk: arm_periph_clk {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <500000000>;
33 };
34
35 /*
36 * Bootloader initialized system infrastructure clock for
37 * serial devices.
38 */
39 CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <100000000>;
43 };
Srinivas Kandagatlac80fe3352014-01-29 16:19:44 +0000[diff] [blame]44
45 CLKS_GMAC0_PHY: clockgenA1@7 {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <25000000>;
49 clock-output-names = "CLKS_GMAC0_PHY";
50 };
51
52 CLKS_ETH1_PHY: clockgenA0@7 {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
56 clock-output-names = "CLKS_ETH1_PHY";
57 };
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +0200[diff] [blame^]58
59 /*
60 * ClockGenAs on SASG1
61 */
62 clockgen-a@fee62000 {
63 reg = <0xfee62000 0xb48>;
64
65 clk_s_a0_pll: clk-s-a0-pll {
66 #clock-cells = <1>;
67 compatible = "st,clkgena-plls-c65";
68
69 clocks = <&clk_sysin>;
70
71 clock-output-names = "clk-s-a0-pll0-hs",
72 "clk-s-a0-pll0-ls",
73 "clk-s-a0-pll1";
74 };
75
76 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
77 #clock-cells = <0>;
78 compatible = "st,clkgena-prediv-c65",
79 "st,clkgena-prediv";
80
81 clocks = <&clk_sysin>;
82
83 clock-output-names = "clk-s-a0-osc-prediv";
84 };
85
86 clk_s_a0_hs: clk-s-a0-hs {
87 #clock-cells = <1>;
88 compatible = "st,clkgena-divmux-c65-hs",
89 "st,clkgena-divmux";
90
91 clocks = <&clk_s_a0_osc_prediv>,
92 <&clk_s_a0_pll 0>, /* PLL0 HS */
93 <&clk_s_a0_pll 2>; /* PLL1 */
94
95 clock-output-names = "clk-s-fdma-0",
96 "clk-s-fdma-1",
97 ""; /* clk-s-jit-sense */
98 /* Fourth output unused */
99 };
100
101 clk_s_a0_ls: clk-s-a0-ls {
102 #clock-cells = <1>;
103 compatible = "st,clkgena-divmux-c65-ls",
104 "st,clkgena-divmux";
105
106 clocks = <&clk_s_a0_osc_prediv>,
107 <&clk_s_a0_pll 1>, /* PLL0 LS */
108 <&clk_s_a0_pll 2>; /* PLL1 */
109
110 clock-output-names = "clk-s-icn-reg-0",
111 "clk-s-icn-if-0",
112 "clk-s-icn-reg-lp-0",
113 "clk-s-emiss",
114 "clk-s-eth1-phy",
115 "clk-s-mii-ref-out";
116 /* Remaining outputs unused */
117 };
118 };
119
120 clockgen-a@fee81000 {
121 reg = <0xfee81000 0xb48>;
122
123 clk_s_a1_pll: clk-s-a1-pll {
124 #clock-cells = <1>;
125 compatible = "st,clkgena-plls-c65";
126
127 clocks = <&clk_sysin>;
128
129 clock-output-names = "clk-s-a1-pll0-hs",
130 "clk-s-a1-pll0-ls",
131 "clk-s-a1-pll1";
132 };
133
134 clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
135 #clock-cells = <0>;
136 compatible = "st,clkgena-prediv-c65",
137 "st,clkgena-prediv";
138
139 clocks = <&clk_sysin>;
140
141 clock-output-names = "clk-s-a1-osc-prediv";
142 };
143
144 clk_s_a1_hs: clk-s-a1-hs {
145 #clock-cells = <1>;
146 compatible = "st,clkgena-divmux-c65-hs",
147 "st,clkgena-divmux";
148
149 clocks = <&clk_s_a1_osc_prediv>,
150 <&clk_s_a1_pll 0>, /* PLL0 HS */
151 <&clk_s_a1_pll 2>; /* PLL1 */
152
153 clock-output-names = "", /* Reserved */
154 "", /* Reserved */
155 "clk-s-stac-phy",
156 "clk-s-vtac-tx-phy";
157 };
158
159 clk_s_a1_ls: clk-s-a1-ls {
160 #clock-cells = <1>;
161 compatible = "st,clkgena-divmux-c65-ls",
162 "st,clkgena-divmux";
163
164 clocks = <&clk_s_a1_osc_prediv>,
165 <&clk_s_a1_pll 1>, /* PLL0 LS */
166 <&clk_s_a1_pll 2>; /* PLL1 */
167
168 clock-output-names = "clk-s-icn-if-2",
169 "clk-s-card-mmc",
170 "clk-s-icn-if-1",
171 "clk-s-gmac0-phy",
172 "clk-s-nand-ctrl",
173 "", /* Reserved */
174 "clk-s-mii0-ref-out",
175 ""; /* clk-s-stac-sys */
176 /* Remaining outputs unused */
177 };
178 };
179
180 /*
181 * ClockGenAs on MPE41
182 */
183 clockgen-a@fde12000 {
184 reg = <0xfde12000 0xb50>;
185
186 clk_m_a0_pll0: clk-m-a0-pll0 {
187 #clock-cells = <1>;
188 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
189
190 clocks = <&clk_sysin>;
191
192 clock-output-names = "clk-m-a0-pll0-phi0",
193 "clk-m-a0-pll0-phi1",
194 "clk-m-a0-pll0-phi2",
195 "clk-m-a0-pll0-phi3";
196 };
197
198 clk_m_a0_pll1: clk-m-a0-pll1 {
199 #clock-cells = <1>;
200 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
201
202 clocks = <&clk_sysin>;
203
204 clock-output-names = "clk-m-a0-pll1-phi0",
205 "clk-m-a0-pll1-phi1",
206 "clk-m-a0-pll1-phi2",
207 "clk-m-a0-pll1-phi3";
208 };
209
210 clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
211 #clock-cells = <0>;
212 compatible = "st,clkgena-prediv-c32",
213 "st,clkgena-prediv";
214
215 clocks = <&clk_sysin>;
216
217 clock-output-names = "clk-m-a0-osc-prediv";
218 };
219
220 clk_m_a0_div0: clk-m-a0-div0 {
221 #clock-cells = <1>;
222 compatible = "st,clkgena-divmux-c32-odf0",
223 "st,clkgena-divmux";
224
225 clocks = <&clk_m_a0_osc_prediv>,
226 <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
227 <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
228
229 clock-output-names = "clk-m-apb-pm", /* Unused */
230 "", /* Unused */
231 "", /* Unused */
232 "", /* Unused */
233 "clk-m-pp-dmu-0",
234 "clk-m-pp-dmu-1",
235 "clk-m-icm-disp",
236 ""; /* Unused */
237 };
238
239 clk_m_a0_div1: clk-m-a0-div1 {
240 #clock-cells = <1>;
241 compatible = "st,clkgena-divmux-c32-odf1",
242 "st,clkgena-divmux";
243
244 clocks = <&clk_m_a0_osc_prediv>,
245 <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
246 <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
247
248 clock-output-names = "", /* Unused */
249 "", /* Unused */
250 "clk-m-a9-ext2f",
251 "clk-m-st40rt",
252 "clk-m-st231-dmu-0",
253 "clk-m-st231-dmu-1",
254 "clk-m-st231-aud",
255 "clk-m-st231-gp-0";
256 };
257
258 clk_m_a0_div2: clk-m-a0-div2 {
259 #clock-cells = <1>;
260 compatible = "st,clkgena-divmux-c32-odf2",
261 "st,clkgena-divmux";
262
263 clocks = <&clk_m_a0_osc_prediv>,
264 <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
265 <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
266
267 clock-output-names = "clk-m-st231-gp-1",
268 "clk-m-icn-cpu",
269 "clk-m-icn-stac",
270 "clk-m-icn-dmu-0",
271 "clk-m-icn-dmu-1",
272 "", /* Unused */
273 "", /* Unused */
274 ""; /* Unused */
275 };
276
277 clk_m_a0_div3: clk-m-a0-div3 {
278 #clock-cells = <1>;
279 compatible = "st,clkgena-divmux-c32-odf3",
280 "st,clkgena-divmux";
281
282 clocks = <&clk_m_a0_osc_prediv>,
283 <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
284 <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
285
286 clock-output-names = "", /* Unused */
287 "", /* Unused */
288 "", /* Unused */
289 "", /* Unused */
290 "", /* Unused */
291 "", /* Unused */
292 "clk-m-icn-eram",
293 "clk-m-a9-trace";
294 };
295 };
296
297 clockgen-a@fd6db000 {
298 reg = <0xfd6db000 0xb50>;
299
300 clk_m_a1_pll0: clk-m-a1-pll0 {
301 #clock-cells = <1>;
302 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
303
304 clocks = <&clk_sysin>;
305
306 clock-output-names = "clk-m-a1-pll0-phi0",
307 "clk-m-a1-pll0-phi1",
308 "clk-m-a1-pll0-phi2",
309 "clk-m-a1-pll0-phi3";
310 };
311
312 clk_m_a1_pll1: clk-m-a1-pll1 {
313 #clock-cells = <1>;
314 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
315
316 clocks = <&clk_sysin>;
317
318 clock-output-names = "clk-m-a1-pll1-phi0",
319 "clk-m-a1-pll1-phi1",
320 "clk-m-a1-pll1-phi2",
321 "clk-m-a1-pll1-phi3";
322 };
323
324 clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
325 #clock-cells = <0>;
326 compatible = "st,clkgena-prediv-c32",
327 "st,clkgena-prediv";
328
329 clocks = <&clk_sysin>;
330
331 clock-output-names = "clk-m-a1-osc-prediv";
332 };
333
334 clk_m_a1_div0: clk-m-a1-div0 {
335 #clock-cells = <1>;
336 compatible = "st,clkgena-divmux-c32-odf0",
337 "st,clkgena-divmux";
338
339 clocks = <&clk_m_a1_osc_prediv>,
340 <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
341 <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
342
343 clock-output-names = "clk-m-fdma-12",
344 "clk-m-fdma-10",
345 "clk-m-fdma-11",
346 "clk-m-hva-lmi",
347 "clk-m-proc-sc",
348 "clk-m-tp",
349 "clk-m-icn-gpu",
350 "clk-m-icn-vdp-0";
351 };
352
353 clk_m_a1_div1: clk-m-a1-div1 {
354 #clock-cells = <1>;
355 compatible = "st,clkgena-divmux-c32-odf1",
356 "st,clkgena-divmux";
357
358 clocks = <&clk_m_a1_osc_prediv>,
359 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
360 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
361
362 clock-output-names = "clk-m-icn-vdp-1",
363 "clk-m-icn-vdp-2",
364 "clk-m-icn-vdp-3",
365 "clk-m-prv-t1-bus",
366 "clk-m-icn-vdp-4",
367 "clk-m-icn-reg-10",
368 "", /* Unused */
369 ""; /* clk-m-icn-st231 */
370 };
371
372 clk_m_a1_div2: clk-m-a1-div2 {
373 #clock-cells = <1>;
374 compatible = "st,clkgena-divmux-c32-odf2",
375 "st,clkgena-divmux";
376
377 clocks = <&clk_m_a1_osc_prediv>,
378 <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
379 <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
380
381 clock-output-names = "clk-m-fvdp-proc-alt",
382 "", /* Unused */
383 "", /* Unused */
384 "", /* Unused */
385 "", /* Unused */
386 "", /* Unused */
387 "", /* Unused */
388 ""; /* Unused */
389 };
390
391 clk_m_a1_div3: clk-m-a1-div3 {
392 #clock-cells = <1>;
393 compatible = "st,clkgena-divmux-c32-odf3",
394 "st,clkgena-divmux";
395
396 clocks = <&clk_m_a1_osc_prediv>,
397 <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
398 <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
399
400 clock-output-names = "", /* Unused */
401 "", /* Unused */
402 "", /* Unused */
403 "", /* Unused */
404 "", /* Unused */
405 "", /* Unused */
406 "", /* Unused */
407 ""; /* Unused */
408 };
409 };
410
411 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
412 #clock-cells = <0>;
413 compatible = "fixed-factor-clock";
414 clocks = <&clk_m_a0_div1 2>;
415 clock-div = <2>;
416 clock-mult = <1>;
417 };
418
419 clockgen-a@fd345000 {
420 reg = <0xfd345000 0xb50>;
421
422 clk_m_a2_pll0: clk-m-a2-pll0 {
423 #clock-cells = <1>;
424 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
425
426 clocks = <&clk_sysin>;
427
428 clock-output-names = "clk-m-a2-pll0-phi0",
429 "clk-m-a2-pll0-phi1",
430 "clk-m-a2-pll0-phi2",
431 "clk-m-a2-pll0-phi3";
432 };
433
434 clk_m_a2_pll1: clk-m-a2-pll1 {
435 #clock-cells = <1>;
436 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
437
438 clocks = <&clk_sysin>;
439
440 clock-output-names = "clk-m-a2-pll1-phi0",
441 "clk-m-a2-pll1-phi1",
442 "clk-m-a2-pll1-phi2",
443 "clk-m-a2-pll1-phi3";
444 };
445
446 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
447 #clock-cells = <0>;
448 compatible = "st,clkgena-prediv-c32",
449 "st,clkgena-prediv";
450
451 clocks = <&clk_sysin>;
452
453 clock-output-names = "clk-m-a2-osc-prediv";
454 };
455
456 clk_m_a2_div0: clk-m-a2-div0 {
457 #clock-cells = <1>;
458 compatible = "st,clkgena-divmux-c32-odf0",
459 "st,clkgena-divmux";
460
461 clocks = <&clk_m_a2_osc_prediv>,
462 <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
463 <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
464
465 clock-output-names = "clk-m-vtac-main-phy",
466 "clk-m-vtac-aux-phy",
467 "clk-m-stac-phy",
468 "clk-m-stac-sys",
469 "", /* clk-m-mpestac-pg */
470 "", /* clk-m-mpestac-wc */
471 "", /* clk-m-mpevtacaux-pg*/
472 ""; /* clk-m-mpevtacmain-pg*/
473 };
474
475 clk_m_a2_div1: clk-m-a2-div1 {
476 #clock-cells = <1>;
477 compatible = "st,clkgena-divmux-c32-odf1",
478 "st,clkgena-divmux";
479
480 clocks = <&clk_m_a2_osc_prediv>,
481 <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
482 <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
483
484 clock-output-names = "", /* clk-m-mpevtacrx0-wc */
485 "", /* clk-m-mpevtacrx1-wc */
486 "clk-m-compo-main",
487 "clk-m-compo-aux",
488 "clk-m-bdisp-0",
489 "clk-m-bdisp-1",
490 "clk-m-icn-bdisp-0",
491 "clk-m-icn-bdisp-1";
492 };
493
494 clk_m_a2_div2: clk-m-a2-div2 {
495 #clock-cells = <1>;
496 compatible = "st,clkgena-divmux-c32-odf2",
497 "st,clkgena-divmux";
498
499 clocks = <&clk_m_a2_osc_prediv>,
500 <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
501 <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
502
503 clock-output-names = "", /* clk-m-icn-hqvdp0 */
504 "", /* clk-m-icn-hqvdp1 */
505 "clk-m-icn-compo",
506 "", /* clk-m-icn-vdpaux */
507 "clk-m-icn-ts",
508 "clk-m-icn-reg-lp-10",
509 "clk-m-dcephy-impctrl",
510 ""; /* Unused */
511 };
512
513 clk_m_a2_div3: clk-m-a2-div3 {
514 #clock-cells = <1>;
515 compatible = "st,clkgena-divmux-c32-odf3",
516 "st,clkgena-divmux";
517
518 clocks = <&clk_m_a2_osc_prediv>,
519 <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
520 <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
521
522 clock-output-names = ""; /* Unused */
523 /* Remaining outputs unused */
524 };
525 };
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100[diff] [blame]526 };
527};