blob: 2c4da874eb164809d8662899f967754442ad1cbd [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Grant Likely8e267f32011-07-19 17:26:54 -06003/include/ "tegra20.dtsi"
4
5/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00006 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -06007 compatible = "nvidia,harmony", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060011 };
12
Stephen Warren20ffbd72012-11-09 16:58:11 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
44 "spia", "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
79 ddc {
80 nvidia,pins = "ddc";
81 nvidia,function = "i2c2";
82 };
83 dta {
84 nvidia,pins = "dta", "dtd";
85 nvidia,function = "sdio2";
86 };
87 dtb {
88 nvidia,pins = "dtb", "dtc", "dte";
89 nvidia,function = "rsvd1";
90 };
91 dtf {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 };
95 gmc {
96 nvidia,pins = "gmc";
97 nvidia,function = "uartd";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
108 nvidia,pins = "hdint", "pta";
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uarta";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
126 "ld3", "ld4", "ld5", "ld6", "ld7",
127 "ld8", "ld9", "ld10", "ld11", "ld12",
128 "ld13", "ld14", "ld15", "ld16", "ld17",
129 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
130 "lhs", "lm0", "lm1", "lpp", "lpw0",
131 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
132 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
133 "lvs";
134 nvidia,function = "displaya";
135 };
136 owc {
137 nvidia,pins = "owc", "spdi", "spdo", "uac";
138 nvidia,function = "rsvd2";
139 };
140 pmc {
141 nvidia,pins = "pmc";
142 nvidia,function = "pwr_on";
143 };
144 rm {
145 nvidia,pins = "rm";
146 nvidia,function = "i2c1";
147 };
148 sdb {
149 nvidia,pins = "sdb", "sdc", "sdd";
150 nvidia,function = "pwm";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 slxc {
157 nvidia,pins = "slxc", "slxd";
158 nvidia,function = "spdif";
159 };
160 spid {
161 nvidia,pins = "spid", "spie", "spif";
162 nvidia,function = "spi1";
163 };
164 spig {
165 nvidia,pins = "spig", "spih";
166 nvidia,function = "spi2_alt";
167 };
168 uaa {
169 nvidia,pins = "uaa", "uab", "uda";
170 nvidia,function = "ulpi";
171 };
172 uad {
173 nvidia,pins = "uad";
174 nvidia,function = "irda";
175 };
176 uca {
177 nvidia,pins = "uca", "ucb";
178 nvidia,function = "uartc";
179 };
180 conf_ata {
181 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600182 "cdev1", "cdev2", "dap1", "dtb", "gma",
183 "gmb", "gmc", "gmd", "gme", "gpu7",
184 "gpv", "i2cp", "pta", "rm", "slxa",
185 "slxk", "spia", "spib", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600186 nvidia,pull = <0>;
187 nvidia,tristate = <0>;
188 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
Stephen Warren563da212012-04-13 16:35:20 -0600194 conf_csus {
195 nvidia,pins = "csus", "spid", "spif";
196 nvidia,pull = <1>;
197 nvidia,tristate = <1>;
198 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600199 conf_crtp {
200 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
201 "dtc", "dte", "dtf", "gpu", "sdio1",
202 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600203 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_ddc {
208 nvidia,pins = "ddc", "dta", "dtd", "kbca",
209 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
210 "sdc";
211 nvidia,pull = <2>;
212 nvidia,tristate = <0>;
213 };
214 conf_hdint {
215 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
216 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
217 "lvp0", "owc", "sdb";
218 nvidia,tristate = <1>;
219 };
220 conf_irrx {
221 nvidia,pins = "irrx", "irtx", "sdd", "spic",
222 "spie", "spih", "uaa", "uab", "uad",
223 "uca", "ucb";
224 nvidia,pull = <2>;
225 nvidia,tristate = <1>;
226 };
227 conf_lc {
228 nvidia,pins = "lc", "ls";
229 nvidia,pull = <2>;
230 };
231 conf_ld0 {
232 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
233 "ld5", "ld6", "ld7", "ld8", "ld9",
234 "ld10", "ld11", "ld12", "ld13", "ld14",
235 "ld15", "ld16", "ld17", "ldi", "lhp0",
236 "lhp1", "lhp2", "lhs", "lm0", "lpp",
237 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
238 "lvs", "pmc";
239 nvidia,tristate = <0>;
240 };
241 conf_ld17_0 {
242 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
243 "ld23_22";
244 nvidia,pull = <1>;
245 };
246 };
247 };
248
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600249 i2s@70002800 {
250 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600251 };
252
253 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600254 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600255 };
256
Grant Likely8e267f32011-07-19 17:26:54 -0600257 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600258 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600259 clock-frequency = <400000>;
260
Stephen Warren797acf72012-01-11 16:09:57 -0700261 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600262 compatible = "wlf,wm8903";
263 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700264 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600265 interrupts = <187 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600266
267 gpio-controller;
268 #gpio-cells = <2>;
269
Stephen Warren797acf72012-01-11 16:09:57 -0700270 micdet-cfg = <0>;
271 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600272 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600273 };
274 };
275
Stephen Warren20ffbd72012-11-09 16:58:11 -0700276 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600277 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700278 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600279 };
280
281 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600282 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600283 clock-frequency = <400000>;
284 };
285
286 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600287 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600288 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000289
290 pmic: tps6586x@34 {
291 compatible = "ti,tps6586x";
292 reg = <0x34>;
293 interrupts = <0 86 0x4>;
294
Stephen Warrenbe972c32012-09-11 11:40:04 -0600295 ti,system-power-controller;
296
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000297 #gpio-cells = <2>;
298 gpio-controller;
299
300 sys-supply = <&vdd_5v0_reg>;
301 vin-sm0-supply = <&sys_reg>;
302 vin-sm1-supply = <&sys_reg>;
303 vin-sm2-supply = <&sys_reg>;
304 vinldo01-supply = <&sm2_reg>;
305 vinldo23-supply = <&sm2_reg>;
306 vinldo4-supply = <&sm2_reg>;
307 vinldo678-supply = <&sm2_reg>;
308 vinldo9-supply = <&sm2_reg>;
309
310 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600311 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000312 regulator-name = "vdd_sys";
313 regulator-always-on;
314 };
315
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600316 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000317 regulator-name = "vdd_sm0,vdd_core";
318 regulator-min-microvolt = <1200000>;
319 regulator-max-microvolt = <1200000>;
320 regulator-always-on;
321 };
322
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600323 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000324 regulator-name = "vdd_sm1,vdd_cpu";
325 regulator-min-microvolt = <1000000>;
326 regulator-max-microvolt = <1000000>;
327 regulator-always-on;
328 };
329
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600330 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000331 regulator-name = "vdd_sm2,vin_ldo*";
332 regulator-min-microvolt = <3700000>;
333 regulator-max-microvolt = <3700000>;
334 regulator-always-on;
335 };
336
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600337 ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000338 regulator-name = "vdd_ldo0,vddio_pex_clk";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 };
342
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600343 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000344 regulator-name = "vdd_ldo1,avdd_pll*";
345 regulator-min-microvolt = <1100000>;
346 regulator-max-microvolt = <1100000>;
347 regulator-always-on;
348 };
349
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600350 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000351 regulator-name = "vdd_ldo2,vdd_rtc";
352 regulator-min-microvolt = <1200000>;
353 regulator-max-microvolt = <1200000>;
354 };
355
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600356 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000357 regulator-name = "vdd_ldo3,avdd_usb*";
358 regulator-min-microvolt = <3300000>;
359 regulator-max-microvolt = <3300000>;
360 regulator-always-on;
361 };
362
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600363 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000364 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
365 regulator-min-microvolt = <1800000>;
366 regulator-max-microvolt = <1800000>;
367 regulator-always-on;
368 };
369
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600370 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000371 regulator-name = "vdd_ldo5,vcore_mmc";
372 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>;
374 regulator-always-on;
375 };
376
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600377 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000378 regulator-name = "vdd_ldo6,avdd_vdac";
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>;
381 };
382
Stephen Warren20ffbd72012-11-09 16:58:11 -0700383 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600384 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000385 regulator-min-microvolt = <3300000>;
386 regulator-max-microvolt = <3300000>;
387 };
388
Stephen Warren20ffbd72012-11-09 16:58:11 -0700389 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000390 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <1800000>;
393 };
394
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600395 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000396 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
397 regulator-min-microvolt = <2850000>;
398 regulator-max-microvolt = <2850000>;
399 regulator-always-on;
400 };
401
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600402 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000403 regulator-name = "vdd_rtc_out,vdd_cell";
404 regulator-min-microvolt = <3300000>;
405 regulator-max-microvolt = <3300000>;
406 regulator-always-on;
407 };
408 };
409 };
Thierry Reding42d25342012-11-09 22:58:43 +0100410
411 temperature-sensor@4c {
412 compatible = "adi,adt7461";
413 reg = <0x4c>;
414 };
Grant Likely8e267f32011-07-19 17:26:54 -0600415 };
416
Stephen Warrenc04abb32012-05-11 17:03:26 -0600417 pmc {
418 nvidia,invert-interrupt;
419 };
420
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600421 usb@c5000000 {
422 status = "okay";
423 };
424
Stephen Warrenc04abb32012-05-11 17:03:26 -0600425 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600426 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600427 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
428 };
429
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600430 usb@c5008000 {
431 status = "okay";
Stephen Warren797acf72012-01-11 16:09:57 -0700432 };
Grant Likely8e267f32011-07-19 17:26:54 -0600433
Venu Byravarasu40e8b3a2013-01-24 15:46:46 +0530434 usb-phy@c5004400 {
435 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
436 };
437
Stephen Warrenc04abb32012-05-11 17:03:26 -0600438 sdhci@c8000200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600439 status = "okay";
Joseph Lo908ab932013-02-22 11:23:39 +0800440 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600441 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
442 power-gpios = <&gpio 155 0>; /* gpio PT3 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200443 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600444 };
445
Stephen Warrenc04abb32012-05-11 17:03:26 -0600446 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600447 status = "okay";
Joseph Lo908ab932013-02-22 11:23:39 +0800448 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600449 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
450 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200451 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600452 };
453
Joseph Lo7021d122013-04-03 19:31:27 +0800454 clocks {
455 compatible = "simple-bus";
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 clk32k_in: clock {
460 compatible = "fixed-clock";
461 reg=<0>;
462 #clock-cells = <0>;
463 clock-frequency = <32768>;
464 };
465 };
466
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530467 kbc {
468 status = "okay";
469 nvidia,debounce-delay-ms = <2>;
470 nvidia,repeat-delay-ms = <160>;
471 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
472 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
473 linux,keymap = <0x00020011 /* KEY_W */
474 0x0003001F /* KEY_S */
475 0x0004001E /* KEY_A */
476 0x0005002C /* KEY_Z */
477 0x000701D0 /* KEY_FN */
478 0x0107008B /* KEY_MENU */
479 0x02060038 /* KEY_LEFTALT */
480 0x02070064 /* KEY_RIGHTALT */
481 0x03000006 /* KEY_5 */
482 0x03010005 /* KEY_4 */
483 0x03020013 /* KEY_R */
484 0x03030012 /* KEY_E */
485 0x03040021 /* KEY_F */
486 0x03050020 /* KEY_D */
487 0x0306002D /* KEY_X */
488 0x04000008 /* KEY_7 */
489 0x04010007 /* KEY_6 */
490 0x04020014 /* KEY_T */
491 0x04030023 /* KEY_H */
492 0x04040022 /* KEY_G */
493 0x0405002F /* KEY_V */
494 0x0406002E /* KEY_C */
495 0x04070039 /* KEY_SPACE */
496 0x0500000A /* KEY_9 */
497 0x05010009 /* KEY_8 */
498 0x05020016 /* KEY_U */
499 0x05030015 /* KEY_Y */
500 0x05040024 /* KEY_J */
501 0x05050031 /* KEY_N */
502 0x05060030 /* KEY_B */
503 0x0507002B /* KEY_BACKSLASH */
504 0x0600000C /* KEY_MINUS */
505 0x0601000B /* KEY_0 */
506 0x06020018 /* KEY_O */
507 0x06030017 /* KEY_I */
508 0x06040026 /* KEY_L */
509 0x06050025 /* KEY_K */
510 0x06060033 /* KEY_COMMA */
511 0x06070032 /* KEY_M */
512 0x0701000D /* KEY_EQUAL */
513 0x0702001B /* KEY_RIGHTBRACE */
514 0x0703001C /* KEY_ENTER */
515 0x0707008B /* KEY_MENU */
516 0x0804002A /* KEY_LEFTSHIFT */
517 0x08050036 /* KEY_RIGHTSHIFT */
518 0x0905001D /* KEY_LEFTCTRL */
519 0x09070061 /* KEY_RIGHTCTRL */
520 0x0B00001A /* KEY_LEFTBRACE */
521 0x0B010019 /* KEY_P */
522 0x0B020028 /* KEY_APOSTROPHE */
523 0x0B030027 /* KEY_SEMICOLON */
524 0x0B040035 /* KEY_SLASH */
525 0x0B050034 /* KEY_DOT */
526 0x0C000044 /* KEY_F10 */
527 0x0C010043 /* KEY_F9 */
528 0x0C02000E /* KEY_BACKSPACE */
529 0x0C030004 /* KEY_3 */
530 0x0C040003 /* KEY_2 */
531 0x0C050067 /* KEY_UP */
532 0x0C0600D2 /* KEY_PRINT */
533 0x0C070077 /* KEY_PAUSE */
534 0x0D00006E /* KEY_INSERT */
535 0x0D01006F /* KEY_DELETE */
536 0x0D030068 /* KEY_PAGEUP */
537 0x0D04006D /* KEY_PAGEDOWN */
538 0x0D05006A /* KEY_RIGHT */
539 0x0D06006C /* KEY_DOWN */
540 0x0D070069 /* KEY_LEFT */
541 0x0E000057 /* KEY_F11 */
542 0x0E010058 /* KEY_F12 */
543 0x0E020042 /* KEY_F8 */
544 0x0E030010 /* KEY_Q */
545 0x0E04003E /* KEY_F4 */
546 0x0E05003D /* KEY_F3 */
547 0x0E060002 /* KEY_1 */
548 0x0E070041 /* KEY_F7 */
549 0x0F000001 /* KEY_ESC */
550 0x0F010029 /* KEY_GRAVE */
551 0x0F02003F /* KEY_F5 */
552 0x0F03000F /* KEY_TAB */
553 0x0F04003B /* KEY_F1 */
554 0x0F05003C /* KEY_F2 */
555 0x0F06003A /* KEY_CAPSLOCK */
556 0x0F070040 /* KEY_F6 */
557 0x14000047 /* KEY_KP7 */
558 0x15000049 /* KEY_KP9 */
559 0x15010048 /* KEY_KP8 */
560 0x1502004B /* KEY_KP4 */
561 0x1504004F /* KEY_KP1 */
562 0x1601004E /* KEY_KPSLASH */
563 0x1602004D /* KEY_KP6 */
564 0x1603004C /* KEY_KP5 */
565 0x16040051 /* KEY_KP3 */
566 0x16050050 /* KEY_KP2 */
567 0x16070052 /* KEY_KP0 */
568 0x1B010037 /* KEY_KPASTERISK */
569 0x1B03004A /* KEY_KPMINUS */
570 0x1B04004E /* KEY_KPPLUS */
571 0x1B050053 /* KEY_KPDOT */
572 0x1C050073 /* KEY_VOLUMEUP */
573 0x1D030066 /* KEY_HOME */
574 0x1D04006B /* KEY_END */
575 0x1D0500E1 /* KEY_BRIGHTNESSUP */
576 0x1D060072 /* KEY_VOLUMEDOWN */
577 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
578 0x1E000045 /* KEY_NUMLOCK */
579 0x1E010046 /* KEY_SCROLLLOCK */
580 0x1E020071 /* KEY_MUTE */
581 0x1F0400D6>; /* KEY_QUESTION */
582 };
583
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000584 regulators {
585 compatible = "simple-bus";
586 #address-cells = <1>;
587 #size-cells = <0>;
588
589 vdd_5v0_reg: regulator@0 {
590 compatible = "regulator-fixed";
591 reg = <0>;
592 regulator-name = "vdd_5v0";
593 regulator-min-microvolt = <5000000>;
594 regulator-max-microvolt = <5000000>;
595 regulator-always-on;
596 };
597
598 regulator@1 {
599 compatible = "regulator-fixed";
600 reg = <1>;
601 regulator-name = "vdd_1v5";
602 regulator-min-microvolt = <1500000>;
603 regulator-max-microvolt = <1500000>;
604 gpio = <&pmic 0 0>;
605 };
606
607 regulator@2 {
608 compatible = "regulator-fixed";
609 reg = <2>;
610 regulator-name = "vdd_1v2";
611 regulator-min-microvolt = <1200000>;
612 regulator-max-microvolt = <1200000>;
613 gpio = <&pmic 1 0>;
614 enable-active-high;
615 };
616
617 regulator@3 {
618 compatible = "regulator-fixed";
619 reg = <3>;
620 regulator-name = "vdd_1v05";
621 regulator-min-microvolt = <1050000>;
622 regulator-max-microvolt = <1050000>;
623 gpio = <&pmic 2 0>;
624 enable-active-high;
625 /* Hack until board-harmony-pcie.c is removed */
626 status = "disabled";
627 };
628
629 regulator@4 {
630 compatible = "regulator-fixed";
631 reg = <4>;
632 regulator-name = "vdd_pnl";
633 regulator-min-microvolt = <2800000>;
634 regulator-max-microvolt = <2800000>;
635 gpio = <&gpio 22 0>; /* gpio PC6 */
636 enable-active-high;
637 };
638
639 regulator@5 {
640 compatible = "regulator-fixed";
641 reg = <5>;
642 regulator-name = "vdd_bl";
643 regulator-min-microvolt = <2800000>;
644 regulator-max-microvolt = <2800000>;
645 gpio = <&gpio 176 0>; /* gpio PW0 */
646 enable-active-high;
647 };
648 };
649
Stephen Warren797acf72012-01-11 16:09:57 -0700650 sound {
651 compatible = "nvidia,tegra-audio-wm8903-harmony",
652 "nvidia,tegra-audio-wm8903";
653 nvidia,model = "NVIDIA Tegra Harmony";
654
655 nvidia,audio-routing =
656 "Headphone Jack", "HPOUTR",
657 "Headphone Jack", "HPOUTL",
658 "Int Spk", "ROP",
659 "Int Spk", "RON",
660 "Int Spk", "LOP",
661 "Int Spk", "LON",
662 "Mic Jack", "MICBIAS",
663 "IN1L", "Mic Jack";
664
665 nvidia,i2s-controller = <&tegra_i2s1>;
666 nvidia,audio-codec = <&wm8903>;
667
668 nvidia,spkr-en-gpios = <&wm8903 2 0>;
669 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
670 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
671 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600672
673 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
674 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600675 };
Grant Likely8e267f32011-07-19 17:26:54 -0600676};