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gerrit-public.fairphone.software / kernel / msm / 00411ee9308e4b5f4b04caaa01685f955e259373 / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: 3105d5e8d9082c675e3b040d8c9bffd8565deb93 [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
Kashyap, Desai31b7f2e2010-03-17 16:28:04 +0530[diff] [blame]2 * Copyright (c) 2000-2010 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]11 * mpi2.h Version: 02.00.18
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
Kashyap, Desai9af05d92011-01-04 11:35:41 +0530[diff] [blame]66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]69 * --------------------------------------------------------------------------
70 */
71
72#ifndef MPI2_H
73#define MPI2_H
74
75
76/*****************************************************************************
77*
78* MPI Version Definitions
79*
80*****************************************************************************/
81
82#define MPI2_VERSION_MAJOR (0x02)
83#define MPI2_VERSION_MINOR (0x00)
84#define MPI2_VERSION_MAJOR_MASK (0xFF00)
85#define MPI2_VERSION_MAJOR_SHIFT (8)
86#define MPI2_VERSION_MINOR_MASK (0x00FF)
87#define MPI2_VERSION_MINOR_SHIFT (0)
88#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
89 MPI2_VERSION_MINOR)
90
91#define MPI2_VERSION_02_00 (0x0200)
92
93/* versioning for this MPI header set */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]94#define MPI2_HEADER_VERSION_UNIT (0x12)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]95#define MPI2_HEADER_VERSION_DEV (0x00)
96#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
97#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
98#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
99#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
100#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
101
102
103/*****************************************************************************
104*
105* IOC State Definitions
106*
107*****************************************************************************/
108
109#define MPI2_IOC_STATE_RESET (0x00000000)
110#define MPI2_IOC_STATE_READY (0x10000000)
111#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
112#define MPI2_IOC_STATE_FAULT (0x40000000)
113
114#define MPI2_IOC_STATE_MASK (0xF0000000)
115#define MPI2_IOC_STATE_SHIFT (28)
116
117/* Fault state range for prodcut specific codes */
118#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
119#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
120
121
122/*****************************************************************************
123*
124* System Interface Register Definitions
125*
126*****************************************************************************/
127
128typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
129{
130 U32 Doorbell; /* 0x00 */
131 U32 WriteSequence; /* 0x04 */
132 U32 HostDiagnostic; /* 0x08 */
133 U32 Reserved1; /* 0x0C */
134 U32 DiagRWData; /* 0x10 */
135 U32 DiagRWAddressLow; /* 0x14 */
136 U32 DiagRWAddressHigh; /* 0x18 */
137 U32 Reserved2[5]; /* 0x1C */
138 U32 HostInterruptStatus; /* 0x30 */
139 U32 HostInterruptMask; /* 0x34 */
140 U32 DCRData; /* 0x38 */
141 U32 DCRAddress; /* 0x3C */
142 U32 Reserved3[2]; /* 0x40 */
143 U32 ReplyFreeHostIndex; /* 0x48 */
144 U32 Reserved4[8]; /* 0x4C */
145 U32 ReplyPostHostIndex; /* 0x6C */
146 U32 Reserved5; /* 0x70 */
147 U32 HCBSize; /* 0x74 */
148 U32 HCBAddressLow; /* 0x78 */
149 U32 HCBAddressHigh; /* 0x7C */
150 U32 Reserved6[16]; /* 0x80 */
151 U32 RequestDescriptorPostLow; /* 0xC0 */
152 U32 RequestDescriptorPostHigh; /* 0xC4 */
153 U32 Reserved7[14]; /* 0xC8 */
154} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
155 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
156
157/*
158 * Defines for working with the Doorbell register.
159 */
160#define MPI2_DOORBELL_OFFSET (0x00000000)
161
162/* IOC --> System values */
163#define MPI2_DOORBELL_USED (0x08000000)
164#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
165#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
166#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
167#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
168
169/* System --> IOC values */
170#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
171#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
172#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
173#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
174
175
176/*
177 * Defines for the WriteSequence register
178 */
179#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
180#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
181#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
182#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
183#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
184#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
185#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
186#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
187#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
188
189/*
190 * Defines for the HostDiagnostic register
191 */
192#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
193
194#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
195#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
196#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
197
198#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
199#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
200#define MPI2_DIAG_HCB_MODE (0x00000100)
201#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
202#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
203#define MPI2_DIAG_RESET_HISTORY (0x00000020)
204#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
205#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
206#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
207
208/*
209 * Offsets for DiagRWData and address
210 */
211#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
212#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
213#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
214
215/*
216 * Defines for the HostInterruptStatus register
217 */
218#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
219#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
220#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
221#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
222#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
223#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
224#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
225
226/*
227 * Defines for the HostInterruptMask register
228 */
229#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
230#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
231#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
232#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
233#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
234#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
235
236/*
237 * Offsets for DCRData and address
238 */
239#define MPI2_DCR_DATA_OFFSET (0x00000038)
240#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
241
242/*
243 * Offset for the Reply Free Queue
244 */
245#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
246
247/*
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]248 * Defines for the Reply Descriptor Post Queue
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]249 */
250#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]251#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
252#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
253#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]254
255/*
256 * Defines for the HCBSize and address
257 */
258#define MPI2_HCB_SIZE_OFFSET (0x00000074)
259#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
260#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
261
262#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
263#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
264
265/*
266 * Offsets for the Request Queue
267 */
268#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
269#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
270
271
272/*****************************************************************************
273*
274* Message Descriptors
275*
276*****************************************************************************/
277
278/* Request Descriptors */
279
280/* Default Request Descriptor */
281typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
282{
283 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]284 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]285 U16 SMID; /* 0x02 */
286 U16 LMID; /* 0x04 */
287 U16 DescriptorTypeDependent; /* 0x06 */
288} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
289 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
290 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
291
292/* defines for the RequestFlags field */
293#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
294#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
295#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
296#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
297#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]298#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]299
300#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
301
302
303/* High Priority Request Descriptor */
304typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
305{
306 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]307 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]308 U16 SMID; /* 0x02 */
309 U16 LMID; /* 0x04 */
310 U16 Reserved1; /* 0x06 */
311} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
312 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
313 Mpi2HighPriorityRequestDescriptor_t,
314 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
315
316
317/* SCSI IO Request Descriptor */
318typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
319{
320 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]321 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]322 U16 SMID; /* 0x02 */
323 U16 LMID; /* 0x04 */
324 U16 DevHandle; /* 0x06 */
325} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
326 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
327 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
328
329
330/* SCSI Target Request Descriptor */
331typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
332{
333 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]334 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]335 U16 SMID; /* 0x02 */
336 U16 LMID; /* 0x04 */
337 U16 IoIndex; /* 0x06 */
338} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
339 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
340 Mpi2SCSITargetRequestDescriptor_t,
341 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
342
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]343
344/* RAID Accelerator Request Descriptor */
345typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
346 U8 RequestFlags; /* 0x00 */
347 U8 MSIxIndex; /* 0x01 */
348 U16 SMID; /* 0x02 */
349 U16 LMID; /* 0x04 */
350 U16 Reserved; /* 0x06 */
351} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
352 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
353 Mpi2RAIDAcceleratorRequestDescriptor_t,
354 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
355
356
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]357/* union of Request Descriptors */
358typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
359{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]360 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
361 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
362 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
363 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
364 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
365 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]366} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
367 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
368
369
370/* Reply Descriptors */
371
372/* Default Reply Descriptor */
373typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
374{
375 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]376 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]377 U16 DescriptorTypeDependent1; /* 0x02 */
378 U32 DescriptorTypeDependent2; /* 0x04 */
379} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
380 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
381
382/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]383#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
384#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
385#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
386#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
387#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
388#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
389#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]390
391/* values for marking a reply descriptor as unused */
392#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
393#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
394
395/* Address Reply Descriptor */
396typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
397{
398 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]399 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]400 U16 SMID; /* 0x02 */
401 U32 ReplyFrameAddress; /* 0x04 */
402} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
403 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
404
405#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
406
407
408/* SCSI IO Success Reply Descriptor */
409typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
410{
411 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]412 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]413 U16 SMID; /* 0x02 */
414 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]415 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]416} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
417 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
418 Mpi2SCSIIOSuccessReplyDescriptor_t,
419 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
420
421
422/* TargetAssist Success Reply Descriptor */
423typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
424{
425 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]426 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]427 U16 SMID; /* 0x02 */
428 U8 SequenceNumber; /* 0x04 */
429 U8 Reserved1; /* 0x05 */
430 U16 IoIndex; /* 0x06 */
431} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
432 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
433 Mpi2TargetAssistSuccessReplyDescriptor_t,
434 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
435
436
437/* Target Command Buffer Reply Descriptor */
438typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
439{
440 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]441 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]442 U8 VP_ID; /* 0x02 */
443 U8 Flags; /* 0x03 */
444 U16 InitiatorDevHandle; /* 0x04 */
445 U16 IoIndex; /* 0x06 */
446} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
447 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
448 Mpi2TargetCommandBufferReplyDescriptor_t,
449 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
450
451/* defines for Flags field */
452#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
453
454
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]455/* RAID Accelerator Success Reply Descriptor */
456typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
457 U8 ReplyFlags; /* 0x00 */
458 U8 MSIxIndex; /* 0x01 */
459 U16 SMID; /* 0x02 */
460 U32 Reserved; /* 0x04 */
461} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
462 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
463 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
464 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
465
466
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]467/* union of Reply Descriptors */
468typedef union _MPI2_REPLY_DESCRIPTORS_UNION
469{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]470 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
471 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
472 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
473 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
474 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
475 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
476 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]477} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
478 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
479
480
481
482/*****************************************************************************
483*
484* Message Functions
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]485*
486*****************************************************************************/
487
488#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
489#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
490#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
491#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
492#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
493#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
494#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
495#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
496#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
497#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
498#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
499#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
500#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
501#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
502#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
503#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
504#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
505#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
506#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
507#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
508#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
509#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
510#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
511#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
512#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]513#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]514/* Host Based Discovery Action */
515#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]516/* Power Management Control */
517#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
518/* beginning of product-specific range */
519#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
520/* end of product-specific range */
521#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
522
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]523
524
525
526/* Doorbell functions */
527#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]528#define MPI2_FUNCTION_HANDSHAKE (0x42)
529
530
531/*****************************************************************************
532*
533* IOC Status Values
534*
535*****************************************************************************/
536
537/* mask for IOCStatus status value */
538#define MPI2_IOCSTATUS_MASK (0x7FFF)
539
540/****************************************************************************
541* Common IOCStatus values for all replies
542****************************************************************************/
543
544#define MPI2_IOCSTATUS_SUCCESS (0x0000)
545#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
546#define MPI2_IOCSTATUS_BUSY (0x0002)
547#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
548#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
549#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
550#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
551#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
552#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
553#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
554
555/****************************************************************************
556* Config IOCStatus values
557****************************************************************************/
558
559#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
560#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
561#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
562#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
563#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
564#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
565
566/****************************************************************************
567* SCSI IO Reply
568****************************************************************************/
569
570#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
571#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
572#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
573#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
574#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
575#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
576#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
577#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
578#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
579#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
580#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
581#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
582
583/****************************************************************************
584* For use by SCSI Initiator and SCSI Target end-to-end data protection
585****************************************************************************/
586
587#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
588#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
589#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
590
591/****************************************************************************
592* SCSI Target values
593****************************************************************************/
594
595#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
596#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
597#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
598#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
599#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
600#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
601#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
602#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
603#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
604#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
605
606/****************************************************************************
607* Serial Attached SCSI values
608****************************************************************************/
609
610#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
611#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
612
613/****************************************************************************
614* Diagnostic Buffer Post / Diagnostic Release values
615****************************************************************************/
616
617#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
618
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]619/****************************************************************************
620* RAID Accelerator values
621****************************************************************************/
622
623#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]624
625/****************************************************************************
626* IOCStatus flag to indicate that log info is available
627****************************************************************************/
628
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]629#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]630
631/****************************************************************************
632* IOCLogInfo Types
633****************************************************************************/
634
635#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
636#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
637#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
638#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
639#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
640#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
641#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
642#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
643
644
645/*****************************************************************************
646*
647* Standard Message Structures
648*
649*****************************************************************************/
650
651/****************************************************************************
652* Request Message Header for all request messages
653****************************************************************************/
654
655typedef struct _MPI2_REQUEST_HEADER
656{
657 U16 FunctionDependent1; /* 0x00 */
658 U8 ChainOffset; /* 0x02 */
659 U8 Function; /* 0x03 */
660 U16 FunctionDependent2; /* 0x04 */
661 U8 FunctionDependent3; /* 0x06 */
662 U8 MsgFlags; /* 0x07 */
663 U8 VP_ID; /* 0x08 */
664 U8 VF_ID; /* 0x09 */
665 U16 Reserved1; /* 0x0A */
666} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
667 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
668
669
670/****************************************************************************
671* Default Reply
672****************************************************************************/
673
674typedef struct _MPI2_DEFAULT_REPLY
675{
676 U16 FunctionDependent1; /* 0x00 */
677 U8 MsgLength; /* 0x02 */
678 U8 Function; /* 0x03 */
679 U16 FunctionDependent2; /* 0x04 */
680 U8 FunctionDependent3; /* 0x06 */
681 U8 MsgFlags; /* 0x07 */
682 U8 VP_ID; /* 0x08 */
683 U8 VF_ID; /* 0x09 */
684 U16 Reserved1; /* 0x0A */
685 U16 FunctionDependent5; /* 0x0C */
686 U16 IOCStatus; /* 0x0E */
687 U32 IOCLogInfo; /* 0x10 */
688} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
689 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
690
691
692/* common version structure/union used in messages and configuration pages */
693
694typedef struct _MPI2_VERSION_STRUCT
695{
696 U8 Dev; /* 0x00 */
697 U8 Unit; /* 0x01 */
698 U8 Minor; /* 0x02 */
699 U8 Major; /* 0x03 */
700} MPI2_VERSION_STRUCT;
701
702typedef union _MPI2_VERSION_UNION
703{
704 MPI2_VERSION_STRUCT Struct;
705 U32 Word;
706} MPI2_VERSION_UNION;
707
708
709/* LUN field defines, common to many structures */
710#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
711#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
712#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
713#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
714#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
715#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
716
717
718/*****************************************************************************
719*
720* Fusion-MPT MPI Scatter Gather Elements
721*
722*****************************************************************************/
723
724/****************************************************************************
725* MPI Simple Element structures
726****************************************************************************/
727
728typedef struct _MPI2_SGE_SIMPLE32
729{
730 U32 FlagsLength;
731 U32 Address;
732} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
733 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
734
735typedef struct _MPI2_SGE_SIMPLE64
736{
737 U32 FlagsLength;
738 U64 Address;
739} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
740 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
741
742typedef struct _MPI2_SGE_SIMPLE_UNION
743{
744 U32 FlagsLength;
745 union
746 {
747 U32 Address32;
748 U64 Address64;
749 } u;
750} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
751 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
752
753
754/****************************************************************************
755* MPI Chain Element structures
756****************************************************************************/
757
758typedef struct _MPI2_SGE_CHAIN32
759{
760 U16 Length;
761 U8 NextChainOffset;
762 U8 Flags;
763 U32 Address;
764} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
765 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
766
767typedef struct _MPI2_SGE_CHAIN64
768{
769 U16 Length;
770 U8 NextChainOffset;
771 U8 Flags;
772 U64 Address;
773} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
774 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
775
776typedef struct _MPI2_SGE_CHAIN_UNION
777{
778 U16 Length;
779 U8 NextChainOffset;
780 U8 Flags;
781 union
782 {
783 U32 Address32;
784 U64 Address64;
785 } u;
786} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
787 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
788
789
790/****************************************************************************
791* MPI Transaction Context Element structures
792****************************************************************************/
793
794typedef struct _MPI2_SGE_TRANSACTION32
795{
796 U8 Reserved;
797 U8 ContextSize;
798 U8 DetailsLength;
799 U8 Flags;
800 U32 TransactionContext[1];
801 U32 TransactionDetails[1];
802} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
803 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
804
805typedef struct _MPI2_SGE_TRANSACTION64
806{
807 U8 Reserved;
808 U8 ContextSize;
809 U8 DetailsLength;
810 U8 Flags;
811 U32 TransactionContext[2];
812 U32 TransactionDetails[1];
813} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
814 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
815
816typedef struct _MPI2_SGE_TRANSACTION96
817{
818 U8 Reserved;
819 U8 ContextSize;
820 U8 DetailsLength;
821 U8 Flags;
822 U32 TransactionContext[3];
823 U32 TransactionDetails[1];
824} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
825 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
826
827typedef struct _MPI2_SGE_TRANSACTION128
828{
829 U8 Reserved;
830 U8 ContextSize;
831 U8 DetailsLength;
832 U8 Flags;
833 U32 TransactionContext[4];
834 U32 TransactionDetails[1];
835} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
836 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
837
838typedef struct _MPI2_SGE_TRANSACTION_UNION
839{
840 U8 Reserved;
841 U8 ContextSize;
842 U8 DetailsLength;
843 U8 Flags;
844 union
845 {
846 U32 TransactionContext32[1];
847 U32 TransactionContext64[2];
848 U32 TransactionContext96[3];
849 U32 TransactionContext128[4];
850 } u;
851 U32 TransactionDetails[1];
852} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
853 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
854
855
856/****************************************************************************
857* MPI SGE union for IO SGL's
858****************************************************************************/
859
860typedef struct _MPI2_MPI_SGE_IO_UNION
861{
862 union
863 {
864 MPI2_SGE_SIMPLE_UNION Simple;
865 MPI2_SGE_CHAIN_UNION Chain;
866 } u;
867} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
868 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
869
870
871/****************************************************************************
872* MPI SGE union for SGL's with Simple and Transaction elements
873****************************************************************************/
874
875typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
876{
877 union
878 {
879 MPI2_SGE_SIMPLE_UNION Simple;
880 MPI2_SGE_TRANSACTION_UNION Transaction;
881 } u;
882} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
883 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
884
885
886/****************************************************************************
887* All MPI SGE types union
888****************************************************************************/
889
890typedef struct _MPI2_MPI_SGE_UNION
891{
892 union
893 {
894 MPI2_SGE_SIMPLE_UNION Simple;
895 MPI2_SGE_CHAIN_UNION Chain;
896 MPI2_SGE_TRANSACTION_UNION Transaction;
897 } u;
898} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
899 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
900
901
902/****************************************************************************
903* MPI SGE field definition and masks
904****************************************************************************/
905
906/* Flags field bit definitions */
907
908#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
909#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
910#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
911#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
912#define MPI2_SGE_FLAGS_DIRECTION (0x04)
913#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
914#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
915
916#define MPI2_SGE_FLAGS_SHIFT (24)
917
918#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
919#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
920
921/* Element Type */
922
923#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
924#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
925#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
926#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
927
928/* Address location */
929
930#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
931
932/* Direction */
933
934#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
935#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
936
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]937#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
938#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
939
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]940/* Address Size */
941
942#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
943#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
944
945/* Context Size */
946
947#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
948#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
949#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
950#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
951
952#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
953#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
954
955/****************************************************************************
956* MPI SGE operation Macros
957****************************************************************************/
958
959/* SIMPLE FlagsLength manipulations... */
960#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
961#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
962#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
963#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
964
965#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
966
967#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
968#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
969#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
970
971/* CAUTION - The following are READ-MODIFY-WRITE! */
972#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
973#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
974
975#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
976
977
978/*****************************************************************************
979*
980* Fusion-MPT IEEE Scatter Gather Elements
981*
982*****************************************************************************/
983
984/****************************************************************************
985* IEEE Simple Element structures
986****************************************************************************/
987
988typedef struct _MPI2_IEEE_SGE_SIMPLE32
989{
990 U32 Address;
991 U32 FlagsLength;
992} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
993 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
994
995typedef struct _MPI2_IEEE_SGE_SIMPLE64
996{
997 U64 Address;
998 U32 Length;
999 U16 Reserved1;
1000 U8 Reserved2;
1001 U8 Flags;
1002} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1003 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1004
1005typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1006{
1007 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1008 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1009} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1010 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1011
1012
1013/****************************************************************************
1014* IEEE Chain Element structures
1015****************************************************************************/
1016
1017typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1018
1019typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1020
1021typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1022{
1023 MPI2_IEEE_SGE_CHAIN32 Chain32;
1024 MPI2_IEEE_SGE_CHAIN64 Chain64;
1025} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1026 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1027
1028
1029/****************************************************************************
1030* All IEEE SGE types union
1031****************************************************************************/
1032
1033typedef struct _MPI2_IEEE_SGE_UNION
1034{
1035 union
1036 {
1037 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1038 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1039 } u;
1040} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1041 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1042
1043
1044/****************************************************************************
1045* IEEE SGE field definitions and masks
1046****************************************************************************/
1047
1048/* Flags field bit definitions */
1049
1050#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1051
1052#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1053
1054#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1055
1056/* Element Type */
1057
1058#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1059#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1060
1061/* Data Location Address Space */
1062
1063#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1064#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1065 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1066#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1067 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1068#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1069#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1070 /* IEEE Simple Element only */
1071#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03)
1072 /* IEEE Chain Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1073
1074/****************************************************************************
1075* IEEE SGE operation Macros
1076****************************************************************************/
1077
1078/* SIMPLE FlagsLength manipulations... */
1079#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1080#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1081#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1082
1083#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1084
1085#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1086#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1087#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1088
1089/* CAUTION - The following are READ-MODIFY-WRITE! */
1090#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1091#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1092
1093
1094
1095
1096/*****************************************************************************
1097*
1098* Fusion-MPT MPI/IEEE Scatter Gather Unions
1099*
1100*****************************************************************************/
1101
1102typedef union _MPI2_SIMPLE_SGE_UNION
1103{
1104 MPI2_SGE_SIMPLE_UNION MpiSimple;
1105 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1106} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1107 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1108
1109
1110typedef union _MPI2_SGE_IO_UNION
1111{
1112 MPI2_SGE_SIMPLE_UNION MpiSimple;
1113 MPI2_SGE_CHAIN_UNION MpiChain;
1114 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1115 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1116} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1117 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1118
1119
1120/****************************************************************************
1121*
1122* Values for SGLFlags field, used in many request messages with an SGL
1123*
1124****************************************************************************/
1125
1126/* values for MPI SGL Data Location Address Space subfield */
1127#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1128#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1129#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1130#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1131#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1132/* values for SGL Type subfield */
1133#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1134#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1135#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1136#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1137
1138
1139#endif
1140