Stephen Boyd | 650e3f0 | 2011-11-08 10:33:03 -0800 | [diff] [blame] | 1 | /* |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 2 | * |
| 3 | * Copyright (C) 2007 Google, Inc. |
| 4 | * Author: Brian Swetland <swetland@google.com> |
| 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and |
| 8 | * may be copied, distributed, and modified under those terms. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
Pavel Machek | 6339f66 | 2009-11-02 11:48:29 +0100 | [diff] [blame] | 17 | |
| 18 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 19 | #include <mach/hardware.h> |
| 20 | #include <mach/msm_iomap.h> |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 21 | #include <mach/msm_serial_hsl_regs.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | |
Stephen Boyd | 650e3f0 | 2011-11-08 10:33:03 -0800 | [diff] [blame] | 23 | #ifdef MSM_DEBUG_UART_PHYS |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 24 | .macro addruart, rp, rv, tmp |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 25 | ldr \rp, =MSM_DEBUG_UART_PHYS |
| 26 | ldr \rv, =MSM_DEBUG_UART_BASE |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | .endm |
| 28 | |
| 29 | .macro senduart,rd,rx |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 30 | #ifdef CONFIG_MSM_HAS_DEBUG_UART_HS |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 31 | @ Clear TX_READY by writing to the UARTDM_CR register |
| 32 | mov r12, #0x300 |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 33 | str r12, [\rx, #UARTDM_CR_OFFSET] |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 34 | @ Write 0x1 to NCF register |
| 35 | mov r12, #0x1 |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 36 | str r12, [\rx, #UARTDM_NCF_TX_OFFSET] |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 37 | @ UARTDM reg. Read to induce delay |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 38 | ldr r12, [\rx, #UARTDM_SR_OFFSET] |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 39 | @ Write the 1 character to UARTDM_TF |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 40 | str \rd, [\rx, #UARTDM_TF_OFFSET] |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 41 | #else |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 42 | teq \rx, #0 |
| 43 | strne \rd, [\rx, #0x0C] |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 44 | #endif |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 45 | .endm |
| 46 | |
| 47 | .macro waituart,rd,rx |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 48 | #ifdef CONFIG_MSM_HAS_DEBUG_UART_HS |
| 49 | @ check for TX_EMT in UARTDM_SR |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 50 | ldr \rd, [\rx, #UARTDM_SR_OFFSET] |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 51 | tst \rd, #0x08 |
| 52 | bne 1002f |
| 53 | @ wait for TXREADY in UARTDM_ISR |
Sathish Ambley | f5bebd6 | 2011-11-03 23:36:36 -0700 | [diff] [blame] | 54 | 1001: ldreq \rd, [\rx, #UARTDM_ISR_OFFSET] |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 55 | tst \rd, #0x80 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 56 | dsb |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 57 | beq 1001b |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 58 | #else |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 59 | @ wait for TX_READY |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 60 | 1001: ldr \rd, [\rx, #0x08] |
| 61 | tst \rd, #0x04 |
| 62 | beq 1001b |
Stephen Boyd | a3d3ef9 | 2011-11-08 10:33:04 -0800 | [diff] [blame] | 63 | #endif |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 64 | 1002: |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 65 | .endm |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 66 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 67 | #else |
| 68 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 69 | .macro addruart, rp, rv |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 70 | .endm |
| 71 | |
| 72 | .macro senduart,rd,rx |
| 73 | .endm |
| 74 | |
| 75 | .macro waituart,rd,rx |
| 76 | .endm |
| 77 | #endif |
| 78 | |
| 79 | .macro busyuart,rd,rx |
| 80 | .endm |