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Stephen Boyd650e3f02011-11-08 10:33:03 -08001/*
Russell Kinga09e64f2008-08-05 16:14:15 +01002 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Pavel Machek6339f662009-11-02 11:48:29 +010017
18
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/hardware.h>
20#include <mach/msm_iomap.h>
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070021#include <mach/msm_serial_hsl_regs.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022
Stephen Boyd650e3f02011-11-08 10:33:03 -080023#ifdef MSM_DEBUG_UART_PHYS
Steve Mucklef132c6c2012-06-06 18:30:57 -070024 .macro addruart, rp, rv, tmp
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025 ldr \rp, =MSM_DEBUG_UART_PHYS
26 ldr \rv, =MSM_DEBUG_UART_BASE
Russell Kinga09e64f2008-08-05 16:14:15 +010027 .endm
28
29 .macro senduart,rd,rx
Stephen Boyda3d3ef92011-11-08 10:33:04 -080030#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031 @ Clear TX_READY by writing to the UARTDM_CR register
32 mov r12, #0x300
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070033 str r12, [\rx, #UARTDM_CR_OFFSET]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070034 @ Write 0x1 to NCF register
35 mov r12, #0x1
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070036 str r12, [\rx, #UARTDM_NCF_TX_OFFSET]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070037 @ UARTDM reg. Read to induce delay
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070038 ldr r12, [\rx, #UARTDM_SR_OFFSET]
Stephen Boyda3d3ef92011-11-08 10:33:04 -080039 @ Write the 1 character to UARTDM_TF
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070040 str \rd, [\rx, #UARTDM_TF_OFFSET]
Stephen Boyda3d3ef92011-11-08 10:33:04 -080041#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042 teq \rx, #0
43 strne \rd, [\rx, #0x0C]
Stephen Boyda3d3ef92011-11-08 10:33:04 -080044#endif
Russell Kinga09e64f2008-08-05 16:14:15 +010045 .endm
46
47 .macro waituart,rd,rx
Stephen Boyda3d3ef92011-11-08 10:33:04 -080048#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
49 @ check for TX_EMT in UARTDM_SR
Sathish Ambleyf5bebd62011-11-03 23:36:36 -070050 ldr \rd, [\rx, #UARTDM_SR_OFFSET]
Stephen Boyda3d3ef92011-11-08 10:33:04 -080051 tst \rd, #0x08
52 bne 1002f
53 @ wait for TXREADY in UARTDM_ISR
Sathish Ambleyf5bebd62011-11-03 23:36:36 -0700541001: ldreq \rd, [\rx, #UARTDM_ISR_OFFSET]
Stephen Boyda3d3ef92011-11-08 10:33:04 -080055 tst \rd, #0x80
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056 dsb
Stephen Boyda3d3ef92011-11-08 10:33:04 -080057 beq 1001b
Stephen Boyda3d3ef92011-11-08 10:33:04 -080058#else
Russell Kinga09e64f2008-08-05 16:14:15 +010059 @ wait for TX_READY
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700601001: ldr \rd, [\rx, #0x08]
61 tst \rd, #0x04
62 beq 1001b
Stephen Boyda3d3ef92011-11-08 10:33:04 -080063#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700641002:
Russell Kinga09e64f2008-08-05 16:14:15 +010065 .endm
Russell Kinga09e64f2008-08-05 16:14:15 +010066
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070067#else
68
Russell Kinga09e64f2008-08-05 16:14:15 +010069 .macro addruart, rp, rv
Russell Kinga09e64f2008-08-05 16:14:15 +010070 .endm
71
72 .macro senduart,rd,rx
73 .endm
74
75 .macro waituart,rd,rx
76 .endm
77#endif
78
79 .macro busyuart,rd,rx
80 .endm