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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/arm/mach-pxa/time.c
3 *
Bill Gatliff7bbb18c2007-07-21 03:39:36 +01004 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
6 *
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/kernel.h>
16#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/interrupt.h>
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010018#include <linux/clockchips.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010020#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/mach/irq.h>
22#include <asm/mach/time.h>
Russell King7ce83012010-12-15 21:48:15 +000023#include <asm/sched_clock.h>
Eric Miao5bf3df32009-01-20 11:04:16 +080024#include <mach/regs-ost.h>
Rob Herring4e611092012-01-03 16:53:48 -060025#include <mach/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010027/*
28 * This is PXA's sched_clock implementation. This has a resolution
29 * of at least 308 ns and a maximum value of 208 days.
30 *
31 * The return value is guaranteed to be monotonic in that range as
32 * long as there is always less than 582 seconds between successive
33 * calls to sched_clock() which should always be the case in practice.
34 */
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010035
Marc Zyngier2f0778af2011-12-15 12:19:23 +010036static u32 notrace pxa_read_sched_clock(void)
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010037{
Marc Zyngier2f0778af2011-12-15 12:19:23 +010038 return OSCR;
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010039}
40
41
Russell Kinga88264c2007-11-12 22:45:16 +000042#define MIN_OSCR_DELTA 16
43
Linus Torvalds1da177e2005-04-16 15:20:36 -070044static irqreturn_t
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010045pxa_ost0_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046{
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010047 struct clock_event_device *c = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Russell Kinga88264c2007-11-12 22:45:16 +000049 /* Disarm the compare/match, signal the event. */
50 OIER &= ~OIER_E0;
51 OSSR = OSSR_M0;
52 c->event_handler(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54 return IRQ_HANDLED;
55}
56
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010057static int
58pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
59{
Uwe Kleine-Königa602f0f2009-12-17 12:43:29 +010060 unsigned long next, oscr;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010061
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010062 OIER |= OIER_E0;
Russell King91bc51d2007-11-08 23:35:46 +000063 next = OSCR + delta;
64 OSMR0 = next;
65 oscr = OSCR;
Russell King91bc51d2007-11-08 23:35:46 +000066
67 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010068}
69
70static void
71pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
72{
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010073 switch (mode) {
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010074 case CLOCK_EVT_MODE_ONESHOT:
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010075 OIER &= ~OIER_E0;
Russell King91bc51d2007-11-08 23:35:46 +000076 OSSR = OSSR_M0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010077 break;
78
79 case CLOCK_EVT_MODE_UNUSED:
80 case CLOCK_EVT_MODE_SHUTDOWN:
81 /* initializing, released, or preparing for suspend */
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010082 OIER &= ~OIER_E0;
Russell King91bc51d2007-11-08 23:35:46 +000083 OSSR = OSSR_M0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010084 break;
Russell Kingdf433092007-10-27 15:15:49 +010085
86 case CLOCK_EVT_MODE_RESUME:
Russell Kinga88264c2007-11-12 22:45:16 +000087 case CLOCK_EVT_MODE_PERIODIC:
Russell Kingdf433092007-10-27 15:15:49 +010088 break;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010089 }
90}
91
92static struct clock_event_device ckevt_pxa_osmr0 = {
93 .name = "osmr0",
Russell Kinga88264c2007-11-12 22:45:16 +000094 .features = CLOCK_EVT_FEAT_ONESHOT,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010095 .rating = 200,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010096 .set_next_event = pxa_osmr0_set_next_event,
97 .set_mode = pxa_osmr0_set_mode,
Linus Torvalds1da177e2005-04-16 15:20:36 -070098};
99
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100100static struct irqaction pxa_ost0_irq = {
101 .name = "ost0",
102 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
103 .handler = pxa_ost0_interrupt,
104 .dev_id = &ckevt_pxa_osmr0,
105};
106
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107static void __init pxa_timer_init(void)
108{
Eric Miao67697172008-12-18 11:10:32 +0800109 unsigned long clock_tick_rate = get_clock_tick_rate();
Russell King08197f62007-09-01 21:12:50 +0100110
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100111 OIER = 0;
112 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
Nicolas Pitre6c3a1582007-08-17 16:55:22 +0100115
Haojian Zhuangccc46e22010-11-24 11:54:23 +0800116 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100117 ckevt_pxa_osmr0.max_delta_ns =
118 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
119 ckevt_pxa_osmr0.min_delta_ns =
Russell Kingdd01b2f2008-01-23 12:34:16 +0000120 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
Rusty Russell320ab2b2008-12-13 21:20:26 +1030121 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100123 setup_irq(IRQ_OST0, &pxa_ost0_irq);
124
Russell King234b6ce2011-05-08 14:09:47 +0100125 clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
126 clocksource_mmio_readl_up);
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100127 clockevents_register_device(&ckevt_pxa_osmr0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128}
129
130#ifdef CONFIG_PM
Russell King4ae78062007-11-12 22:48:12 +0000131static unsigned long osmr[4], oier, oscr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133static void pxa_timer_suspend(void)
134{
135 osmr[0] = OSMR0;
136 osmr[1] = OSMR1;
137 osmr[2] = OSMR2;
138 osmr[3] = OSMR3;
139 oier = OIER;
Russell King4ae78062007-11-12 22:48:12 +0000140 oscr = OSCR;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141}
142
143static void pxa_timer_resume(void)
144{
Russell King4ae78062007-11-12 22:48:12 +0000145 /*
146 * Ensure that we have at least MIN_OSCR_DELTA between match
147 * register 0 and the OSCR, to guarantee that we will receive
148 * the one-shot timer interrupt. We adjust OSMR0 in preference
149 * to OSCR to guarantee that OSCR is monotonically incrementing.
150 */
151 if (osmr[0] - oscr < MIN_OSCR_DELTA)
152 osmr[0] += MIN_OSCR_DELTA;
153
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 OSMR0 = osmr[0];
155 OSMR1 = osmr[1];
156 OSMR2 = osmr[2];
157 OSMR3 = osmr[3];
158 OIER = oier;
Russell King4ae78062007-11-12 22:48:12 +0000159 OSCR = oscr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160}
161#else
162#define pxa_timer_suspend NULL
163#define pxa_timer_resume NULL
164#endif
165
166struct sys_timer pxa_timer = {
167 .init = pxa_timer_init,
168 .suspend = pxa_timer_suspend,
169 .resume = pxa_timer_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170};