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gerrit-public.fairphone.software / kernel / msm / 0d6c97742993a00ee2cbfbd6d68fba669c17bf50 / . / arch / arm / mach-davinci / include / mach / asp.h
blob: 019c647334174b263199d5ed2f1a9e82639233e4 [file] [log] [blame]
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]1/*
2 * <mach/asp.h> - DaVinci Audio Serial Port support
3 */
4#ifndef __ASM_ARCH_DAVINCI_ASP_H
5#define __ASM_ARCH_DAVINCI_ASP_H
6
7#include <mach/irqs.h>
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]8#include <mach/edma.h>
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]9
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]10/* Bases of dm644x and dm355 register banks */
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]11#define DAVINCI_ASP0_BASE 0x01E02000
12#define DAVINCI_ASP1_BASE 0x01E04000
13
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]14/* Bases of dm646x register banks */
15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
17
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]18/* Bases of da850/da830 McASP0 register banks */
19#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
20
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]21/* Bases of da830 McASP1 register banks */
22#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
23
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]24/* EDMA channels of dm644x and dm355 */
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]25#define DAVINCI_DMA_ASP0_TX 2
26#define DAVINCI_DMA_ASP0_RX 3
27#define DAVINCI_DMA_ASP1_TX 8
28#define DAVINCI_DMA_ASP1_RX 9
29
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]30/* EDMA channels of dm646x */
31#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
32#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
33#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
34
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]35/* EDMA channels of da850/da830 McASP0 */
36#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
37#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
38
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]39/* EDMA channels of da830 McASP1 */
40#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
41#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
42
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]43/* Interrupts */
44#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
45#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
46#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
47#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
48
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]49struct snd_platform_data {
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]50 u32 tx_dma_offset;
51 u32 rx_dma_offset;
52 enum dma_event_q eventq_no; /* event queue number */
53 unsigned int codec_fmt;
Troy Kisky0d6c9772009-11-18 17:49:51 -0700[diff] [blame^]54 /*
55 * Allowing this is more efficient and eliminates left and right swaps
56 * caused by underruns, but will swap the left and right channels
57 * when compared to previous behavior.
58 */
59 unsigned enable_channel_combine:1;
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]60
61 /* McASP specific fields */
62 int tdm_slots;
63 u8 op_mode;
64 u8 num_serializer;
65 u8 *serial_dir;
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]66 u8 version;
67 u8 txnumevt;
68 u8 rxnumevt;
69};
70
71enum {
72 MCASP_VERSION_1 = 0, /* DM646x */
73 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]74};
75
76#define INACTIVE_MODE 0
77#define TX_MODE 1
78#define RX_MODE 2
79
80#define DAVINCI_MCASP_IIS_MODE 0
81#define DAVINCI_MCASP_DIT_MODE 1
82
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]83#endif /* __ASM_ARCH_DAVINCI_ASP_H */