blob: 8a68cea4a3ee6af7860ae65f4ccab119b10cc425 [file] [log] [blame]
Mark Browna2342ae2009-07-29 21:21:49 +01001/*
2 * wm_hubs.c -- WM8993/4 common code
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
Mark Brown79ef0ab2011-08-01 13:02:17 +090020#include <linux/mfd/wm8994/registers.h>
Mark Browna2342ae2009-07-29 21:21:49 +010021#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
Mark Browna2342ae2009-07-29 21:21:49 +010025#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "wm8993.h"
29#include "wm_hubs.h"
30
31const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
32EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
33
34static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
35static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
36static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
37static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
38static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
39static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
40static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
41static const unsigned int spkboost_tlv[] = {
Clemens Ladisch028aa632011-11-20 15:15:31 +010042 TLV_DB_RANGE_HEAD(2),
Mark Browna2342ae2009-07-29 21:21:49 +010043 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
44 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
45};
46static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
47
48static const char *speaker_ref_text[] = {
49 "SPKVDD/2",
50 "VMID",
51};
52
53static const struct soc_enum speaker_ref =
54 SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
55
56static const char *speaker_mode_text[] = {
57 "Class D",
58 "Class AB",
59};
60
61static const struct soc_enum speaker_mode =
62 SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
63
Mark Brown4dcc93d2010-03-29 17:18:41 +010064static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
Mark Browna2342ae2009-07-29 21:21:49 +010065{
Mark Brownd96ca3c2011-07-12 15:25:03 +090066 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Browna2342ae2009-07-29 21:21:49 +010067 unsigned int reg;
68 int count = 0;
Mark Brown1479c3f2011-07-15 17:33:26 +090069 int timeout;
Mark Brown4dcc93d2010-03-29 17:18:41 +010070 unsigned int val;
71
72 val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
73
74 /* Trigger the command */
75 snd_soc_write(codec, WM8993_DC_SERVO_0, val);
Mark Browna2342ae2009-07-29 21:21:49 +010076
77 dev_dbg(codec->dev, "Waiting for DC servo...\n");
Mark Brown3ed70742010-01-20 17:39:45 +000078
Mark Brown1479c3f2011-07-15 17:33:26 +090079 if (hubs->dcs_done_irq)
80 timeout = 4;
81 else
82 timeout = 400;
83
84 do {
85 count++;
86
87 if (hubs->dcs_done_irq)
88 wait_for_completion_timeout(&hubs->dcs_done,
89 msecs_to_jiffies(250));
90 else
91 msleep(1);
Mark Brownd96ca3c2011-07-12 15:25:03 +090092
Mark Brown4dcc93d2010-03-29 17:18:41 +010093 reg = snd_soc_read(codec, WM8993_DC_SERVO_0);
Mark Brown1479c3f2011-07-15 17:33:26 +090094 dev_dbg(codec->dev, "DC servo: %x\n", reg);
95 } while (reg & op && count < timeout);
Mark Browna2342ae2009-07-29 21:21:49 +010096
Mark Brown4dcc93d2010-03-29 17:18:41 +010097 if (reg & op)
Mark Brown5a9f91c2011-02-17 12:05:46 -080098 dev_err(codec->dev, "Timed out waiting for DC Servo %x\n",
99 op);
Mark Browna2342ae2009-07-29 21:21:49 +0100100}
101
Mark Brownd96ca3c2011-07-12 15:25:03 +0900102irqreturn_t wm_hubs_dcs_done(int irq, void *data)
103{
104 struct wm_hubs_data *hubs = data;
105
106 complete(&hubs->dcs_done);
107
108 return IRQ_HANDLED;
109}
110EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
111
Mark Browna2342ae2009-07-29 21:21:49 +0100112/*
Mark Brown3ed70742010-01-20 17:39:45 +0000113 * Startup calibration of the DC servo
114 */
115static void calibrate_dc_servo(struct snd_soc_codec *codec)
116{
Mark Brownb2c812e2010-04-14 15:35:19 +0900117 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Brown20a4e7f2011-01-21 12:47:33 +0000118 s8 offset;
Mark Brown79ef0ab2011-08-01 13:02:17 +0900119 u16 reg, reg_l, reg_r, dcs_cfg, dcs_reg;
120
121 switch (hubs->dcs_readback_mode) {
122 case 2:
123 dcs_reg = WM8994_DC_SERVO_4E;
124 break;
125 default:
126 dcs_reg = WM8993_DC_SERVO_3;
127 break;
128 }
Mark Brown3ed70742010-01-20 17:39:45 +0000129
Mark Brownfec6dd82010-10-27 13:48:36 -0700130 /* If we're using a digital only path and have a previously
131 * callibrated DC servo offset stored then use that. */
132 if (hubs->class_w && hubs->class_w_dcs) {
133 dev_dbg(codec->dev, "Using cached DC servo offset %x\n",
134 hubs->class_w_dcs);
Mark Brown79ef0ab2011-08-01 13:02:17 +0900135 snd_soc_write(codec, dcs_reg, hubs->class_w_dcs);
Mark Brownfec6dd82010-10-27 13:48:36 -0700136 wait_for_dc_servo(codec,
137 WM8993_DCS_TRIG_DAC_WR_0 |
138 WM8993_DCS_TRIG_DAC_WR_1);
139 return;
140 }
141
Mark Brownf9acf9f2011-06-07 23:23:52 +0100142 if (hubs->series_startup) {
Mark Brown11cef5f2010-11-26 17:23:44 +0000143 /* Set for 32 series updates */
144 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
145 WM8993_DCS_SERIES_NO_01_MASK,
146 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
147 wait_for_dc_servo(codec,
148 WM8993_DCS_TRIG_SERIES_0 |
149 WM8993_DCS_TRIG_SERIES_1);
150 } else {
151 wait_for_dc_servo(codec,
152 WM8993_DCS_TRIG_STARTUP_0 |
153 WM8993_DCS_TRIG_STARTUP_1);
154 }
Mark Brown3ed70742010-01-20 17:39:45 +0000155
Mark Brownfec6dd82010-10-27 13:48:36 -0700156 /* Different chips in the family support different readback
157 * methods.
158 */
159 switch (hubs->dcs_readback_mode) {
160 case 0:
161 reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
Joe Perchesef995e32010-11-15 09:09:17 -0800162 & WM8993_DCS_INTEG_CHAN_0_MASK;
Mark Brownfec6dd82010-10-27 13:48:36 -0700163 reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
164 & WM8993_DCS_INTEG_CHAN_1_MASK;
165 break;
Mark Brown79ef0ab2011-08-01 13:02:17 +0900166 case 2:
Mark Brownfec6dd82010-10-27 13:48:36 -0700167 case 1:
Mark Brown79ef0ab2011-08-01 13:02:17 +0900168 reg = snd_soc_read(codec, dcs_reg);
Mark Brownd5b040c2011-06-07 23:28:45 +0100169 reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
Mark Brownfec6dd82010-10-27 13:48:36 -0700170 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
Mark Brownd5b040c2011-06-07 23:28:45 +0100171 reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
Mark Brownfec6dd82010-10-27 13:48:36 -0700172 break;
173 default:
Mark Brown9e3be1e2010-11-02 09:58:49 -0400174 WARN(1, "Unknown DCS readback method\n");
Mark Brownfec6dd82010-10-27 13:48:36 -0700175 break;
176 }
177
178 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
179
Mark Brown3ed70742010-01-20 17:39:45 +0000180 /* Apply correction to DC servo result */
Mark Brown4537c4e2011-08-01 13:10:16 +0900181 if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
182 dev_dbg(codec->dev,
183 "Applying %d/%d code DC servo correction\n",
184 hubs->dcs_codes_l, hubs->dcs_codes_r);
Mark Brown3ed70742010-01-20 17:39:45 +0000185
Mark Brownd5b040c2011-06-07 23:28:45 +0100186 /* HPOUT1R */
187 offset = reg_r;
Mark Brown4537c4e2011-08-01 13:10:16 +0900188 offset += hubs->dcs_codes_r;
Mark Brown20a4e7f2011-01-21 12:47:33 +0000189 dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
Mark Brown3ed70742010-01-20 17:39:45 +0000190
Mark Brownd5b040c2011-06-07 23:28:45 +0100191 /* HPOUT1L */
192 offset = reg_l;
Mark Brown4537c4e2011-08-01 13:10:16 +0900193 offset += hubs->dcs_codes_l;
Mark Brown20a4e7f2011-01-21 12:47:33 +0000194 dcs_cfg |= (u8)offset;
Mark Brown3ed70742010-01-20 17:39:45 +0000195
Mark Brown3254d282010-05-10 14:56:03 +0100196 dev_dbg(codec->dev, "DCS result: %x\n", dcs_cfg);
197
Mark Brown3ed70742010-01-20 17:39:45 +0000198 /* Do it */
Mark Brown79ef0ab2011-08-01 13:02:17 +0900199 snd_soc_write(codec, dcs_reg, dcs_cfg);
Mark Brown4dcc93d2010-03-29 17:18:41 +0100200 wait_for_dc_servo(codec,
201 WM8993_DCS_TRIG_DAC_WR_0 |
202 WM8993_DCS_TRIG_DAC_WR_1);
Mark Brownfec6dd82010-10-27 13:48:36 -0700203 } else {
Mark Brownd5b040c2011-06-07 23:28:45 +0100204 dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
205 dcs_cfg |= reg_l;
Mark Brown3ed70742010-01-20 17:39:45 +0000206 }
Mark Brownfec6dd82010-10-27 13:48:36 -0700207
208 /* Save the callibrated offset if we're in class W mode and
209 * therefore don't have any analogue signal mixed in. */
210 if (hubs->class_w)
211 hubs->class_w_dcs = dcs_cfg;
Mark Brown3ed70742010-01-20 17:39:45 +0000212}
213
214/*
Mark Browna2342ae2009-07-29 21:21:49 +0100215 * Update the DC servo calibration on gain changes
216 */
217static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
Mark Brown3ed70742010-01-20 17:39:45 +0000218 struct snd_ctl_elem_value *ucontrol)
Mark Browna2342ae2009-07-29 21:21:49 +0100219{
220 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brownb2c812e2010-04-14 15:35:19 +0900221 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Browna2342ae2009-07-29 21:21:49 +0100222 int ret;
223
Peter Ujfalusic4671a92011-10-06 09:59:12 +0300224 ret = snd_soc_put_volsw(kcontrol, ucontrol);
Mark Browna2342ae2009-07-29 21:21:49 +0100225
Mark Brownfec6dd82010-10-27 13:48:36 -0700226 /* Updating the analogue gains invalidates the DC servo cache */
227 hubs->class_w_dcs = 0;
228
Mark Brownae9d8602010-03-29 16:34:42 +0100229 /* If we're applying an offset correction then updating the
230 * callibration would be likely to introduce further offsets. */
Mark Brown4537c4e2011-08-01 13:10:16 +0900231 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
Mark Brownae9d8602010-03-29 16:34:42 +0100232 return ret;
233
Mark Browna2342ae2009-07-29 21:21:49 +0100234 /* Only need to do this if the outputs are active */
235 if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
236 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
237 snd_soc_update_bits(codec,
238 WM8993_DC_SERVO_0,
239 WM8993_DCS_TRIG_SINGLE_0 |
240 WM8993_DCS_TRIG_SINGLE_1,
241 WM8993_DCS_TRIG_SINGLE_0 |
242 WM8993_DCS_TRIG_SINGLE_1);
243
244 return ret;
245}
246
247static const struct snd_kcontrol_new analogue_snd_controls[] = {
248SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
249 inpga_tlv),
250SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800251SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100252
253SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
254 inpga_tlv),
255SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800256SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100257
258
259SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
260 inpga_tlv),
261SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800262SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100263
264SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
265 inpga_tlv),
266SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800267SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100268
269SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
270 inmix_sw_tlv),
271SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
272 inmix_sw_tlv),
273SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
274 inmix_tlv),
275SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
276SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
277 inmix_tlv),
278
279SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
280 inmix_sw_tlv),
281SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
282 inmix_sw_tlv),
283SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
284 inmix_tlv),
285SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
286SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
287 inmix_tlv),
288
289SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
290 outmix_tlv),
291SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
292 outmix_tlv),
293SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
294 outmix_tlv),
295SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
296 outmix_tlv),
297SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
298 outmix_tlv),
299SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
300 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
301SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
302 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
303SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
304 outmix_tlv),
305
306SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
307 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
308SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
309 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
310SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
311 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
312SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
313 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
314SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
315 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
316SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
317 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
318SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
319 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
320SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
321 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
322
323SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
324 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
325SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
326 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
327SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
328 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
329
330SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
331SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
332
333SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
334 5, 1, 1, wm_hubs_spkmix_tlv),
335SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
336 4, 1, 1, wm_hubs_spkmix_tlv),
337SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
338 3, 1, 1, wm_hubs_spkmix_tlv),
339
340SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
341 5, 1, 1, wm_hubs_spkmix_tlv),
342SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
343 4, 1, 1, wm_hubs_spkmix_tlv),
344SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
345 3, 1, 1, wm_hubs_spkmix_tlv),
346
347SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
348 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
349 0, 3, 1, spkmixout_tlv),
350SOC_DOUBLE_R_TLV("Speaker Volume",
351 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
352 0, 63, 0, outpga_tlv),
353SOC_DOUBLE_R("Speaker Switch",
354 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
355 6, 1, 0),
356SOC_DOUBLE_R("Speaker ZC Switch",
357 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
358 7, 1, 0),
Uk Kimed8cc472010-12-05 17:26:07 +0900359SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
Mark Browna2342ae2009-07-29 21:21:49 +0100360 spkboost_tlv),
361SOC_ENUM("Speaker Reference", speaker_ref),
362SOC_ENUM("Speaker Mode", speaker_mode),
363
Peter Ujfalusi0f9887d2011-10-05 10:29:19 +0300364SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
365 WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
Peter Ujfalusic4671a92011-10-06 09:59:12 +0300366 0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
Peter Ujfalusi0f9887d2011-10-05 10:29:19 +0300367 outpga_tlv),
368
Mark Browna2342ae2009-07-29 21:21:49 +0100369SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
370 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
371SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
372 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
373
374SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
375SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
376SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
377 line_tlv),
378
379SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
380SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
381SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
382 line_tlv),
383};
384
Mark Brown3ed70742010-01-20 17:39:45 +0000385static int hp_supply_event(struct snd_soc_dapm_widget *w,
386 struct snd_kcontrol *kcontrol, int event)
387{
388 struct snd_soc_codec *codec = w->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900389 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Brown3ed70742010-01-20 17:39:45 +0000390
391 switch (event) {
392 case SND_SOC_DAPM_PRE_PMU:
393 switch (hubs->hp_startup_mode) {
394 case 0:
395 break;
396 case 1:
397 /* Enable the headphone amp */
398 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
399 WM8993_HPOUT1L_ENA |
400 WM8993_HPOUT1R_ENA,
401 WM8993_HPOUT1L_ENA |
402 WM8993_HPOUT1R_ENA);
403
404 /* Enable the second stage */
405 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
406 WM8993_HPOUT1L_DLY |
407 WM8993_HPOUT1R_DLY,
408 WM8993_HPOUT1L_DLY |
409 WM8993_HPOUT1R_DLY);
410 break;
411 default:
412 dev_err(codec->dev, "Unknown HP startup mode %d\n",
413 hubs->hp_startup_mode);
414 break;
415 }
416
417 case SND_SOC_DAPM_PRE_PMD:
418 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
419 WM8993_CP_ENA, 0);
420 break;
421 }
422
423 return 0;
424}
425
Mark Browna2342ae2009-07-29 21:21:49 +0100426static int hp_event(struct snd_soc_dapm_widget *w,
427 struct snd_kcontrol *kcontrol, int event)
428{
429 struct snd_soc_codec *codec = w->codec;
430 unsigned int reg = snd_soc_read(codec, WM8993_ANALOGUE_HP_0);
431
432 switch (event) {
433 case SND_SOC_DAPM_POST_PMU:
434 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
435 WM8993_CP_ENA, WM8993_CP_ENA);
436
437 msleep(5);
438
439 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
440 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
441 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
442
443 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
444 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
445
Mark Brown3ed70742010-01-20 17:39:45 +0000446 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
Mark Brownf9925d42011-07-28 12:44:44 +0100447 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
Mark Brown3ed70742010-01-20 17:39:45 +0000448
449 calibrate_dc_servo(codec);
Mark Browna2342ae2009-07-29 21:21:49 +0100450
451 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
452 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
453 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
454 break;
455
456 case SND_SOC_DAPM_PRE_PMD:
Mark Brown3ed70742010-01-20 17:39:45 +0000457 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
Mark Brown6adb26b2010-05-10 16:13:11 +0100458 WM8993_HPOUT1L_OUTP |
459 WM8993_HPOUT1R_OUTP |
Mark Brown3ed70742010-01-20 17:39:45 +0000460 WM8993_HPOUT1L_RMV_SHORT |
461 WM8993_HPOUT1R_RMV_SHORT, 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100462
Mark Brown3ed70742010-01-20 17:39:45 +0000463 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
Mark Brown6adb26b2010-05-10 16:13:11 +0100464 WM8993_HPOUT1L_DLY |
465 WM8993_HPOUT1R_DLY, 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100466
Mark Brown395e4b72010-05-10 21:06:14 +0100467 snd_soc_write(codec, WM8993_DC_SERVO_0, 0);
468
Mark Browna2342ae2009-07-29 21:21:49 +0100469 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
470 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
471 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100472 break;
473 }
474
475 return 0;
476}
477
478static int earpiece_event(struct snd_soc_dapm_widget *w,
479 struct snd_kcontrol *control, int event)
480{
481 struct snd_soc_codec *codec = w->codec;
482 u16 reg = snd_soc_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
483
484 switch (event) {
485 case SND_SOC_DAPM_PRE_PMU:
486 reg |= WM8993_HPOUT2_IN_ENA;
487 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
488 udelay(50);
489 break;
490
491 case SND_SOC_DAPM_POST_PMD:
492 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
493 break;
494
495 default:
496 BUG();
497 break;
498 }
499
500 return 0;
501}
502
503static const struct snd_kcontrol_new in1l_pga[] = {
504SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
505SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
506};
507
508static const struct snd_kcontrol_new in1r_pga[] = {
509SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
510SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
511};
512
513static const struct snd_kcontrol_new in2l_pga[] = {
514SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
515SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
516};
517
518static const struct snd_kcontrol_new in2r_pga[] = {
519SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
520SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
521};
522
523static const struct snd_kcontrol_new mixinl[] = {
524SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
525SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
526};
527
528static const struct snd_kcontrol_new mixinr[] = {
529SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
530SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
531};
532
533static const struct snd_kcontrol_new left_output_mixer[] = {
534SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
535SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
536SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
537SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
538SOC_DAPM_SINGLE("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
539SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
540SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
541SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
542};
543
544static const struct snd_kcontrol_new right_output_mixer[] = {
545SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
546SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
547SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
548SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
549SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
550SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
551SOC_DAPM_SINGLE("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
552SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
553};
554
555static const struct snd_kcontrol_new earpiece_mixer[] = {
556SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
557SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
558SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
559};
560
561static const struct snd_kcontrol_new left_speaker_boost[] = {
562SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
563SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
564SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
565};
566
567static const struct snd_kcontrol_new right_speaker_boost[] = {
568SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
569SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
570SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
571};
572
573static const struct snd_kcontrol_new line1_mix[] = {
574SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
575SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
576SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
577};
578
579static const struct snd_kcontrol_new line1n_mix[] = {
580SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
581SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
582};
583
584static const struct snd_kcontrol_new line1p_mix[] = {
585SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
586};
587
588static const struct snd_kcontrol_new line2_mix[] = {
Mark Brown43b6cec2012-02-01 23:46:58 +0000589SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
590SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100591SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
592};
593
594static const struct snd_kcontrol_new line2n_mix[] = {
UK KIM114395c2012-01-28 01:52:22 +0900595SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
596SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100597};
598
599static const struct snd_kcontrol_new line2p_mix[] = {
600SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
601};
602
603static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
604SND_SOC_DAPM_INPUT("IN1LN"),
605SND_SOC_DAPM_INPUT("IN1LP"),
606SND_SOC_DAPM_INPUT("IN2LN"),
Joonyoung Shim34825942009-12-04 15:12:10 +0900607SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
Mark Browna2342ae2009-07-29 21:21:49 +0100608SND_SOC_DAPM_INPUT("IN1RN"),
609SND_SOC_DAPM_INPUT("IN1RP"),
610SND_SOC_DAPM_INPUT("IN2RN"),
Joonyoung Shim34825942009-12-04 15:12:10 +0900611SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
Mark Browna2342ae2009-07-29 21:21:49 +0100612
Mark Brown91e20852011-12-02 16:01:41 +0000613SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
614SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100615
Mark Brown77231ab2012-01-20 12:19:43 +0000616SND_SOC_DAPM_SUPPLY("LINEOUT_VMID_BUF", WM8993_ANTIPOP1, 7, 0, NULL, 0),
617
Mark Browna2342ae2009-07-29 21:21:49 +0100618SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
619 in1l_pga, ARRAY_SIZE(in1l_pga)),
620SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
621 in1r_pga, ARRAY_SIZE(in1r_pga)),
622
623SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
624 in2l_pga, ARRAY_SIZE(in2l_pga)),
625SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
626 in2r_pga, ARRAY_SIZE(in2r_pga)),
627
Mark Browna2342ae2009-07-29 21:21:49 +0100628SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
629 mixinl, ARRAY_SIZE(mixinl)),
630SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
631 mixinr, ARRAY_SIZE(mixinr)),
632
Mark Browna2342ae2009-07-29 21:21:49 +0100633SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
634 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
635SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
636 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
637
638SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
639SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
640
Mark Brown3ed70742010-01-20 17:39:45 +0000641SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
642 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Browna2342ae2009-07-29 21:21:49 +0100643SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0,
644 NULL, 0,
645 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
646
647SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
648 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
649SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
650 NULL, 0, earpiece_event,
651 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
652
653SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
654 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
655SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
656 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
657
Mark Brown03431972011-11-04 17:11:54 +0000658SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100659SND_SOC_DAPM_PGA("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
660 NULL, 0),
661SND_SOC_DAPM_PGA("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
662 NULL, 0),
663
664SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
665 line1_mix, ARRAY_SIZE(line1_mix)),
666SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
667 line2_mix, ARRAY_SIZE(line2_mix)),
668
669SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
670 line1n_mix, ARRAY_SIZE(line1n_mix)),
671SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
672 line1p_mix, ARRAY_SIZE(line1p_mix)),
673SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
674 line2n_mix, ARRAY_SIZE(line2n_mix)),
675SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
676 line2p_mix, ARRAY_SIZE(line2p_mix)),
677
678SND_SOC_DAPM_PGA("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
679 NULL, 0),
680SND_SOC_DAPM_PGA("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
681 NULL, 0),
682SND_SOC_DAPM_PGA("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
683 NULL, 0),
684SND_SOC_DAPM_PGA("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
685 NULL, 0),
686
687SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
688SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
689SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
690SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
691SND_SOC_DAPM_OUTPUT("HPOUT1L"),
692SND_SOC_DAPM_OUTPUT("HPOUT1R"),
693SND_SOC_DAPM_OUTPUT("HPOUT2P"),
694SND_SOC_DAPM_OUTPUT("HPOUT2N"),
695SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
696SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
697SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
698SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
699};
700
701static const struct snd_soc_dapm_route analogue_routes[] = {
Mark Brown4baafdd2011-02-18 15:05:53 -0800702 { "MICBIAS1", NULL, "CLK_SYS" },
703 { "MICBIAS2", NULL, "CLK_SYS" },
704
Mark Browna2342ae2009-07-29 21:21:49 +0100705 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
706 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
707
Mark Brown4e04ada2011-07-15 15:12:31 +0900708 { "IN1L PGA", NULL, "VMID" },
709 { "IN1R PGA", NULL, "VMID" },
710 { "IN2L PGA", NULL, "VMID" },
711 { "IN2R PGA", NULL, "VMID" },
712
Mark Browna2342ae2009-07-29 21:21:49 +0100713 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
714 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
715
Joonyoung Shim34825942009-12-04 15:12:10 +0900716 { "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
Mark Browna2342ae2009-07-29 21:21:49 +0100717 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
718
Joonyoung Shim34825942009-12-04 15:12:10 +0900719 { "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +0100720 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
721
Joonyoung Shim34825942009-12-04 15:12:10 +0900722 { "Direct Voice", NULL, "IN2LP:VXRN" },
723 { "Direct Voice", NULL, "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +0100724
725 { "MIXINL", "IN1L Switch", "IN1L PGA" },
726 { "MIXINL", "IN2L Switch", "IN2L PGA" },
727 { "MIXINL", NULL, "Direct Voice" },
728 { "MIXINL", NULL, "IN1LP" },
729 { "MIXINL", NULL, "Left Output Mixer" },
Mark Brown4e04ada2011-07-15 15:12:31 +0900730 { "MIXINL", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100731
732 { "MIXINR", "IN1R Switch", "IN1R PGA" },
733 { "MIXINR", "IN2R Switch", "IN2R PGA" },
734 { "MIXINR", NULL, "Direct Voice" },
735 { "MIXINR", NULL, "IN1RP" },
736 { "MIXINR", NULL, "Right Output Mixer" },
Mark Brown4e04ada2011-07-15 15:12:31 +0900737 { "MIXINR", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100738
739 { "ADCL", NULL, "MIXINL" },
740 { "ADCR", NULL, "MIXINR" },
741
742 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
743 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
744 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
745 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
Joonyoung Shim34825942009-12-04 15:12:10 +0900746 { "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
Mark Browna2342ae2009-07-29 21:21:49 +0100747 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
748 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
749
750 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
751 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
752 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
753 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
Joonyoung Shim34825942009-12-04 15:12:10 +0900754 { "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +0100755 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
756 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
757
758 { "Left Output PGA", NULL, "Left Output Mixer" },
759 { "Left Output PGA", NULL, "TOCLK" },
760
761 { "Right Output PGA", NULL, "Right Output Mixer" },
762 { "Right Output PGA", NULL, "TOCLK" },
763
764 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
765 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
766 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
767
Mark Brown4e04ada2011-07-15 15:12:31 +0900768 { "Earpiece Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100769 { "Earpiece Driver", NULL, "Earpiece Mixer" },
770 { "HPOUT2N", NULL, "Earpiece Driver" },
771 { "HPOUT2P", NULL, "Earpiece Driver" },
772
773 { "SPKL", "Input Switch", "MIXINL" },
774 { "SPKL", "IN1LP Switch", "IN1LP" },
Mark Brown39cca162011-04-08 16:32:16 +0900775 { "SPKL", "Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100776 { "SPKL", NULL, "TOCLK" },
777
778 { "SPKR", "Input Switch", "MIXINR" },
779 { "SPKR", "IN1RP Switch", "IN1RP" },
Mark Brown39cca162011-04-08 16:32:16 +0900780 { "SPKR", "Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100781 { "SPKR", NULL, "TOCLK" },
782
783 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
784 { "SPKL Boost", "SPKL Switch", "SPKL" },
785 { "SPKL Boost", "SPKR Switch", "SPKR" },
786
787 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
788 { "SPKR Boost", "SPKR Switch", "SPKR" },
789 { "SPKR Boost", "SPKL Switch", "SPKL" },
790
Mark Brown4e04ada2011-07-15 15:12:31 +0900791 { "SPKL Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100792 { "SPKL Driver", NULL, "SPKL Boost" },
793 { "SPKL Driver", NULL, "CLK_SYS" },
Mark Brown03431972011-11-04 17:11:54 +0000794 { "SPKL Driver", NULL, "TSHUT" },
Mark Browna2342ae2009-07-29 21:21:49 +0100795
Mark Brown4e04ada2011-07-15 15:12:31 +0900796 { "SPKR Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100797 { "SPKR Driver", NULL, "SPKR Boost" },
798 { "SPKR Driver", NULL, "CLK_SYS" },
Mark Brown03431972011-11-04 17:11:54 +0000799 { "SPKR Driver", NULL, "TSHUT" },
Mark Browna2342ae2009-07-29 21:21:49 +0100800
801 { "SPKOUTLP", NULL, "SPKL Driver" },
802 { "SPKOUTLN", NULL, "SPKL Driver" },
803 { "SPKOUTRP", NULL, "SPKR Driver" },
804 { "SPKOUTRN", NULL, "SPKR Driver" },
805
Mark Brown39cca162011-04-08 16:32:16 +0900806 { "Left Headphone Mux", "Mixer", "Left Output PGA" },
807 { "Right Headphone Mux", "Mixer", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100808
809 { "Headphone PGA", NULL, "Left Headphone Mux" },
810 { "Headphone PGA", NULL, "Right Headphone Mux" },
Mark Brown4e04ada2011-07-15 15:12:31 +0900811 { "Headphone PGA", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100812 { "Headphone PGA", NULL, "CLK_SYS" },
Mark Brown3ed70742010-01-20 17:39:45 +0000813 { "Headphone PGA", NULL, "Headphone Supply" },
Mark Browna2342ae2009-07-29 21:21:49 +0100814
815 { "HPOUT1L", NULL, "Headphone PGA" },
816 { "HPOUT1R", NULL, "Headphone PGA" },
817
Mark Brown4e04ada2011-07-15 15:12:31 +0900818 { "LINEOUT1N Driver", NULL, "VMID" },
819 { "LINEOUT1P Driver", NULL, "VMID" },
820 { "LINEOUT2N Driver", NULL, "VMID" },
821 { "LINEOUT2P Driver", NULL, "VMID" },
822
Mark Browna2342ae2009-07-29 21:21:49 +0100823 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
824 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
825 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
826 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
827};
828
829static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
830 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
831 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700832 { "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100833
834 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
835 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
836};
837
838static const struct snd_soc_dapm_route lineout1_se_routes[] = {
Mark Brown77231ab2012-01-20 12:19:43 +0000839 { "LINEOUT1N Mixer", NULL, "LINEOUT_VMID_BUF" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700840 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
841 { "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100842
Mark Brown77231ab2012-01-20 12:19:43 +0000843 { "LINEOUT1P Mixer", NULL, "LINEOUT_VMID_BUF" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700844 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100845
846 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
847 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
848};
849
850static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
Mark Brownee767442012-01-31 11:55:32 +0000851 { "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
852 { "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700853 { "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100854
855 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
856 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
857};
858
859static const struct snd_soc_dapm_route lineout2_se_routes[] = {
Mark Brown77231ab2012-01-20 12:19:43 +0000860 { "LINEOUT2N Mixer", NULL, "LINEOUT_VMID_BUF" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700861 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
862 { "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100863
Mark Brown77231ab2012-01-20 12:19:43 +0000864 { "LINEOUT2P Mixer", NULL, "LINEOUT_VMID_BUF" },
Mark Brownd0b48af2011-05-14 17:21:28 -0700865 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +0100866
867 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
868 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
869};
870
871int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
872{
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200873 struct snd_soc_dapm_context *dapm = &codec->dapm;
874
Mark Browna2342ae2009-07-29 21:21:49 +0100875 /* Latch volume update bits & default ZC on */
876 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
877 WM8993_IN1_VU, WM8993_IN1_VU);
878 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
879 WM8993_IN1_VU, WM8993_IN1_VU);
880 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
881 WM8993_IN2_VU, WM8993_IN2_VU);
882 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
883 WM8993_IN2_VU, WM8993_IN2_VU);
884
Mark Brownfb5af532011-05-15 12:18:38 -0700885 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
886 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
Mark Browna2342ae2009-07-29 21:21:49 +0100887 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
888 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
889
890 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
Mark Brownfb5af532011-05-15 12:18:38 -0700891 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
892 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
Mark Browna2342ae2009-07-29 21:21:49 +0100893 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
894 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
895 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
896
897 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
Mark Brownfb5af532011-05-15 12:18:38 -0700898 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
899 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
Mark Browna2342ae2009-07-29 21:21:49 +0100900 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
901 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
902 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
903
904 snd_soc_add_controls(codec, analogue_snd_controls,
905 ARRAY_SIZE(analogue_snd_controls));
906
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200907 snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
Mark Browna2342ae2009-07-29 21:21:49 +0100908 ARRAY_SIZE(analogue_dapm_widgets));
909 return 0;
910}
911EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
912
913int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
914 int lineout1_diff, int lineout2_diff)
915{
Mark Brownd96ca3c2011-07-12 15:25:03 +0900916 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200917 struct snd_soc_dapm_context *dapm = &codec->dapm;
918
Mark Brownd96ca3c2011-07-12 15:25:03 +0900919 init_completion(&hubs->dcs_done);
920
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200921 snd_soc_dapm_add_routes(dapm, analogue_routes,
Mark Browna2342ae2009-07-29 21:21:49 +0100922 ARRAY_SIZE(analogue_routes));
923
924 if (lineout1_diff)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200925 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +0100926 lineout1_diff_routes,
927 ARRAY_SIZE(lineout1_diff_routes));
928 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200929 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +0100930 lineout1_se_routes,
931 ARRAY_SIZE(lineout1_se_routes));
932
933 if (lineout2_diff)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200934 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +0100935 lineout2_diff_routes,
936 ARRAY_SIZE(lineout2_diff_routes));
937 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200938 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +0100939 lineout2_se_routes,
940 ARRAY_SIZE(lineout2_se_routes));
941
942 return 0;
943}
944EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
945
Mark Brownaa983d92009-09-30 14:16:11 +0100946int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
947 int lineout1_diff, int lineout2_diff,
948 int lineout1fb, int lineout2fb,
949 int jd_scthr, int jd_thr, int micbias1_lvl,
950 int micbias2_lvl)
951{
952 if (!lineout1_diff)
953 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
954 WM8993_LINEOUT1_MODE,
955 WM8993_LINEOUT1_MODE);
956 if (!lineout2_diff)
957 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
958 WM8993_LINEOUT2_MODE,
959 WM8993_LINEOUT2_MODE);
960
Mark Brown821dd912010-01-21 11:33:20 +0000961 /* If the line outputs are differential then we aren't presenting
962 * VMID as an output and can disable it.
963 */
964 if (lineout1_diff && lineout2_diff)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200965 codec->dapm.idle_bias_off = 1;
Mark Brown821dd912010-01-21 11:33:20 +0000966
Mark Brownaa983d92009-09-30 14:16:11 +0100967 if (lineout1fb)
968 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
969 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
970
971 if (lineout2fb)
972 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
973 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
974
975 snd_soc_update_bits(codec, WM8993_MICBIAS,
976 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
977 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
978 jd_scthr << WM8993_JD_SCTHR_SHIFT |
979 jd_thr << WM8993_JD_THR_SHIFT |
980 micbias1_lvl |
981 micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
982
983 return 0;
984}
985EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
986
Mark Browna2342ae2009-07-29 21:21:49 +0100987MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
988MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
989MODULE_LICENSE("GPL");