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gerrit-public.fairphone.software / kernel / msm / 2f6d7d26b892f267f8fa9af9eb91e1da928548b9 / . / arch / arm / mach-msm / clock-8226.c
blob: a8a76edab96b6a2cd8790e1764270916889ccb95 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]27#include <mach/clock-generic.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]28
29#include "clock-local2.h"
30#include "clock-pll.h"
31#include "clock-rpm.h"
32#include "clock-voter.h"
33#include "clock-mdss-8974.h"
34#include "clock.h"
35
36enum {
37 GCC_BASE,
38 MMSS_BASE,
39 LPASS_BASE,
40 APCS_BASE,
41 APCS_PLL_BASE,
42 N_BASES,
43};
44
45static void __iomem *virt_bases[N_BASES];
46
47#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
48#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
49#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
50#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
51
52/* Mux source select values */
53#define xo_source_val 0
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]54#define xo_a_clk_source_val 0
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]55#define gpll0_source_val 1
56#define gpll1_source_val 2
57
58#define xo_mm_source_val 0
59#define mmpll0_pll_mm_source_val 1
60#define mmpll1_pll_mm_source_val 2
61#define mmpll2_pll_mm_source_val 3
62#define gpll0_mm_source_val 5
63#define dsipll_750_mm_source_val 1
64#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]65#define dsipll0_byte_mm_source_val 1
66#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]67
68#define gpll1_hsic_source_val 4
69
70#define xo_lpass_source_val 0
71#define lpaaudio_pll_lpass_source_val 1
72#define gpll0_lpass_source_val 5
73
74/* Prevent a divider of -1 */
75#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
76
77#define F_GCC(f, s, div, m, n) \
78 { \
79 .freq_hz = (f), \
80 .src_clk = &s.c, \
81 .m_val = (m), \
82 .n_val = ~((n)-(m)) * !!(n), \
83 .d_val = ~(n),\
84 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
85 | BVAL(10, 8, s##_source_val), \
86 }
87
88#define F_MMSS(f, s, div, m, n) \
89 { \
90 .freq_hz = (f), \
91 .src_clk = &s.c, \
92 .m_val = (m), \
93 .n_val = ~((n)-(m)) * !!(n), \
94 .d_val = ~(n),\
95 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
96 | BVAL(10, 8, s##_mm_source_val), \
97 }
98
99#define F_MDSS(f, s, div, m, n) \
100 { \
101 .freq_hz = (f), \
102 .m_val = (m), \
103 .n_val = ~((n)-(m)) * !!(n), \
104 .d_val = ~(n),\
105 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
106 | BVAL(10, 8, s##_mm_source_val), \
107 }
108
109#define F_HSIC(f, s, div, m, n) \
110 { \
111 .freq_hz = (f), \
112 .src_clk = &s.c, \
113 .m_val = (m), \
114 .n_val = ~((n)-(m)) * !!(n), \
115 .d_val = ~(n),\
116 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
117 | BVAL(10, 8, s##_hsic_source_val), \
118 }
119
120#define F_LPASS(f, s, div, m, n) \
121 { \
122 .freq_hz = (f), \
123 .src_clk = &s.c, \
124 .m_val = (m), \
125 .n_val = ~((n)-(m)) * !!(n), \
126 .d_val = ~(n),\
127 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
128 | BVAL(10, 8, s##_lpass_source_val), \
129 }
130
131#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
132 { \
133 .freq_hz = (f), \
134 .l_val = (l), \
135 .m_val = (m), \
136 .n_val = (n), \
137 .pre_div_val = BVAL(12, 12, (pre_div)), \
138 .post_div_val = BVAL(9, 8, (post_div)), \
139 .vco_val = BVAL(29, 28, (vco)), \
140 }
141
142#define VDD_DIG_FMAX_MAP1(l1, f1) \
143 .vdd_class = &vdd_dig, \
144 .fmax = (unsigned long[VDD_DIG_NUM]) { \
145 [VDD_DIG_##l1] = (f1), \
146 }, \
147 .num_fmax = VDD_DIG_NUM
148
149#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
150 .vdd_class = &vdd_dig, \
151 .fmax = (unsigned long[VDD_DIG_NUM]) { \
152 [VDD_DIG_##l1] = (f1), \
153 [VDD_DIG_##l2] = (f2), \
154 }, \
155 .num_fmax = VDD_DIG_NUM
156
157#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
158 .vdd_class = &vdd_dig, \
159 .fmax = (unsigned long[VDD_DIG_NUM]) { \
160 [VDD_DIG_##l1] = (f1), \
161 [VDD_DIG_##l2] = (f2), \
162 [VDD_DIG_##l3] = (f3), \
163 }, \
164 .num_fmax = VDD_DIG_NUM
165
166enum vdd_dig_levels {
167 VDD_DIG_NONE,
168 VDD_DIG_LOW,
169 VDD_DIG_NOMINAL,
170 VDD_DIG_HIGH,
171 VDD_DIG_NUM
172};
173
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]174static int vdd_corner[] = {
175 RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
176 RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_LOW */
177 RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
178 RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_HIGH */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]179};
180
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]181static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]182
183#define RPM_MISC_CLK_TYPE 0x306b6c63
184#define RPM_BUS_CLK_TYPE 0x316b6c63
185#define RPM_MEM_CLK_TYPE 0x326b6c63
186
187#define RPM_SMD_KEY_ENABLE 0x62616E45
188
189#define CXO_ID 0x0
190#define QDSS_ID 0x1
191
192#define PNOC_ID 0x0
193#define SNOC_ID 0x1
194#define CNOC_ID 0x2
195#define MMSSNOC_AHB_ID 0x3
196
197#define BIMC_ID 0x0
198#define OXILI_ID 0x1
199#define OCMEM_ID 0x2
200
201#define D0_ID 1
202#define D1_ID 2
203#define A0_ID 4
204#define A1_ID 5
205#define A2_ID 6
206#define DIFF_CLK_ID 7
207#define DIV_CLK1_ID 11
208#define DIV_CLK2_ID 12
209
210DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
211DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
212DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
213DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
214 MMSSNOC_AHB_ID, NULL);
215
216DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
217DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
218 NULL);
219DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
220 NULL);
221
222DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
223 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
224DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
225
226DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
227DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
228DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
229DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
230DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
232DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
234
235DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
239DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
240
241struct measure_mux_entry {
242 struct clk *c;
243 int base;
244 u32 debug_mux;
245};
246
247static struct branch_clk oxilicx_axi_clk;
248
249#define MSS_DEBUG_CLOCK_CTL 0x0078
250#define LPASS_DEBUG_CLK_CTL 0x29000
251#define GLB_CLK_DIAG 0x01C
252#define GLB_TEST_BUS_SEL 0x020
253
254#define MMPLL0_PLL_MODE (0x0000)
255#define MMPLL0_PLL_L_VAL (0x0004)
256#define MMPLL0_PLL_M_VAL (0x0008)
257#define MMPLL0_PLL_N_VAL (0x000C)
258#define MMPLL0_PLL_USER_CTL (0x0010)
259#define MMPLL0_PLL_STATUS (0x001C)
260#define MMPLL1_PLL_MODE (0x0040)
261#define MMPLL1_PLL_L_VAL (0x0044)
262#define MMPLL1_PLL_M_VAL (0x0048)
263#define MMPLL1_PLL_N_VAL (0x004C)
264#define MMPLL1_PLL_USER_CTL (0x0050)
265#define MMPLL1_PLL_STATUS (0x005C)
266#define MMSS_PLL_VOTE_APCS (0x0100)
267#define VCODEC0_CMD_RCGR (0x1000)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]268#define VENUS0_BCR (0x1020)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]269#define VENUS0_VCODEC0_CBCR (0x1028)
270#define VENUS0_AHB_CBCR (0x1030)
271#define VENUS0_AXI_CBCR (0x1034)
272#define PCLK0_CMD_RCGR (0x2000)
273#define MDP_CMD_RCGR (0x2040)
274#define VSYNC_CMD_RCGR (0x2080)
275#define BYTE0_CMD_RCGR (0x2120)
276#define ESC0_CMD_RCGR (0x2160)
277#define MDSS_AHB_CBCR (0x2308)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]278#define MDSS_BCR (0x2300)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]279#define MDSS_AXI_CBCR (0x2310)
280#define MDSS_PCLK0_CBCR (0x2314)
281#define MDSS_MDP_CBCR (0x231C)
282#define MDSS_MDP_LUT_CBCR (0x2320)
283#define MDSS_VSYNC_CBCR (0x2328)
284#define MDSS_BYTE0_CBCR (0x233C)
285#define MDSS_ESC0_CBCR (0x2344)
286#define CSI0PHYTIMER_CMD_RCGR (0x3000)
287#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
288#define CSI1PHYTIMER_CMD_RCGR (0x3030)
289#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
290#define CSI0_CMD_RCGR (0x3090)
291#define CAMSS_CSI0_CBCR (0x30B4)
292#define CAMSS_CSI0_AHB_CBCR (0x30BC)
293#define CAMSS_CSI0PHY_CBCR (0x30C4)
294#define CAMSS_CSI0RDI_CBCR (0x30D4)
295#define CAMSS_CSI0PIX_CBCR (0x30E4)
296#define CSI1_CMD_RCGR (0x3100)
297#define CAMSS_CSI1_CBCR (0x3124)
298#define CAMSS_CSI1_AHB_CBCR (0x3128)
299#define CAMSS_CSI1PHY_CBCR (0x3134)
300#define CAMSS_CSI1RDI_CBCR (0x3144)
301#define CAMSS_CSI1PIX_CBCR (0x3154)
302#define CAMSS_ISPIF_AHB_CBCR (0x3224)
303#define CCI_CMD_RCGR (0x3300)
304#define CAMSS_CCI_CCI_CBCR (0x3344)
305#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
306#define MCLK0_CMD_RCGR (0x3360)
307#define CAMSS_MCLK0_CBCR (0x3384)
308#define MCLK1_CMD_RCGR (0x3390)
309#define CAMSS_MCLK1_CBCR (0x33B4)
310#define MMSS_GP0_CMD_RCGR (0x3420)
311#define CAMSS_GP0_CBCR (0x3444)
312#define MMSS_GP1_CMD_RCGR (0x3450)
313#define CAMSS_GP1_CBCR (0x3474)
314#define CAMSS_TOP_AHB_CBCR (0x3484)
315#define CAMSS_MICRO_AHB_CBCR (0x3494)
316#define JPEG0_CMD_RCGR (0x3500)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]317#define CAMSS_JPEG_BCR (0x35A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]318#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
319#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
320#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
321#define VFE0_CMD_RCGR (0x3600)
322#define CPP_CMD_RCGR (0x3640)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]323#define CAMSS_VFE_BCR (0x36A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]324#define CAMSS_VFE_VFE0_CBCR (0x36A8)
325#define CAMSS_VFE_CPP_CBCR (0x36B0)
326#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
327#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
328#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]329#define CAMSS_CSI_VFE0_BCR (0x3700)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]330#define CAMSS_CSI_VFE0_CBCR (0x3704)
331#define OXILI_GFX3D_CBCR (0x4028)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]332#define OXILICX_BCR (0x4030)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]333#define OXILICX_AXI_CBCR (0x4038)
334#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]335#define MMPLL2_PLL_MODE (0x4100)
336#define MMPLL2_PLL_STATUS (0x411C)
337#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
338#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
339#define MMSS_MISC_AHB_CBCR (0x502C)
340#define AXI_CMD_RCGR (0x5040)
341#define MMSS_S0_AXI_CBCR (0x5064)
342#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
343#define MMSS_DEBUG_CLK_CTL (0x0900)
344#define GPLL0_MODE (0x0000)
345#define GPLL0_L_VAL (0x0004)
346#define GPLL0_M_VAL (0x0008)
347#define GPLL0_N_VAL (0x000C)
348#define GPLL0_USER_CTL (0x0010)
349#define GPLL0_STATUS (0x001C)
350#define GPLL1_MODE (0x0040)
351#define GPLL1_L_VAL (0x0044)
352#define GPLL1_M_VAL (0x0048)
353#define GPLL1_N_VAL (0x004C)
354#define GPLL1_USER_CTL (0x0050)
355#define GPLL1_STATUS (0x005C)
356#define PERIPH_NOC_AHB_CBCR (0x0184)
357#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
358#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
359#define MSS_CFG_AHB_CBCR (0x0280)
360#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
361#define USB_HS_HSIC_BCR (0x0400)
362#define USB_HSIC_AHB_CBCR (0x0408)
363#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
364#define USB_HSIC_SYSTEM_CBCR (0x040C)
365#define USB_HSIC_CMD_RCGR (0x0440)
366#define USB_HSIC_CBCR (0x0410)
367#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
368#define USB_HSIC_IO_CAL_CBCR (0x0414)
369#define USB_HS_BCR (0x0480)
370#define USB_HS_SYSTEM_CBCR (0x0484)
371#define USB_HS_AHB_CBCR (0x0488)
372#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
373#define USB2A_PHY_SLEEP_CBCR (0x04AC)
374#define SDCC1_APPS_CMD_RCGR (0x04D0)
375#define SDCC1_APPS_CBCR (0x04C4)
376#define SDCC1_AHB_CBCR (0x04C8)
377#define SDCC2_APPS_CMD_RCGR (0x0510)
378#define SDCC2_APPS_CBCR (0x0504)
379#define SDCC2_AHB_CBCR (0x0508)
380#define SDCC3_APPS_CMD_RCGR (0x0550)
381#define SDCC3_APPS_CBCR (0x0544)
382#define SDCC3_AHB_CBCR (0x0548)
383#define BLSP1_AHB_CBCR (0x05C4)
384#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
385#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
386#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
387#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
388#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
389#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
390#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
391#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
392#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
393#define BLSP1_UART1_APPS_CBCR (0x0684)
394#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
395#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
396#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
397#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
398#define BLSP1_UART2_APPS_CBCR (0x0704)
399#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
400#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
401#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
402#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
403#define BLSP1_UART3_APPS_CBCR (0x0784)
404#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
405#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
406#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
407#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
408#define BLSP1_UART4_APPS_CBCR (0x0804)
409#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
410#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
411#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
412#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
413#define BLSP1_UART5_APPS_CBCR (0x0884)
414#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
415#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
416#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
417#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
418#define BLSP1_UART6_APPS_CBCR (0x0904)
419#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
420#define PDM_AHB_CBCR (0x0CC4)
421#define PDM_XO4_CBCR (0x0CC8)
422#define PDM2_CBCR (0x0CCC)
423#define PDM2_CMD_RCGR (0x0CD0)
424#define PRNG_AHB_CBCR (0x0D04)
425#define BAM_DMA_AHB_CBCR (0x0D44)
426#define BOOT_ROM_AHB_CBCR (0x0E04)
427#define CE1_CMD_RCGR (0x1050)
428#define CE1_CBCR (0x1044)
429#define CE1_AXI_CBCR (0x1048)
430#define CE1_AHB_CBCR (0x104C)
431#define GCC_XO_DIV4_CBCR (0x10C8)
432#define LPASS_Q6_AXI_CBCR (0x11C0)
433#define APCS_GPLL_ENA_VOTE (0x1480)
434#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
435#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
436#define GCC_DEBUG_CLK_CTL (0x1880)
437#define CLOCK_FRQ_MEASURE_CTL (0x1884)
438#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
439#define PLLTEST_PAD_CFG (0x188C)
440#define GP1_CBCR (0x1900)
441#define GP1_CMD_RCGR (0x1904)
442#define GP2_CBCR (0x1940)
443#define GP2_CMD_RCGR (0x1944)
444#define GP3_CBCR (0x1980)
445#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]446#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]447#define Q6SS_AHB_LFABIF_CBCR (0x22000)
448#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]449#define Q6SS_XO_CBCR (0x26000)
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]450#define KPSS_AHB_CMD_RCGR (0x120C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]451
452static unsigned int soft_vote_gpll0;
453
454static struct pll_vote_clk gpll0 = {
455 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
456 .en_mask = BIT(0),
457 .status_reg = (void __iomem *)GPLL0_STATUS,
458 .status_mask = BIT(17),
459 .soft_vote = &soft_vote_gpll0,
460 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
461 .base = &virt_bases[GCC_BASE],
462 .c = {
463 .rate = 600000000,
464 .parent = &xo.c,
465 .dbg_name = "gpll0",
466 .ops = &clk_ops_pll_acpu_vote,
467 CLK_INIT(gpll0.c),
468 },
469};
470
471/*Don't vote for xo if using this clock to allow xo shutdown*/
472static struct pll_vote_clk gpll0_ao = {
473 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
474 .en_mask = BIT(0),
475 .status_reg = (void __iomem *)GPLL0_STATUS,
476 .status_mask = BIT(17),
477 .soft_vote = &soft_vote_gpll0,
478 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
479 .base = &virt_bases[GCC_BASE],
480 .c = {
481 .rate = 600000000,
482 .dbg_name = "gpll0_ao",
483 .ops = &clk_ops_pll_acpu_vote,
484 CLK_INIT(gpll0_ao.c),
485 },
486};
487
488static struct pll_vote_clk gpll1 = {
489 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
490 .en_mask = BIT(1),
491 .status_reg = (void __iomem *)GPLL1_STATUS,
492 .status_mask = BIT(17),
493 .base = &virt_bases[GCC_BASE],
494 .c = {
495 .rate = 480000000,
496 .parent = &xo.c,
497 .dbg_name = "gpll1",
498 .ops = &clk_ops_pll_vote,
499 CLK_INIT(gpll1.c),
500 },
501};
502
503static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]504 F_GCC( 19200000, xo, 1, 0, 0),
505 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]506 F_END
507};
508
509static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
510 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
511 .set_rate = set_rate_hid,
512 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
513 .current_freq = &rcg_dummy_freq,
514 .base = &virt_bases[GCC_BASE],
515 .c = {
516 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
517 .ops = &clk_ops_rcg,
518 VDD_DIG_FMAX_MAP1(LOW, 50000000),
519 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
520 },
521};
522
523static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
524 F_GCC( 960000, xo, 10, 1, 2),
525 F_GCC( 4800000, xo, 4, 0, 0),
526 F_GCC( 9600000, xo, 2, 0, 0),
527 F_GCC( 15000000, gpll0, 10, 1, 4),
528 F_GCC( 19200000, xo, 1, 0, 0),
529 F_GCC( 25000000, gpll0, 12, 1, 2),
530 F_GCC( 50000000, gpll0, 12, 0, 0),
531 F_END
532};
533
534static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
535 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
536 .set_rate = set_rate_mnd,
537 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
538 .current_freq = &rcg_dummy_freq,
539 .base = &virt_bases[GCC_BASE],
540 .c = {
541 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
542 .ops = &clk_ops_rcg_mnd,
543 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
544 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
545 },
546};
547
548static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
549 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
550 .set_rate = set_rate_hid,
551 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
552 .current_freq = &rcg_dummy_freq,
553 .base = &virt_bases[GCC_BASE],
554 .c = {
555 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
556 .ops = &clk_ops_rcg,
557 VDD_DIG_FMAX_MAP1(LOW, 50000000),
558 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
559 },
560};
561
562static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
563 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
564 .set_rate = set_rate_mnd,
565 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
566 .current_freq = &rcg_dummy_freq,
567 .base = &virt_bases[GCC_BASE],
568 .c = {
569 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
570 .ops = &clk_ops_rcg_mnd,
571 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
572 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
573 },
574};
575
576static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
577 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
578 .set_rate = set_rate_hid,
579 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
580 .current_freq = &rcg_dummy_freq,
581 .base = &virt_bases[GCC_BASE],
582 .c = {
583 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
584 .ops = &clk_ops_rcg,
585 VDD_DIG_FMAX_MAP1(LOW, 50000000),
586 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
587 },
588};
589
590static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
591 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
592 .set_rate = set_rate_mnd,
593 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
594 .current_freq = &rcg_dummy_freq,
595 .base = &virt_bases[GCC_BASE],
596 .c = {
597 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
598 .ops = &clk_ops_rcg_mnd,
599 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
600 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
601 },
602};
603
604static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
605 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
606 .set_rate = set_rate_hid,
607 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
608 .current_freq = &rcg_dummy_freq,
609 .base = &virt_bases[GCC_BASE],
610 .c = {
611 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
612 .ops = &clk_ops_rcg,
613 VDD_DIG_FMAX_MAP1(LOW, 50000000),
614 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
615 },
616};
617
618static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
619 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
620 .set_rate = set_rate_mnd,
621 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
622 .current_freq = &rcg_dummy_freq,
623 .base = &virt_bases[GCC_BASE],
624 .c = {
625 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
626 .ops = &clk_ops_rcg_mnd,
627 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
628 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
629 },
630};
631
632static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
633 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
634 .set_rate = set_rate_hid,
635 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
636 .current_freq = &rcg_dummy_freq,
637 .base = &virt_bases[GCC_BASE],
638 .c = {
639 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
640 .ops = &clk_ops_rcg,
641 VDD_DIG_FMAX_MAP1(LOW, 50000000),
642 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
643 },
644};
645
646static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
647 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
648 .set_rate = set_rate_mnd,
649 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
650 .current_freq = &rcg_dummy_freq,
651 .base = &virt_bases[GCC_BASE],
652 .c = {
653 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
654 .ops = &clk_ops_rcg_mnd,
655 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
656 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
657 },
658};
659
660static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
661 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
662 .set_rate = set_rate_hid,
663 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
664 .current_freq = &rcg_dummy_freq,
665 .base = &virt_bases[GCC_BASE],
666 .c = {
667 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
668 .ops = &clk_ops_rcg,
669 VDD_DIG_FMAX_MAP1(LOW, 50000000),
670 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
671 },
672};
673
674static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
675 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
676 .set_rate = set_rate_mnd,
677 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
678 .current_freq = &rcg_dummy_freq,
679 .base = &virt_bases[GCC_BASE],
680 .c = {
681 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
682 .ops = &clk_ops_rcg_mnd,
683 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
684 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
685 },
686};
687
688static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
689 F_GCC( 3686400, gpll0, 1, 96, 15625),
690 F_GCC( 7372800, gpll0, 1, 192, 15625),
691 F_GCC( 14745600, gpll0, 1, 384, 15625),
692 F_GCC( 16000000, gpll0, 5, 2, 15),
693 F_GCC( 19200000, xo, 1, 0, 0),
694 F_GCC( 24000000, gpll0, 5, 1, 5),
695 F_GCC( 32000000, gpll0, 1, 4, 75),
696 F_GCC( 40000000, gpll0, 15, 0, 0),
697 F_GCC( 46400000, gpll0, 1, 29, 375),
698 F_GCC( 48000000, gpll0, 12.5, 0, 0),
699 F_GCC( 51200000, gpll0, 1, 32, 375),
700 F_GCC( 56000000, gpll0, 1, 7, 75),
701 F_GCC( 58982400, gpll0, 1, 1536, 15625),
702 F_GCC( 60000000, gpll0, 10, 0, 0),
703 F_END
704};
705
706static struct rcg_clk blsp1_uart1_apps_clk_src = {
707 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
708 .set_rate = set_rate_mnd,
709 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
710 .current_freq = &rcg_dummy_freq,
711 .base = &virt_bases[GCC_BASE],
712 .c = {
713 .dbg_name = "blsp1_uart1_apps_clk_src",
714 .ops = &clk_ops_rcg_mnd,
715 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
716 CLK_INIT(blsp1_uart1_apps_clk_src.c),
717 },
718};
719
720static struct rcg_clk blsp1_uart2_apps_clk_src = {
721 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
722 .set_rate = set_rate_mnd,
723 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
724 .current_freq = &rcg_dummy_freq,
725 .base = &virt_bases[GCC_BASE],
726 .c = {
727 .dbg_name = "blsp1_uart2_apps_clk_src",
728 .ops = &clk_ops_rcg_mnd,
729 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
730 CLK_INIT(blsp1_uart2_apps_clk_src.c),
731 },
732};
733
734static struct rcg_clk blsp1_uart3_apps_clk_src = {
735 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
736 .set_rate = set_rate_mnd,
737 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
738 .current_freq = &rcg_dummy_freq,
739 .base = &virt_bases[GCC_BASE],
740 .c = {
741 .dbg_name = "blsp1_uart3_apps_clk_src",
742 .ops = &clk_ops_rcg_mnd,
743 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
744 CLK_INIT(blsp1_uart3_apps_clk_src.c),
745 },
746};
747
748static struct rcg_clk blsp1_uart4_apps_clk_src = {
749 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
750 .set_rate = set_rate_mnd,
751 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
752 .current_freq = &rcg_dummy_freq,
753 .base = &virt_bases[GCC_BASE],
754 .c = {
755 .dbg_name = "blsp1_uart4_apps_clk_src",
756 .ops = &clk_ops_rcg_mnd,
757 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
758 CLK_INIT(blsp1_uart4_apps_clk_src.c),
759 },
760};
761
762static struct rcg_clk blsp1_uart5_apps_clk_src = {
763 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
764 .set_rate = set_rate_mnd,
765 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
766 .current_freq = &rcg_dummy_freq,
767 .base = &virt_bases[GCC_BASE],
768 .c = {
769 .dbg_name = "blsp1_uart5_apps_clk_src",
770 .ops = &clk_ops_rcg_mnd,
771 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
772 CLK_INIT(blsp1_uart5_apps_clk_src.c),
773 },
774};
775
776static struct rcg_clk blsp1_uart6_apps_clk_src = {
777 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
778 .set_rate = set_rate_mnd,
779 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
780 .current_freq = &rcg_dummy_freq,
781 .base = &virt_bases[GCC_BASE],
782 .c = {
783 .dbg_name = "blsp1_uart6_apps_clk_src",
784 .ops = &clk_ops_rcg_mnd,
785 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
786 CLK_INIT(blsp1_uart6_apps_clk_src.c),
787 },
788};
789
790static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
791 F_GCC( 50000000, gpll0, 12, 0, 0),
792 F_GCC( 100000000, gpll0, 6, 0, 0),
793 F_END
794};
795
796static struct rcg_clk ce1_clk_src = {
797 .cmd_rcgr_reg = CE1_CMD_RCGR,
798 .set_rate = set_rate_hid,
799 .freq_tbl = ftbl_gcc_ce1_clk,
800 .current_freq = &rcg_dummy_freq,
801 .base = &virt_bases[GCC_BASE],
802 .c = {
803 .dbg_name = "ce1_clk_src",
804 .ops = &clk_ops_rcg,
805 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
806 CLK_INIT(ce1_clk_src.c),
807 },
808};
809
810static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
811 F_GCC( 19200000, xo, 1, 0, 0),
812 F_END
813};
814
815static struct rcg_clk gp1_clk_src = {
816 .cmd_rcgr_reg = GP1_CMD_RCGR,
817 .set_rate = set_rate_mnd,
818 .freq_tbl = ftbl_gcc_gp1_3_clk,
819 .current_freq = &rcg_dummy_freq,
820 .base = &virt_bases[GCC_BASE],
821 .c = {
822 .dbg_name = "gp1_clk_src",
823 .ops = &clk_ops_rcg_mnd,
824 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
825 CLK_INIT(gp1_clk_src.c),
826 },
827};
828
829static struct rcg_clk gp2_clk_src = {
830 .cmd_rcgr_reg = GP2_CMD_RCGR,
831 .set_rate = set_rate_mnd,
832 .freq_tbl = ftbl_gcc_gp1_3_clk,
833 .current_freq = &rcg_dummy_freq,
834 .base = &virt_bases[GCC_BASE],
835 .c = {
836 .dbg_name = "gp2_clk_src",
837 .ops = &clk_ops_rcg_mnd,
838 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
839 CLK_INIT(gp2_clk_src.c),
840 },
841};
842
843static struct rcg_clk gp3_clk_src = {
844 .cmd_rcgr_reg = GP3_CMD_RCGR,
845 .set_rate = set_rate_mnd,
846 .freq_tbl = ftbl_gcc_gp1_3_clk,
847 .current_freq = &rcg_dummy_freq,
848 .base = &virt_bases[GCC_BASE],
849 .c = {
850 .dbg_name = "gp3_clk_src",
851 .ops = &clk_ops_rcg_mnd,
852 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
853 CLK_INIT(gp3_clk_src.c),
854 },
855};
856
857static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
858 F_GCC( 60000000, gpll0, 10, 0, 0),
859 F_END
860};
861
862static struct rcg_clk pdm2_clk_src = {
863 .cmd_rcgr_reg = PDM2_CMD_RCGR,
864 .set_rate = set_rate_hid,
865 .freq_tbl = ftbl_gcc_pdm2_clk,
866 .current_freq = &rcg_dummy_freq,
867 .base = &virt_bases[GCC_BASE],
868 .c = {
869 .dbg_name = "pdm2_clk_src",
870 .ops = &clk_ops_rcg,
871 VDD_DIG_FMAX_MAP1(LOW, 60000000),
872 CLK_INIT(pdm2_clk_src.c),
873 },
874};
875
876static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
877 F_GCC( 144000, xo, 16, 3, 25),
878 F_GCC( 400000, xo, 12, 1, 4),
879 F_GCC( 20000000, gpll0, 15, 1, 2),
880 F_GCC( 25000000, gpll0, 12, 1, 2),
881 F_GCC( 50000000, gpll0, 12, 0, 0),
882 F_GCC( 100000000, gpll0, 6, 0, 0),
883 F_GCC( 200000000, gpll0, 3, 0, 0),
884 F_END
885};
886
887static struct rcg_clk sdcc1_apps_clk_src = {
888 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
889 .set_rate = set_rate_mnd,
890 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
891 .current_freq = &rcg_dummy_freq,
892 .base = &virt_bases[GCC_BASE],
893 .c = {
894 .dbg_name = "sdcc1_apps_clk_src",
895 .ops = &clk_ops_rcg_mnd,
896 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
897 CLK_INIT(sdcc1_apps_clk_src.c),
898 },
899};
900
901static struct rcg_clk sdcc2_apps_clk_src = {
902 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
903 .set_rate = set_rate_mnd,
904 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
905 .current_freq = &rcg_dummy_freq,
906 .base = &virt_bases[GCC_BASE],
907 .c = {
908 .dbg_name = "sdcc2_apps_clk_src",
909 .ops = &clk_ops_rcg_mnd,
910 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
911 CLK_INIT(sdcc2_apps_clk_src.c),
912 },
913};
914
915static struct rcg_clk sdcc3_apps_clk_src = {
916 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
917 .set_rate = set_rate_mnd,
918 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
919 .current_freq = &rcg_dummy_freq,
920 .base = &virt_bases[GCC_BASE],
921 .c = {
922 .dbg_name = "sdcc3_apps_clk_src",
923 .ops = &clk_ops_rcg_mnd,
924 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
925 CLK_INIT(sdcc3_apps_clk_src.c),
926 },
927};
928
929static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
930 F_GCC( 75000000, gpll0, 8, 0, 0),
931 F_END
932};
933
934static struct rcg_clk usb_hs_system_clk_src = {
935 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
936 .set_rate = set_rate_hid,
937 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
938 .current_freq = &rcg_dummy_freq,
939 .base = &virt_bases[GCC_BASE],
940 .c = {
941 .dbg_name = "usb_hs_system_clk_src",
942 .ops = &clk_ops_rcg,
943 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
944 CLK_INIT(usb_hs_system_clk_src.c),
945 },
946};
947
948static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
949 F_HSIC( 480000000, gpll1, 0, 0, 0),
950 F_END
951};
952
953static struct rcg_clk usb_hsic_clk_src = {
954 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
955 .set_rate = set_rate_hid,
956 .freq_tbl = ftbl_gcc_usb_hsic_clk,
957 .current_freq = &rcg_dummy_freq,
958 .base = &virt_bases[GCC_BASE],
959 .c = {
960 .dbg_name = "usb_hsic_clk_src",
961 .ops = &clk_ops_rcg,
962 VDD_DIG_FMAX_MAP1(LOW, 480000000),
963 CLK_INIT(usb_hsic_clk_src.c),
964 },
965};
966
967static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
968 F_GCC( 9600000, xo, 2, 0, 0),
969 F_END
970};
971
972static struct rcg_clk usb_hsic_io_cal_clk_src = {
973 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
974 .set_rate = set_rate_hid,
975 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
976 .current_freq = &rcg_dummy_freq,
977 .base = &virt_bases[GCC_BASE],
978 .c = {
979 .dbg_name = "usb_hsic_io_cal_clk_src",
980 .ops = &clk_ops_rcg,
981 VDD_DIG_FMAX_MAP1(LOW, 9600000),
982 CLK_INIT(usb_hsic_io_cal_clk_src.c),
983 },
984};
985
986static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
987 F_GCC( 75000000, gpll0, 8, 0, 0),
988 F_END
989};
990
991static struct rcg_clk usb_hsic_system_clk_src = {
992 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
993 .set_rate = set_rate_hid,
994 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
995 .current_freq = &rcg_dummy_freq,
996 .base = &virt_bases[GCC_BASE],
997 .c = {
998 .dbg_name = "usb_hsic_system_clk_src",
999 .ops = &clk_ops_rcg,
1000 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
1001 CLK_INIT(usb_hsic_system_clk_src.c),
1002 },
1003};
1004
1005static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1006 .cbcr_reg = BAM_DMA_AHB_CBCR,
1007 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1008 .en_mask = BIT(12),
1009 .base = &virt_bases[GCC_BASE],
1010 .c = {
1011 .dbg_name = "gcc_bam_dma_ahb_clk",
1012 .ops = &clk_ops_vote,
1013 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1014 },
1015};
1016
1017static struct local_vote_clk gcc_blsp1_ahb_clk = {
1018 .cbcr_reg = BLSP1_AHB_CBCR,
1019 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1020 .en_mask = BIT(17),
1021 .base = &virt_bases[GCC_BASE],
1022 .c = {
1023 .dbg_name = "gcc_blsp1_ahb_clk",
1024 .ops = &clk_ops_vote,
1025 CLK_INIT(gcc_blsp1_ahb_clk.c),
1026 },
1027};
1028
1029static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1030 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1031 .has_sibling = 0,
1032 .base = &virt_bases[GCC_BASE],
1033 .c = {
1034 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1035 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1036 .ops = &clk_ops_branch,
1037 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1038 },
1039};
1040
1041static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1042 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1043 .has_sibling = 0,
1044 .base = &virt_bases[GCC_BASE],
1045 .c = {
1046 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1047 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1048 .ops = &clk_ops_branch,
1049 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1050 },
1051};
1052
1053static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1054 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1055 .has_sibling = 0,
1056 .base = &virt_bases[GCC_BASE],
1057 .c = {
1058 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1059 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1060 .ops = &clk_ops_branch,
1061 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1062 },
1063};
1064
1065static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1066 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1067 .has_sibling = 0,
1068 .base = &virt_bases[GCC_BASE],
1069 .c = {
1070 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1071 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1072 .ops = &clk_ops_branch,
1073 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1074 },
1075};
1076
1077static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1078 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1079 .has_sibling = 0,
1080 .base = &virt_bases[GCC_BASE],
1081 .c = {
1082 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1083 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1084 .ops = &clk_ops_branch,
1085 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1086 },
1087};
1088
1089static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1090 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1091 .has_sibling = 0,
1092 .base = &virt_bases[GCC_BASE],
1093 .c = {
1094 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1095 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1096 .ops = &clk_ops_branch,
1097 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1098 },
1099};
1100
1101static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1102 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1103 .has_sibling = 0,
1104 .base = &virt_bases[GCC_BASE],
1105 .c = {
1106 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1107 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1108 .ops = &clk_ops_branch,
1109 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1110 },
1111};
1112
1113static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1114 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1115 .has_sibling = 0,
1116 .base = &virt_bases[GCC_BASE],
1117 .c = {
1118 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1119 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1120 .ops = &clk_ops_branch,
1121 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1122 },
1123};
1124
1125static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1126 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1127 .has_sibling = 0,
1128 .base = &virt_bases[GCC_BASE],
1129 .c = {
1130 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1131 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1132 .ops = &clk_ops_branch,
1133 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1134 },
1135};
1136
1137static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1138 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1139 .has_sibling = 0,
1140 .base = &virt_bases[GCC_BASE],
1141 .c = {
1142 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1143 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1144 .ops = &clk_ops_branch,
1145 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1146 },
1147};
1148
1149static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1150 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1151 .has_sibling = 0,
1152 .base = &virt_bases[GCC_BASE],
1153 .c = {
1154 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1155 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1156 .ops = &clk_ops_branch,
1157 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1158 },
1159};
1160
1161static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1162 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1163 .has_sibling = 0,
1164 .base = &virt_bases[GCC_BASE],
1165 .c = {
1166 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1167 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1168 .ops = &clk_ops_branch,
1169 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1170 },
1171};
1172
1173static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1174 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1175 .has_sibling = 0,
1176 .base = &virt_bases[GCC_BASE],
1177 .c = {
1178 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1179 .parent = &blsp1_uart1_apps_clk_src.c,
1180 .ops = &clk_ops_branch,
1181 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1182 },
1183};
1184
1185static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1186 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1187 .has_sibling = 0,
1188 .base = &virt_bases[GCC_BASE],
1189 .c = {
1190 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1191 .parent = &blsp1_uart2_apps_clk_src.c,
1192 .ops = &clk_ops_branch,
1193 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1194 },
1195};
1196
1197static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1198 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1199 .has_sibling = 0,
1200 .base = &virt_bases[GCC_BASE],
1201 .c = {
1202 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1203 .parent = &blsp1_uart3_apps_clk_src.c,
1204 .ops = &clk_ops_branch,
1205 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1206 },
1207};
1208
1209static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1210 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1211 .has_sibling = 0,
1212 .base = &virt_bases[GCC_BASE],
1213 .c = {
1214 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1215 .parent = &blsp1_uart4_apps_clk_src.c,
1216 .ops = &clk_ops_branch,
1217 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1218 },
1219};
1220
1221static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1222 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1223 .has_sibling = 0,
1224 .base = &virt_bases[GCC_BASE],
1225 .c = {
1226 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1227 .parent = &blsp1_uart5_apps_clk_src.c,
1228 .ops = &clk_ops_branch,
1229 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1230 },
1231};
1232
1233static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1234 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1235 .has_sibling = 0,
1236 .base = &virt_bases[GCC_BASE],
1237 .c = {
1238 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1239 .parent = &blsp1_uart6_apps_clk_src.c,
1240 .ops = &clk_ops_branch,
1241 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1242 },
1243};
1244
1245static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1246 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1247 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1248 .en_mask = BIT(10),
1249 .base = &virt_bases[GCC_BASE],
1250 .c = {
1251 .dbg_name = "gcc_boot_rom_ahb_clk",
1252 .ops = &clk_ops_vote,
1253 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1254 },
1255};
1256
1257static struct local_vote_clk gcc_ce1_ahb_clk = {
1258 .cbcr_reg = CE1_AHB_CBCR,
1259 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1260 .en_mask = BIT(3),
1261 .base = &virt_bases[GCC_BASE],
1262 .c = {
1263 .dbg_name = "gcc_ce1_ahb_clk",
1264 .ops = &clk_ops_vote,
1265 CLK_INIT(gcc_ce1_ahb_clk.c),
1266 },
1267};
1268
1269static struct local_vote_clk gcc_ce1_axi_clk = {
1270 .cbcr_reg = CE1_AXI_CBCR,
1271 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1272 .en_mask = BIT(4),
1273 .base = &virt_bases[GCC_BASE],
1274 .c = {
1275 .dbg_name = "gcc_ce1_axi_clk",
1276 .ops = &clk_ops_vote,
1277 CLK_INIT(gcc_ce1_axi_clk.c),
1278 },
1279};
1280
1281static struct local_vote_clk gcc_ce1_clk = {
1282 .cbcr_reg = CE1_CBCR,
1283 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1284 .en_mask = BIT(5),
1285 .base = &virt_bases[GCC_BASE],
1286 .c = {
1287 .dbg_name = "gcc_ce1_clk",
1288 .ops = &clk_ops_vote,
1289 CLK_INIT(gcc_ce1_clk.c),
1290 },
1291};
1292
1293static struct branch_clk gcc_gp1_clk = {
1294 .cbcr_reg = GP1_CBCR,
1295 .has_sibling = 0,
1296 .base = &virt_bases[GCC_BASE],
1297 .c = {
1298 .dbg_name = "gcc_gp1_clk",
1299 .parent = &gp1_clk_src.c,
1300 .ops = &clk_ops_branch,
1301 CLK_INIT(gcc_gp1_clk.c),
1302 },
1303};
1304
1305static struct branch_clk gcc_gp2_clk = {
1306 .cbcr_reg = GP2_CBCR,
1307 .has_sibling = 0,
1308 .base = &virt_bases[GCC_BASE],
1309 .c = {
1310 .dbg_name = "gcc_gp2_clk",
1311 .parent = &gp2_clk_src.c,
1312 .ops = &clk_ops_branch,
1313 CLK_INIT(gcc_gp2_clk.c),
1314 },
1315};
1316
1317static struct branch_clk gcc_gp3_clk = {
1318 .cbcr_reg = GP3_CBCR,
1319 .has_sibling = 0,
1320 .base = &virt_bases[GCC_BASE],
1321 .c = {
1322 .dbg_name = "gcc_gp3_clk",
1323 .parent = &gp3_clk_src.c,
1324 .ops = &clk_ops_branch,
1325 CLK_INIT(gcc_gp3_clk.c),
1326 },
1327};
1328
1329static struct branch_clk gcc_lpass_q6_axi_clk = {
1330 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1331 .has_sibling = 1,
1332 .base = &virt_bases[GCC_BASE],
1333 .c = {
1334 .dbg_name = "gcc_lpass_q6_axi_clk",
1335 .ops = &clk_ops_branch,
1336 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1337 },
1338};
1339
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1340static struct branch_clk gcc_mss_cfg_ahb_clk = {
1341 .cbcr_reg = MSS_CFG_AHB_CBCR,
1342 .has_sibling = 1,
1343 .base = &virt_bases[GCC_BASE],
1344 .c = {
1345 .dbg_name = "gcc_mss_cfg_ahb_clk",
1346 .ops = &clk_ops_branch,
1347 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1348 },
1349};
1350
1351static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1352 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1353 .has_sibling = 1,
1354 .base = &virt_bases[GCC_BASE],
1355 .c = {
1356 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1357 .ops = &clk_ops_branch,
1358 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1359 },
1360};
1361
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1362static struct branch_clk gcc_pdm2_clk = {
1363 .cbcr_reg = PDM2_CBCR,
1364 .has_sibling = 0,
1365 .base = &virt_bases[GCC_BASE],
1366 .c = {
1367 .dbg_name = "gcc_pdm2_clk",
1368 .parent = &pdm2_clk_src.c,
1369 .ops = &clk_ops_branch,
1370 CLK_INIT(gcc_pdm2_clk.c),
1371 },
1372};
1373
1374static struct branch_clk gcc_pdm_ahb_clk = {
1375 .cbcr_reg = PDM_AHB_CBCR,
1376 .has_sibling = 1,
1377 .base = &virt_bases[GCC_BASE],
1378 .c = {
1379 .dbg_name = "gcc_pdm_ahb_clk",
1380 .ops = &clk_ops_branch,
1381 CLK_INIT(gcc_pdm_ahb_clk.c),
1382 },
1383};
1384
1385static struct branch_clk gcc_pdm_xo4_clk = {
1386 .cbcr_reg = PDM_XO4_CBCR,
1387 .has_sibling = 1,
1388 .base = &virt_bases[GCC_BASE],
1389 .c = {
1390 .dbg_name = "gcc_pdm_xo4_clk",
1391 .parent = &xo.c,
1392 .ops = &clk_ops_branch,
1393 CLK_INIT(gcc_pdm_xo4_clk.c),
1394 },
1395};
1396
1397static struct branch_clk gcc_periph_noc_ahb_clk = {
1398 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1399 .has_sibling = 1,
1400 .base = &virt_bases[GCC_BASE],
1401 .c = {
1402 .dbg_name = "gcc_periph_noc_ahb_clk",
1403 .ops = &clk_ops_branch,
1404 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1405 },
1406};
1407
1408static struct local_vote_clk gcc_prng_ahb_clk = {
1409 .cbcr_reg = PRNG_AHB_CBCR,
1410 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1411 .en_mask = BIT(13),
1412 .base = &virt_bases[GCC_BASE],
1413 .c = {
1414 .dbg_name = "gcc_prng_ahb_clk",
1415 .ops = &clk_ops_vote,
1416 CLK_INIT(gcc_prng_ahb_clk.c),
1417 },
1418};
1419
1420static struct branch_clk gcc_sdcc1_ahb_clk = {
1421 .cbcr_reg = SDCC1_AHB_CBCR,
1422 .has_sibling = 1,
1423 .base = &virt_bases[GCC_BASE],
1424 .c = {
1425 .dbg_name = "gcc_sdcc1_ahb_clk",
1426 .ops = &clk_ops_branch,
1427 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1428 },
1429};
1430
1431static struct branch_clk gcc_sdcc1_apps_clk = {
1432 .cbcr_reg = SDCC1_APPS_CBCR,
1433 .has_sibling = 0,
1434 .base = &virt_bases[GCC_BASE],
1435 .c = {
1436 .dbg_name = "gcc_sdcc1_apps_clk",
1437 .parent = &sdcc1_apps_clk_src.c,
1438 .ops = &clk_ops_branch,
1439 CLK_INIT(gcc_sdcc1_apps_clk.c),
1440 },
1441};
1442
1443static struct branch_clk gcc_sdcc2_ahb_clk = {
1444 .cbcr_reg = SDCC2_AHB_CBCR,
1445 .has_sibling = 1,
1446 .base = &virt_bases[GCC_BASE],
1447 .c = {
1448 .dbg_name = "gcc_sdcc2_ahb_clk",
1449 .ops = &clk_ops_branch,
1450 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1451 },
1452};
1453
1454static struct branch_clk gcc_sdcc2_apps_clk = {
1455 .cbcr_reg = SDCC2_APPS_CBCR,
1456 .has_sibling = 0,
1457 .base = &virt_bases[GCC_BASE],
1458 .c = {
1459 .dbg_name = "gcc_sdcc2_apps_clk",
1460 .parent = &sdcc2_apps_clk_src.c,
1461 .ops = &clk_ops_branch,
1462 CLK_INIT(gcc_sdcc2_apps_clk.c),
1463 },
1464};
1465
1466static struct branch_clk gcc_sdcc3_ahb_clk = {
1467 .cbcr_reg = SDCC3_AHB_CBCR,
1468 .has_sibling = 1,
1469 .base = &virt_bases[GCC_BASE],
1470 .c = {
1471 .dbg_name = "gcc_sdcc3_ahb_clk",
1472 .ops = &clk_ops_branch,
1473 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1474 },
1475};
1476
1477static struct branch_clk gcc_sdcc3_apps_clk = {
1478 .cbcr_reg = SDCC3_APPS_CBCR,
1479 .has_sibling = 0,
1480 .base = &virt_bases[GCC_BASE],
1481 .c = {
1482 .dbg_name = "gcc_sdcc3_apps_clk",
1483 .parent = &sdcc3_apps_clk_src.c,
1484 .ops = &clk_ops_branch,
1485 CLK_INIT(gcc_sdcc3_apps_clk.c),
1486 },
1487};
1488
1489static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1490 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1491 .has_sibling = 1,
1492 .base = &virt_bases[GCC_BASE],
1493 .c = {
1494 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1495 .ops = &clk_ops_branch,
1496 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1497 },
1498};
1499
1500static struct branch_clk gcc_usb_hs_ahb_clk = {
1501 .cbcr_reg = USB_HS_AHB_CBCR,
1502 .has_sibling = 1,
1503 .base = &virt_bases[GCC_BASE],
1504 .c = {
1505 .dbg_name = "gcc_usb_hs_ahb_clk",
1506 .ops = &clk_ops_branch,
1507 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1508 },
1509};
1510
1511static struct branch_clk gcc_usb_hs_system_clk = {
1512 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1513 .has_sibling = 0,
1514 .bcr_reg = USB_HS_BCR,
1515 .base = &virt_bases[GCC_BASE],
1516 .c = {
1517 .dbg_name = "gcc_usb_hs_system_clk",
1518 .parent = &usb_hs_system_clk_src.c,
1519 .ops = &clk_ops_branch,
1520 CLK_INIT(gcc_usb_hs_system_clk.c),
1521 },
1522};
1523
1524static struct branch_clk gcc_usb_hsic_ahb_clk = {
1525 .cbcr_reg = USB_HSIC_AHB_CBCR,
1526 .has_sibling = 1,
1527 .base = &virt_bases[GCC_BASE],
1528 .c = {
1529 .dbg_name = "gcc_usb_hsic_ahb_clk",
1530 .ops = &clk_ops_branch,
1531 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1532 },
1533};
1534
1535static struct branch_clk gcc_usb_hsic_clk = {
1536 .cbcr_reg = USB_HSIC_CBCR,
1537 .has_sibling = 0,
1538 .bcr_reg = USB_HS_HSIC_BCR,
1539 .base = &virt_bases[GCC_BASE],
1540 .c = {
1541 .dbg_name = "gcc_usb_hsic_clk",
1542 .parent = &usb_hsic_clk_src.c,
1543 .ops = &clk_ops_branch,
1544 CLK_INIT(gcc_usb_hsic_clk.c),
1545 },
1546};
1547
1548static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1549 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1550 .has_sibling = 0,
1551 .base = &virt_bases[GCC_BASE],
1552 .c = {
1553 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1554 .parent = &usb_hsic_io_cal_clk_src.c,
1555 .ops = &clk_ops_branch,
1556 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1557 },
1558};
1559
1560static struct branch_clk gcc_usb_hsic_system_clk = {
1561 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1562 .has_sibling = 0,
1563 .bcr_reg = USB_HS_HSIC_BCR,
1564 .base = &virt_bases[GCC_BASE],
1565 .c = {
1566 .dbg_name = "gcc_usb_hsic_system_clk",
1567 .parent = &usb_hsic_system_clk_src.c,
1568 .ops = &clk_ops_branch,
1569 CLK_INIT(gcc_usb_hsic_system_clk.c),
1570 },
1571};
1572
1573static struct measure_mux_entry measure_mux_GCC[] = {
1574 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1575 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1576 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1577 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1578 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1579 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1580 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1581 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1582 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1583 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1584 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1585 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1586 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1587 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1588 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1589 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1590 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1591 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1592 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1593 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1594 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1595 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1596 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1597 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1598 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1599 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1600 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1601 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1602 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1603 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1604 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1605 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1606 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1607 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1608 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1609 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1610 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1611 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1612 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1613 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1614 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1615 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1616 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1617 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1618 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1619 {&dummy_clk, N_BASES, 0x0000},
1620};
1621
1622static struct pll_vote_clk mmpll0_pll = {
1623 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1624 .en_mask = BIT(0),
1625 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1626 .status_mask = BIT(17),
1627 .base = &virt_bases[MMSS_BASE],
1628 .c = {
1629 .rate = 800000000,
1630 .parent = &xo.c,
1631 .dbg_name = "mmpll0_pll",
1632 .ops = &clk_ops_pll_vote,
1633 CLK_INIT(mmpll0_pll.c),
1634 },
1635};
1636
1637static struct pll_vote_clk mmpll1_pll = {
1638 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1639 .en_mask = BIT(1),
1640 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1641 .status_mask = BIT(17),
1642 .base = &virt_bases[MMSS_BASE],
1643 .c = {
1644 .rate = 1000000000,
1645 .parent = &xo.c,
1646 .dbg_name = "mmpll1_pll",
1647 .ops = &clk_ops_pll_vote,
1648 CLK_INIT(mmpll1_pll.c),
1649 },
1650};
1651
1652static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1653 F_MMSS( 19200000, xo, 1, 0, 0),
1654 F_MMSS( 37500000, gpll0, 16, 0, 0),
1655 F_MMSS( 50000000, gpll0, 12, 0, 0),
1656 F_MMSS( 75000000, gpll0, 8, 0, 0),
1657 F_MMSS( 100000000, gpll0, 6, 0, 0),
1658 F_MMSS( 150000000, gpll0, 4, 0, 0),
1659 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1660 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1661 F_END
1662};
1663
1664static struct rcg_clk axi_clk_src = {
1665 .cmd_rcgr_reg = AXI_CMD_RCGR,
1666 .set_rate = set_rate_hid,
1667 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1668 .current_freq = &rcg_dummy_freq,
1669 .base = &virt_bases[MMSS_BASE],
1670 .c = {
1671 .dbg_name = "axi_clk_src",
1672 .ops = &clk_ops_rcg,
1673 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1674 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1675 CLK_INIT(axi_clk_src.c),
1676 },
1677};
1678
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1679static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1680 F_MMSS( 100000000, gpll0, 6, 0, 0),
1681 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1682 F_END
1683};
1684
1685static struct rcg_clk csi0_clk_src = {
1686 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1687 .set_rate = set_rate_hid,
1688 .freq_tbl = ftbl_camss_csi0_1_clk,
1689 .current_freq = &rcg_dummy_freq,
1690 .base = &virt_bases[MMSS_BASE],
1691 .c = {
1692 .dbg_name = "csi0_clk_src",
1693 .ops = &clk_ops_rcg,
1694 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1695 CLK_INIT(csi0_clk_src.c),
1696 },
1697};
1698
1699static struct rcg_clk csi1_clk_src = {
1700 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1701 .set_rate = set_rate_hid,
1702 .freq_tbl = ftbl_camss_csi0_1_clk,
1703 .current_freq = &rcg_dummy_freq,
1704 .base = &virt_bases[MMSS_BASE],
1705 .c = {
1706 .dbg_name = "csi1_clk_src",
1707 .ops = &clk_ops_rcg,
1708 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1709 CLK_INIT(csi1_clk_src.c),
1710 },
1711};
1712
1713static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1714 F_MMSS( 37500000, gpll0, 16, 0, 0),
1715 F_MMSS( 50000000, gpll0, 12, 0, 0),
1716 F_MMSS( 60000000, gpll0, 10, 0, 0),
1717 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1718 F_MMSS( 100000000, gpll0, 6, 0, 0),
1719 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1720 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1721 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1722 F_MMSS( 200000000, gpll0, 3, 0, 0),
1723 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1724 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1725 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1726 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1727 F_END
1728};
1729
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1730static unsigned long camss_vfe_vfe0_fmax_v2[VDD_DIG_NUM] = {
1731 150000000, 320000000, 400000000,
1732};
1733
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1734static struct rcg_clk vfe0_clk_src = {
1735 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1736 .set_rate = set_rate_hid,
1737 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1738 .current_freq = &rcg_dummy_freq,
1739 .base = &virt_bases[MMSS_BASE],
1740 .c = {
1741 .dbg_name = "vfe0_clk_src",
1742 .ops = &clk_ops_rcg,
1743 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1744 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1745 CLK_INIT(vfe0_clk_src.c),
1746 },
1747};
1748
1749static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1750 F_MMSS( 37500000, gpll0, 16, 0, 0),
1751 F_MMSS( 60000000, gpll0, 10, 0, 0),
1752 F_MMSS( 75000000, gpll0, 8, 0, 0),
1753 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1754 F_MMSS( 100000000, gpll0, 6, 0, 0),
1755 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1756 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1757 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1758 F_END
1759};
1760
1761static struct rcg_clk mdp_clk_src = {
1762 .cmd_rcgr_reg = MDP_CMD_RCGR,
1763 .set_rate = set_rate_hid,
1764 .freq_tbl = ftbl_mdss_mdp_clk,
1765 .current_freq = &rcg_dummy_freq,
1766 .base = &virt_bases[MMSS_BASE],
1767 .c = {
1768 .dbg_name = "mdp_clk_src",
1769 .ops = &clk_ops_rcg,
1770 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1771 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1772 CLK_INIT(mdp_clk_src.c),
1773 },
1774};
1775
1776static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1777 F_MMSS( 75000000, gpll0, 8, 0, 0),
1778 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1779 F_MMSS( 200000000, gpll0, 3, 0, 0),
1780 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1781 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1782 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1783 F_END
1784};
1785
1786static struct rcg_clk jpeg0_clk_src = {
1787 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1788 .set_rate = set_rate_hid,
1789 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1790 .current_freq = &rcg_dummy_freq,
1791 .base = &virt_bases[MMSS_BASE],
1792 .c = {
1793 .dbg_name = "jpeg0_clk_src",
1794 .ops = &clk_ops_rcg,
1795 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1796 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1797 CLK_INIT(jpeg0_clk_src.c),
1798 },
1799};
1800
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1801struct clk_ops clk_ops_pixel_clock;
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1802
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1803static long round_rate_pixel(struct clk *clk, unsigned long rate)
1804{
1805 int frac_num[] = {3, 2, 4, 1};
1806 int frac_den[] = {8, 9, 9, 1};
1807 int delta = 100000;
1808 int i;
1809
1810 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1811 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1812 unsigned long src_rate;
1813
1814 src_rate = clk_round_rate(clk->parent, request);
1815 if ((src_rate < (request - delta)) ||
1816 (src_rate > (request + delta)))
1817 continue;
1818
1819 return (src_rate * frac_num[i]) / frac_den[i];
1820 }
1821
1822 return -EINVAL;
1823}
1824
1825
1826static int set_rate_pixel(struct clk *clk, unsigned long rate)
1827{
1828 struct rcg_clk *rcg = to_rcg_clk(clk);
1829 struct clk_freq_tbl *pixel_freq = rcg->current_freq;
1830 int frac_num[] = {3, 2, 4, 1};
1831 int frac_den[] = {8, 9, 9, 1};
1832 int delta = 100000;
1833 int i, rc;
1834
1835 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1836 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1837 unsigned long src_rate;
1838
1839 src_rate = clk_round_rate(clk->parent, request);
1840 if ((src_rate < (request - delta)) ||
1841 (src_rate > (request + delta)))
1842 continue;
1843
1844 rc = clk_set_rate(clk->parent, src_rate);
1845 if (rc)
1846 return rc;
1847
1848 pixel_freq->div_src_val &= ~BM(4, 0);
1849 if (frac_den[i] == frac_num[i]) {
1850 pixel_freq->m_val = 0;
1851 pixel_freq->n_val = 0;
1852 } else {
1853 pixel_freq->m_val = frac_num[i];
1854 pixel_freq->n_val = ~(frac_den[i] - frac_num[i]);
1855 pixel_freq->d_val = ~frac_den[i];
1856 }
1857 set_rate_mnd(rcg, pixel_freq);
1858 return 0;
1859 }
1860 return -EINVAL;
1861}
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1862
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1863static struct clk_freq_tbl pixel_freq_tbl[] = {
1864 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1865 .src_clk = &pixel_clk_src_8226.c,
1866 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val)
1867 | BVAL(4, 0, 0),
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1868 },
1869 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1870};
1871
1872static struct rcg_clk pclk0_clk_src = {
1873 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1874 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1875 .base = &virt_bases[MMSS_BASE],
1876 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1877 .parent = &pixel_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1878 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1879 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1880 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1881 CLK_INIT(pclk0_clk_src.c),
1882 },
1883};
1884
1885static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1886 F_MMSS( 66700000, gpll0, 9, 0, 0),
1887 F_MMSS( 100000000, gpll0, 6, 0, 0),
1888 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1889 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1890 F_END
1891};
1892
1893static struct rcg_clk vcodec0_clk_src = {
1894 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1895 .set_rate = set_rate_mnd,
1896 .freq_tbl = ftbl_venus0_vcodec0_clk,
1897 .current_freq = &rcg_dummy_freq,
1898 .base = &virt_bases[MMSS_BASE],
1899 .c = {
1900 .dbg_name = "vcodec0_clk_src",
1901 .ops = &clk_ops_rcg_mnd,
Patrick Daly59c74322013-06-07 12:00:42 -0700[diff] [blame]1902 VDD_DIG_FMAX_MAP3(LOW, 66700000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1903 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1904 CLK_INIT(vcodec0_clk_src.c),
1905 },
1906};
1907
1908static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1909 F_MMSS( 19200000, xo, 1, 0, 0),
1910 F_END
1911};
1912
1913static struct rcg_clk cci_clk_src = {
1914 .cmd_rcgr_reg = CCI_CMD_RCGR,
1915 .set_rate = set_rate_mnd,
1916 .freq_tbl = ftbl_camss_cci_cci_clk,
1917 .current_freq = &rcg_dummy_freq,
1918 .base = &virt_bases[MMSS_BASE],
1919 .c = {
1920 .dbg_name = "cci_clk_src",
1921 .ops = &clk_ops_rcg_mnd,
1922 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1923 CLK_INIT(cci_clk_src.c),
1924 },
1925};
1926
1927static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1928 F_MMSS( 10000, xo, 16, 1, 120),
1929 F_MMSS( 24000, xo, 16, 1, 50),
1930 F_MMSS( 6000000, gpll0, 10, 1, 10),
1931 F_MMSS( 12000000, gpll0, 10, 1, 5),
1932 F_MMSS( 13000000, gpll0, 4, 13, 150),
1933 F_MMSS( 24000000, gpll0, 5, 1, 5),
1934 F_END
1935};
1936
1937static struct rcg_clk mmss_gp0_clk_src = {
1938 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1939 .set_rate = set_rate_mnd,
1940 .freq_tbl = ftbl_camss_gp0_1_clk,
1941 .current_freq = &rcg_dummy_freq,
1942 .base = &virt_bases[MMSS_BASE],
1943 .c = {
1944 .dbg_name = "mmss_gp0_clk_src",
1945 .ops = &clk_ops_rcg_mnd,
1946 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1947 CLK_INIT(mmss_gp0_clk_src.c),
1948 },
1949};
1950
1951static struct rcg_clk mmss_gp1_clk_src = {
1952 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1953 .set_rate = set_rate_mnd,
1954 .freq_tbl = ftbl_camss_gp0_1_clk,
1955 .current_freq = &rcg_dummy_freq,
1956 .base = &virt_bases[MMSS_BASE],
1957 .c = {
1958 .dbg_name = "mmss_gp1_clk_src",
1959 .ops = &clk_ops_rcg_mnd,
1960 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1961 CLK_INIT(mmss_gp1_clk_src.c),
1962 },
1963};
1964
1965static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1966 F_MMSS( 19200000, xo, 1, 0, 0),
1967 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1968 F_MMSS( 66670000, gpll0, 9, 0, 0),
1969 F_END
1970};
1971
1972static struct rcg_clk mclk0_clk_src = {
1973 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1974 .set_rate = set_rate_mnd,
1975 .freq_tbl = ftbl_camss_mclk0_1_clk,
1976 .current_freq = &rcg_dummy_freq,
1977 .base = &virt_bases[MMSS_BASE],
1978 .c = {
1979 .dbg_name = "mclk0_clk_src",
1980 .ops = &clk_ops_rcg_mnd,
1981 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1982 CLK_INIT(mclk0_clk_src.c),
1983 },
1984};
1985
1986static struct rcg_clk mclk1_clk_src = {
1987 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1988 .set_rate = set_rate_mnd,
1989 .freq_tbl = ftbl_camss_mclk0_1_clk,
1990 .current_freq = &rcg_dummy_freq,
1991 .base = &virt_bases[MMSS_BASE],
1992 .c = {
1993 .dbg_name = "mclk1_clk_src",
1994 .ops = &clk_ops_rcg_mnd,
1995 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1996 CLK_INIT(mclk1_clk_src.c),
1997 },
1998};
1999
2000static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
2001 F_MMSS( 100000000, gpll0, 6, 0, 0),
2002 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
2003 F_END
2004};
2005
2006static struct rcg_clk csi0phytimer_clk_src = {
2007 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
2008 .set_rate = set_rate_hid,
2009 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2010 .current_freq = &rcg_dummy_freq,
2011 .base = &virt_bases[MMSS_BASE],
2012 .c = {
2013 .dbg_name = "csi0phytimer_clk_src",
2014 .ops = &clk_ops_rcg,
2015 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2016 CLK_INIT(csi0phytimer_clk_src.c),
2017 },
2018};
2019
2020static struct rcg_clk csi1phytimer_clk_src = {
2021 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
2022 .set_rate = set_rate_hid,
2023 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2024 .current_freq = &rcg_dummy_freq,
2025 .base = &virt_bases[MMSS_BASE],
2026 .c = {
2027 .dbg_name = "csi1phytimer_clk_src",
2028 .ops = &clk_ops_rcg,
2029 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2030 CLK_INIT(csi1phytimer_clk_src.c),
2031 },
2032};
2033
2034static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
2035 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2036 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2037 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
2038 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2039 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2040 F_END
2041};
2042
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2043static unsigned long camss_vfe_cpp_fmax_v2[VDD_DIG_NUM] = {
2044 150000000, 320000000, 400000000,
2045};
2046
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2047static struct rcg_clk cpp_clk_src = {
2048 .cmd_rcgr_reg = CPP_CMD_RCGR,
2049 .set_rate = set_rate_hid,
2050 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2051 .current_freq = &rcg_dummy_freq,
2052 .base = &virt_bases[MMSS_BASE],
2053 .c = {
2054 .dbg_name = "cpp_clk_src",
2055 .ops = &clk_ops_rcg,
2056 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2057 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2058 CLK_INIT(cpp_clk_src.c),
2059 },
2060};
2061
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2062static struct clk_freq_tbl byte_freq_tbl[] = {
2063 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2064 .src_clk = &byte_clk_src_8226.c,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2065 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
2066 },
2067 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2068};
2069
2070static struct rcg_clk byte0_clk_src = {
2071 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2072 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2073 .base = &virt_bases[MMSS_BASE],
2074 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2075 .parent = &byte_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2076 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2077 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2078 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2079 CLK_INIT(byte0_clk_src.c),
2080 },
2081};
2082
2083static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2084 F_MDSS( 19200000, xo, 1, 0, 0),
2085 F_END
2086};
2087
2088static struct rcg_clk esc0_clk_src = {
2089 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2090 .set_rate = set_rate_hid,
2091 .freq_tbl = ftbl_mdss_esc0_clk,
2092 .current_freq = &rcg_dummy_freq,
2093 .base = &virt_bases[MMSS_BASE],
2094 .c = {
2095 .dbg_name = "esc0_clk_src",
2096 .ops = &clk_ops_rcg,
2097 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2098 CLK_INIT(esc0_clk_src.c),
2099 },
2100};
2101
2102static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2103 F_MDSS( 19200000, xo, 1, 0, 0),
2104 F_END
2105};
2106
2107static struct rcg_clk vsync_clk_src = {
2108 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2109 .set_rate = set_rate_hid,
2110 .freq_tbl = ftbl_mdss_vsync_clk,
2111 .current_freq = &rcg_dummy_freq,
2112 .base = &virt_bases[MMSS_BASE],
2113 .c = {
2114 .dbg_name = "vsync_clk_src",
2115 .ops = &clk_ops_rcg,
2116 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2117 CLK_INIT(vsync_clk_src.c),
2118 },
2119};
2120
2121static struct branch_clk camss_cci_cci_ahb_clk = {
2122 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2123 .has_sibling = 1,
2124 .base = &virt_bases[MMSS_BASE],
2125 .c = {
2126 .dbg_name = "camss_cci_cci_ahb_clk",
2127 .ops = &clk_ops_branch,
2128 CLK_INIT(camss_cci_cci_ahb_clk.c),
2129 },
2130};
2131
2132static struct branch_clk camss_cci_cci_clk = {
2133 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2134 .has_sibling = 0,
2135 .base = &virt_bases[MMSS_BASE],
2136 .c = {
2137 .dbg_name = "camss_cci_cci_clk",
2138 .parent = &cci_clk_src.c,
2139 .ops = &clk_ops_branch,
2140 CLK_INIT(camss_cci_cci_clk.c),
2141 },
2142};
2143
2144static struct branch_clk camss_csi0_ahb_clk = {
2145 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2146 .has_sibling = 1,
2147 .base = &virt_bases[MMSS_BASE],
2148 .c = {
2149 .dbg_name = "camss_csi0_ahb_clk",
2150 .ops = &clk_ops_branch,
2151 CLK_INIT(camss_csi0_ahb_clk.c),
2152 },
2153};
2154
2155static struct branch_clk camss_csi0_clk = {
2156 .cbcr_reg = CAMSS_CSI0_CBCR,
2157 .has_sibling = 1,
2158 .base = &virt_bases[MMSS_BASE],
2159 .c = {
2160 .dbg_name = "camss_csi0_clk",
2161 .parent = &csi0_clk_src.c,
2162 .ops = &clk_ops_branch,
2163 CLK_INIT(camss_csi0_clk.c),
2164 },
2165};
2166
2167static struct branch_clk camss_csi0phy_clk = {
2168 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2169 .has_sibling = 1,
2170 .base = &virt_bases[MMSS_BASE],
2171 .c = {
2172 .dbg_name = "camss_csi0phy_clk",
2173 .parent = &csi0_clk_src.c,
2174 .ops = &clk_ops_branch,
2175 CLK_INIT(camss_csi0phy_clk.c),
2176 },
2177};
2178
2179static struct branch_clk camss_csi0pix_clk = {
2180 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2181 .has_sibling = 1,
2182 .base = &virt_bases[MMSS_BASE],
2183 .c = {
2184 .dbg_name = "camss_csi0pix_clk",
2185 .parent = &csi0_clk_src.c,
2186 .ops = &clk_ops_branch,
2187 CLK_INIT(camss_csi0pix_clk.c),
2188 },
2189};
2190
2191static struct branch_clk camss_csi0rdi_clk = {
2192 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2193 .has_sibling = 1,
2194 .base = &virt_bases[MMSS_BASE],
2195 .c = {
2196 .dbg_name = "camss_csi0rdi_clk",
2197 .parent = &csi0_clk_src.c,
2198 .ops = &clk_ops_branch,
2199 CLK_INIT(camss_csi0rdi_clk.c),
2200 },
2201};
2202
2203static struct branch_clk camss_csi1_ahb_clk = {
2204 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2205 .has_sibling = 1,
2206 .base = &virt_bases[MMSS_BASE],
2207 .c = {
2208 .dbg_name = "camss_csi1_ahb_clk",
2209 .ops = &clk_ops_branch,
2210 CLK_INIT(camss_csi1_ahb_clk.c),
2211 },
2212};
2213
2214static struct branch_clk camss_csi1_clk = {
2215 .cbcr_reg = CAMSS_CSI1_CBCR,
2216 .has_sibling = 1,
2217 .base = &virt_bases[MMSS_BASE],
2218 .c = {
2219 .dbg_name = "camss_csi1_clk",
2220 .parent = &csi1_clk_src.c,
2221 .ops = &clk_ops_branch,
2222 CLK_INIT(camss_csi1_clk.c),
2223 },
2224};
2225
2226static struct branch_clk camss_csi1phy_clk = {
2227 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2228 .has_sibling = 1,
2229 .base = &virt_bases[MMSS_BASE],
2230 .c = {
2231 .dbg_name = "camss_csi1phy_clk",
2232 .parent = &csi1_clk_src.c,
2233 .ops = &clk_ops_branch,
2234 CLK_INIT(camss_csi1phy_clk.c),
2235 },
2236};
2237
2238static struct branch_clk camss_csi1pix_clk = {
2239 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2240 .has_sibling = 1,
2241 .base = &virt_bases[MMSS_BASE],
2242 .c = {
2243 .dbg_name = "camss_csi1pix_clk",
2244 .parent = &csi1_clk_src.c,
2245 .ops = &clk_ops_branch,
2246 CLK_INIT(camss_csi1pix_clk.c),
2247 },
2248};
2249
2250static struct branch_clk camss_csi1rdi_clk = {
2251 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2252 .has_sibling = 1,
2253 .base = &virt_bases[MMSS_BASE],
2254 .c = {
2255 .dbg_name = "camss_csi1rdi_clk",
2256 .parent = &csi1_clk_src.c,
2257 .ops = &clk_ops_branch,
2258 CLK_INIT(camss_csi1rdi_clk.c),
2259 },
2260};
2261
2262static struct branch_clk camss_csi_vfe0_clk = {
2263 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2264 .bcr_reg = CAMSS_CSI_VFE0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2265 .has_sibling = 1,
2266 .base = &virt_bases[MMSS_BASE],
2267 .c = {
2268 .dbg_name = "camss_csi_vfe0_clk",
2269 .parent = &vfe0_clk_src.c,
2270 .ops = &clk_ops_branch,
2271 CLK_INIT(camss_csi_vfe0_clk.c),
2272 },
2273};
2274
2275static struct branch_clk camss_gp0_clk = {
2276 .cbcr_reg = CAMSS_GP0_CBCR,
2277 .has_sibling = 0,
2278 .base = &virt_bases[MMSS_BASE],
2279 .c = {
2280 .dbg_name = "camss_gp0_clk",
2281 .parent = &mmss_gp0_clk_src.c,
2282 .ops = &clk_ops_branch,
2283 CLK_INIT(camss_gp0_clk.c),
2284 },
2285};
2286
2287static struct branch_clk camss_gp1_clk = {
2288 .cbcr_reg = CAMSS_GP1_CBCR,
2289 .has_sibling = 0,
2290 .base = &virt_bases[MMSS_BASE],
2291 .c = {
2292 .dbg_name = "camss_gp1_clk",
2293 .parent = &mmss_gp1_clk_src.c,
2294 .ops = &clk_ops_branch,
2295 CLK_INIT(camss_gp1_clk.c),
2296 },
2297};
2298
2299static struct branch_clk camss_ispif_ahb_clk = {
2300 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2301 .has_sibling = 1,
2302 .base = &virt_bases[MMSS_BASE],
2303 .c = {
2304 .dbg_name = "camss_ispif_ahb_clk",
2305 .ops = &clk_ops_branch,
2306 CLK_INIT(camss_ispif_ahb_clk.c),
2307 },
2308};
2309
2310static struct branch_clk camss_jpeg_jpeg0_clk = {
2311 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2312 .bcr_reg = CAMSS_JPEG_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2313 .has_sibling = 0,
2314 .base = &virt_bases[MMSS_BASE],
2315 .c = {
2316 .dbg_name = "camss_jpeg_jpeg0_clk",
2317 .parent = &jpeg0_clk_src.c,
2318 .ops = &clk_ops_branch,
2319 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2320 },
2321};
2322
2323static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2324 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2325 .has_sibling = 1,
2326 .base = &virt_bases[MMSS_BASE],
2327 .c = {
2328 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2329 .ops = &clk_ops_branch,
2330 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2331 },
2332};
2333
2334static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2335 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2336 .has_sibling = 1,
2337 .base = &virt_bases[MMSS_BASE],
2338 .c = {
2339 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2340 .parent = &axi_clk_src.c,
2341 .ops = &clk_ops_branch,
2342 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2343 },
2344};
2345
2346static struct branch_clk camss_mclk0_clk = {
2347 .cbcr_reg = CAMSS_MCLK0_CBCR,
2348 .has_sibling = 0,
2349 .base = &virt_bases[MMSS_BASE],
2350 .c = {
2351 .dbg_name = "camss_mclk0_clk",
2352 .parent = &mclk0_clk_src.c,
2353 .ops = &clk_ops_branch,
2354 CLK_INIT(camss_mclk0_clk.c),
2355 },
2356};
2357
2358static struct branch_clk camss_mclk1_clk = {
2359 .cbcr_reg = CAMSS_MCLK1_CBCR,
2360 .has_sibling = 0,
2361 .base = &virt_bases[MMSS_BASE],
2362 .c = {
2363 .dbg_name = "camss_mclk1_clk",
2364 .parent = &mclk1_clk_src.c,
2365 .ops = &clk_ops_branch,
2366 CLK_INIT(camss_mclk1_clk.c),
2367 },
2368};
2369
2370static struct branch_clk camss_micro_ahb_clk = {
2371 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2372 .has_sibling = 1,
2373 .base = &virt_bases[MMSS_BASE],
2374 .c = {
2375 .dbg_name = "camss_micro_ahb_clk",
2376 .ops = &clk_ops_branch,
2377 CLK_INIT(camss_micro_ahb_clk.c),
2378 },
2379};
2380
2381static struct branch_clk camss_phy0_csi0phytimer_clk = {
2382 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2383 .has_sibling = 0,
2384 .base = &virt_bases[MMSS_BASE],
2385 .c = {
2386 .dbg_name = "camss_phy0_csi0phytimer_clk",
2387 .parent = &csi0phytimer_clk_src.c,
2388 .ops = &clk_ops_branch,
2389 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2390 },
2391};
2392
2393static struct branch_clk camss_phy1_csi1phytimer_clk = {
2394 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2395 .has_sibling = 0,
2396 .base = &virt_bases[MMSS_BASE],
2397 .c = {
2398 .dbg_name = "camss_phy1_csi1phytimer_clk",
2399 .parent = &csi1phytimer_clk_src.c,
2400 .ops = &clk_ops_branch,
2401 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2402 },
2403};
2404
2405static struct branch_clk camss_top_ahb_clk = {
2406 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2407 .has_sibling = 1,
2408 .base = &virt_bases[MMSS_BASE],
2409 .c = {
2410 .dbg_name = "camss_top_ahb_clk",
2411 .ops = &clk_ops_branch,
2412 CLK_INIT(camss_top_ahb_clk.c),
2413 },
2414};
2415
2416static struct branch_clk camss_vfe_cpp_ahb_clk = {
2417 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2418 .has_sibling = 1,
2419 .base = &virt_bases[MMSS_BASE],
2420 .c = {
2421 .dbg_name = "camss_vfe_cpp_ahb_clk",
2422 .ops = &clk_ops_branch,
2423 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2424 },
2425};
2426
2427static struct branch_clk camss_vfe_cpp_clk = {
2428 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2429 .has_sibling = 0,
2430 .base = &virt_bases[MMSS_BASE],
2431 .c = {
2432 .dbg_name = "camss_vfe_cpp_clk",
2433 .parent = &cpp_clk_src.c,
2434 .ops = &clk_ops_branch,
2435 CLK_INIT(camss_vfe_cpp_clk.c),
2436 },
2437};
2438
2439static struct branch_clk camss_vfe_vfe0_clk = {
2440 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2441 .bcr_reg = CAMSS_VFE_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2442 .has_sibling = 1,
2443 .base = &virt_bases[MMSS_BASE],
2444 .c = {
2445 .dbg_name = "camss_vfe_vfe0_clk",
2446 .parent = &vfe0_clk_src.c,
2447 .ops = &clk_ops_branch,
2448 CLK_INIT(camss_vfe_vfe0_clk.c),
2449 },
2450};
2451
2452static struct branch_clk camss_vfe_vfe_ahb_clk = {
2453 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2454 .has_sibling = 1,
2455 .base = &virt_bases[MMSS_BASE],
2456 .c = {
2457 .dbg_name = "camss_vfe_vfe_ahb_clk",
2458 .ops = &clk_ops_branch,
2459 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2460 },
2461};
2462
2463static struct branch_clk camss_vfe_vfe_axi_clk = {
2464 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2465 .has_sibling = 1,
2466 .base = &virt_bases[MMSS_BASE],
2467 .c = {
2468 .dbg_name = "camss_vfe_vfe_axi_clk",
2469 .parent = &axi_clk_src.c,
2470 .ops = &clk_ops_branch,
2471 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2472 },
2473};
2474
2475static struct branch_clk mdss_ahb_clk = {
2476 .cbcr_reg = MDSS_AHB_CBCR,
2477 .has_sibling = 1,
2478 .base = &virt_bases[MMSS_BASE],
2479 .c = {
2480 .dbg_name = "mdss_ahb_clk",
2481 .ops = &clk_ops_branch,
2482 CLK_INIT(mdss_ahb_clk.c),
2483 },
2484};
2485
2486static struct branch_clk mdss_axi_clk = {
2487 .cbcr_reg = MDSS_AXI_CBCR,
2488 .has_sibling = 1,
2489 .base = &virt_bases[MMSS_BASE],
2490 .c = {
2491 .dbg_name = "mdss_axi_clk",
2492 .parent = &axi_clk_src.c,
2493 .ops = &clk_ops_branch,
2494 CLK_INIT(mdss_axi_clk.c),
2495 },
2496};
2497
2498static struct branch_clk mdss_byte0_clk = {
2499 .cbcr_reg = MDSS_BYTE0_CBCR,
2500 .has_sibling = 0,
2501 .base = &virt_bases[MMSS_BASE],
2502 .c = {
2503 .dbg_name = "mdss_byte0_clk",
2504 .parent = &byte0_clk_src.c,
2505 .ops = &clk_ops_branch,
2506 CLK_INIT(mdss_byte0_clk.c),
2507 },
2508};
2509
2510static struct branch_clk mdss_esc0_clk = {
2511 .cbcr_reg = MDSS_ESC0_CBCR,
2512 .has_sibling = 0,
2513 .base = &virt_bases[MMSS_BASE],
2514 .c = {
2515 .dbg_name = "mdss_esc0_clk",
2516 .parent = &esc0_clk_src.c,
2517 .ops = &clk_ops_branch,
2518 CLK_INIT(mdss_esc0_clk.c),
2519 },
2520};
2521
2522static struct branch_clk mdss_mdp_clk = {
2523 .cbcr_reg = MDSS_MDP_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2524 .bcr_reg = MDSS_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2525 .has_sibling = 1,
2526 .base = &virt_bases[MMSS_BASE],
2527 .c = {
2528 .dbg_name = "mdss_mdp_clk",
2529 .parent = &mdp_clk_src.c,
2530 .ops = &clk_ops_branch,
2531 CLK_INIT(mdss_mdp_clk.c),
2532 },
2533};
2534
2535static struct branch_clk mdss_mdp_lut_clk = {
2536 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2537 .has_sibling = 1,
2538 .base = &virt_bases[MMSS_BASE],
2539 .c = {
2540 .dbg_name = "mdss_mdp_lut_clk",
2541 .parent = &mdp_clk_src.c,
2542 .ops = &clk_ops_branch,
2543 CLK_INIT(mdss_mdp_lut_clk.c),
2544 },
2545};
2546
2547static struct branch_clk mdss_pclk0_clk = {
2548 .cbcr_reg = MDSS_PCLK0_CBCR,
2549 .has_sibling = 0,
2550 .base = &virt_bases[MMSS_BASE],
2551 .c = {
2552 .dbg_name = "mdss_pclk0_clk",
2553 .parent = &pclk0_clk_src.c,
2554 .ops = &clk_ops_branch,
2555 CLK_INIT(mdss_pclk0_clk.c),
2556 },
2557};
2558
2559static struct branch_clk mdss_vsync_clk = {
2560 .cbcr_reg = MDSS_VSYNC_CBCR,
2561 .has_sibling = 0,
2562 .base = &virt_bases[MMSS_BASE],
2563 .c = {
2564 .dbg_name = "mdss_vsync_clk",
2565 .parent = &vsync_clk_src.c,
2566 .ops = &clk_ops_branch,
2567 CLK_INIT(mdss_vsync_clk.c),
2568 },
2569};
2570
2571static struct branch_clk mmss_misc_ahb_clk = {
2572 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2573 .has_sibling = 1,
2574 .base = &virt_bases[MMSS_BASE],
2575 .c = {
2576 .dbg_name = "mmss_misc_ahb_clk",
2577 .ops = &clk_ops_branch,
2578 CLK_INIT(mmss_misc_ahb_clk.c),
2579 },
2580};
2581
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2582static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2583 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2584 .has_sibling = 1,
2585 .base = &virt_bases[MMSS_BASE],
2586 .c = {
2587 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2588 .ops = &clk_ops_branch,
2589 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2590 },
2591};
2592
2593static struct branch_clk mmss_mmssnoc_axi_clk = {
2594 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2595 .has_sibling = 1,
2596 .base = &virt_bases[MMSS_BASE],
2597 .c = {
2598 .dbg_name = "mmss_mmssnoc_axi_clk",
2599 .parent = &axi_clk_src.c,
2600 .ops = &clk_ops_branch,
2601 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2602 },
2603};
2604
2605static struct branch_clk mmss_s0_axi_clk = {
2606 .cbcr_reg = MMSS_S0_AXI_CBCR,
2607 .has_sibling = 0,
2608 .max_div = 0,
2609 .base = &virt_bases[MMSS_BASE],
2610 .c = {
2611 .dbg_name = "mmss_s0_axi_clk",
2612 .parent = &axi_clk_src.c,
2613 .ops = &clk_ops_branch,
2614 CLK_INIT(mmss_s0_axi_clk.c),
2615 .depends = &mmss_mmssnoc_axi_clk.c,
2616 },
2617};
2618
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2619static struct branch_clk oxili_gfx3d_clk = {
2620 .cbcr_reg = OXILI_GFX3D_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2621 .bcr_reg = OXILICX_BCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2622 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2623 .max_div = 0,
2624 .base = &virt_bases[MMSS_BASE],
2625 .c = {
2626 .dbg_name = "oxili_gfx3d_clk",
2627 .parent = &gfx3d_clk_src.c,
2628 .ops = &clk_ops_branch,
2629 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2630 },
2631};
2632
2633static struct branch_clk oxilicx_ahb_clk = {
2634 .cbcr_reg = OXILICX_AHB_CBCR,
2635 .has_sibling = 1,
2636 .base = &virt_bases[MMSS_BASE],
2637 .c = {
2638 .dbg_name = "oxilicx_ahb_clk",
2639 .ops = &clk_ops_branch,
2640 CLK_INIT(oxilicx_ahb_clk.c),
2641 },
2642};
2643
2644static struct branch_clk oxilicx_axi_clk = {
2645 .cbcr_reg = OXILICX_AXI_CBCR,
2646 .has_sibling = 1,
2647 .base = &virt_bases[MMSS_BASE],
2648 .c = {
2649 .dbg_name = "oxilicx_axi_clk",
2650 .parent = &axi_clk_src.c,
2651 .ops = &clk_ops_branch,
2652 CLK_INIT(oxilicx_axi_clk.c),
2653 },
2654};
2655
2656static struct branch_clk venus0_ahb_clk = {
2657 .cbcr_reg = VENUS0_AHB_CBCR,
2658 .has_sibling = 1,
2659 .base = &virt_bases[MMSS_BASE],
2660 .c = {
2661 .dbg_name = "venus0_ahb_clk",
2662 .ops = &clk_ops_branch,
2663 CLK_INIT(venus0_ahb_clk.c),
2664 },
2665};
2666
2667static struct branch_clk venus0_axi_clk = {
2668 .cbcr_reg = VENUS0_AXI_CBCR,
2669 .has_sibling = 1,
2670 .base = &virt_bases[MMSS_BASE],
2671 .c = {
2672 .dbg_name = "venus0_axi_clk",
2673 .parent = &axi_clk_src.c,
2674 .ops = &clk_ops_branch,
2675 CLK_INIT(venus0_axi_clk.c),
2676 },
2677};
2678
2679static struct branch_clk venus0_vcodec0_clk = {
2680 .cbcr_reg = VENUS0_VCODEC0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2681 .bcr_reg = VENUS0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2682 .has_sibling = 0,
2683 .base = &virt_bases[MMSS_BASE],
2684 .c = {
2685 .dbg_name = "venus0_vcodec0_clk",
2686 .parent = &vcodec0_clk_src.c,
2687 .ops = &clk_ops_branch,
2688 CLK_INIT(venus0_vcodec0_clk.c),
2689 },
2690};
2691
2692static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2693 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2694 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2695 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2696 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2697 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2698 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2699 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2700 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2701 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2702 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2703 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2704 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2705 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2706 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2707 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2708 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2709 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2710 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2711 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2712 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2713 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2714 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2715 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2716 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2717 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2718 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2719 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2720 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2721 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2722 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2723 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2724 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2725 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2726 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2727 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2728 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2729 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2730 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2731 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2732 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2733 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2734 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2735 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2736 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2737 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2738 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2739 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2740 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2741 {&dummy_clk, N_BASES, 0x0000},
2742};
2743
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2744static struct branch_clk q6ss_ahb_lfabif_clk = {
2745 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2746 .has_sibling = 1,
2747 .base = &virt_bases[LPASS_BASE],
2748 .c = {
2749 .dbg_name = "q6ss_ahb_lfabif_clk",
2750 .ops = &clk_ops_branch,
2751 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2752 },
2753};
2754
2755static struct branch_clk q6ss_ahbm_clk = {
2756 .cbcr_reg = Q6SS_AHBM_CBCR,
2757 .has_sibling = 1,
2758 .base = &virt_bases[LPASS_BASE],
2759 .c = {
2760 .dbg_name = "q6ss_ahbm_clk",
2761 .ops = &clk_ops_branch,
2762 CLK_INIT(q6ss_ahbm_clk.c),
2763 },
2764};
2765
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2766static struct branch_clk q6ss_xo_clk = {
2767 .cbcr_reg = Q6SS_XO_CBCR,
2768 .has_sibling = 1,
2769 .bcr_reg = Q6SS_BCR,
2770 .base = &virt_bases[LPASS_BASE],
2771 .c = {
2772 .dbg_name = "q6ss_xo_clk",
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2773 .ops = &clk_ops_branch,
2774 CLK_INIT(q6ss_xo_clk.c),
2775 },
2776};
2777
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2778static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2779 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2780 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2781 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2782 {&dummy_clk, N_BASES, 0x0000},
2783};
2784
2785
2786static DEFINE_CLK_MEASURE(apc0_m_clk);
2787static DEFINE_CLK_MEASURE(apc1_m_clk);
2788static DEFINE_CLK_MEASURE(apc2_m_clk);
2789static DEFINE_CLK_MEASURE(apc3_m_clk);
2790static DEFINE_CLK_MEASURE(l2_m_clk);
2791
2792static struct measure_mux_entry measure_mux_APSS[] = {
2793 {&apc0_m_clk, APCS_BASE, 0x00010},
2794 {&apc1_m_clk, APCS_BASE, 0x00114},
2795 {&apc2_m_clk, APCS_BASE, 0x00220},
2796 {&apc3_m_clk, APCS_BASE, 0x00324},
2797 {&l2_m_clk, APCS_BASE, 0x01000},
2798 {&dummy_clk, N_BASES, 0x0000}
2799};
2800
2801#define APCS_SH_PLL_MODE (0x000)
2802#define APCS_SH_PLL_L_VAL (0x004)
2803#define APCS_SH_PLL_M_VAL (0x008)
2804#define APCS_SH_PLL_N_VAL (0x00C)
2805#define APCS_SH_PLL_USER_CTL (0x010)
2806#define APCS_SH_PLL_CONFIG_CTL (0x014)
2807#define APCS_SH_PLL_STATUS (0x01C)
2808
2809enum vdd_sr2_pll_levels {
2810 VDD_SR2_PLL_OFF,
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2811 VDD_SR2_PLL_SVS,
2812 VDD_SR2_PLL_NOM,
2813 VDD_SR2_PLL_TUR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2814 VDD_SR2_PLL_NUM
2815};
2816
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]2817static int vdd_sr2_levels[] = {
2818 0, RPM_REGULATOR_CORNER_NONE, /* VDD_SR2_PLL_OFF */
2819 1800000, RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_SR2_PLL_SVS */
2820 1800000, RPM_REGULATOR_CORNER_NORMAL, /* VDD_SR2_PLL_NOM */
2821 1800000, RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_SR2_PLL_TUR */
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2822};
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2823
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]2824static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
2825 vdd_sr2_levels, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2826
2827static struct pll_freq_tbl apcs_pll_freq[] = {
Patrick Daly83806032013-03-25 15:18:24 -0700[diff] [blame]2828 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2829 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2830 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyf363c252013-03-21 12:08:37 -0700[diff] [blame]2831 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2832 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Daly66e32aa2013-05-30 15:11:52 -0700[diff] [blame]2833 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
2834 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
2835 F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2836 PLL_F_END
2837};
2838
2839static struct pll_clk a7sspll = {
2840 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2841 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2842 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2843 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2844 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2845 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2846 .freq_tbl = apcs_pll_freq,
2847 .masks = {
2848 .vco_mask = BM(29, 28),
2849 .pre_div_mask = BIT(12),
2850 .post_div_mask = BM(9, 8),
2851 .mn_en_mask = BIT(24),
2852 .main_output_mask = BIT(0),
2853 },
2854 .base = &virt_bases[APCS_PLL_BASE],
2855 .c = {
Patrick Daly9bdc8a52013-03-21 19:12:40 -0700[diff] [blame]2856 .parent = &xo_a_clk.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2857 .dbg_name = "a7sspll",
2858 .ops = &clk_ops_sr2_pll,
2859 .vdd_class = &vdd_sr2_pll,
2860 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2861 [VDD_SR2_PLL_SVS] = 1000000000,
2862 [VDD_SR2_PLL_NOM] = 1900000000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2863 },
2864 .num_fmax = VDD_SR2_PLL_NUM,
2865 CLK_INIT(a7sspll.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2866 },
2867};
2868
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2869static struct clk_freq_tbl ftbl_kpss_ahb_clk[] = {
2870 F_GCC(19200000, xo_a_clk, 0, 0, 0),
2871 F_GCC(37500000, gpll0, 16, 0, 0),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2872 F_END
2873};
2874
2875static struct rcg_clk kpss_ahb_clk_src = {
2876 .cmd_rcgr_reg = KPSS_AHB_CMD_RCGR,
2877 .set_rate = set_rate_hid,
2878 .freq_tbl = ftbl_kpss_ahb_clk,
2879 .current_freq = &rcg_dummy_freq,
2880 .base = &virt_bases[GCC_BASE],
2881 .c = {
2882 .dbg_name = "kpss_ahb_clk_src",
2883 .ops = &clk_ops_rcg,
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2884 CLK_INIT(kpss_ahb_clk_src.c),
2885 },
2886};
2887
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2888static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2889static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2890static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2891static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2892static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2893static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2894
2895static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2896static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2897static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2898static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2899static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2900static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2901static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2902
2903static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2904
Patrick Daly4aef16c2013-04-17 15:44:12 -0700[diff] [blame]2905static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, 100000000);
2906static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, 100000000);
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]2907static DEFINE_CLK_VOTER(gud_ce1_clk_src, &ce1_clk_src.c, 100000000);
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]2908
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2909static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c);
2910static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c);
2911static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c);
2912static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c);
2913static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c);
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]2914static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, &xo.c);
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2915
2916
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2917#ifdef CONFIG_DEBUG_FS
2918static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2919{
2920 struct measure_clk *clk = to_measure_clk(c);
2921 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2922 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2923 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2924 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2925 measure_mux_GCC,
2926 measure_mux_MMSS,
2927 measure_mux_LPASS,
2928 measure_mux_APSS,
2929 NULL
2930 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2931 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2932
2933 if (!parent)
2934 return -EINVAL;
2935
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2936 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2937 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2938 if (mux->c == parent) {
2939 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2940 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2941 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2942 }
2943
2944 if (mux->c == &dummy_clk)
2945 return -EINVAL;
2946
2947 spin_lock_irqsave(&local_clock_reg_lock, flags);
2948 /*
2949 * Program the test vector, measurement period (sample_ticks)
2950 * and scaling multiplier.
2951 */
2952 clk->sample_ticks = 0x10000;
2953 clk->multiplier = 1;
2954
2955 switch (mux->base) {
2956
2957 case GCC_BASE:
2958 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2959 clk_sel = mux->debug_mux;
2960 break;
2961
2962 case MMSS_BASE:
2963 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2964 clk_sel = 0x02C;
2965 regval = BVAL(11, 0, mux->debug_mux);
2966 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2967
2968 /* Activate debug clock output */
2969 regval |= BIT(16);
2970 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2971 break;
2972
2973 case LPASS_BASE:
2974 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2975 clk_sel = 0x161;
2976 regval = BVAL(11, 0, mux->debug_mux);
2977 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2978
2979 /* Activate debug clock output */
2980 regval |= BIT(20);
2981 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2982 break;
2983
2984 case APCS_BASE:
2985 clk->multiplier = 4;
2986 clk_sel = 362;
2987 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2988 regval &= ~0xC0037335;
2989 /* configure a divider of 4 */
2990 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2991 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2992 break;
2993
2994 default:
2995 return -EINVAL;
2996 }
2997
2998 /* Set debug mux clock index */
2999 regval = BVAL(8, 0, clk_sel);
3000 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
3001
3002 /* Activate debug clock output */
3003 regval |= BIT(16);
3004 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
3005
3006 /* Make sure test vector is set before starting measurements. */
3007 mb();
3008 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3009
3010 return 0;
3011}
3012
3013/* Sample clock for 'ticks' reference clock ticks. */
3014static u32 run_measurement(unsigned ticks)
3015{
3016 /* Stop counters and set the XO4 counter start value. */
3017 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3018
3019 /* Wait for timer to become ready. */
3020 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3021 BIT(25)) != 0)
3022 cpu_relax();
3023
3024 /* Run measurement and wait for completion. */
3025 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3026 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3027 BIT(25)) == 0)
3028 cpu_relax();
3029
3030 /* Return measured ticks. */
3031 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3032 BM(24, 0);
3033}
3034
3035/*
3036 * Perform a hardware rate measurement for a given clock.
3037 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
3038 */
3039static unsigned long measure_clk_get_rate(struct clk *c)
3040{
3041 unsigned long flags;
3042 u32 gcc_xo4_reg_backup;
3043 u64 raw_count_short, raw_count_full;
3044 struct measure_clk *clk = to_measure_clk(c);
3045 unsigned ret;
3046
3047 ret = clk_prepare_enable(&xo.c);
3048 if (ret) {
3049 pr_warn("CXO clock failed to enable. Can't measure\n");
3050 return 0;
3051 }
3052
3053 spin_lock_irqsave(&local_clock_reg_lock, flags);
3054
3055 /* Enable CXO/4 and RINGOSC branch. */
3056 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3057 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3058
3059 /*
3060 * The ring oscillator counter will not reset if the measured clock
3061 * is not running. To detect this, run a short measurement before
3062 * the full measurement. If the raw results of the two are the same
3063 * then the clock must be off.
3064 */
3065
3066 /* Run a short measurement. (~1 ms) */
3067 raw_count_short = run_measurement(0x1000);
3068 /* Run a full measurement. (~14 ms) */
3069 raw_count_full = run_measurement(clk->sample_ticks);
3070
3071 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3072
3073 /* Return 0 if the clock is off. */
3074 if (raw_count_full == raw_count_short) {
3075 ret = 0;
3076 } else {
3077 /* Compute rate in Hz. */
3078 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
3079 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
3080 ret = (raw_count_full * clk->multiplier);
3081 }
3082
Patrick Dalye095edb2013-05-23 14:13:09 -0700[diff] [blame]3083 /* Set pin to gcc_debug_clock, enable output mode, disable input mode */
3084 writel_relaxed(0x51200, GCC_REG_BASE(PLLTEST_PAD_CFG));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3085 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3086
3087 clk_disable_unprepare(&xo.c);
3088
3089 return ret;
3090}
3091
3092#else /* !CONFIG_DEBUG_FS */
3093static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3094{
3095 return -EINVAL;
3096}
3097
3098static unsigned long measure_clk_get_rate(struct clk *clk)
3099{
3100 return 0;
3101}
3102#endif /* CONFIG_DEBUG_FS */
3103
3104static struct clk_ops clk_ops_measure = {
3105 .set_parent = measure_clk_set_parent,
3106 .get_rate = measure_clk_get_rate,
3107};
3108
3109static struct measure_clk measure_clk = {
3110 .c = {
3111 .dbg_name = "measure_clk",
3112 .ops = &clk_ops_measure,
3113 CLK_INIT(measure_clk.c),
3114 },
3115 .multiplier = 1,
3116};
3117
3118static struct clk_lookup msm_clocks_8226[] = {
3119 /* Debug Clocks */
3120 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3121 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3122 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3123 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3124 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3125 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3126
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]3127 /* LPM Resources */
3128 CLK_LOOKUP("xo", cxo_lpm_clk.c, "fc4281d0.qcom,mpm"),
3129
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3130 /* PIL-LPASS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3131 CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3132 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3133 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3134 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3135 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3136
3137 /* PIL-MODEM */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3138 CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3139 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3140 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3141 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3142 /* NFC */
3143 CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "2-000e"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3144 /* PIL-PRONTO */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3145 CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3146
3147 /* PIL-VENUS */
3148 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3149 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3150 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3151 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3152 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3153
3154 /* ACPUCLOCK */
3155 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3156 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3157 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3158 CLK_LOOKUP("kpss_ahb", kpss_ahb_clk_src.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3159
3160 /* WCNSS CLOCKS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3161 CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"),
Vikram Mulukutla7e5b3112013-04-15 16:32:40 -0700[diff] [blame]3162 CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3163
3164 /* BUS DRIVER */
3165 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3166 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3167 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3168 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3169 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3170 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3171 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3172 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3173 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3174 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3175 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3176 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3177 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3178
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3179 /* CoreSight clocks */
3180 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3181 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3182 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3183 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3184 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3185 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3186 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3187 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3188 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3189 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3190 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3191 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3192 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3193 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3194 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3195 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3196 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3197 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3198 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3199 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3200 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3201 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3202 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3203 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3204 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3205 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3206 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3207 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3208 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3209 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3210 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3211 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3212 CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3213
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3214 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3215 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3216 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3217 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3218 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3219 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3220 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3221 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3222 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3223 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3224 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3225 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3226 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3227 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Aparna Das664239c2013-05-03 20:13:50 -0700[diff] [blame]3228 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.jtagmm"),
3229 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.jtagmm"),
3230 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.jtagmm"),
3231 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3232 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3233 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3234 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3235 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3236 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3237 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3238 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3239 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3240 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3241 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3242 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3243 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3244 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3245 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3246 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"),
3247
3248 CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3249
3250 /* HSUSB-OTG Clocks */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3251 CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3252 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3253 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3254
3255 /* SPS CLOCKS */
3256 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3257 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3258 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3259 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3260
3261 /* I2C Clocks */
3262 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3263 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3264
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3265 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3266 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3267
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3268 /* I2C Clocks nfc */
3269 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"),
3270 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3271 /* lsuart-v14 Clocks */
3272 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3273 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3274
3275 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3276 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3277
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3278 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3279 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3280
3281 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3282 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3283 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3284 CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3285
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]3286 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "mcd"),
3287 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "mcd"),
3288 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "mcd"),
3289 CLK_LOOKUP("core_clk_src", gud_ce1_clk_src.c, "mcd"),
3290
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3291 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3292 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3293 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3294 CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"),
3295
3296 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""),
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3297
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3298 /* SDCC */
3299 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3300 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3301 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3302 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3303
3304 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3305 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3306 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3307 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3308
3309 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3310 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3311
3312 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3313 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3314
3315
3316 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3317 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3318 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3319 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3320 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3321 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3322 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3323 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3324 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3325 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3326 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3327
3328 CLK_LOOKUP("gpll0", gpll0.c, ""),
3329 CLK_LOOKUP("gpll1", gpll1.c, ""),
3330 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3331 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3332
3333 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3334 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3335 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3336 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3337 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3338 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3339 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3340 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3341 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3342 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3343 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3344 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3345 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3346 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3347 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3348 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3349 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3350 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3351 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3352 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3353
3354 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3355 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3356 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3357 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3358 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3359 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3360 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3361 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3362
3363 /* Multimedia clocks */
3364 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3365 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3366 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
Aravind Venkateswaran6b6d9c42013-05-06 16:10:03 -0700[diff] [blame]3367 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922800.qcom,mdss_dsi"),
3368 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd922800.qcom,mdss_dsi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3369
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3370 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3371 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3372 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3373 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3374 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3375 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3376
3377 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3378 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3379
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]3380 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fd8c1024.qcom,gdsc"),
3381 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd8c2304.qcom,gdsc"),
3382 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd8c2304.qcom,gdsc"),
3383 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fd8c35a4.qcom,gdsc"),
3384 CLK_LOOKUP("core_clk", camss_vfe_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3385 CLK_LOOKUP("csi_clk", camss_csi_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3386 CLK_LOOKUP("cpp_clk", camss_vfe_cpp_clk.c, "fd8c36a4.qcom,gdsc"),
3387 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fd8c4034.qcom,gdsc"),
3388
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3389 /* MM sensor clocks */
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3390 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3391 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3392 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3393 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3394 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3395 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3396 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3397 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3398
3399 /* CCI clocks */
3400 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3401 "fda0c000.qcom,cci"),
3402 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3403 "fda0c000.qcom,cci"),
3404 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3405 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3406
3407 /* CSIPHY clocks */
3408 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3409 "fda0ac00.qcom,csiphy"),
3410 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3411 "fda0ac00.qcom,csiphy"),
3412 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3413 "fda0ac00.qcom,csiphy"),
3414 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3415 "fda0ac00.qcom,csiphy"),
3416 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3417 "fda0b000.qcom,csiphy"),
3418 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3419 "fda0b000.qcom,csiphy"),
3420 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3421 "fda0b000.qcom,csiphy"),
3422 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3423 "fda0b000.qcom,csiphy"),
3424
3425 /* CSID clocks */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3426 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3427 "fda08000.qcom,csid"),
3428 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3429 "fda08000.qcom,csid"),
3430 CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c,
3431 "fda08000.qcom,csid"),
3432 CLK_LOOKUP("csi_src_clk", csi0_clk_src.c,
3433 "fda08000.qcom,csid"),
3434 CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c,
3435 "fda08000.qcom,csid"),
3436 CLK_LOOKUP("csi_clk", camss_csi0_clk.c,
3437 "fda08000.qcom,csid"),
3438 CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c,
3439 "fda08000.qcom,csid"),
3440 CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c,
3441 "fda08000.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3442
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3443
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3444 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3445 "fda08400.qcom,csid"),
3446 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3447 "fda08400.qcom,csid"),
3448 CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c,
3449 "fda08400.qcom,csid"),
3450 CLK_LOOKUP("csi_src_clk", csi1_clk_src.c,
3451 "fda08400.qcom,csid"),
3452 CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c,
3453 "fda08400.qcom,csid"),
3454 CLK_LOOKUP("csi_clk", camss_csi1_clk.c,
3455 "fda08400.qcom,csid"),
3456 CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c,
3457 "fda08400.qcom,csid"),
3458 CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c,
3459 "fda08400.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3460
3461 /* ISPIF clocks */
Sreesudhan Ramakrish Ramkumarecdcfce2013-04-17 12:58:26 -0700[diff] [blame]3462 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3463 "fda0a000.qcom,ispif"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3464 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3465 "fda0a000.qcom,ispif"),
3466 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3467 "fda0a000.qcom,ispif"),
3468
3469 /* VFE clocks */
3470 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3471 "fda10000.qcom,vfe"),
3472 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3473 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3474 "fda10000.qcom,vfe"),
3475 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3476 "fda10000.qcom,vfe"),
3477 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3478 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3479
3480 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3481 "fda44000.qcom,iommu"),
3482 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3483 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3484
3485 /* Jpeg Clocks */
3486 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3487 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3488 "fda1c000.qcom,jpeg"),
3489 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3490 "fda1c000.qcom,jpeg"),
3491 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3492 "fda1c000.qcom,jpeg"),
3493
3494 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3495 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3496 "fda64000.qcom,iommu"),
3497 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3498 "fda64000.qcom,iommu"),
3499
Su Liudb7b2062013-03-14 20:57:15 -0700[diff] [blame]3500 CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c,
3501 "fda04000.qcom,cpp"),
3502 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3503 "fda04000.qcom,cpp"),
3504 CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c,
3505 "fda04000.qcom,cpp"),
3506 CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"),
3507 CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"),
3508 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"),
3509 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3510 "fda04000.qcom,cpp"),
3511 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"),
3512
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3513 /* KGSL Clocks */
3514 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3515 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3516 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3517 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3518
3519 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3520 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3521 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3522
3523 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3524
3525 /* Venus Clocks */
3526 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3527 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3528 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3529
3530 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3531 "fdc84000.qcom,iommu"),
3532 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3533 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3534 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3535 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3536 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3537 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3538
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3539 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3540 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3541 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3542
3543 /* Audio clocks */
3544 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3545 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3546 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3547 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3548 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3549 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3550
Hariprasad Dhalinarasimha1fa54392013-03-21 15:57:51 -0700[diff] [blame]3551 /* Add QCEDEV clocks */
3552 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"),
3553 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"),
3554 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"),
3555 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"),
3556
3557 /* Add QCRYPTO clocks */
3558 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd404000.qcom,qcrypto"),
3559 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd404000.qcom,qcrypto"),
3560 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd404000.qcom,qcrypto"),
3561 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd404000.qcom,qcrypto"),
3562
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3563 /* DSI PLL clocks */
3564 CLK_LOOKUP("", dsi_vco_clk_8226.c, ""),
3565 CLK_LOOKUP("", analog_postdiv_clk_8226.c, ""),
3566 CLK_LOOKUP("", indirect_path_div2_clk_8226.c, ""),
3567 CLK_LOOKUP("", pixel_clk_src_8226.c, ""),
3568 CLK_LOOKUP("", byte_mux_8226.c, ""),
3569 CLK_LOOKUP("", byte_clk_src_8226.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3570};
3571
3572static struct clk_lookup msm_clocks_8226_rumi[] = {
3573 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3574 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3575 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3576 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3577 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3578 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3579 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3580 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3581 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3582 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3583};
3584
3585struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3586 .table = msm_clocks_8226_rumi,
3587 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3588};
3589
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3590static void __init reg_init(void)
3591{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3592 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3593
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3594 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3595 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3596 regval |= BIT(0);
3597 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3598
3599 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3600 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3601 */
3602 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3603}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3604
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3605static void __init msm8226_clock_post_init(void)
3606{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3607 /*
3608 * Hold an active set vote for CXO; this is because CXO is expected
3609 * to remain on whenever CPUs aren't power collapsed.
3610 */
3611 clk_prepare_enable(&xo_a_clk.c);
3612
Patrick Dalyfd3df102013-05-28 18:08:22 -0700[diff] [blame]3613 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3614 clk_set_rate(&axi_clk_src.c, 200000000);
3615
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3616 /* Set rates for single-rate clocks. */
3617 clk_set_rate(&usb_hs_system_clk_src.c,
3618 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3619 clk_set_rate(&usb_hsic_clk_src.c,
3620 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3621 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3622 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3623 clk_set_rate(&usb_hsic_system_clk_src.c,
3624 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3625 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3626 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3627 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3628 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3629 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3630 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3631
3632 clk_set_rate(&kpss_ahb_clk_src.c, 19200000);
3633 clk_prepare_enable(&kpss_ahb_clk_src.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3634}
3635
3636#define GCC_CC_PHYS 0xFC400000
3637#define GCC_CC_SIZE SZ_16K
3638
3639#define MMSS_CC_PHYS 0xFD8C0000
3640#define MMSS_CC_SIZE SZ_256K
3641
3642#define LPASS_CC_PHYS 0xFE000000
3643#define LPASS_CC_SIZE SZ_256K
3644
3645#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3646#define APCS_KPSS_SH_PLL_SIZE SZ_64
3647
3648#define APCS_KPSS_GLB_PHYS 0xF9011000
3649#define APCS_KPSS_GLB_SIZE SZ_4K
3650
3651
3652static void __init msm8226_clock_pre_init(void)
3653{
3654 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3655 if (!virt_bases[GCC_BASE])
3656 panic("clock-8226: Unable to ioremap GCC memory!");
3657
3658 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3659 if (!virt_bases[MMSS_BASE])
3660 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3661
3662 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3663 if (!virt_bases[LPASS_BASE])
3664 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3665
3666 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3667 APCS_KPSS_GLB_SIZE);
3668 if (!virt_bases[APCS_BASE])
3669 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3670
3671 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3672 APCS_KPSS_SH_PLL_SIZE);
3673 if (!virt_bases[APCS_PLL_BASE])
3674 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3675
3676 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3677
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3678 vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig");
3679 if (IS_ERR(vdd_dig.regulator[0]))
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3680 panic("clock-8226: Unable to get the vdd_dig regulator!");
3681
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3682 vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll");
3683 if (IS_ERR(vdd_sr2_pll.regulator[0]))
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3684 panic("clock-8226: Unable to get the sr2_pll regulator!");
3685
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]3686 vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig");
3687 if (IS_ERR(vdd_sr2_pll.regulator[1]))
3688 panic("clock-8226: Unable to get the vdd_sr2_dig regulator!");
3689
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3690 /*
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3691 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3692 * source. Sleep set vote is 0.
3693 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3694 * access mmss clock controller registers.
3695 */
3696 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3697
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3698 enable_rpm_scaling();
3699
3700 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3701
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]3702 /* v2 specific changes */
3703 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
3704 cpp_clk_src.c.fmax = camss_vfe_cpp_fmax_v2;
3705 vfe0_clk_src.c.fmax = camss_vfe_vfe0_fmax_v2;
3706 }
3707
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3708 clk_ops_pixel_clock = clk_ops_pixel;
3709 clk_ops_pixel_clock.set_rate = set_rate_pixel;
3710 clk_ops_pixel_clock.round_rate = round_rate_pixel;
3711
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3712 /*
3713 * MDSS needs the ahb clock and needs to init before we register the
3714 * lookup table.
3715 */
3716 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3717}
3718
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3719struct clock_init_data msm8226_clock_init_data __initdata = {
3720 .table = msm_clocks_8226,
3721 .size = ARRAY_SIZE(msm_clocks_8226),
3722 .pre_init = msm8226_clock_pre_init,
3723 .post_init = msm8226_clock_post_init,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3724};