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SAN People73a59c12006-01-09 17:05:41 +00001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * linux/arch/arm/mach-at91/gpio.c
SAN People73a59c12006-01-09 17:05:41 +00003 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
Andrew Victorf2173832006-09-27 13:23:00 +010012#include <linux/clk.h>
SAN People73a59c12006-01-09 17:05:41 +000013#include <linux/errno.h>
Thomas Gleixner07d265d2006-07-01 23:01:50 +010014#include <linux/interrupt.h>
15#include <linux/irq.h>
Andrew Victorb66545e2007-11-23 16:09:10 +010016#include <linux/debugfs.h>
17#include <linux/seq_file.h>
SAN People73a59c12006-01-09 17:05:41 +000018#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/module.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
SAN People73a59c12006-01-09 17:05:41 +000022
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/hardware.h>
24#include <mach/at91_pio.h>
25#include <mach/gpio.h>
SAN People73a59c12006-01-09 17:05:41 +000026
Andrew Victorf2173832006-09-27 13:23:00 +010027#include "generic.h"
28
29
30static struct at91_gpio_bank *gpio;
31static int gpio_banks;
32
SAN People73a59c12006-01-09 17:05:41 +000033
34static inline void __iomem *pin_to_controller(unsigned pin)
35{
SAN People73a59c12006-01-09 17:05:41 +000036 pin -= PIN_BASE;
37 pin /= 32;
Andrew Victorf2173832006-09-27 13:23:00 +010038 if (likely(pin < gpio_banks))
David Brownelle83aff52008-01-04 18:30:24 +010039 return gpio[pin].regbase;
SAN People73a59c12006-01-09 17:05:41 +000040
41 return NULL;
42}
43
44static inline unsigned pin_to_mask(unsigned pin)
45{
46 pin -= PIN_BASE;
47 return 1 << (pin % 32);
48}
49
50
51/*--------------------------------------------------------------------------*/
52
53/* Not all hardware capabilities are exposed through these calls; they
54 * only encapsulate the most common features and modes. (So if you
55 * want to change signals in groups, do it directly.)
56 *
57 * Bootloaders will usually handle some of the pin multiplexing setup.
58 * The intent is certainly that by the time Linux is fully booted, all
59 * pins should have been fully initialized. These setup calls should
60 * only be used by board setup routines, or possibly in driver probe().
61 *
62 * For bootloaders doing all that setup, these calls could be inlined
63 * as NOPs so Linux won't duplicate any setup code
64 */
65
66
67/*
David Brownella31c4ee2007-02-12 00:53:13 -080068 * mux the pin to the "GPIO" peripheral role.
69 */
70int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
71{
72 void __iomem *pio = pin_to_controller(pin);
73 unsigned mask = pin_to_mask(pin);
74
75 if (!pio)
76 return -EINVAL;
77 __raw_writel(mask, pio + PIO_IDR);
78 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
79 __raw_writel(mask, pio + PIO_PER);
80 return 0;
81}
82EXPORT_SYMBOL(at91_set_GPIO_periph);
83
84
85/*
SAN People73a59c12006-01-09 17:05:41 +000086 * mux the pin to the "A" internal peripheral role.
87 */
88int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
89{
90 void __iomem *pio = pin_to_controller(pin);
91 unsigned mask = pin_to_mask(pin);
92
93 if (!pio)
94 return -EINVAL;
95
96 __raw_writel(mask, pio + PIO_IDR);
97 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
98 __raw_writel(mask, pio + PIO_ASR);
99 __raw_writel(mask, pio + PIO_PDR);
100 return 0;
101}
102EXPORT_SYMBOL(at91_set_A_periph);
103
104
105/*
106 * mux the pin to the "B" internal peripheral role.
107 */
108int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
109{
110 void __iomem *pio = pin_to_controller(pin);
111 unsigned mask = pin_to_mask(pin);
112
113 if (!pio)
114 return -EINVAL;
115
116 __raw_writel(mask, pio + PIO_IDR);
117 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
118 __raw_writel(mask, pio + PIO_BSR);
119 __raw_writel(mask, pio + PIO_PDR);
120 return 0;
121}
122EXPORT_SYMBOL(at91_set_B_periph);
123
124
125/*
126 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
127 * configure it for an input.
128 */
129int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
130{
131 void __iomem *pio = pin_to_controller(pin);
132 unsigned mask = pin_to_mask(pin);
133
134 if (!pio)
135 return -EINVAL;
136
137 __raw_writel(mask, pio + PIO_IDR);
138 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
139 __raw_writel(mask, pio + PIO_ODR);
140 __raw_writel(mask, pio + PIO_PER);
141 return 0;
142}
143EXPORT_SYMBOL(at91_set_gpio_input);
144
145
146/*
147 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
148 * and configure it for an output.
149 */
150int __init_or_module at91_set_gpio_output(unsigned pin, int value)
151{
152 void __iomem *pio = pin_to_controller(pin);
153 unsigned mask = pin_to_mask(pin);
154
155 if (!pio)
156 return -EINVAL;
157
158 __raw_writel(mask, pio + PIO_IDR);
159 __raw_writel(mask, pio + PIO_PUDR);
160 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
161 __raw_writel(mask, pio + PIO_OER);
162 __raw_writel(mask, pio + PIO_PER);
163 return 0;
164}
165EXPORT_SYMBOL(at91_set_gpio_output);
166
167
168/*
169 * enable/disable the glitch filter; mostly used with IRQ handling.
170 */
171int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
172{
173 void __iomem *pio = pin_to_controller(pin);
174 unsigned mask = pin_to_mask(pin);
175
176 if (!pio)
177 return -EINVAL;
178 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
179 return 0;
180}
181EXPORT_SYMBOL(at91_set_deglitch);
182
Andrew Victordf666b92006-02-22 21:23:35 +0000183/*
184 * enable/disable the multi-driver; This is only valid for output and
185 * allows the output pin to run as an open collector output.
186 */
187int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
188{
189 void __iomem *pio = pin_to_controller(pin);
190 unsigned mask = pin_to_mask(pin);
191
192 if (!pio)
193 return -EINVAL;
194
195 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
196 return 0;
197}
198EXPORT_SYMBOL(at91_set_multi_drive);
199
SAN People73a59c12006-01-09 17:05:41 +0000200/*--------------------------------------------------------------------------*/
201
David Brownella31c4ee2007-02-12 00:53:13 -0800202/* new-style GPIO calls; these expect at91_set_GPIO_periph to have been
203 * called, and maybe at91_set_multi_drive() for putout pins.
204 */
205
206int gpio_direction_input(unsigned pin)
207{
208 void __iomem *pio = pin_to_controller(pin);
209 unsigned mask = pin_to_mask(pin);
210
211 if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
212 return -EINVAL;
Andrew Victor0ebffe32007-02-22 09:38:52 +0100213 __raw_writel(mask, pio + PIO_ODR);
David Brownella31c4ee2007-02-12 00:53:13 -0800214 return 0;
215}
216EXPORT_SYMBOL(gpio_direction_input);
217
David Brownell28735a72007-03-16 13:38:14 -0800218int gpio_direction_output(unsigned pin, int value)
David Brownella31c4ee2007-02-12 00:53:13 -0800219{
220 void __iomem *pio = pin_to_controller(pin);
221 unsigned mask = pin_to_mask(pin);
222
223 if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
224 return -EINVAL;
David Brownell28735a72007-03-16 13:38:14 -0800225 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
David Brownella31c4ee2007-02-12 00:53:13 -0800226 __raw_writel(mask, pio + PIO_OER);
227 return 0;
228}
229EXPORT_SYMBOL(gpio_direction_output);
230
231/*--------------------------------------------------------------------------*/
232
SAN People73a59c12006-01-09 17:05:41 +0000233/*
234 * assuming the pin is muxed as a gpio output, set its value.
235 */
236int at91_set_gpio_value(unsigned pin, int value)
237{
238 void __iomem *pio = pin_to_controller(pin);
239 unsigned mask = pin_to_mask(pin);
240
241 if (!pio)
242 return -EINVAL;
243 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
244 return 0;
245}
246EXPORT_SYMBOL(at91_set_gpio_value);
247
248
249/*
250 * read the pin's value (works even if it's not muxed as a gpio).
251 */
252int at91_get_gpio_value(unsigned pin)
253{
254 void __iomem *pio = pin_to_controller(pin);
255 unsigned mask = pin_to_mask(pin);
256 u32 pdsr;
257
258 if (!pio)
259 return -EINVAL;
260 pdsr = __raw_readl(pio + PIO_PDSR);
261 return (pdsr & mask) != 0;
262}
263EXPORT_SYMBOL(at91_get_gpio_value);
264
265/*--------------------------------------------------------------------------*/
266
Andrew Victor814138f2006-06-19 15:26:54 +0100267#ifdef CONFIG_PM
268
Andrew Victorf2173832006-09-27 13:23:00 +0100269static u32 wakeups[MAX_GPIO_BANKS];
270static u32 backups[MAX_GPIO_BANKS];
Andrew Victor814138f2006-06-19 15:26:54 +0100271
272static int gpio_irq_set_wake(unsigned pin, unsigned state)
273{
274 unsigned mask = pin_to_mask(pin);
Andrew Victor3ea163e2007-01-09 13:47:29 +0100275 unsigned bank = (pin - PIN_BASE) / 32;
Andrew Victor814138f2006-06-19 15:26:54 +0100276
Andrew Victor3ea163e2007-01-09 13:47:29 +0100277 if (unlikely(bank >= MAX_GPIO_BANKS))
Andrew Victor814138f2006-06-19 15:26:54 +0100278 return -EINVAL;
279
280 if (state)
Andrew Victor3ea163e2007-01-09 13:47:29 +0100281 wakeups[bank] |= mask;
Andrew Victor814138f2006-06-19 15:26:54 +0100282 else
Andrew Victor3ea163e2007-01-09 13:47:29 +0100283 wakeups[bank] &= ~mask;
284
285 set_irq_wake(gpio[bank].id, state);
Andrew Victor814138f2006-06-19 15:26:54 +0100286
287 return 0;
288}
289
290void at91_gpio_suspend(void)
291{
292 int i;
293
Andrew Victorf2173832006-09-27 13:23:00 +0100294 for (i = 0; i < gpio_banks; i++) {
David Brownelle83aff52008-01-04 18:30:24 +0100295 void __iomem *pio = gpio[i].regbase;
Andrew Victor814138f2006-06-19 15:26:54 +0100296
David Brownelle83aff52008-01-04 18:30:24 +0100297 backups[i] = __raw_readl(pio + PIO_IMR);
298 __raw_writel(backups[i], pio + PIO_IDR);
299 __raw_writel(wakeups[i], pio + PIO_IER);
Andrew Victor814138f2006-06-19 15:26:54 +0100300
Andrew Victor3ea163e2007-01-09 13:47:29 +0100301 if (!wakeups[i])
302 clk_disable(gpio[i].clock);
303 else {
Andrew Victor814138f2006-06-19 15:26:54 +0100304#ifdef CONFIG_PM_DEBUG
Andrew Victor3ea163e2007-01-09 13:47:29 +0100305 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
Andrew Victor814138f2006-06-19 15:26:54 +0100306#endif
307 }
308 }
309}
310
311void at91_gpio_resume(void)
312{
313 int i;
314
Andrew Victorf2173832006-09-27 13:23:00 +0100315 for (i = 0; i < gpio_banks; i++) {
David Brownelle83aff52008-01-04 18:30:24 +0100316 void __iomem *pio = gpio[i].regbase;
Andrew Victor814138f2006-06-19 15:26:54 +0100317
Andrew Victor3ea163e2007-01-09 13:47:29 +0100318 if (!wakeups[i])
319 clk_enable(gpio[i].clock);
320
David Brownelle83aff52008-01-04 18:30:24 +0100321 __raw_writel(wakeups[i], pio + PIO_IDR);
322 __raw_writel(backups[i], pio + PIO_IER);
Andrew Victorf2173832006-09-27 13:23:00 +0100323 }
Andrew Victor814138f2006-06-19 15:26:54 +0100324}
325
326#else
327#define gpio_irq_set_wake NULL
328#endif
329
SAN People73a59c12006-01-09 17:05:41 +0000330
331/* Several AIC controller irqs are dispatched through this GPIO handler.
332 * To use any AT91_PIN_* as an externally triggered IRQ, first call
333 * at91_set_gpio_input() then maybe enable its glitch filter.
334 * Then just request_irq() with the pin ID; it works like any ARM IRQ
335 * handler, though it always triggers on rising and falling edges.
336 *
337 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
338 * configuring them with at91_set_a_periph() or at91_set_b_periph().
339 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
340 */
341
342static void gpio_irq_mask(unsigned pin)
343{
344 void __iomem *pio = pin_to_controller(pin);
345 unsigned mask = pin_to_mask(pin);
346
347 if (pio)
348 __raw_writel(mask, pio + PIO_IDR);
349}
350
351static void gpio_irq_unmask(unsigned pin)
352{
353 void __iomem *pio = pin_to_controller(pin);
354 unsigned mask = pin_to_mask(pin);
355
356 if (pio)
357 __raw_writel(mask, pio + PIO_IER);
358}
359
360static int gpio_irq_type(unsigned pin, unsigned type)
361{
David Brownelle83aff52008-01-04 18:30:24 +0100362 switch (type) {
363 case IRQ_TYPE_NONE:
364 case IRQ_TYPE_EDGE_BOTH:
365 return 0;
366 default:
367 return -EINVAL;
368 }
SAN People73a59c12006-01-09 17:05:41 +0000369}
370
David Brownell38c677c2006-08-01 22:26:25 +0100371static struct irq_chip gpio_irqchip = {
372 .name = "GPIO",
SAN People73a59c12006-01-09 17:05:41 +0000373 .mask = gpio_irq_mask,
374 .unmask = gpio_irq_unmask,
375 .set_type = gpio_irq_type,
Andrew Victor814138f2006-06-19 15:26:54 +0100376 .set_wake = gpio_irq_set_wake,
SAN People73a59c12006-01-09 17:05:41 +0000377};
378
Russell King10dd5ce2006-11-23 11:41:32 +0000379static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
SAN People73a59c12006-01-09 17:05:41 +0000380{
381 unsigned pin;
Russell King10dd5ce2006-11-23 11:41:32 +0000382 struct irq_desc *gpio;
David Brownelle83aff52008-01-04 18:30:24 +0100383 struct at91_gpio_bank *bank;
SAN People73a59c12006-01-09 17:05:41 +0000384 void __iomem *pio;
385 u32 isr;
386
David Brownelle83aff52008-01-04 18:30:24 +0100387 bank = get_irq_chip_data(irq);
388 pio = bank->regbase;
SAN People73a59c12006-01-09 17:05:41 +0000389
390 /* temporarily mask (level sensitive) parent IRQ */
391 desc->chip->ack(irq);
392 for (;;) {
David Brownelle83aff52008-01-04 18:30:24 +0100393 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
394 * When there none are pending, we're finished unless we need
395 * to process multiple banks (like ID_PIOCDE on sam9263).
396 */
SAN People73a59c12006-01-09 17:05:41 +0000397 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
David Brownelle83aff52008-01-04 18:30:24 +0100398 if (!isr) {
399 if (!bank->next)
400 break;
401 bank = bank->next;
402 pio = bank->regbase;
403 continue;
404 }
SAN People73a59c12006-01-09 17:05:41 +0000405
David Brownelle83aff52008-01-04 18:30:24 +0100406 pin = bank->chipbase;
David Brownell085eefb2008-10-21 23:34:23 +0100407 gpio = &irq_desc[pin];
SAN People73a59c12006-01-09 17:05:41 +0000408
409 while (isr) {
Andrew Victorabbea712006-02-24 22:27:50 +0000410 if (isr & 1) {
Thomas Gleixner07d265d2006-07-01 23:01:50 +0100411 if (unlikely(gpio->depth)) {
Andrew Victorabbea712006-02-24 22:27:50 +0000412 /*
413 * The core ARM interrupt handler lazily disables IRQs so
414 * another IRQ must be generated before it actually gets
415 * here to be disabled on the GPIO controller.
416 */
417 gpio_irq_mask(pin);
418 }
419 else
Dmitry Baryshkovd8aa0252008-10-09 13:36:24 +0100420 generic_handle_irq(pin);
Andrew Victorabbea712006-02-24 22:27:50 +0000421 }
SAN People73a59c12006-01-09 17:05:41 +0000422 pin++;
423 gpio++;
424 isr >>= 1;
425 }
426 }
427 desc->chip->unmask(irq);
428 /* now it may re-trigger */
429}
430
Andrew Victorf2173832006-09-27 13:23:00 +0100431/*--------------------------------------------------------------------------*/
SAN People73a59c12006-01-09 17:05:41 +0000432
Andrew Victorb66545e2007-11-23 16:09:10 +0100433#ifdef CONFIG_DEBUG_FS
434
435static int at91_gpio_show(struct seq_file *s, void *unused)
436{
437 int bank, j;
438
439 /* print heading */
440 seq_printf(s, "Pin\t");
441 for (bank = 0; bank < gpio_banks; bank++) {
442 seq_printf(s, "PIO%c\t", 'A' + bank);
443 };
444 seq_printf(s, "\n\n");
445
446 /* print pin status */
447 for (j = 0; j < 32; j++) {
448 seq_printf(s, "%i:\t", j);
449
450 for (bank = 0; bank < gpio_banks; bank++) {
451 unsigned pin = PIN_BASE + (32 * bank) + j;
452 void __iomem *pio = pin_to_controller(pin);
453 unsigned mask = pin_to_mask(pin);
454
455 if (__raw_readl(pio + PIO_PSR) & mask)
456 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
457 else
458 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
459
460 seq_printf(s, "\t");
461 }
462
463 seq_printf(s, "\n");
464 }
465
466 return 0;
467}
468
469static int at91_gpio_open(struct inode *inode, struct file *file)
470{
471 return single_open(file, at91_gpio_show, NULL);
472}
473
474static const struct file_operations at91_gpio_operations = {
475 .open = at91_gpio_open,
476 .read = seq_read,
477 .llseek = seq_lseek,
478 .release = single_release,
479};
480
481static int __init at91_gpio_debugfs_init(void)
482{
483 /* /sys/kernel/debug/at91_gpio */
484 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
485 return 0;
486}
487postcore_initcall(at91_gpio_debugfs_init);
488
489#endif
490
491/*--------------------------------------------------------------------------*/
492
Andrew Victor2b768b62009-02-11 21:39:05 +0100493/*
494 * This lock class tells lockdep that GPIO irqs are in a different
David Brownell37aca702008-03-05 00:08:29 +0100495 * category than their parents, so it won't report false recursion.
496 */
497static struct lock_class_key gpio_lock_class;
498
Andrew Victorf2173832006-09-27 13:23:00 +0100499/*
500 * Called from the processor-specific init to enable GPIO interrupt support.
501 */
502void __init at91_gpio_irq_setup(void)
503{
David Brownelle83aff52008-01-04 18:30:24 +0100504 unsigned pioc, pin;
505 struct at91_gpio_bank *this, *prev;
Andrew Victorf2173832006-09-27 13:23:00 +0100506
David Brownelle83aff52008-01-04 18:30:24 +0100507 for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL;
508 pioc++ < gpio_banks;
509 prev = this, this++) {
510 unsigned id = this->id;
SAN People73a59c12006-01-09 17:05:41 +0000511 unsigned i;
512
David Brownelle83aff52008-01-04 18:30:24 +0100513 __raw_writel(~0, this->regbase + PIO_IDR);
SAN People73a59c12006-01-09 17:05:41 +0000514
David Brownelle83aff52008-01-04 18:30:24 +0100515 for (i = 0, pin = this->chipbase; i < 32; i++, pin++) {
David Brownell37aca702008-03-05 00:08:29 +0100516 lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
517
Andrew Victor814138f2006-06-19 15:26:54 +0100518 /*
519 * Can use the "simple" and not "edge" handler since it's
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +0200520 * shorter, and the AIC handles interrupts sanely.
Andrew Victor814138f2006-06-19 15:26:54 +0100521 */
SAN People73a59c12006-01-09 17:05:41 +0000522 set_irq_chip(pin, &gpio_irqchip);
Russell King10dd5ce2006-11-23 11:41:32 +0000523 set_irq_handler(pin, handle_simple_irq);
SAN People73a59c12006-01-09 17:05:41 +0000524 set_irq_flags(pin, IRQF_VALID);
525 }
526
David Brownelle83aff52008-01-04 18:30:24 +0100527 /* The toplevel handler handles one bank of GPIOs, except
528 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
529 * the list, so we only set up that handler.
530 */
531 if (prev && prev->next == this)
532 continue;
533
534 set_irq_chip_data(id, this);
SAN People73a59c12006-01-09 17:05:41 +0000535 set_irq_chained_handler(id, gpio_irq_handler);
SAN People73a59c12006-01-09 17:05:41 +0000536 }
Andrew Victorf2173832006-09-27 13:23:00 +0100537 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
538}
539
540/*
541 * Called from the processor-specific init to enable GPIO pin support.
542 */
543void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
544{
David Brownelle83aff52008-01-04 18:30:24 +0100545 unsigned i;
546 struct at91_gpio_bank *last;
547
Andrew Victorf2173832006-09-27 13:23:00 +0100548 BUG_ON(nr_banks > MAX_GPIO_BANKS);
549
550 gpio = data;
551 gpio_banks = nr_banks;
David Brownelle83aff52008-01-04 18:30:24 +0100552
553 for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
554 data->chipbase = PIN_BASE + i * 32;
555 data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
556
Andrew Victor2b768b62009-02-11 21:39:05 +0100557 /* enable PIO controller's clock */
558 clk_enable(data->clock);
559
560 /*
561 * Some processors share peripheral ID between multiple GPIO banks.
562 * SAM9263 (PIOC, PIOD, PIOE)
563 * CAP9 (PIOA, PIOB, PIOC, PIOD)
564 */
David Brownelle83aff52008-01-04 18:30:24 +0100565 if (last && last->id == data->id)
566 last->next = data;
567 }
SAN People73a59c12006-01-09 17:05:41 +0000568}