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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Robert Hancockfbbb2622006-10-27 19:08:41 -070032 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/pci.h>
42#include <linux/init.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050046#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <scsi/scsi_host.h>
Robert Hancockfbbb2622006-10-27 19:08:41 -070048#include <scsi/scsi_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <linux/libata.h>
50
51#define DRV_NAME "sata_nv"
Robert Hancockcdf56bc2007-01-03 18:13:57 -060052#define DRV_VERSION "3.3"
Robert Hancockfbbb2622006-10-27 19:08:41 -070053
54#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jeff Garzik10ad05d2006-03-22 23:50:50 -050056enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090057 NV_MMIO_BAR = 5,
58
Jeff Garzik10ad05d2006-03-22 23:50:50 -050059 NV_PORTS = 2,
60 NV_PIO_MASK = 0x1f,
61 NV_MWDMA_MASK = 0x07,
62 NV_UDMA_MASK = 0x7f,
63 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Tejun Heo27e4b272006-06-17 15:49:55 +090066 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050067 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050068 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090069 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050070 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heo27e4b272006-06-17 15:49:55 +090072 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
Tejun Heo39f87582006-06-17 15:49:56 +090080 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090081 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090083
Tejun Heo27e4b272006-06-17 15:49:55 +090084 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050085 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
Jeff Garzik10ad05d2006-03-22 23:50:50 -050088 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
Robert Hancockfbbb2622006-10-27 19:08:41 -070091 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
166 NV_ADMA_STAT_TIMEOUT,
167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
Robert Hancock2dec7552006-11-26 14:20:19 -0600170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700171
Jeff Garzik10ad05d2006-03-22 23:50:50 -0500172};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
Robert Hancockfbbb2622006-10-27 19:08:41 -0700174/* ADMA Physical Region Descriptor - one SG segment */
175struct nv_adma_prd {
176 __le64 addr;
177 __le32 len;
178 u8 flags;
179 u8 packet_len;
180 __le16 reserved;
181};
182
183enum nv_adma_regbits {
184 CMDEND = (1 << 15), /* end of command list */
185 WNB = (1 << 14), /* wait-not-BSY */
186 IGN = (1 << 13), /* ignore this entry */
187 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
188 DA2 = (1 << (2 + 8)),
189 DA1 = (1 << (1 + 8)),
190 DA0 = (1 << (0 + 8)),
191};
192
193/* ADMA Command Parameter Block
194 The first 5 SG segments are stored inside the Command Parameter Block itself.
195 If there are more than 5 segments the remainder are stored in a separate
196 memory area indicated by next_aprd. */
197struct nv_adma_cpb {
198 u8 resp_flags; /* 0 */
199 u8 reserved1; /* 1 */
200 u8 ctl_flags; /* 2 */
201 /* len is length of taskfile in 64 bit words */
202 u8 len; /* 3 */
203 u8 tag; /* 4 */
204 u8 next_cpb_idx; /* 5 */
205 __le16 reserved2; /* 6-7 */
206 __le16 tf[12]; /* 8-31 */
207 struct nv_adma_prd aprd[5]; /* 32-111 */
208 __le64 next_aprd; /* 112-119 */
209 __le64 reserved3; /* 120-127 */
210};
211
212
213struct nv_adma_port_priv {
214 struct nv_adma_cpb *cpb;
215 dma_addr_t cpb_dma;
216 struct nv_adma_prd *aprd;
217 dma_addr_t aprd_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600218 void __iomem * ctl_block;
219 void __iomem * gen_block;
220 void __iomem * notifier_clear_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700221 u8 flags;
222};
223
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600224struct nv_host_priv {
225 unsigned long type;
226};
227
Robert Hancockfbbb2622006-10-27 19:08:41 -0700228#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
229
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600231static void nv_remove_one (struct pci_dev *pdev);
232static int nv_pci_device_resume(struct pci_dev *pdev);
Jeff Garzikcca39742006-08-24 03:19:22 -0400233static void nv_ck804_host_stop(struct ata_host *host);
David Howells7d12e782006-10-05 14:55:46 +0100234static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
235static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
236static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
238static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
Tejun Heo39f87582006-06-17 15:49:56 +0900240static void nv_nf2_freeze(struct ata_port *ap);
241static void nv_nf2_thaw(struct ata_port *ap);
242static void nv_ck804_freeze(struct ata_port *ap);
243static void nv_ck804_thaw(struct ata_port *ap);
244static void nv_error_handler(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700245static int nv_adma_slave_config(struct scsi_device *sdev);
Robert Hancock2dec7552006-11-26 14:20:19 -0600246static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700247static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
248static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
249static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
250static void nv_adma_irq_clear(struct ata_port *ap);
251static int nv_adma_port_start(struct ata_port *ap);
252static void nv_adma_port_stop(struct ata_port *ap);
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600253static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
254static int nv_adma_port_resume(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700255static void nv_adma_error_handler(struct ata_port *ap);
256static void nv_adma_host_stop(struct ata_host *host);
257static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc);
258static void nv_adma_bmdma_start(struct ata_queued_cmd *qc);
259static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc);
260static u8 nv_adma_bmdma_status(struct ata_port *ap);
Tejun Heo39f87582006-06-17 15:49:56 +0900261
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262enum nv_host_type
263{
264 GENERIC,
265 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900266 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700267 CK804,
268 ADMA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269};
270
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500271static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400272 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
273 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
274 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
275 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
276 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
277 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
278 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
279 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
287 PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
Daniel Drake541134c2005-07-03 13:44:39 +0100289 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
290 PCI_ANY_ID, PCI_ANY_ID,
291 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400292
293 { } /* terminate list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294};
295
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296static struct pci_driver nv_pci_driver = {
297 .name = DRV_NAME,
298 .id_table = nv_pci_tbl,
299 .probe = nv_init_one,
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600300 .suspend = ata_pci_device_suspend,
301 .resume = nv_pci_device_resume,
302 .remove = nv_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303};
304
Jeff Garzik193515d2005-11-07 00:59:37 -0500305static struct scsi_host_template nv_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 .module = THIS_MODULE,
307 .name = DRV_NAME,
308 .ioctl = ata_scsi_ioctl,
309 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 .can_queue = ATA_DEF_QUEUE,
311 .this_id = ATA_SHT_THIS_ID,
312 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
314 .emulated = ATA_SHT_EMULATED,
315 .use_clustering = ATA_SHT_USE_CLUSTERING,
316 .proc_name = DRV_NAME,
317 .dma_boundary = ATA_DMA_BOUNDARY,
318 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900319 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 .bios_param = ata_std_bios_param,
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600321 .suspend = ata_scsi_device_suspend,
322 .resume = ata_scsi_device_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323};
324
Robert Hancockfbbb2622006-10-27 19:08:41 -0700325static struct scsi_host_template nv_adma_sht = {
326 .module = THIS_MODULE,
327 .name = DRV_NAME,
328 .ioctl = ata_scsi_ioctl,
329 .queuecommand = ata_scsi_queuecmd,
330 .can_queue = NV_ADMA_MAX_CPBS,
331 .this_id = ATA_SHT_THIS_ID,
332 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700333 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
334 .emulated = ATA_SHT_EMULATED,
335 .use_clustering = ATA_SHT_USE_CLUSTERING,
336 .proc_name = DRV_NAME,
337 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
338 .slave_configure = nv_adma_slave_config,
339 .slave_destroy = ata_scsi_slave_destroy,
340 .bios_param = ata_std_bios_param,
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600341 .suspend = ata_scsi_device_suspend,
342 .resume = ata_scsi_device_resume,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700343};
344
Tejun Heoada364e2006-06-17 15:49:56 +0900345static const struct ata_port_operations nv_generic_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 .port_disable = ata_port_disable,
347 .tf_load = ata_tf_load,
348 .tf_read = ata_tf_read,
349 .exec_command = ata_exec_command,
350 .check_status = ata_check_status,
351 .dev_select = ata_std_dev_select,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 .bmdma_setup = ata_bmdma_setup,
353 .bmdma_start = ata_bmdma_start,
354 .bmdma_stop = ata_bmdma_stop,
355 .bmdma_status = ata_bmdma_status,
356 .qc_prep = ata_qc_prep,
357 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900358 .freeze = ata_bmdma_freeze,
359 .thaw = ata_bmdma_thaw,
360 .error_handler = nv_error_handler,
361 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900362 .data_xfer = ata_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900363 .irq_handler = nv_generic_interrupt,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900365 .irq_on = ata_irq_on,
366 .irq_ack = ata_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 .scr_read = nv_scr_read,
368 .scr_write = nv_scr_write,
369 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370};
371
Tejun Heoada364e2006-06-17 15:49:56 +0900372static const struct ata_port_operations nv_nf2_ops = {
373 .port_disable = ata_port_disable,
374 .tf_load = ata_tf_load,
375 .tf_read = ata_tf_read,
376 .exec_command = ata_exec_command,
377 .check_status = ata_check_status,
378 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900379 .bmdma_setup = ata_bmdma_setup,
380 .bmdma_start = ata_bmdma_start,
381 .bmdma_stop = ata_bmdma_stop,
382 .bmdma_status = ata_bmdma_status,
383 .qc_prep = ata_qc_prep,
384 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900385 .freeze = nv_nf2_freeze,
386 .thaw = nv_nf2_thaw,
387 .error_handler = nv_error_handler,
388 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900389 .data_xfer = ata_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900390 .irq_handler = nv_nf2_interrupt,
391 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900392 .irq_on = ata_irq_on,
393 .irq_ack = ata_irq_ack,
Tejun Heoada364e2006-06-17 15:49:56 +0900394 .scr_read = nv_scr_read,
395 .scr_write = nv_scr_write,
396 .port_start = ata_port_start,
Tejun Heoada364e2006-06-17 15:49:56 +0900397};
398
399static const struct ata_port_operations nv_ck804_ops = {
400 .port_disable = ata_port_disable,
401 .tf_load = ata_tf_load,
402 .tf_read = ata_tf_read,
403 .exec_command = ata_exec_command,
404 .check_status = ata_check_status,
405 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900406 .bmdma_setup = ata_bmdma_setup,
407 .bmdma_start = ata_bmdma_start,
408 .bmdma_stop = ata_bmdma_stop,
409 .bmdma_status = ata_bmdma_status,
410 .qc_prep = ata_qc_prep,
411 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900412 .freeze = nv_ck804_freeze,
413 .thaw = nv_ck804_thaw,
414 .error_handler = nv_error_handler,
415 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900416 .data_xfer = ata_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900417 .irq_handler = nv_ck804_interrupt,
418 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900419 .irq_on = ata_irq_on,
420 .irq_ack = ata_irq_ack,
Tejun Heoada364e2006-06-17 15:49:56 +0900421 .scr_read = nv_scr_read,
422 .scr_write = nv_scr_write,
423 .port_start = ata_port_start,
Tejun Heoada364e2006-06-17 15:49:56 +0900424 .host_stop = nv_ck804_host_stop,
425};
426
Robert Hancockfbbb2622006-10-27 19:08:41 -0700427static const struct ata_port_operations nv_adma_ops = {
428 .port_disable = ata_port_disable,
429 .tf_load = ata_tf_load,
430 .tf_read = ata_tf_read,
Robert Hancock2dec7552006-11-26 14:20:19 -0600431 .check_atapi_dma = nv_adma_check_atapi_dma,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700432 .exec_command = ata_exec_command,
433 .check_status = ata_check_status,
434 .dev_select = ata_std_dev_select,
435 .bmdma_setup = nv_adma_bmdma_setup,
436 .bmdma_start = nv_adma_bmdma_start,
437 .bmdma_stop = nv_adma_bmdma_stop,
438 .bmdma_status = nv_adma_bmdma_status,
439 .qc_prep = nv_adma_qc_prep,
440 .qc_issue = nv_adma_qc_issue,
441 .freeze = nv_ck804_freeze,
442 .thaw = nv_ck804_thaw,
443 .error_handler = nv_adma_error_handler,
444 .post_internal_cmd = nv_adma_bmdma_stop,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900445 .data_xfer = ata_data_xfer,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700446 .irq_handler = nv_adma_interrupt,
447 .irq_clear = nv_adma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900448 .irq_on = ata_irq_on,
449 .irq_ack = ata_irq_ack,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700450 .scr_read = nv_scr_read,
451 .scr_write = nv_scr_write,
452 .port_start = nv_adma_port_start,
453 .port_stop = nv_adma_port_stop,
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600454 .port_suspend = nv_adma_port_suspend,
455 .port_resume = nv_adma_port_resume,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700456 .host_stop = nv_adma_host_stop,
457};
458
Tejun Heoada364e2006-06-17 15:49:56 +0900459static struct ata_port_info nv_port_info[] = {
460 /* generic */
461 {
462 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900463 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
464 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900465 .pio_mask = NV_PIO_MASK,
466 .mwdma_mask = NV_MWDMA_MASK,
467 .udma_mask = NV_UDMA_MASK,
468 .port_ops = &nv_generic_ops,
469 },
470 /* nforce2/3 */
471 {
472 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900473 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
474 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900475 .pio_mask = NV_PIO_MASK,
476 .mwdma_mask = NV_MWDMA_MASK,
477 .udma_mask = NV_UDMA_MASK,
478 .port_ops = &nv_nf2_ops,
479 },
480 /* ck804 */
481 {
482 .sht = &nv_sht,
Tejun Heo722420f2006-09-28 17:49:22 +0900483 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
484 ATA_FLAG_HRST_TO_RESUME,
Tejun Heoada364e2006-06-17 15:49:56 +0900485 .pio_mask = NV_PIO_MASK,
486 .mwdma_mask = NV_MWDMA_MASK,
487 .udma_mask = NV_UDMA_MASK,
488 .port_ops = &nv_ck804_ops,
489 },
Robert Hancockfbbb2622006-10-27 19:08:41 -0700490 /* ADMA */
491 {
492 .sht = &nv_adma_sht,
493 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600494 ATA_FLAG_HRST_TO_RESUME |
Robert Hancockfbbb2622006-10-27 19:08:41 -0700495 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
496 .pio_mask = NV_PIO_MASK,
497 .mwdma_mask = NV_MWDMA_MASK,
498 .udma_mask = NV_UDMA_MASK,
499 .port_ops = &nv_adma_ops,
500 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501};
502
503MODULE_AUTHOR("NVIDIA");
504MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
505MODULE_LICENSE("GPL");
506MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
507MODULE_VERSION(DRV_VERSION);
508
Robert Hancockfbbb2622006-10-27 19:08:41 -0700509static int adma_enabled = 1;
510
Robert Hancock2dec7552006-11-26 14:20:19 -0600511static void nv_adma_register_mode(struct ata_port *ap)
512{
Robert Hancock2dec7552006-11-26 14:20:19 -0600513 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600514 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800515 u16 tmp, status;
516 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600517
518 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
519 return;
520
Robert Hancocka2cfe812007-02-05 16:26:03 -0800521 status = readw(mmio + NV_ADMA_STAT);
522 while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
523 ndelay(50);
524 status = readw(mmio + NV_ADMA_STAT);
525 count++;
526 }
527 if(count == 20)
528 ata_port_printk(ap, KERN_WARNING,
529 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
530 status);
531
Robert Hancock2dec7552006-11-26 14:20:19 -0600532 tmp = readw(mmio + NV_ADMA_CTL);
533 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
534
Robert Hancocka2cfe812007-02-05 16:26:03 -0800535 count = 0;
536 status = readw(mmio + NV_ADMA_STAT);
537 while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
538 ndelay(50);
539 status = readw(mmio + NV_ADMA_STAT);
540 count++;
541 }
542 if(count == 20)
543 ata_port_printk(ap, KERN_WARNING,
544 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
545 status);
546
Robert Hancock2dec7552006-11-26 14:20:19 -0600547 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
548}
549
550static void nv_adma_mode(struct ata_port *ap)
551{
Robert Hancock2dec7552006-11-26 14:20:19 -0600552 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600553 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800554 u16 tmp, status;
555 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600556
557 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
558 return;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500559
Robert Hancock2dec7552006-11-26 14:20:19 -0600560 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
561
562 tmp = readw(mmio + NV_ADMA_CTL);
563 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
564
Robert Hancocka2cfe812007-02-05 16:26:03 -0800565 status = readw(mmio + NV_ADMA_STAT);
566 while(((status & NV_ADMA_STAT_LEGACY) ||
567 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
568 ndelay(50);
569 status = readw(mmio + NV_ADMA_STAT);
570 count++;
571 }
572 if(count == 20)
573 ata_port_printk(ap, KERN_WARNING,
574 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
575 status);
576
Robert Hancock2dec7552006-11-26 14:20:19 -0600577 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
578}
579
Robert Hancockfbbb2622006-10-27 19:08:41 -0700580static int nv_adma_slave_config(struct scsi_device *sdev)
581{
582 struct ata_port *ap = ata_shost_to_port(sdev->host);
Robert Hancock2dec7552006-11-26 14:20:19 -0600583 struct nv_adma_port_priv *pp = ap->private_data;
584 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700585 u64 bounce_limit;
586 unsigned long segment_boundary;
587 unsigned short sg_tablesize;
588 int rc;
Robert Hancock2dec7552006-11-26 14:20:19 -0600589 int adma_enable;
590 u32 current_reg, new_reg, config_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700591
592 rc = ata_scsi_slave_config(sdev);
593
594 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
595 /* Not a proper libata device, ignore */
596 return rc;
597
598 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
599 /*
600 * NVIDIA reports that ADMA mode does not support ATAPI commands.
601 * Therefore ATAPI commands are sent through the legacy interface.
602 * However, the legacy interface only supports 32-bit DMA.
603 * Restrict DMA parameters as required by the legacy interface
604 * when an ATAPI device is connected.
605 */
606 bounce_limit = ATA_DMA_MASK;
607 segment_boundary = ATA_DMA_BOUNDARY;
608 /* Subtract 1 since an extra entry may be needed for padding, see
609 libata-scsi.c */
610 sg_tablesize = LIBATA_MAX_PRD - 1;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500611
Robert Hancock2dec7552006-11-26 14:20:19 -0600612 /* Since the legacy DMA engine is in use, we need to disable ADMA
613 on the port. */
614 adma_enable = 0;
615 nv_adma_register_mode(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700616 }
617 else {
618 bounce_limit = *ap->dev->dma_mask;
619 segment_boundary = NV_ADMA_DMA_BOUNDARY;
620 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
Robert Hancock2dec7552006-11-26 14:20:19 -0600621 adma_enable = 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700622 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500623
Robert Hancock2dec7552006-11-26 14:20:19 -0600624 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700625
Robert Hancock2dec7552006-11-26 14:20:19 -0600626 if(ap->port_no == 1)
627 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
628 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
629 else
630 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
631 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500632
Robert Hancock2dec7552006-11-26 14:20:19 -0600633 if(adma_enable) {
634 new_reg = current_reg | config_mask;
635 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
636 }
637 else {
638 new_reg = current_reg & ~config_mask;
639 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
640 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500641
Robert Hancock2dec7552006-11-26 14:20:19 -0600642 if(current_reg != new_reg)
643 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500644
Robert Hancockfbbb2622006-10-27 19:08:41 -0700645 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
646 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
647 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
648 ata_port_printk(ap, KERN_INFO,
649 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
650 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
651 return rc;
652}
653
Robert Hancock2dec7552006-11-26 14:20:19 -0600654static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
655{
656 struct nv_adma_port_priv *pp = qc->ap->private_data;
657 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
658}
659
660static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700661{
662 unsigned int idx = 0;
663
664 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device | WNB);
665
666 if ((tf->flags & ATA_TFLAG_LBA48) == 0) {
667 cpb[idx++] = cpu_to_le16(IGN);
668 cpb[idx++] = cpu_to_le16(IGN);
669 cpb[idx++] = cpu_to_le16(IGN);
670 cpb[idx++] = cpu_to_le16(IGN);
671 cpb[idx++] = cpu_to_le16(IGN);
672 }
673 else {
674 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature);
675 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
676 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
677 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
678 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
679 }
680 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
681 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
682 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
683 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
684 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
685
686 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
687
688 return idx;
689}
690
Robert Hancock5bd28a42007-02-05 16:26:01 -0800691static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700692{
693 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock2dec7552006-11-26 14:20:19 -0600694 u8 flags = pp->cpb[cpb_num].resp_flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700695
696 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
697
Robert Hancock5bd28a42007-02-05 16:26:01 -0800698 if (unlikely((force_err ||
699 flags & (NV_CPB_RESP_ATA_ERR |
700 NV_CPB_RESP_CMD_ERR |
701 NV_CPB_RESP_CPB_ERR)))) {
702 struct ata_eh_info *ehi = &ap->eh_info;
703 int freeze = 0;
704
705 ata_ehi_clear_desc(ehi);
706 ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x", flags );
707 if (flags & NV_CPB_RESP_ATA_ERR) {
708 ata_ehi_push_desc(ehi, ": ATA error");
709 ehi->err_mask |= AC_ERR_DEV;
710 } else if (flags & NV_CPB_RESP_CMD_ERR) {
711 ata_ehi_push_desc(ehi, ": CMD error");
712 ehi->err_mask |= AC_ERR_DEV;
713 } else if (flags & NV_CPB_RESP_CPB_ERR) {
714 ata_ehi_push_desc(ehi, ": CPB error");
715 ehi->err_mask |= AC_ERR_SYSTEM;
716 freeze = 1;
717 } else {
718 /* notifier error, but no error in CPB flags? */
719 ehi->err_mask |= AC_ERR_OTHER;
720 freeze = 1;
721 }
722 /* Kill all commands. EH will determine what actually failed. */
723 if (freeze)
724 ata_port_freeze(ap);
725 else
726 ata_port_abort(ap);
727 return 1;
728 }
729
Robert Hancockfbbb2622006-10-27 19:08:41 -0700730 if (flags & NV_CPB_RESP_DONE) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700731 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800732 VPRINTK("CPB flags done, flags=0x%x\n", flags);
733 if (likely(qc)) {
734 /* Grab the ATA port status for non-NCQ commands.
Robert Hancockfbbb2622006-10-27 19:08:41 -0700735 For NCQ commands the current status may have nothing to do with
736 the command just completed. */
Robert Hancock5bd28a42007-02-05 16:26:01 -0800737 if (qc->tf.protocol != ATA_PROT_NCQ) {
738 u8 ata_status = readb(pp->ctl_block + (ATA_REG_STATUS * 4));
739 qc->err_mask |= ac_err_mask(ata_status);
740 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700741 DPRINTK("Completing qc from tag %d with err_mask %u\n",cpb_num,
742 qc->err_mask);
743 ata_qc_complete(qc);
744 }
745 }
Robert Hancock5bd28a42007-02-05 16:26:01 -0800746 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700747}
748
Robert Hancock2dec7552006-11-26 14:20:19 -0600749static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
750{
751 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
Robert Hancock2dec7552006-11-26 14:20:19 -0600752
753 /* freeze if hotplugged */
754 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
755 ata_port_freeze(ap);
756 return 1;
757 }
758
759 /* bail out if not our interrupt */
760 if (!(irq_stat & NV_INT_DEV))
761 return 0;
762
763 /* DEV interrupt w/ no active qc? */
764 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
765 ata_check_status(ap);
766 return 1;
767 }
768
769 /* handle interrupt */
Robert Hancockf740d162007-01-23 20:09:02 -0600770 return ata_host_intr(ap, qc);
Robert Hancock2dec7552006-11-26 14:20:19 -0600771}
772
Robert Hancockfbbb2622006-10-27 19:08:41 -0700773static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
774{
775 struct ata_host *host = dev_instance;
776 int i, handled = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600777 u32 notifier_clears[2];
Robert Hancockfbbb2622006-10-27 19:08:41 -0700778
779 spin_lock(&host->lock);
780
781 for (i = 0; i < host->n_ports; i++) {
782 struct ata_port *ap = host->ports[i];
Robert Hancock2dec7552006-11-26 14:20:19 -0600783 notifier_clears[i] = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700784
785 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
786 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600787 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700788 u16 status;
789 u32 gen_ctl;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700790 u32 notifier, notifier_error;
791
792 /* if in ATA register mode, use standard ata interrupt handler */
793 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900794 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
Robert Hancock2dec7552006-11-26 14:20:19 -0600795 >> (NV_INT_PORT_SHIFT * i);
Robert Hancockf740d162007-01-23 20:09:02 -0600796 if(ata_tag_valid(ap->active_tag))
797 /** NV_INT_DEV indication seems unreliable at times
798 at least in ADMA mode. Force it on always when a
799 command is active, to prevent losing interrupts. */
800 irq_stat |= NV_INT_DEV;
Robert Hancock2dec7552006-11-26 14:20:19 -0600801 handled += nv_host_intr(ap, irq_stat);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700802 continue;
803 }
804
805 notifier = readl(mmio + NV_ADMA_NOTIFIER);
806 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
Robert Hancock2dec7552006-11-26 14:20:19 -0600807 notifier_clears[i] = notifier | notifier_error;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700808
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600809 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700810
Robert Hancockfbbb2622006-10-27 19:08:41 -0700811 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
812 !notifier_error)
813 /* Nothing to do */
814 continue;
815
816 status = readw(mmio + NV_ADMA_STAT);
817
818 /* Clear status. Ensure the controller sees the clearing before we start
819 looking at any of the CPB statuses, so that any CPB completions after
820 this point in the handler will raise another interrupt. */
821 writew(status, mmio + NV_ADMA_STAT);
822 readw(mmio + NV_ADMA_STAT); /* flush posted write */
823 rmb();
824
Robert Hancock5bd28a42007-02-05 16:26:01 -0800825 handled++; /* irq handled if we got here */
826
827 /* freeze if hotplugged or controller error */
828 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
829 NV_ADMA_STAT_HOTUNPLUG |
Robert Hancock5278b502007-02-11 18:36:56 -0600830 NV_ADMA_STAT_TIMEOUT |
831 NV_ADMA_STAT_SERROR))) {
Robert Hancock5bd28a42007-02-05 16:26:01 -0800832 struct ata_eh_info *ehi = &ap->eh_info;
833
834 ata_ehi_clear_desc(ehi);
835 ata_ehi_push_desc(ehi, "ADMA status 0x%08x", status );
836 if (status & NV_ADMA_STAT_TIMEOUT) {
837 ehi->err_mask |= AC_ERR_SYSTEM;
838 ata_ehi_push_desc(ehi, ": timeout");
839 } else if (status & NV_ADMA_STAT_HOTPLUG) {
840 ata_ehi_hotplugged(ehi);
841 ata_ehi_push_desc(ehi, ": hotplug");
842 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
843 ata_ehi_hotplugged(ehi);
844 ata_ehi_push_desc(ehi, ": hot unplug");
Robert Hancock5278b502007-02-11 18:36:56 -0600845 } else if (status & NV_ADMA_STAT_SERROR) {
846 /* let libata analyze SError and figure out the cause */
847 ata_ehi_push_desc(ehi, ": SError");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800848 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700849 ata_port_freeze(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700850 continue;
851 }
852
Robert Hancock5bd28a42007-02-05 16:26:01 -0800853 if (status & (NV_ADMA_STAT_DONE |
854 NV_ADMA_STAT_CPBERR)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700855 /** Check CPBs for completed commands */
856
Robert Hancock5bd28a42007-02-05 16:26:01 -0800857 if (ata_tag_valid(ap->active_tag)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700858 /* Non-NCQ command */
Robert Hancock5bd28a42007-02-05 16:26:01 -0800859 nv_adma_check_cpb(ap, ap->active_tag,
860 notifier_error & (1 << ap->active_tag));
861 } else {
862 int pos, error = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700863 u32 active = ap->sactive;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800864
865 while ((pos = ffs(active)) && !error) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700866 pos--;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800867 error = nv_adma_check_cpb(ap, pos,
868 notifier_error & (1 << pos) );
Robert Hancockfbbb2622006-10-27 19:08:41 -0700869 active &= ~(1 << pos );
870 }
871 }
872 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700873 }
874 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500875
Robert Hancock2dec7552006-11-26 14:20:19 -0600876 if(notifier_clears[0] || notifier_clears[1]) {
877 /* Note: Both notifier clear registers must be written
878 if either is set, even if one is zero, according to NVIDIA. */
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600879 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
880 writel(notifier_clears[0], pp->notifier_clear_block);
881 pp = host->ports[1]->private_data;
882 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancock2dec7552006-11-26 14:20:19 -0600883 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700884
885 spin_unlock(&host->lock);
886
887 return IRQ_RETVAL(handled);
888}
889
890static void nv_adma_irq_clear(struct ata_port *ap)
891{
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600892 struct nv_adma_port_priv *pp = ap->private_data;
893 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700894 u16 status = readw(mmio + NV_ADMA_STAT);
895 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
896 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900897 void __iomem *dma_stat_addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700898
899 /* clear ADMA status */
900 writew(status, mmio + NV_ADMA_STAT);
901 writel(notifier | notifier_error,
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600902 pp->notifier_clear_block);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700903
904 /** clear legacy status */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900905 iowrite8(ioread8(dma_stat_addr), dma_stat_addr);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700906}
907
908static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc)
909{
Robert Hancock2dec7552006-11-26 14:20:19 -0600910 struct ata_port *ap = qc->ap;
911 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
912 struct nv_adma_port_priv *pp = ap->private_data;
913 u8 dmactl;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700914
Robert Hancock2dec7552006-11-26 14:20:19 -0600915 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700916 WARN_ON(1);
917 return;
918 }
919
Robert Hancock2dec7552006-11-26 14:20:19 -0600920 /* load PRD table addr. */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900921 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
Robert Hancock2dec7552006-11-26 14:20:19 -0600922
923 /* specify data direction, triple-check start bit is clear */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900924 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Robert Hancock2dec7552006-11-26 14:20:19 -0600925 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
926 if (!rw)
927 dmactl |= ATA_DMA_WR;
928
Tejun Heo0d5ff562007-02-01 15:06:36 +0900929 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Robert Hancock2dec7552006-11-26 14:20:19 -0600930
931 /* issue r/w command */
932 ata_exec_command(ap, &qc->tf);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700933}
934
935static void nv_adma_bmdma_start(struct ata_queued_cmd *qc)
936{
Robert Hancock2dec7552006-11-26 14:20:19 -0600937 struct ata_port *ap = qc->ap;
938 struct nv_adma_port_priv *pp = ap->private_data;
939 u8 dmactl;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700940
Robert Hancock2dec7552006-11-26 14:20:19 -0600941 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700942 WARN_ON(1);
943 return;
944 }
945
Robert Hancock2dec7552006-11-26 14:20:19 -0600946 /* start host DMA transaction */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900947 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
948 iowrite8(dmactl | ATA_DMA_START,
949 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700950}
951
952static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc)
953{
Robert Hancock2dec7552006-11-26 14:20:19 -0600954 struct ata_port *ap = qc->ap;
955 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700956
Robert Hancock2dec7552006-11-26 14:20:19 -0600957 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
Robert Hancockfbbb2622006-10-27 19:08:41 -0700958 return;
959
Robert Hancock2dec7552006-11-26 14:20:19 -0600960 /* clear start/stop bit */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900961 iowrite8(ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
962 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Robert Hancock2dec7552006-11-26 14:20:19 -0600963
964 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
965 ata_altstatus(ap); /* dummy read */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700966}
967
968static u8 nv_adma_bmdma_status(struct ata_port *ap)
969{
Robert Hancockfbbb2622006-10-27 19:08:41 -0700970 struct nv_adma_port_priv *pp = ap->private_data;
971
Robert Hancock2dec7552006-11-26 14:20:19 -0600972 WARN_ON(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE));
Robert Hancockfbbb2622006-10-27 19:08:41 -0700973
Tejun Heo0d5ff562007-02-01 15:06:36 +0900974 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700975}
976
977static int nv_adma_port_start(struct ata_port *ap)
978{
979 struct device *dev = ap->host->dev;
980 struct nv_adma_port_priv *pp;
981 int rc;
982 void *mem;
983 dma_addr_t mem_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600984 void __iomem *mmio;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700985 u16 tmp;
986
987 VPRINTK("ENTER\n");
988
989 rc = ata_port_start(ap);
990 if (rc)
991 return rc;
992
Tejun Heo24dc5f32007-01-20 16:00:28 +0900993 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
994 if (!pp)
995 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700996
Tejun Heo0d5ff562007-02-01 15:06:36 +0900997 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600998 ap->port_no * NV_ADMA_PORT_SIZE;
999 pp->ctl_block = mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001000 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001001 pp->notifier_clear_block = pp->gen_block +
1002 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1003
Tejun Heo24dc5f32007-01-20 16:00:28 +09001004 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1005 &mem_dma, GFP_KERNEL);
1006 if (!mem)
1007 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001008 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1009
1010 /*
1011 * First item in chunk of DMA memory:
1012 * 128-byte command parameter block (CPB)
1013 * one for each command tag
1014 */
1015 pp->cpb = mem;
1016 pp->cpb_dma = mem_dma;
1017
1018 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1019 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1020
1021 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1022 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1023
1024 /*
1025 * Second item: block of ADMA_SGTBL_LEN s/g entries
1026 */
1027 pp->aprd = mem;
1028 pp->aprd_dma = mem_dma;
1029
1030 ap->private_data = pp;
1031
1032 /* clear any outstanding interrupt conditions */
1033 writew(0xffff, mmio + NV_ADMA_STAT);
1034
1035 /* initialize port variables */
1036 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1037
1038 /* clear CPB fetch count */
1039 writew(0, mmio + NV_ADMA_CPB_COUNT);
1040
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001041 /* clear GO for register mode, enable interrupt */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001042 tmp = readw(mmio + NV_ADMA_CTL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001043 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001044
1045 tmp = readw(mmio + NV_ADMA_CTL);
1046 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1047 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1048 udelay(1);
1049 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1050 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1051
1052 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001053}
1054
1055static void nv_adma_port_stop(struct ata_port *ap)
1056{
Robert Hancockfbbb2622006-10-27 19:08:41 -07001057 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001058 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001059
1060 VPRINTK("ENTER\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07001061 writew(0, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001062}
1063
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001064static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1065{
1066 struct nv_adma_port_priv *pp = ap->private_data;
1067 void __iomem *mmio = pp->ctl_block;
1068
1069 /* Go to register mode - clears GO */
1070 nv_adma_register_mode(ap);
1071
1072 /* clear CPB fetch count */
1073 writew(0, mmio + NV_ADMA_CPB_COUNT);
1074
1075 /* disable interrupt, shut down port */
1076 writew(0, mmio + NV_ADMA_CTL);
1077
1078 return 0;
1079}
1080
1081static int nv_adma_port_resume(struct ata_port *ap)
1082{
1083 struct nv_adma_port_priv *pp = ap->private_data;
1084 void __iomem *mmio = pp->ctl_block;
1085 u16 tmp;
1086
1087 /* set CPB block location */
1088 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1089 writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1090
1091 /* clear any outstanding interrupt conditions */
1092 writew(0xffff, mmio + NV_ADMA_STAT);
1093
1094 /* initialize port variables */
1095 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1096
1097 /* clear CPB fetch count */
1098 writew(0, mmio + NV_ADMA_CPB_COUNT);
1099
1100 /* clear GO for register mode, enable interrupt */
1101 tmp = readw(mmio + NV_ADMA_CTL);
1102 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
1103
1104 tmp = readw(mmio + NV_ADMA_CTL);
1105 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1106 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1107 udelay(1);
1108 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1109 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1110
1111 return 0;
1112}
Robert Hancockfbbb2622006-10-27 19:08:41 -07001113
1114static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port)
1115{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001116 void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR];
Robert Hancockfbbb2622006-10-27 19:08:41 -07001117 struct ata_ioports *ioport = &probe_ent->port[port];
1118
1119 VPRINTK("ENTER\n");
1120
1121 mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE;
1122
Tejun Heo0d5ff562007-02-01 15:06:36 +09001123 ioport->cmd_addr = mmio;
1124 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001125 ioport->error_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001126 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1127 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1128 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1129 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1130 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1131 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001132 ioport->status_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001133 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001134 ioport->altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001135 ioport->ctl_addr = mmio + 0x20;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001136}
1137
1138static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
1139{
1140 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1141 unsigned int i;
1142 u32 tmp32;
1143
1144 VPRINTK("ENTER\n");
1145
1146 /* enable ADMA on the ports */
1147 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1148 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1149 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1150 NV_MCP_SATA_CFG_20_PORT1_EN |
1151 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1152
1153 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1154
1155 for (i = 0; i < probe_ent->n_ports; i++)
1156 nv_adma_setup_port(probe_ent, i);
1157
Robert Hancockfbbb2622006-10-27 19:08:41 -07001158 return 0;
1159}
1160
1161static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1162 struct scatterlist *sg,
1163 int idx,
1164 struct nv_adma_prd *aprd)
1165{
Robert Hancock2dec7552006-11-26 14:20:19 -06001166 u8 flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001167
1168 memset(aprd, 0, sizeof(struct nv_adma_prd));
1169
1170 flags = 0;
1171 if (qc->tf.flags & ATA_TFLAG_WRITE)
1172 flags |= NV_APRD_WRITE;
1173 if (idx == qc->n_elem - 1)
1174 flags |= NV_APRD_END;
1175 else if (idx != 4)
1176 flags |= NV_APRD_CONT;
1177
1178 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1179 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
Robert Hancock2dec7552006-11-26 14:20:19 -06001180 aprd->flags = flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001181}
1182
1183static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1184{
1185 struct nv_adma_port_priv *pp = qc->ap->private_data;
1186 unsigned int idx;
1187 struct nv_adma_prd *aprd;
1188 struct scatterlist *sg;
1189
1190 VPRINTK("ENTER\n");
1191
1192 idx = 0;
1193
1194 ata_for_each_sg(sg, qc) {
1195 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1196 nv_adma_fill_aprd(qc, sg, idx, aprd);
1197 idx++;
1198 }
1199 if (idx > 5)
1200 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1201}
1202
Robert Hancock382a6652007-02-05 16:26:02 -08001203static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1204{
1205 struct nv_adma_port_priv *pp = qc->ap->private_data;
1206
1207 /* ADMA engine can only be used for non-ATAPI DMA commands,
1208 or interrupt-driven no-data commands. */
1209 if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1210 (qc->tf.flags & ATA_TFLAG_POLLING))
1211 return 1;
1212
1213 if((qc->flags & ATA_QCFLAG_DMAMAP) ||
1214 (qc->tf.protocol == ATA_PROT_NODATA))
1215 return 0;
1216
1217 return 1;
1218}
1219
Robert Hancockfbbb2622006-10-27 19:08:41 -07001220static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1221{
1222 struct nv_adma_port_priv *pp = qc->ap->private_data;
1223 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1224 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
Robert Hancockfbbb2622006-10-27 19:08:41 -07001225 NV_CPB_CTL_IEN;
1226
Robert Hancock382a6652007-02-05 16:26:02 -08001227 if (nv_adma_use_reg_mode(qc)) {
Robert Hancock2dec7552006-11-26 14:20:19 -06001228 nv_adma_register_mode(qc->ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001229 ata_qc_prep(qc);
1230 return;
1231 }
1232
1233 memset(cpb, 0, sizeof(struct nv_adma_cpb));
1234
1235 cpb->len = 3;
1236 cpb->tag = qc->tag;
1237 cpb->next_cpb_idx = 0;
1238
1239 /* turn on NCQ flags for NCQ commands */
1240 if (qc->tf.protocol == ATA_PROT_NCQ)
1241 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1242
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001243 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1244
Robert Hancockfbbb2622006-10-27 19:08:41 -07001245 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1246
Robert Hancock382a6652007-02-05 16:26:02 -08001247 if(qc->flags & ATA_QCFLAG_DMAMAP) {
1248 nv_adma_fill_sg(qc, cpb);
1249 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1250 } else
1251 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001252
1253 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1254 finished filling in all of the contents */
1255 wmb();
1256 cpb->ctl_flags = ctl_flags;
1257}
1258
1259static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1260{
Robert Hancock2dec7552006-11-26 14:20:19 -06001261 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001262 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001263
1264 VPRINTK("ENTER\n");
1265
Robert Hancock382a6652007-02-05 16:26:02 -08001266 if (nv_adma_use_reg_mode(qc)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001267 /* use ATA register mode */
Robert Hancock382a6652007-02-05 16:26:02 -08001268 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001269 nv_adma_register_mode(qc->ap);
1270 return ata_qc_issue_prot(qc);
1271 } else
1272 nv_adma_mode(qc->ap);
1273
1274 /* write append register, command tag in lower 8 bits
1275 and (number of cpbs to append -1) in top 8 bits */
1276 wmb();
1277 writew(qc->tag, mmio + NV_ADMA_APPEND);
1278
1279 DPRINTK("Issued tag %u\n",qc->tag);
1280
1281 return 0;
1282}
1283
David Howells7d12e782006-10-05 14:55:46 +01001284static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285{
Jeff Garzikcca39742006-08-24 03:19:22 -04001286 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 unsigned int i;
1288 unsigned int handled = 0;
1289 unsigned long flags;
1290
Jeff Garzikcca39742006-08-24 03:19:22 -04001291 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292
Jeff Garzikcca39742006-08-24 03:19:22 -04001293 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294 struct ata_port *ap;
1295
Jeff Garzikcca39742006-08-24 03:19:22 -04001296 ap = host->ports[i];
Tejun Heoc1389502005-08-22 14:59:24 +09001297 if (ap &&
Jeff Garzik029f5462006-04-02 10:30:40 -04001298 !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299 struct ata_queued_cmd *qc;
1300
1301 qc = ata_qc_from_tag(ap, ap->active_tag);
Albert Leee50362e2005-09-27 17:39:50 +08001302 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303 handled += ata_host_intr(ap, qc);
Andrew Chewb8870302006-01-04 19:13:04 -08001304 else
1305 // No request pending? Clear interrupt status
1306 // anyway, in case there's one pending.
1307 ap->ops->check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308 }
1309
1310 }
1311
Jeff Garzikcca39742006-08-24 03:19:22 -04001312 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313
1314 return IRQ_RETVAL(handled);
1315}
1316
Jeff Garzikcca39742006-08-24 03:19:22 -04001317static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +09001318{
1319 int i, handled = 0;
1320
Jeff Garzikcca39742006-08-24 03:19:22 -04001321 for (i = 0; i < host->n_ports; i++) {
1322 struct ata_port *ap = host->ports[i];
Tejun Heoada364e2006-06-17 15:49:56 +09001323
1324 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1325 handled += nv_host_intr(ap, irq_stat);
1326
1327 irq_stat >>= NV_INT_PORT_SHIFT;
1328 }
1329
1330 return IRQ_RETVAL(handled);
1331}
1332
David Howells7d12e782006-10-05 14:55:46 +01001333static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001334{
Jeff Garzikcca39742006-08-24 03:19:22 -04001335 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001336 u8 irq_stat;
1337 irqreturn_t ret;
1338
Jeff Garzikcca39742006-08-24 03:19:22 -04001339 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001340 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
Jeff Garzikcca39742006-08-24 03:19:22 -04001341 ret = nv_do_interrupt(host, irq_stat);
1342 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001343
1344 return ret;
1345}
1346
David Howells7d12e782006-10-05 14:55:46 +01001347static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001348{
Jeff Garzikcca39742006-08-24 03:19:22 -04001349 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001350 u8 irq_stat;
1351 irqreturn_t ret;
1352
Jeff Garzikcca39742006-08-24 03:19:22 -04001353 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001354 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Jeff Garzikcca39742006-08-24 03:19:22 -04001355 ret = nv_do_interrupt(host, irq_stat);
1356 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001357
1358 return ret;
1359}
1360
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1362{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363 if (sc_reg > SCR_CONTROL)
1364 return 0xffffffffU;
1365
Tejun Heo0d5ff562007-02-01 15:06:36 +09001366 return ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367}
1368
1369static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1370{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371 if (sc_reg > SCR_CONTROL)
1372 return;
1373
Tejun Heo0d5ff562007-02-01 15:06:36 +09001374 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375}
1376
Tejun Heo39f87582006-06-17 15:49:56 +09001377static void nv_nf2_freeze(struct ata_port *ap)
1378{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001379 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001380 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1381 u8 mask;
1382
Tejun Heo0d5ff562007-02-01 15:06:36 +09001383 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001384 mask &= ~(NV_INT_ALL << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001385 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001386}
1387
1388static void nv_nf2_thaw(struct ata_port *ap)
1389{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001390 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001391 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1392 u8 mask;
1393
Tejun Heo0d5ff562007-02-01 15:06:36 +09001394 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
Tejun Heo39f87582006-06-17 15:49:56 +09001395
Tejun Heo0d5ff562007-02-01 15:06:36 +09001396 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001397 mask |= (NV_INT_MASK << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001398 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001399}
1400
1401static void nv_ck804_freeze(struct ata_port *ap)
1402{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001403 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001404 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1405 u8 mask;
1406
1407 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1408 mask &= ~(NV_INT_ALL << shift);
1409 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1410}
1411
1412static void nv_ck804_thaw(struct ata_port *ap)
1413{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001414 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001415 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1416 u8 mask;
1417
1418 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1419
1420 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1421 mask |= (NV_INT_MASK << shift);
1422 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1423}
1424
1425static int nv_hardreset(struct ata_port *ap, unsigned int *class)
1426{
1427 unsigned int dummy;
1428
1429 /* SATA hardreset fails to retrieve proper device signature on
1430 * some controllers. Don't classify on hardreset. For more
1431 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1432 */
1433 return sata_std_hardreset(ap, &dummy);
1434}
1435
1436static void nv_error_handler(struct ata_port *ap)
1437{
1438 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1439 nv_hardreset, ata_std_postreset);
1440}
1441
Robert Hancockfbbb2622006-10-27 19:08:41 -07001442static void nv_adma_error_handler(struct ata_port *ap)
1443{
1444 struct nv_adma_port_priv *pp = ap->private_data;
1445 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001446 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001447 int i;
1448 u16 tmp;
1449
Robert Hancockfbbb2622006-10-27 19:08:41 -07001450 /* Push us back into port register mode for error handling. */
1451 nv_adma_register_mode(ap);
1452
Robert Hancockfbbb2622006-10-27 19:08:41 -07001453 /* Mark all of the CPBs as invalid to prevent them from being executed */
1454 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1455 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1456
1457 /* clear CPB fetch count */
1458 writew(0, mmio + NV_ADMA_CPB_COUNT);
1459
1460 /* Reset channel */
1461 tmp = readw(mmio + NV_ADMA_CTL);
1462 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1463 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1464 udelay(1);
1465 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1466 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1467 }
1468
1469 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1470 nv_hardreset, ata_std_postreset);
1471}
1472
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1474{
1475 static int printed_version = 0;
Jeff Garzik29da9f62006-09-25 21:56:33 -04001476 struct ata_port_info *ppi[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477 struct ata_probe_ent *probe_ent;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001478 struct nv_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479 int rc;
1480 u32 bar;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001481 void __iomem *base;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001482 unsigned long type = ent->driver_data;
1483 int mask_set = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484
1485 // Make sure this is a SATA controller by counting the number of bars
1486 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1487 // it's an IDE controller and we ignore it.
1488 for (bar=0; bar<6; bar++)
1489 if (pci_resource_start(pdev, bar) == 0)
1490 return -ENODEV;
1491
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001492 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001493 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
Tejun Heo24dc5f32007-01-20 16:00:28 +09001495 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001497 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498
1499 rc = pci_request_regions(pdev, DRV_NAME);
1500 if (rc) {
Tejun Heo24dc5f32007-01-20 16:00:28 +09001501 pcim_pin_device(pdev);
1502 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503 }
1504
Robert Hancockfbbb2622006-10-27 19:08:41 -07001505 if(type >= CK804 && adma_enabled) {
1506 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1507 type = ADMA;
1508 if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
1509 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1510 mask_set = 1;
1511 }
1512
1513 if(!mask_set) {
1514 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1515 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001516 return rc;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001517 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1518 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001519 return rc;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001520 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521
1522 rc = -ENOMEM;
1523
Tejun Heo24dc5f32007-01-20 16:00:28 +09001524 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001525 if (!hpriv)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001526 return -ENOMEM;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001527
Robert Hancockfbbb2622006-10-27 19:08:41 -07001528 ppi[0] = ppi[1] = &nv_port_info[type];
Jeff Garzik29da9f62006-09-25 21:56:33 -04001529 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 if (!probe_ent)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001531 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532
Tejun Heo0d5ff562007-02-01 15:06:36 +09001533 if (!pcim_iomap(pdev, NV_MMIO_BAR, 0))
Tejun Heo24dc5f32007-01-20 16:00:28 +09001534 return -EIO;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001535 probe_ent->iomap = pcim_iomap_table(pdev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001536
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001537 probe_ent->private_data = hpriv;
1538 hpriv->type = type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539
Tejun Heo0d5ff562007-02-01 15:06:36 +09001540 base = probe_ent->iomap[NV_MMIO_BAR];
Jeff Garzik02cbd922006-03-22 23:59:46 -05001541 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1542 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1543
Tejun Heoada364e2006-06-17 15:49:56 +09001544 /* enable SATA space for CK804 */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001545 if (type >= CK804) {
Tejun Heoada364e2006-06-17 15:49:56 +09001546 u8 regval;
1547
1548 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1549 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1550 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1551 }
1552
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 pci_set_master(pdev);
1554
Robert Hancockfbbb2622006-10-27 19:08:41 -07001555 if (type == ADMA) {
1556 rc = nv_adma_host_init(probe_ent);
1557 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001558 return rc;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001559 }
1560
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561 rc = ata_device_add(probe_ent);
1562 if (rc != NV_PORTS)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001563 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564
Tejun Heo24dc5f32007-01-20 16:00:28 +09001565 devm_kfree(&pdev->dev, probe_ent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567}
1568
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001569static void nv_remove_one (struct pci_dev *pdev)
1570{
1571 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1572 struct nv_host_priv *hpriv = host->private_data;
1573
1574 ata_pci_remove_one(pdev);
1575 kfree(hpriv);
1576}
1577
1578static int nv_pci_device_resume(struct pci_dev *pdev)
1579{
1580 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1581 struct nv_host_priv *hpriv = host->private_data;
Robert Hancockce053fa2007-02-05 16:26:04 -08001582 int rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001583
Robert Hancockce053fa2007-02-05 16:26:04 -08001584 rc = ata_pci_device_do_resume(pdev);
1585 if(rc)
1586 return rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001587
1588 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1589 if(hpriv->type >= CK804) {
1590 u8 regval;
1591
1592 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1593 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1594 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1595 }
1596 if(hpriv->type == ADMA) {
1597 u32 tmp32;
1598 struct nv_adma_port_priv *pp;
1599 /* enable/disable ADMA on the ports appropriately */
1600 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1601
1602 pp = host->ports[0]->private_data;
1603 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1604 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1605 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1606 else
1607 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
1608 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1609 pp = host->ports[1]->private_data;
1610 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1611 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
1612 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1613 else
1614 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
1615 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1616
1617 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1618 }
1619 }
1620
1621 ata_host_resume(host);
1622
1623 return 0;
1624}
1625
Jeff Garzikcca39742006-08-24 03:19:22 -04001626static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +09001627{
Jeff Garzikcca39742006-08-24 03:19:22 -04001628 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +09001629 u8 regval;
1630
1631 /* disable SATA space for CK804 */
1632 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1633 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1634 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
Tejun Heoada364e2006-06-17 15:49:56 +09001635}
1636
Robert Hancockfbbb2622006-10-27 19:08:41 -07001637static void nv_adma_host_stop(struct ata_host *host)
1638{
1639 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001640 u32 tmp32;
1641
Robert Hancockfbbb2622006-10-27 19:08:41 -07001642 /* disable ADMA on the ports */
1643 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1644 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1645 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1646 NV_MCP_SATA_CFG_20_PORT1_EN |
1647 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1648
1649 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1650
1651 nv_ck804_host_stop(host);
1652}
1653
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654static int __init nv_init(void)
1655{
Pavel Roskinb7887192006-08-10 18:13:18 +09001656 return pci_register_driver(&nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657}
1658
1659static void __exit nv_exit(void)
1660{
1661 pci_unregister_driver(&nv_pci_driver);
1662}
1663
1664module_init(nv_init);
1665module_exit(nv_exit);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001666module_param_named(adma, adma_enabled, bool, 0444);
1667MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");