blob: 4c81a71b8877e4262c6574e5e5eb669b88b3610d [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
Jeff Garzikfb9f8902007-03-02 18:17:22 -05002 * pata_cmd64x.c - CMD64x PATA for new ATA layer
Jeff Garzik669a5db2006-08-29 18:12:40 -04003 * (C) 2005 Red Hat Inc
Alan Coxab771632008-10-27 15:09:10 +00004 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +01005 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
Jeff Garzik669a5db2006-08-29 18:12:40 -04006 *
7 * Based upon
8 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
9 *
10 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
11 * Note, this driver is not used at all on other systems because
12 * there the "BIOS" has done all of the following already.
13 * Due to massive hardware bugs, UltraDMA is only supported
14 * on the 646U2 and not on the 646U.
15 *
16 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
17 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
18 *
19 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
20 *
21 * TODO
22 * Testing work
23 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040024
Jeff Garzik669a5db2006-08-29 18:12:40 -040025#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <scsi/scsi_host.h>
32#include <linux/libata.h>
33
34#define DRV_NAME "pata_cmd64x"
Jeff Garzik06393af2009-12-20 15:39:55 -050035#define DRV_VERSION "0.2.5"
Jeff Garzik669a5db2006-08-29 18:12:40 -040036
37/*
38 * CMD64x specific registers definition.
39 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040040
Jeff Garzik669a5db2006-08-29 18:12:40 -040041enum {
42 CFR = 0x50,
Bartlomiej Zolnierkiewicz03a849e2010-01-18 18:15:11 +010043 CFR_INTR_CH0 = 0x04,
Jeff Garzik669a5db2006-08-29 18:12:40 -040044 CMDTIM = 0x52,
45 ARTTIM0 = 0x53,
46 DRWTIM0 = 0x54,
47 ARTTIM1 = 0x55,
48 DRWTIM1 = 0x56,
49 ARTTIM23 = 0x57,
50 ARTTIM23_DIS_RA2 = 0x04,
51 ARTTIM23_DIS_RA3 = 0x08,
52 ARTTIM23_INTR_CH1 = 0x10,
Jeff Garzik669a5db2006-08-29 18:12:40 -040053 DRWTIM2 = 0x58,
54 BRST = 0x59,
55 DRWTIM3 = 0x5b,
56 BMIDECR0 = 0x70,
57 MRDMODE = 0x71,
58 MRDMODE_INTR_CH0 = 0x04,
59 MRDMODE_INTR_CH1 = 0x08,
Jeff Garzik669a5db2006-08-29 18:12:40 -040060 BMIDESR0 = 0x72,
61 UDIDETCR0 = 0x73,
62 DTPR0 = 0x74,
63 BMIDECR1 = 0x78,
64 BMIDECSR = 0x79,
Jeff Garzik669a5db2006-08-29 18:12:40 -040065 UDIDETCR1 = 0x7B,
66 DTPR1 = 0x7C
67};
68
Jeff Garzika73984a2007-03-09 08:37:46 -050069static int cmd648_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -040070{
71 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
72 u8 r;
73
74 /* Check cable detect bits */
75 pci_read_config_byte(pdev, BMIDECSR, &r);
76 if (r & (1 << ap->port_no))
Jeff Garzika73984a2007-03-09 08:37:46 -050077 return ATA_CBL_PATA80;
78 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -040079}
80
81/**
Alan Cox05d1eff2007-08-10 13:59:49 -070082 * cmd64x_set_piomode - set PIO and MWDMA timing
Jeff Garzik669a5db2006-08-29 18:12:40 -040083 * @ap: ATA interface
84 * @adev: ATA device
Alan Cox05d1eff2007-08-10 13:59:49 -070085 * @mode: mode
Jeff Garzik669a5db2006-08-29 18:12:40 -040086 *
Alan Cox05d1eff2007-08-10 13:59:49 -070087 * Called to do the PIO and MWDMA mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -040088 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040089
Alan Cox05d1eff2007-08-10 13:59:49 -070090static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
Jeff Garzik669a5db2006-08-29 18:12:40 -040091{
92 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
93 struct ata_timing t;
94 const unsigned long T = 1000000 / 33;
95 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
Jeff Garzik85cd7252006-08-31 00:03:49 -040096
Jeff Garzik669a5db2006-08-29 18:12:40 -040097 u8 reg;
Jeff Garzik85cd7252006-08-31 00:03:49 -040098
Jeff Garzik669a5db2006-08-29 18:12:40 -040099 /* Port layout is not logical so use a table */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400100 const u8 arttim_port[2][2] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101 { ARTTIM0, ARTTIM1 },
102 { ARTTIM23, ARTTIM23 }
103 };
104 const u8 drwtim_port[2][2] = {
105 { DRWTIM0, DRWTIM1 },
106 { DRWTIM2, DRWTIM3 }
107 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400108
Jeff Garzik669a5db2006-08-29 18:12:40 -0400109 int arttim = arttim_port[ap->port_no][adev->devno];
110 int drwtim = drwtim_port[ap->port_no][adev->devno];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400111
Alan Cox05d1eff2007-08-10 13:59:49 -0700112 /* ata_timing_compute is smart and will produce timings for MWDMA
113 that don't violate the drives PIO capabilities. */
114 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
116 return;
117 }
118 if (ap->port_no) {
119 /* Slave has shared address setup */
120 struct ata_device *pair = ata_dev_pair(adev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400121
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122 if (pair) {
123 struct ata_timing tp;
Bartlomiej Zolnierkiewiczd62f5572010-01-18 18:15:04 +0100124
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
126 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
Bartlomiej Zolnierkiewiczd62f5572010-01-18 18:15:04 +0100127 if (pair->dma_mode) {
128 ata_timing_compute(pair, pair->dma_mode,
129 &tp, T, 0);
130 ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
131 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 }
133 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400134
Jeff Garzik669a5db2006-08-29 18:12:40 -0400135 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
136 t.active, t.recover, t.setup);
137 if (t.recover > 16) {
138 t.active += t.recover - 16;
139 t.recover = 16;
140 }
141 if (t.active > 16)
142 t.active = 16;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400143
Jeff Garzik669a5db2006-08-29 18:12:40 -0400144 /* Now convert the clocks into values we can actually stuff into
145 the chip */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400146
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +0100147 if (t.recover == 16)
148 t.recover = 0;
149 else if (t.recover > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400150 t.recover--;
151 else
152 t.recover = 15;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400153
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 if (t.setup > 4)
155 t.setup = 0xC0;
156 else
157 t.setup = setup_data[t.setup];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400158
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159 t.active &= 0x0F; /* 0 = 16 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400160
Jeff Garzik669a5db2006-08-29 18:12:40 -0400161 /* Load setup timing */
162 pci_read_config_byte(pdev, arttim, &reg);
163 reg &= 0x3F;
164 reg |= t.setup;
165 pci_write_config_byte(pdev, arttim, reg);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400166
Jeff Garzik669a5db2006-08-29 18:12:40 -0400167 /* Load active/recovery */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400168 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400169}
170
171/**
Alan Cox05d1eff2007-08-10 13:59:49 -0700172 * cmd64x_set_piomode - set initial PIO mode data
173 * @ap: ATA interface
174 * @adev: ATA device
175 *
176 * Used when configuring the devices ot set the PIO timings. All the
177 * actual work is done by the PIO/MWDMA setting helper
178 */
179
180static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
181{
182 cmd64x_set_timing(ap, adev, adev->pio_mode);
183}
184
185/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 * cmd64x_set_dmamode - set initial DMA mode data
187 * @ap: ATA interface
188 * @adev: ATA device
189 *
190 * Called to do the DMA mode setup.
191 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400192
Jeff Garzik669a5db2006-08-29 18:12:40 -0400193static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
194{
195 static const u8 udma_data[] = {
Alan6a40da02007-01-24 11:49:03 +0000196 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400198
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
200 u8 regU, regD;
201
202 int pciU = UDIDETCR0 + 8 * ap->port_no;
203 int pciD = BMIDESR0 + 8 * ap->port_no;
204 int shift = 2 * adev->devno;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400205
Jeff Garzik669a5db2006-08-29 18:12:40 -0400206 pci_read_config_byte(pdev, pciD, &regD);
207 pci_read_config_byte(pdev, pciU, &regU);
208
Alan6a40da02007-01-24 11:49:03 +0000209 /* DMA bits off */
210 regD &= ~(0x20 << adev->devno);
211 /* DMA control bits */
212 regU &= ~(0x30 << shift);
213 /* DMA timing bits */
214 regU &= ~(0x05 << adev->devno);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400215
Alan6a40da02007-01-24 11:49:03 +0000216 if (adev->dma_mode >= XFER_UDMA_0) {
Adrian Bunk24b7ce92007-10-20 01:02:48 +0200217 /* Merge the timing value */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400218 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
Alan6a40da02007-01-24 11:49:03 +0000219 /* Merge the control bits */
220 regU |= 1 << adev->devno; /* UDMA on */
Bartlomiej Zolnierkiewicz509426b2009-12-20 19:22:33 +0100221 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
Alan6a40da02007-01-24 11:49:03 +0000222 regU |= 4 << adev->devno;
Alan Cox05d1eff2007-08-10 13:59:49 -0700223 } else {
224 regU &= ~ (1 << adev->devno); /* UDMA off */
225 cmd64x_set_timing(ap, adev, adev->dma_mode);
226 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400227
228 regD |= 0x20 << adev->devno;
229
230 pci_write_config_byte(pdev, pciU, regU);
231 pci_write_config_byte(pdev, pciD, regD);
232}
233
234/**
235 * cmd648_dma_stop - DMA stop callback
236 * @qc: Command in progress
237 *
238 * DMA has completed.
239 */
240
241static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
242{
243 struct ata_port *ap = qc->ap;
244 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
245 u8 dma_intr;
Alan6a40da02007-01-24 11:49:03 +0000246 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
Bartlomiej Zolnierkiewiczc754d9b62010-01-18 18:15:18 +0100247 int dma_reg = ap->port_no ? ARTTIM23 : CFR;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400248
Jeff Garzik669a5db2006-08-29 18:12:40 -0400249 ata_bmdma_stop(qc);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400250
Jeff Garzik669a5db2006-08-29 18:12:40 -0400251 pci_read_config_byte(pdev, dma_reg, &dma_intr);
252 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
253}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400254
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255/**
Jeff Garzik06393af2009-12-20 15:39:55 -0500256 * cmd646r1_dma_stop - DMA stop callback
Jeff Garzik669a5db2006-08-29 18:12:40 -0400257 * @qc: Command in progress
258 *
Jeff Garzik06393af2009-12-20 15:39:55 -0500259 * Stub for now while investigating the r1 quirk in the old driver.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400260 */
261
Jeff Garzik06393af2009-12-20 15:39:55 -0500262static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400263{
264 ata_bmdma_stop(qc);
265}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400266
Jeff Garzik669a5db2006-08-29 18:12:40 -0400267static struct scsi_host_template cmd64x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900268 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400269};
270
Tejun Heo029cfd62008-03-25 12:22:49 +0900271static const struct ata_port_operations cmd64x_base_ops = {
272 .inherits = &ata_bmdma_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 .set_piomode = cmd64x_set_piomode,
274 .set_dmamode = cmd64x_set_dmamode,
Tejun Heo029cfd62008-03-25 12:22:49 +0900275};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400276
Tejun Heo029cfd62008-03-25 12:22:49 +0900277static struct ata_port_operations cmd64x_port_ops = {
278 .inherits = &cmd64x_base_ops,
Jeff Garzika73984a2007-03-09 08:37:46 -0500279 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400280};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281
282static struct ata_port_operations cmd646r1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900283 .inherits = &cmd64x_base_ops,
Jeff Garzik06393af2009-12-20 15:39:55 -0500284 .bmdma_stop = cmd646r1_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900285 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400286};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287
288static struct ata_port_operations cmd648_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900289 .inherits = &cmd64x_base_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400290 .bmdma_stop = cmd648_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900291 .cable_detect = cmd648_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400292};
293
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
295{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200296 static const struct ata_port_info cmd_info[6] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297 { /* CMD 643 - no UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400298 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100299 .pio_mask = ATA_PIO4,
300 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400301 .port_ops = &cmd64x_port_ops
302 },
303 { /* CMD 646 with broken UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400304 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100305 .pio_mask = ATA_PIO4,
306 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307 .port_ops = &cmd64x_port_ops
308 },
309 { /* CMD 646 with working UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400310 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100311 .pio_mask = ATA_PIO4,
312 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100313 .udma_mask = ATA_UDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314 .port_ops = &cmd64x_port_ops
315 },
316 { /* CMD 646 rev 1 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400317 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100318 .pio_mask = ATA_PIO4,
319 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400320 .port_ops = &cmd646r1_port_ops
321 },
322 { /* CMD 648 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400323 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100324 .pio_mask = ATA_PIO4,
325 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100326 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400327 .port_ops = &cmd648_port_ops
328 },
329 { /* CMD 649 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400330 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100331 .pio_mask = ATA_PIO4,
332 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100333 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400334 .port_ops = &cmd648_port_ops
335 }
336 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200337 const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400338 u8 mrdmode;
Tejun Heof08048e2008-03-25 12:22:47 +0900339 int rc;
340
341 rc = pcim_enable_device(pdev);
342 if (rc)
343 return rc;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400344
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345 if (id->driver_data == 0) /* 643 */
Tejun Heo9363c382008-04-07 22:47:16 +0900346 ata_pci_bmdma_clear_simplex(pdev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400347
Jeff Garzik669a5db2006-08-29 18:12:40 -0400348 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
349 /* Does UDMA work ? */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400350 if (pdev->revision > 4)
Tejun Heo1626aeb2007-05-04 12:43:58 +0200351 ppi[0] = &cmd_info[2];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400352 /* Early rev with other problems ? */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400353 else if (pdev->revision == 1)
Tejun Heo1626aeb2007-05-04 12:43:58 +0200354 ppi[0] = &cmd_info[3];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400355 }
356
357 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
358 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
359 mrdmode &= ~ 0x30; /* IRQ set up */
360 mrdmode |= 0x02; /* Memory read line enable */
361 pci_write_config_byte(pdev, MRDMODE, mrdmode);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400362
Jeff Garzik06393af2009-12-20 15:39:55 -0500363 /* Force PIO 0 here.. */
364
Jeff Garzik669a5db2006-08-29 18:12:40 -0400365 /* PPC specific fixup copied from old driver */
366#ifdef CONFIG_PPC
367 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
368#endif
Jeff Garzik85cd7252006-08-31 00:03:49 -0400369
Alan Cox16ea0fc2010-02-23 02:26:06 -0500370 return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400371}
372
Tejun Heo438ac6d2007-03-02 17:31:26 +0900373#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000374static int cmd64x_reinit_one(struct pci_dev *pdev)
375{
Tejun Heof08048e2008-03-25 12:22:47 +0900376 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Alan7f72a372006-11-22 16:59:07 +0000377 u8 mrdmode;
Tejun Heof08048e2008-03-25 12:22:47 +0900378 int rc;
379
380 rc = ata_pci_device_do_resume(pdev);
381 if (rc)
382 return rc;
383
Alan7f72a372006-11-22 16:59:07 +0000384 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
385 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
386 mrdmode &= ~ 0x30; /* IRQ set up */
387 mrdmode |= 0x02; /* Memory read line enable */
388 pci_write_config_byte(pdev, MRDMODE, mrdmode);
389#ifdef CONFIG_PPC
390 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
391#endif
Tejun Heof08048e2008-03-25 12:22:47 +0900392 ata_host_resume(host);
393 return 0;
Alan7f72a372006-11-22 16:59:07 +0000394}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900395#endif
Alan7f72a372006-11-22 16:59:07 +0000396
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400397static const struct pci_device_id cmd64x[] = {
398 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
399 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
400 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
401 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
402
403 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400404};
405
406static struct pci_driver cmd64x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400407 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400408 .id_table = cmd64x,
409 .probe = cmd64x_init_one,
Alan7f72a372006-11-22 16:59:07 +0000410 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900411#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000412 .suspend = ata_pci_device_suspend,
413 .resume = cmd64x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900414#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400415};
416
417static int __init cmd64x_init(void)
418{
419 return pci_register_driver(&cmd64x_pci_driver);
420}
421
Jeff Garzik669a5db2006-08-29 18:12:40 -0400422static void __exit cmd64x_exit(void)
423{
424 pci_unregister_driver(&cmd64x_pci_driver);
425}
426
Jeff Garzik669a5db2006-08-29 18:12:40 -0400427MODULE_AUTHOR("Alan Cox");
428MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
429MODULE_LICENSE("GPL");
430MODULE_DEVICE_TABLE(pci, cmd64x);
431MODULE_VERSION(DRV_VERSION);
432
433module_init(cmd64x_init);
434module_exit(cmd64x_exit);