Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2/3 CM module functions |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 13 | #include <linux/types.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/spinlock.h> |
| 16 | #include <linux/list.h> |
| 17 | #include <linux/errno.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/io.h> |
| 20 | |
Tony Lindgren | 2b43e4e | 2012-03-03 09:47:45 -0800 | [diff] [blame] | 21 | #include <plat/hardware.h> |
| 22 | |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 23 | #include "iomap.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 24 | #include "common.h" |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 25 | #include "cm.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 26 | #include "cm2xxx_3xxx.h" |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 27 | #include "cm-regbits-24xx.h" |
| 28 | #include "cm-regbits-34xx.h" |
| 29 | |
Paul Walmsley | 92618ff | 2011-02-25 15:39:27 -0700 | [diff] [blame] | 30 | /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ |
Paul Walmsley | 0fd0c21 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 31 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
| 32 | #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 |
| 33 | |
Paul Walmsley | 92618ff | 2011-02-25 15:39:27 -0700 | [diff] [blame] | 34 | /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ |
| 35 | #define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 |
| 36 | #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 |
| 37 | |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 38 | static const u8 cm_idlest_offs[] = { |
| 39 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 |
| 40 | }; |
| 41 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 42 | u32 omap2_cm_read_mod_reg(s16 module, u16 idx) |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 43 | { |
| 44 | return __raw_readl(cm_base + module + idx); |
| 45 | } |
| 46 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 47 | void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 48 | { |
| 49 | __raw_writel(val, cm_base + module + idx); |
| 50 | } |
| 51 | |
| 52 | /* Read-modify-write a register in a CM module. Caller must lock */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 53 | u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 54 | { |
| 55 | u32 v; |
| 56 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 57 | v = omap2_cm_read_mod_reg(module, idx); |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 58 | v &= ~mask; |
| 59 | v |= bits; |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 60 | omap2_cm_write_mod_reg(v, module, idx); |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 61 | |
| 62 | return v; |
| 63 | } |
| 64 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 65 | u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 66 | { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 67 | return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 68 | } |
| 69 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 70 | u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 71 | { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 72 | return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 73 | } |
| 74 | |
Paul Walmsley | 55ae350 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 75 | /* |
| 76 | * |
| 77 | */ |
| 78 | |
| 79 | static void _write_clktrctrl(u8 c, s16 module, u32 mask) |
| 80 | { |
| 81 | u32 v; |
| 82 | |
| 83 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); |
| 84 | v &= ~mask; |
| 85 | v |= c << __ffs(mask); |
| 86 | omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); |
| 87 | } |
| 88 | |
| 89 | bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask) |
| 90 | { |
| 91 | u32 v; |
| 92 | bool ret = 0; |
| 93 | |
| 94 | BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx()); |
| 95 | |
| 96 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); |
| 97 | v &= mask; |
| 98 | v >>= __ffs(mask); |
| 99 | |
| 100 | if (cpu_is_omap24xx()) |
| 101 | ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; |
| 102 | else |
| 103 | ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; |
| 104 | |
| 105 | return ret; |
| 106 | } |
| 107 | |
| 108 | void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) |
| 109 | { |
| 110 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); |
| 111 | } |
| 112 | |
| 113 | void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) |
| 114 | { |
| 115 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); |
| 116 | } |
| 117 | |
| 118 | void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) |
| 119 | { |
| 120 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); |
| 121 | } |
| 122 | |
| 123 | void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) |
| 124 | { |
| 125 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); |
| 126 | } |
| 127 | |
| 128 | void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) |
| 129 | { |
| 130 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); |
| 131 | } |
| 132 | |
| 133 | void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) |
| 134 | { |
| 135 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); |
| 136 | } |
| 137 | |
Paul Walmsley | 0fd0c21 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 138 | /* |
| 139 | * DPLL autoidle control |
| 140 | */ |
| 141 | |
| 142 | static void _omap2xxx_set_dpll_autoidle(u8 m) |
| 143 | { |
| 144 | u32 v; |
| 145 | |
| 146 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); |
| 147 | v &= ~OMAP24XX_AUTO_DPLL_MASK; |
| 148 | v |= m << OMAP24XX_AUTO_DPLL_SHIFT; |
| 149 | omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); |
| 150 | } |
| 151 | |
| 152 | void omap2xxx_cm_set_dpll_disable_autoidle(void) |
| 153 | { |
| 154 | _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP); |
| 155 | } |
| 156 | |
| 157 | void omap2xxx_cm_set_dpll_auto_low_power_stop(void) |
| 158 | { |
| 159 | _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); |
| 160 | } |
Paul Walmsley | 55ae350 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 161 | |
| 162 | /* |
Paul Walmsley | 92618ff | 2011-02-25 15:39:27 -0700 | [diff] [blame] | 163 | * APLL autoidle control |
| 164 | */ |
| 165 | |
| 166 | static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) |
| 167 | { |
| 168 | u32 v; |
| 169 | |
| 170 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); |
| 171 | v &= ~mask; |
| 172 | v |= m << __ffs(mask); |
| 173 | omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); |
| 174 | } |
| 175 | |
| 176 | void omap2xxx_cm_set_apll54_disable_autoidle(void) |
| 177 | { |
| 178 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, |
| 179 | OMAP24XX_AUTO_54M_MASK); |
| 180 | } |
| 181 | |
| 182 | void omap2xxx_cm_set_apll54_auto_low_power_stop(void) |
| 183 | { |
| 184 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, |
| 185 | OMAP24XX_AUTO_54M_MASK); |
| 186 | } |
| 187 | |
| 188 | void omap2xxx_cm_set_apll96_disable_autoidle(void) |
| 189 | { |
| 190 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, |
| 191 | OMAP24XX_AUTO_96M_MASK); |
| 192 | } |
| 193 | |
| 194 | void omap2xxx_cm_set_apll96_auto_low_power_stop(void) |
| 195 | { |
| 196 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, |
| 197 | OMAP24XX_AUTO_96M_MASK); |
| 198 | } |
| 199 | |
| 200 | /* |
Paul Walmsley | 55ae350 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 201 | * |
| 202 | */ |
| 203 | |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 204 | /** |
| 205 | * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby |
| 206 | * @prcm_mod: PRCM module offset |
| 207 | * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) |
| 208 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check |
| 209 | * |
| 210 | * XXX document |
| 211 | */ |
| 212 | int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) |
| 213 | { |
| 214 | int ena = 0, i = 0; |
| 215 | u8 cm_idlest_reg; |
| 216 | u32 mask; |
| 217 | |
| 218 | if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) |
| 219 | return -EINVAL; |
| 220 | |
| 221 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; |
| 222 | |
Kevin Hilman | 6405616 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 223 | mask = 1 << idlest_shift; |
| 224 | |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 225 | if (cpu_is_omap24xx()) |
Kevin Hilman | 6405616 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 226 | ena = mask; |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 227 | else if (cpu_is_omap34xx()) |
| 228 | ena = 0; |
| 229 | else |
| 230 | BUG(); |
| 231 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 232 | omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), |
Paul Walmsley | 6f8b7ff | 2009-12-08 16:33:16 -0700 | [diff] [blame] | 233 | MAX_MODULE_READY_TIME, i); |
Paul Walmsley | 71348bc | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 234 | |
| 235 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
| 236 | } |
| 237 | |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 238 | /* |
| 239 | * Context save/restore code - OMAP3 only |
| 240 | */ |
| 241 | #ifdef CONFIG_ARCH_OMAP3 |
| 242 | struct omap3_cm_regs { |
| 243 | u32 iva2_cm_clksel1; |
| 244 | u32 iva2_cm_clksel2; |
| 245 | u32 cm_sysconfig; |
| 246 | u32 sgx_cm_clksel; |
| 247 | u32 dss_cm_clksel; |
| 248 | u32 cam_cm_clksel; |
| 249 | u32 per_cm_clksel; |
| 250 | u32 emu_cm_clksel; |
| 251 | u32 emu_cm_clkstctrl; |
Eduardo Valentin | a8ae645 | 2011-04-13 18:21:07 +0300 | [diff] [blame] | 252 | u32 pll_cm_autoidle; |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 253 | u32 pll_cm_autoidle2; |
| 254 | u32 pll_cm_clksel4; |
| 255 | u32 pll_cm_clksel5; |
| 256 | u32 pll_cm_clken2; |
| 257 | u32 cm_polctrl; |
| 258 | u32 iva2_cm_fclken; |
| 259 | u32 iva2_cm_clken_pll; |
| 260 | u32 core_cm_fclken1; |
| 261 | u32 core_cm_fclken3; |
| 262 | u32 sgx_cm_fclken; |
| 263 | u32 wkup_cm_fclken; |
| 264 | u32 dss_cm_fclken; |
| 265 | u32 cam_cm_fclken; |
| 266 | u32 per_cm_fclken; |
| 267 | u32 usbhost_cm_fclken; |
| 268 | u32 core_cm_iclken1; |
| 269 | u32 core_cm_iclken2; |
| 270 | u32 core_cm_iclken3; |
| 271 | u32 sgx_cm_iclken; |
| 272 | u32 wkup_cm_iclken; |
| 273 | u32 dss_cm_iclken; |
| 274 | u32 cam_cm_iclken; |
| 275 | u32 per_cm_iclken; |
| 276 | u32 usbhost_cm_iclken; |
| 277 | u32 iva2_cm_autoidle2; |
| 278 | u32 mpu_cm_autoidle2; |
| 279 | u32 iva2_cm_clkstctrl; |
| 280 | u32 mpu_cm_clkstctrl; |
| 281 | u32 core_cm_clkstctrl; |
| 282 | u32 sgx_cm_clkstctrl; |
| 283 | u32 dss_cm_clkstctrl; |
| 284 | u32 cam_cm_clkstctrl; |
| 285 | u32 per_cm_clkstctrl; |
| 286 | u32 neon_cm_clkstctrl; |
| 287 | u32 usbhost_cm_clkstctrl; |
| 288 | u32 core_cm_autoidle1; |
| 289 | u32 core_cm_autoidle2; |
| 290 | u32 core_cm_autoidle3; |
| 291 | u32 wkup_cm_autoidle; |
| 292 | u32 dss_cm_autoidle; |
| 293 | u32 cam_cm_autoidle; |
| 294 | u32 per_cm_autoidle; |
| 295 | u32 usbhost_cm_autoidle; |
| 296 | u32 sgx_cm_sleepdep; |
| 297 | u32 dss_cm_sleepdep; |
| 298 | u32 cam_cm_sleepdep; |
| 299 | u32 per_cm_sleepdep; |
| 300 | u32 usbhost_cm_sleepdep; |
| 301 | u32 cm_clkout_ctrl; |
| 302 | }; |
| 303 | |
| 304 | static struct omap3_cm_regs cm_context; |
| 305 | |
| 306 | void omap3_cm_save_context(void) |
| 307 | { |
| 308 | cm_context.iva2_cm_clksel1 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 309 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 310 | cm_context.iva2_cm_clksel2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 311 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 312 | cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); |
| 313 | cm_context.sgx_cm_clksel = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 314 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 315 | cm_context.dss_cm_clksel = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 316 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 317 | cm_context.cam_cm_clksel = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 318 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 319 | cm_context.per_cm_clksel = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 320 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 321 | cm_context.emu_cm_clksel = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 322 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 323 | cm_context.emu_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 324 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); |
Eduardo Valentin | a8ae645 | 2011-04-13 18:21:07 +0300 | [diff] [blame] | 325 | /* |
| 326 | * As per erratum i671, ROM code does not respect the PER DPLL |
| 327 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. |
| 328 | * In this case, even though this register has been saved in |
| 329 | * scratchpad contents, we need to restore AUTO_PERIPH_DPLL |
| 330 | * by ourselves. So, we need to save it anyway. |
| 331 | */ |
| 332 | cm_context.pll_cm_autoidle = |
| 333 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 334 | cm_context.pll_cm_autoidle2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 335 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 336 | cm_context.pll_cm_clksel4 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 337 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 338 | cm_context.pll_cm_clksel5 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 339 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 340 | cm_context.pll_cm_clken2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 341 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 342 | cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); |
| 343 | cm_context.iva2_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 344 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 345 | cm_context.iva2_cm_clken_pll = |
| 346 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 347 | cm_context.core_cm_fclken1 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 348 | omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 349 | cm_context.core_cm_fclken3 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 350 | omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 351 | cm_context.sgx_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 352 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 353 | cm_context.wkup_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 354 | omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 355 | cm_context.dss_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 356 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 357 | cm_context.cam_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 358 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 359 | cm_context.per_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 360 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 361 | cm_context.usbhost_cm_fclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 362 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 363 | cm_context.core_cm_iclken1 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 364 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 365 | cm_context.core_cm_iclken2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 366 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 367 | cm_context.core_cm_iclken3 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 368 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 369 | cm_context.sgx_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 370 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 371 | cm_context.wkup_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 372 | omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 373 | cm_context.dss_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 374 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 375 | cm_context.cam_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 376 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 377 | cm_context.per_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 378 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 379 | cm_context.usbhost_cm_iclken = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 380 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 381 | cm_context.iva2_cm_autoidle2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 382 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 383 | cm_context.mpu_cm_autoidle2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 384 | omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 385 | cm_context.iva2_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 386 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 387 | cm_context.mpu_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 388 | omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 389 | cm_context.core_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 390 | omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 391 | cm_context.sgx_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 392 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 393 | cm_context.dss_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 394 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 395 | cm_context.cam_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 396 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 397 | cm_context.per_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 398 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 399 | cm_context.neon_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 400 | omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 401 | cm_context.usbhost_cm_clkstctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 402 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
| 403 | OMAP2_CM_CLKSTCTRL); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 404 | cm_context.core_cm_autoidle1 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 405 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 406 | cm_context.core_cm_autoidle2 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 407 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 408 | cm_context.core_cm_autoidle3 = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 409 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 410 | cm_context.wkup_cm_autoidle = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 411 | omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 412 | cm_context.dss_cm_autoidle = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 413 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 414 | cm_context.cam_cm_autoidle = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 415 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 416 | cm_context.per_cm_autoidle = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 417 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 418 | cm_context.usbhost_cm_autoidle = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 419 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 420 | cm_context.sgx_cm_sleepdep = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 421 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, |
| 422 | OMAP3430_CM_SLEEPDEP); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 423 | cm_context.dss_cm_sleepdep = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 424 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 425 | cm_context.cam_cm_sleepdep = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 426 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 427 | cm_context.per_cm_sleepdep = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 428 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 429 | cm_context.usbhost_cm_sleepdep = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 430 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
| 431 | OMAP3430_CM_SLEEPDEP); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 432 | cm_context.cm_clkout_ctrl = |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 433 | omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, |
| 434 | OMAP3_CM_CLKOUT_CTRL_OFFSET); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | void omap3_cm_restore_context(void) |
| 438 | { |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 439 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, |
| 440 | CM_CLKSEL1); |
| 441 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, |
| 442 | CM_CLKSEL2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 443 | __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 444 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, |
| 445 | CM_CLKSEL); |
| 446 | omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, |
| 447 | CM_CLKSEL); |
| 448 | omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, |
| 449 | CM_CLKSEL); |
| 450 | omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, |
| 451 | CM_CLKSEL); |
| 452 | omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, |
| 453 | CM_CLKSEL1); |
| 454 | omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, |
| 455 | OMAP2_CM_CLKSTCTRL); |
Eduardo Valentin | a8ae645 | 2011-04-13 18:21:07 +0300 | [diff] [blame] | 456 | /* |
| 457 | * As per erratum i671, ROM code does not respect the PER DPLL |
| 458 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. |
| 459 | * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves. |
| 460 | */ |
| 461 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, |
| 462 | CM_AUTOIDLE); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 463 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, |
| 464 | CM_AUTOIDLE2); |
| 465 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, |
| 466 | OMAP3430ES2_CM_CLKSEL4); |
| 467 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, |
| 468 | OMAP3430ES2_CM_CLKSEL5); |
| 469 | omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, |
| 470 | OMAP3430ES2_CM_CLKEN2); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 471 | __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 472 | omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, |
| 473 | CM_FCLKEN); |
| 474 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, |
| 475 | OMAP3430_CM_CLKEN_PLL); |
| 476 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, |
| 477 | CM_FCLKEN1); |
| 478 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, |
| 479 | OMAP3430ES2_CM_FCLKEN3); |
| 480 | omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, |
| 481 | CM_FCLKEN); |
| 482 | omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); |
| 483 | omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, |
| 484 | CM_FCLKEN); |
| 485 | omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, |
| 486 | CM_FCLKEN); |
| 487 | omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, |
| 488 | CM_FCLKEN); |
| 489 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, |
| 490 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); |
| 491 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, |
| 492 | CM_ICLKEN1); |
| 493 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, |
| 494 | CM_ICLKEN2); |
| 495 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, |
| 496 | CM_ICLKEN3); |
| 497 | omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, |
| 498 | CM_ICLKEN); |
| 499 | omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); |
| 500 | omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, |
| 501 | CM_ICLKEN); |
| 502 | omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, |
| 503 | CM_ICLKEN); |
| 504 | omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, |
| 505 | CM_ICLKEN); |
| 506 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, |
| 507 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); |
| 508 | omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, |
| 509 | CM_AUTOIDLE2); |
| 510 | omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, |
| 511 | CM_AUTOIDLE2); |
| 512 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, |
| 513 | OMAP2_CM_CLKSTCTRL); |
| 514 | omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, |
| 515 | OMAP2_CM_CLKSTCTRL); |
| 516 | omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, |
| 517 | OMAP2_CM_CLKSTCTRL); |
| 518 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, |
| 519 | OMAP2_CM_CLKSTCTRL); |
| 520 | omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, |
| 521 | OMAP2_CM_CLKSTCTRL); |
| 522 | omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, |
| 523 | OMAP2_CM_CLKSTCTRL); |
| 524 | omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, |
| 525 | OMAP2_CM_CLKSTCTRL); |
| 526 | omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, |
| 527 | OMAP2_CM_CLKSTCTRL); |
| 528 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, |
| 529 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); |
| 530 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, |
| 531 | CM_AUTOIDLE1); |
| 532 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, |
| 533 | CM_AUTOIDLE2); |
| 534 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, |
| 535 | CM_AUTOIDLE3); |
| 536 | omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, |
| 537 | CM_AUTOIDLE); |
| 538 | omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, |
| 539 | CM_AUTOIDLE); |
| 540 | omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, |
| 541 | CM_AUTOIDLE); |
| 542 | omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, |
| 543 | CM_AUTOIDLE); |
| 544 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, |
| 545 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); |
| 546 | omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, |
| 547 | OMAP3430_CM_SLEEPDEP); |
| 548 | omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, |
| 549 | OMAP3430_CM_SLEEPDEP); |
| 550 | omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, |
| 551 | OMAP3430_CM_SLEEPDEP); |
| 552 | omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, |
| 553 | OMAP3430_CM_SLEEPDEP); |
| 554 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, |
| 555 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); |
| 556 | omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, |
| 557 | OMAP3_CM_CLKOUT_CTRL_OFFSET); |
Paul Walmsley | f0611a5 | 2010-12-21 15:30:56 -0700 | [diff] [blame] | 558 | } |
| 559 | #endif |