Shuzhen Wang | ce65086 | 2011-08-17 15:27:01 -0700 | [diff] [blame] | 1 | #ifndef __MSM_ISP_H__ |
| 2 | #define __MSM_ISP_H__ |
| 3 | |
Kiran Kumar H N | dd12847 | 2011-12-01 09:35:34 -0800 | [diff] [blame] | 4 | #define BIT(nr) (1UL << (nr)) |
| 5 | |
Shuzhen Wang | ce65086 | 2011-08-17 15:27:01 -0700 | [diff] [blame] | 6 | /* ISP message IDs */ |
| 7 | #define MSG_ID_RESET_ACK 0 |
| 8 | #define MSG_ID_START_ACK 1 |
| 9 | #define MSG_ID_STOP_ACK 2 |
| 10 | #define MSG_ID_UPDATE_ACK 3 |
| 11 | #define MSG_ID_OUTPUT_P 4 |
| 12 | #define MSG_ID_OUTPUT_T 5 |
| 13 | #define MSG_ID_OUTPUT_S 6 |
| 14 | #define MSG_ID_OUTPUT_V 7 |
| 15 | #define MSG_ID_SNAPSHOT_DONE 8 |
| 16 | #define MSG_ID_STATS_AEC 9 |
| 17 | #define MSG_ID_STATS_AF 10 |
| 18 | #define MSG_ID_STATS_AWB 11 |
| 19 | #define MSG_ID_STATS_RS 12 |
| 20 | #define MSG_ID_STATS_CS 13 |
| 21 | #define MSG_ID_STATS_IHIST 14 |
| 22 | #define MSG_ID_STATS_SKIN 15 |
| 23 | #define MSG_ID_EPOCH1 16 |
| 24 | #define MSG_ID_EPOCH2 17 |
| 25 | #define MSG_ID_SYNC_TIMER0_DONE 18 |
| 26 | #define MSG_ID_SYNC_TIMER1_DONE 19 |
| 27 | #define MSG_ID_SYNC_TIMER2_DONE 20 |
| 28 | #define MSG_ID_ASYNC_TIMER0_DONE 21 |
| 29 | #define MSG_ID_ASYNC_TIMER1_DONE 22 |
| 30 | #define MSG_ID_ASYNC_TIMER2_DONE 23 |
| 31 | #define MSG_ID_ASYNC_TIMER3_DONE 24 |
| 32 | #define MSG_ID_AE_OVERFLOW 25 |
| 33 | #define MSG_ID_AF_OVERFLOW 26 |
| 34 | #define MSG_ID_AWB_OVERFLOW 27 |
| 35 | #define MSG_ID_RS_OVERFLOW 28 |
| 36 | #define MSG_ID_CS_OVERFLOW 29 |
| 37 | #define MSG_ID_IHIST_OVERFLOW 30 |
| 38 | #define MSG_ID_SKIN_OVERFLOW 31 |
| 39 | #define MSG_ID_AXI_ERROR 32 |
| 40 | #define MSG_ID_CAMIF_OVERFLOW 33 |
| 41 | #define MSG_ID_VIOLATION 34 |
| 42 | #define MSG_ID_CAMIF_ERROR 35 |
| 43 | #define MSG_ID_BUS_OVERFLOW 36 |
| 44 | #define MSG_ID_SOF_ACK 37 |
| 45 | #define MSG_ID_STOP_REC_ACK 38 |
Suresh Vankadara | 055cb8e | 2012-01-18 00:50:04 +0530 | [diff] [blame] | 46 | #define MSG_ID_STATS_AWB_AEC 39 |
Kiran Kumar H N | dd12847 | 2011-12-01 09:35:34 -0800 | [diff] [blame] | 47 | #define MSG_ID_OUTPUT_PRIMARY 40 |
| 48 | #define MSG_ID_OUTPUT_SECONDARY 41 |
Shuzhen Wang | 7476824 | 2011-09-02 17:38:01 -0700 | [diff] [blame] | 49 | #define MSG_ID_STATS_COMPOSITE 42 |
Nishant Pandit | 28feb3d | 2012-04-26 23:56:22 +0530 | [diff] [blame] | 50 | #define MSG_ID_OUTPUT_TERTIARY1 43 |
Kiran Kumar H N | 1bc7b22 | 2012-06-23 16:28:11 -0700 | [diff] [blame] | 51 | #define MSG_ID_STOP_LS_ACK 44 |
Nishant Pandit | 5dd5442 | 2012-06-26 22:52:44 +0530 | [diff] [blame] | 52 | #define MSG_ID_OUTPUT_TERTIARY2 45 |
Lakshmi Narayana Kalavala | bc315ea | 2012-07-24 09:55:48 -0700 | [diff] [blame] | 53 | #define MSG_ID_STATS_BG 46 |
| 54 | #define MSG_ID_STATS_BF 47 |
| 55 | #define MSG_ID_STATS_BHIST 48 |
Shuzhen Wang | 196a27c | 2012-07-23 23:01:52 -0700 | [diff] [blame] | 56 | #define MSG_ID_RDI0_UPDATE_ACK 49 |
| 57 | #define MSG_ID_RDI1_UPDATE_ACK 50 |
| 58 | #define MSG_ID_RDI2_UPDATE_ACK 51 |
Nishant Pandit | d778571 | 2012-07-31 19:09:11 +0530 | [diff] [blame] | 59 | #define MSG_ID_PIX0_UPDATE_ACK 52 |
| 60 | #define MSG_ID_PREV_STOP_ACK 53 |
Peter Liu | efc1225 | 2012-09-13 12:19:13 -0700 | [diff] [blame] | 61 | #define MSG_ID_STATS_BE 54 |
Nishant Pandit | d778571 | 2012-07-31 19:09:11 +0530 | [diff] [blame] | 62 | |
Shuzhen Wang | ce65086 | 2011-08-17 15:27:01 -0700 | [diff] [blame] | 63 | |
| 64 | /* ISP command IDs */ |
| 65 | #define VFE_CMD_DUMMY_0 0 |
| 66 | #define VFE_CMD_SET_CLK 1 |
| 67 | #define VFE_CMD_RESET 2 |
| 68 | #define VFE_CMD_START 3 |
| 69 | #define VFE_CMD_TEST_GEN_START 4 |
| 70 | #define VFE_CMD_OPERATION_CFG 5 |
| 71 | #define VFE_CMD_AXI_OUT_CFG 6 |
| 72 | #define VFE_CMD_CAMIF_CFG 7 |
| 73 | #define VFE_CMD_AXI_INPUT_CFG 8 |
| 74 | #define VFE_CMD_BLACK_LEVEL_CFG 9 |
Ujwal Patel | edcbdcc | 2011-08-24 09:14:14 -0700 | [diff] [blame] | 75 | #define VFE_CMD_MESH_ROLL_OFF_CFG 10 |
Shuzhen Wang | ce65086 | 2011-08-17 15:27:01 -0700 | [diff] [blame] | 76 | #define VFE_CMD_DEMUX_CFG 11 |
| 77 | #define VFE_CMD_FOV_CFG 12 |
| 78 | #define VFE_CMD_MAIN_SCALER_CFG 13 |
| 79 | #define VFE_CMD_WB_CFG 14 |
| 80 | #define VFE_CMD_COLOR_COR_CFG 15 |
| 81 | #define VFE_CMD_RGB_G_CFG 16 |
| 82 | #define VFE_CMD_LA_CFG 17 |
| 83 | #define VFE_CMD_CHROMA_EN_CFG 18 |
| 84 | #define VFE_CMD_CHROMA_SUP_CFG 19 |
| 85 | #define VFE_CMD_MCE_CFG 20 |
| 86 | #define VFE_CMD_SK_ENHAN_CFG 21 |
| 87 | #define VFE_CMD_ASF_CFG 22 |
| 88 | #define VFE_CMD_S2Y_CFG 23 |
| 89 | #define VFE_CMD_S2CbCr_CFG 24 |
| 90 | #define VFE_CMD_CHROMA_SUBS_CFG 25 |
| 91 | #define VFE_CMD_OUT_CLAMP_CFG 26 |
| 92 | #define VFE_CMD_FRAME_SKIP_CFG 27 |
| 93 | #define VFE_CMD_DUMMY_1 28 |
| 94 | #define VFE_CMD_DUMMY_2 29 |
| 95 | #define VFE_CMD_DUMMY_3 30 |
| 96 | #define VFE_CMD_UPDATE 31 |
| 97 | #define VFE_CMD_BL_LVL_UPDATE 32 |
| 98 | #define VFE_CMD_DEMUX_UPDATE 33 |
| 99 | #define VFE_CMD_FOV_UPDATE 34 |
| 100 | #define VFE_CMD_MAIN_SCALER_UPDATE 35 |
| 101 | #define VFE_CMD_WB_UPDATE 36 |
| 102 | #define VFE_CMD_COLOR_COR_UPDATE 37 |
| 103 | #define VFE_CMD_RGB_G_UPDATE 38 |
| 104 | #define VFE_CMD_LA_UPDATE 39 |
| 105 | #define VFE_CMD_CHROMA_EN_UPDATE 40 |
| 106 | #define VFE_CMD_CHROMA_SUP_UPDATE 41 |
| 107 | #define VFE_CMD_MCE_UPDATE 42 |
| 108 | #define VFE_CMD_SK_ENHAN_UPDATE 43 |
| 109 | #define VFE_CMD_S2CbCr_UPDATE 44 |
| 110 | #define VFE_CMD_S2Y_UPDATE 45 |
| 111 | #define VFE_CMD_ASF_UPDATE 46 |
| 112 | #define VFE_CMD_FRAME_SKIP_UPDATE 47 |
| 113 | #define VFE_CMD_CAMIF_FRAME_UPDATE 48 |
| 114 | #define VFE_CMD_STATS_AF_UPDATE 49 |
| 115 | #define VFE_CMD_STATS_AE_UPDATE 50 |
| 116 | #define VFE_CMD_STATS_AWB_UPDATE 51 |
| 117 | #define VFE_CMD_STATS_RS_UPDATE 52 |
| 118 | #define VFE_CMD_STATS_CS_UPDATE 53 |
| 119 | #define VFE_CMD_STATS_SKIN_UPDATE 54 |
| 120 | #define VFE_CMD_STATS_IHIST_UPDATE 55 |
| 121 | #define VFE_CMD_DUMMY_4 56 |
| 122 | #define VFE_CMD_EPOCH1_ACK 57 |
| 123 | #define VFE_CMD_EPOCH2_ACK 58 |
| 124 | #define VFE_CMD_START_RECORDING 59 |
| 125 | #define VFE_CMD_STOP_RECORDING 60 |
| 126 | #define VFE_CMD_DUMMY_5 61 |
| 127 | #define VFE_CMD_DUMMY_6 62 |
| 128 | #define VFE_CMD_CAPTURE 63 |
| 129 | #define VFE_CMD_DUMMY_7 64 |
| 130 | #define VFE_CMD_STOP 65 |
| 131 | #define VFE_CMD_GET_HW_VERSION 66 |
| 132 | #define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 |
| 133 | #define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 |
| 134 | #define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 |
| 135 | #define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 |
| 136 | #define VFE_CMD_JPEG_OUT_BUF_ENQ 71 |
| 137 | #define VFE_CMD_RAW_OUT_BUF_ENQ 72 |
| 138 | #define VFE_CMD_RAW_IN_BUF_ENQ 73 |
| 139 | #define VFE_CMD_STATS_AF_ENQ 74 |
| 140 | #define VFE_CMD_STATS_AE_ENQ 75 |
| 141 | #define VFE_CMD_STATS_AWB_ENQ 76 |
| 142 | #define VFE_CMD_STATS_RS_ENQ 77 |
| 143 | #define VFE_CMD_STATS_CS_ENQ 78 |
| 144 | #define VFE_CMD_STATS_SKIN_ENQ 79 |
| 145 | #define VFE_CMD_STATS_IHIST_ENQ 80 |
| 146 | #define VFE_CMD_DUMMY_8 81 |
| 147 | #define VFE_CMD_JPEG_ENC_CFG 82 |
| 148 | #define VFE_CMD_DUMMY_9 83 |
| 149 | #define VFE_CMD_STATS_AF_START 84 |
| 150 | #define VFE_CMD_STATS_AF_STOP 85 |
| 151 | #define VFE_CMD_STATS_AE_START 86 |
| 152 | #define VFE_CMD_STATS_AE_STOP 87 |
| 153 | #define VFE_CMD_STATS_AWB_START 88 |
| 154 | #define VFE_CMD_STATS_AWB_STOP 89 |
| 155 | #define VFE_CMD_STATS_RS_START 90 |
| 156 | #define VFE_CMD_STATS_RS_STOP 91 |
| 157 | #define VFE_CMD_STATS_CS_START 92 |
| 158 | #define VFE_CMD_STATS_CS_STOP 93 |
| 159 | #define VFE_CMD_STATS_SKIN_START 94 |
| 160 | #define VFE_CMD_STATS_SKIN_STOP 95 |
| 161 | #define VFE_CMD_STATS_IHIST_START 96 |
| 162 | #define VFE_CMD_STATS_IHIST_STOP 97 |
| 163 | #define VFE_CMD_DUMMY_10 98 |
| 164 | #define VFE_CMD_SYNC_TIMER_SETTING 99 |
| 165 | #define VFE_CMD_ASYNC_TIMER_SETTING 100 |
| 166 | #define VFE_CMD_LIVESHOT 101 |
| 167 | #define VFE_CMD_LA_SETUP 102 |
| 168 | #define VFE_CMD_LINEARIZATION_CFG 103 |
| 169 | #define VFE_CMD_DEMOSAICV3 104 |
| 170 | #define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 |
| 171 | #define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 |
| 172 | #define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 |
| 173 | #define VFE_CMD_DEMOSAICV3_ABF_CFG 108 |
| 174 | #define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 |
| 175 | #define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 |
| 176 | #define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 |
| 177 | #define VFE_CMD_XBAR_CFG 112 |
Ujwal Patel | 1fe4c9c | 2011-10-07 12:19:52 -0700 | [diff] [blame] | 178 | #define VFE_CMD_MODULE_CFG 113 |
Shuzhen Wang | ce65086 | 2011-08-17 15:27:01 -0700 | [diff] [blame] | 179 | #define VFE_CMD_ZSL 114 |
| 180 | #define VFE_CMD_LINEARIZATION_UPDATE 115 |
| 181 | #define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 |
| 182 | #define VFE_CMD_CLF_CFG 117 |
| 183 | #define VFE_CMD_CLF_LUMA_UPDATE 118 |
| 184 | #define VFE_CMD_CLF_CHROMA_UPDATE 119 |
Ujwal Patel | edcbdcc | 2011-08-24 09:14:14 -0700 | [diff] [blame] | 185 | #define VFE_CMD_PCA_ROLL_OFF_CFG 120 |
| 186 | #define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 |
Ujwal Patel | 6e4308d | 2011-10-25 11:24:52 -0700 | [diff] [blame] | 187 | #define VFE_CMD_GET_REG_DUMP 122 |
| 188 | #define VFE_CMD_GET_LINEARIZATON_TABLE 123 |
| 189 | #define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 |
| 190 | #define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 |
| 191 | #define VFE_CMD_GET_RGB_G_TABLE 126 |
| 192 | #define VFE_CMD_GET_LA_TABLE 127 |
Azam Sadiq Pasha Kapatrala Syed | 5156dd4 | 2011-10-27 19:30:13 -0700 | [diff] [blame] | 193 | #define VFE_CMD_DEMOSAICV3_UPDATE 128 |
Suresh Vankadara | 055cb8e | 2012-01-18 00:50:04 +0530 | [diff] [blame] | 194 | #define VFE_CMD_ACTIVE_REGION_CFG 129 |
| 195 | #define VFE_CMD_COLOR_PROCESSING_CONFIG 130 |
| 196 | #define VFE_CMD_STATS_WB_AEC_CONFIG 131 |
| 197 | #define VFE_CMD_STATS_WB_AEC_UPDATE 132 |
| 198 | #define VFE_CMD_Y_GAMMA_CONFIG 133 |
| 199 | #define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 |
| 200 | #define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 |
Kiran Kumar H N | dd12847 | 2011-12-01 09:35:34 -0800 | [diff] [blame] | 201 | #define VFE_CMD_CAPTURE_RAW 136 |
| 202 | #define VFE_CMD_STOP_LIVESHOT 137 |
Sandeep Kodimela | c6f7867 | 2012-03-07 10:44:04 +0530 | [diff] [blame] | 203 | #define VFE_CMD_RECONFIG_VFE 138 |
Lakshmi Narayana Kalavala | 2db3384 | 2012-06-26 22:41:32 -0700 | [diff] [blame] | 204 | #define VFE_CMD_STATS_REQBUF 139 |
| 205 | #define VFE_CMD_STATS_ENQUEUEBUF 140 |
| 206 | #define VFE_CMD_STATS_FLUSH_BUFQ 141 |
Lakshmi Narayana Kalavala | 58243db | 2012-07-24 00:06:27 -0700 | [diff] [blame] | 207 | #define VFE_CMD_STATS_UNREGBUF 142 |
Lakshmi Narayana Kalavala | bc315ea | 2012-07-24 09:55:48 -0700 | [diff] [blame] | 208 | #define VFE_CMD_STATS_BG_START 143 |
| 209 | #define VFE_CMD_STATS_BG_STOP 144 |
| 210 | #define VFE_CMD_STATS_BF_START 145 |
| 211 | #define VFE_CMD_STATS_BF_STOP 146 |
| 212 | #define VFE_CMD_STATS_BHIST_START 147 |
| 213 | #define VFE_CMD_STATS_BHIST_STOP 148 |
Shuzhen Wang | 5c190ad | 2012-07-09 16:30:51 -0700 | [diff] [blame] | 214 | #define VFE_CMD_RESET_2 149 |
Kevin Chan | 9943057 | 2012-07-22 02:23:43 -0700 | [diff] [blame] | 215 | #define VFE_CMD_FOV_ENC_CFG 150 |
| 216 | #define VFE_CMD_FOV_VIEW_CFG 151 |
| 217 | #define VFE_CMD_FOV_ENC_UPDATE 152 |
| 218 | #define VFE_CMD_FOV_VIEW_UPDATE 153 |
| 219 | #define VFE_CMD_SCALER_ENC_CFG 154 |
| 220 | #define VFE_CMD_SCALER_VIEW_CFG 155 |
| 221 | #define VFE_CMD_SCALER_ENC_UPDATE 156 |
| 222 | #define VFE_CMD_SCALER_VIEW_UPDATE 157 |
| 223 | #define VFE_CMD_COLORXFORM_ENC_CFG 158 |
| 224 | #define VFE_CMD_COLORXFORM_VIEW_CFG 159 |
| 225 | #define VFE_CMD_COLORXFORM_ENC_UPDATE 160 |
| 226 | #define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 |
| 227 | #define VFE_CMD_TEST_GEN_CFG 162 |
Peter Liu | efc1225 | 2012-09-13 12:19:13 -0700 | [diff] [blame] | 228 | #define VFE_CMD_STATS_BE_START 163 |
| 229 | #define VFE_CMD_STATS_BE_STOP 164 |
Shuzhen Wang | 6b0f332 | 2011-08-26 12:14:43 -0700 | [diff] [blame] | 230 | struct msm_isp_cmd { |
| 231 | int32_t id; |
| 232 | uint16_t length; |
| 233 | void *value; |
| 234 | }; |
| 235 | |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 236 | #define VPE_CMD_DUMMY_0 0 |
| 237 | #define VPE_CMD_INIT 1 |
| 238 | #define VPE_CMD_DEINIT 2 |
| 239 | #define VPE_CMD_ENABLE 3 |
| 240 | #define VPE_CMD_DISABLE 4 |
| 241 | #define VPE_CMD_RESET 5 |
| 242 | #define VPE_CMD_FLUSH 6 |
| 243 | #define VPE_CMD_OPERATION_MODE_CFG 7 |
| 244 | #define VPE_CMD_INPUT_PLANE_CFG 8 |
| 245 | #define VPE_CMD_OUTPUT_PLANE_CFG 9 |
| 246 | #define VPE_CMD_INPUT_PLANE_UPDATE 10 |
| 247 | #define VPE_CMD_SCALE_CFG_TYPE 11 |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 248 | #define VPE_CMD_ZOOM 13 |
Kevin Chan | 318d7cb | 2011-11-29 14:24:26 -0800 | [diff] [blame] | 249 | #define VPE_CMD_MAX 14 |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 250 | |
| 251 | #define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ |
| 252 | #define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ |
| 253 | #define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ |
| 254 | |
| 255 | #define MCTL_CMD_DUMMY_0 0 /* not used */ |
| 256 | #define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ |
| 257 | #define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ |
| 258 | #define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 259 | |
| 260 | /* event typese sending to MCTL PP module */ |
| 261 | #define MCTL_PP_EVENT_NOTUSED 0 |
| 262 | #define MCTL_PP_EVENT_CMD_ACK 1 |
| 263 | |
Kiran Kumar H N | 8f68c59 | 2012-01-06 15:11:47 -0800 | [diff] [blame] | 264 | #define VPE_OPERATION_MODE_CFG_LEN 4 |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 265 | #define VPE_INPUT_PLANE_CFG_LEN 24 |
Kiran Kumar H N | 8f68c59 | 2012-01-06 15:11:47 -0800 | [diff] [blame] | 266 | #define VPE_OUTPUT_PLANE_CFG_LEN 20 |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 267 | #define VPE_INPUT_PLANE_UPDATE_LEN 12 |
| 268 | #define VPE_SCALER_CONFIG_LEN 260 |
| 269 | #define VPE_DIS_OFFSET_CFG_LEN 12 |
| 270 | |
Jignesh Mehta | bde8424 | 2012-02-16 13:21:22 -0800 | [diff] [blame] | 271 | |
| 272 | #define CAPTURE_WIDTH 1280 |
| 273 | #define IMEM_Y_SIZE (CAPTURE_WIDTH*16) |
| 274 | #define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) |
| 275 | |
| 276 | #define IMEM_Y_PING_OFFSET 0x2E000000 |
| 277 | #define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) |
| 278 | |
| 279 | #define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) |
| 280 | #define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) |
| 281 | |
Jignesh Mehta | 6cf8a74 | 2012-02-04 23:40:50 -0800 | [diff] [blame] | 282 | |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 283 | struct msm_vpe_op_mode_cfg { |
| 284 | uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; |
| 285 | }; |
| 286 | |
| 287 | struct msm_vpe_input_plane_cfg { |
| 288 | uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; |
| 289 | }; |
| 290 | |
| 291 | struct msm_vpe_output_plane_cfg { |
| 292 | uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; |
| 293 | }; |
| 294 | |
| 295 | struct msm_vpe_input_plane_update_cfg { |
| 296 | uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; |
| 297 | }; |
| 298 | |
| 299 | struct msm_vpe_scaler_cfg { |
| 300 | uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; |
| 301 | }; |
| 302 | |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 303 | struct msm_vpe_flush_frame_buffer { |
| 304 | uint32_t src_buf_handle; |
| 305 | uint32_t dest_buf_handle; |
| 306 | int path; |
| 307 | }; |
| 308 | |
| 309 | struct msm_mctl_pp_frame_buffer { |
| 310 | uint32_t buf_handle; |
| 311 | int path; |
| 312 | }; |
| 313 | struct msm_mctl_pp_divert_pp { |
| 314 | int path; |
Mingcheng Zhu | 8feaa3f | 2011-11-23 11:33:52 -0800 | [diff] [blame] | 315 | int enable; |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 316 | }; |
| 317 | struct msm_vpe_clock_rate { |
| 318 | uint32_t rate; |
| 319 | }; |
Kiran Kumar H N | 2e68e33 | 2012-08-07 21:07:30 -0700 | [diff] [blame] | 320 | |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 321 | #define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) |
| 322 | #define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) |
| 323 | |
Nishant Pandit | 5dd5442 | 2012-06-26 22:52:44 +0530 | [diff] [blame] | 324 | #define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) |
| 325 | #define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) |
| 326 | #define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) |
| 327 | #define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) |
| 328 | #define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) |
| 329 | #define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) |
| 330 | #define VFE_OUTPUTS_PREVIEW BIT(6) |
| 331 | #define VFE_OUTPUTS_VIDEO BIT(7) |
| 332 | #define VFE_OUTPUTS_RAW BIT(8) |
| 333 | #define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) |
| 334 | #define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) |
| 335 | #define VFE_OUTPUTS_RDI0 BIT(11) |
| 336 | #define VFE_OUTPUTS_RDI1 BIT(12) |
Kiran Kumar H N | dd12847 | 2011-12-01 09:35:34 -0800 | [diff] [blame] | 337 | |
Kevin Chan | 2df27e6 | 2012-06-15 00:06:54 -0700 | [diff] [blame] | 338 | struct msm_frame_info { |
Kiran Kumar H N | 9078590 | 2012-07-05 13:59:38 -0700 | [diff] [blame] | 339 | uint32_t inst_handle; |
Kevin Chan | 2df27e6 | 2012-06-15 00:06:54 -0700 | [diff] [blame] | 340 | uint32_t path; |
| 341 | }; |
| 342 | |
Mingcheng Zhu | 8e9f99e | 2011-08-26 16:33:32 -0700 | [diff] [blame] | 343 | #endif /*__MSM_ISP_H__*/ |
| 344 | |