Tianyi Gou | c1e049f8 | 2011-11-23 14:20:16 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/elf.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/iopoll.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/regulator/consumer.h> |
| 25 | |
| 26 | #include "peripheral-loader.h" |
| 27 | #include "scm-pas.h" |
| 28 | |
| 29 | #define PRONTO_PMU_COMMON_GDSCR 0x24 |
| 30 | #define PRONTO_PMU_COMMON_GDSCR_SW_COLLAPSE BIT(0) |
| 31 | #define CLK_DIS_WAIT 12 |
| 32 | #define EN_FEW_WAIT 16 |
| 33 | #define EN_REST_WAIT 20 |
| 34 | |
| 35 | #define PRONTO_PMU_COMMON_CPU_CBCR 0x30 |
| 36 | #define PRONTO_PMU_COMMON_CPU_CBCR_CLK_EN BIT(0) |
| 37 | #define PRONTO_PMU_COMMON_CPU_CLK_OFF BIT(31) |
| 38 | |
| 39 | #define PRONTO_PMU_COMMON_AHB_CBCR 0x34 |
| 40 | #define PRONTO_PMU_COMMON_AHB_CBCR_CLK_EN BIT(0) |
| 41 | #define PRONTO_PMU_COMMON_AHB_CLK_OFF BIT(31) |
| 42 | |
| 43 | #define PRONTO_PMU_COMMON_CSR 0x1040 |
| 44 | #define PRONTO_PMU_COMMON_CSR_A2XB_CFG_EN BIT(0) |
| 45 | |
| 46 | #define PRONTO_PMU_SOFT_RESET 0x104C |
| 47 | #define PRONTO_PMU_SOFT_RESET_CRCM_CCPU_SOFT_RESET BIT(10) |
| 48 | |
| 49 | #define PRONTO_PMU_CCPU_CTL 0x2000 |
| 50 | #define PRONTO_PMU_CCPU_CTL_REMAP_EN BIT(2) |
| 51 | #define PRONTO_PMU_CCPU_CTL_HIGH_IVT BIT(0) |
| 52 | |
| 53 | #define PRONTO_PMU_CCPU_BOOT_REMAP_ADDR 0x2004 |
| 54 | |
| 55 | #define CLK_CTL_WCNSS_RESTART_BIT BIT(0) |
| 56 | |
| 57 | #define AXI_HALTREQ 0x0 |
| 58 | #define AXI_HALTACK 0x4 |
| 59 | #define AXI_IDLE 0x8 |
| 60 | |
| 61 | #define HALT_ACK_TIMEOUT_US 500000 |
| 62 | #define CLK_UPDATE_TIMEOUT_US 500000 |
| 63 | |
| 64 | struct pronto_data { |
| 65 | void __iomem *base; |
| 66 | void __iomem *reset_base; |
| 67 | void __iomem *axi_halt_base; |
| 68 | unsigned long start_addr; |
| 69 | struct pil_device *pil; |
| 70 | struct clk *cxo; |
| 71 | struct regulator *vreg; |
| 72 | }; |
| 73 | |
| 74 | static int pil_pronto_make_proxy_vote(struct pil_desc *pil) |
| 75 | { |
| 76 | struct pronto_data *drv = dev_get_drvdata(pil->dev); |
| 77 | int ret; |
| 78 | |
| 79 | ret = regulator_enable(drv->vreg); |
| 80 | if (ret) { |
| 81 | dev_err(pil->dev, "failed to enable pll supply\n"); |
| 82 | goto err; |
| 83 | } |
| 84 | ret = clk_prepare_enable(drv->cxo); |
| 85 | if (ret) { |
| 86 | dev_err(pil->dev, "failed to enable cxo\n"); |
| 87 | goto err_clk; |
| 88 | } |
| 89 | return 0; |
| 90 | err_clk: |
| 91 | regulator_disable(drv->vreg); |
| 92 | err: |
| 93 | return ret; |
| 94 | } |
| 95 | |
| 96 | static void pil_pronto_remove_proxy_vote(struct pil_desc *pil) |
| 97 | { |
| 98 | struct pronto_data *drv = dev_get_drvdata(pil->dev); |
| 99 | regulator_disable(drv->vreg); |
| 100 | clk_disable_unprepare(drv->cxo); |
| 101 | } |
| 102 | |
| 103 | static int pil_pronto_init_image(struct pil_desc *pil, const u8 *metadata, |
| 104 | size_t size) |
| 105 | { |
| 106 | const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata; |
| 107 | struct pronto_data *drv = dev_get_drvdata(pil->dev); |
| 108 | drv->start_addr = ehdr->e_entry; |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | static int pil_pronto_reset(struct pil_desc *pil) |
| 113 | { |
| 114 | u32 reg; |
| 115 | int rc; |
| 116 | struct pronto_data *drv = dev_get_drvdata(pil->dev); |
| 117 | void __iomem *base = drv->base; |
| 118 | unsigned long start_addr = drv->start_addr; |
| 119 | |
Matt Wagantall | 33c2ec7 | 2012-07-26 20:26:57 -0700 | [diff] [blame] | 120 | /* Deassert reset to subsystem and wait for propagation */ |
Tianyi Gou | c1e049f8 | 2011-11-23 14:20:16 -0800 | [diff] [blame] | 121 | reg = readl_relaxed(drv->reset_base); |
| 122 | reg &= ~CLK_CTL_WCNSS_RESTART_BIT; |
| 123 | writel_relaxed(reg, drv->reset_base); |
| 124 | mb(); |
Matt Wagantall | 33c2ec7 | 2012-07-26 20:26:57 -0700 | [diff] [blame] | 125 | udelay(2); |
Tianyi Gou | c1e049f8 | 2011-11-23 14:20:16 -0800 | [diff] [blame] | 126 | |
| 127 | /* Configure boot address */ |
| 128 | writel_relaxed(start_addr >> 16, base + |
| 129 | PRONTO_PMU_CCPU_BOOT_REMAP_ADDR); |
| 130 | |
| 131 | /* Use the high vector table */ |
| 132 | reg = readl_relaxed(base + PRONTO_PMU_CCPU_CTL); |
| 133 | reg |= PRONTO_PMU_CCPU_CTL_REMAP_EN | PRONTO_PMU_CCPU_CTL_HIGH_IVT; |
| 134 | writel_relaxed(reg, base + PRONTO_PMU_CCPU_CTL); |
| 135 | |
| 136 | /* Turn on AHB clock of common_ss */ |
| 137 | reg = readl_relaxed(base + PRONTO_PMU_COMMON_AHB_CBCR); |
| 138 | reg |= PRONTO_PMU_COMMON_AHB_CBCR_CLK_EN; |
| 139 | writel_relaxed(reg, base + PRONTO_PMU_COMMON_AHB_CBCR); |
| 140 | |
| 141 | /* Turn on CPU clock of common_ss */ |
| 142 | reg = readl_relaxed(base + PRONTO_PMU_COMMON_CPU_CBCR); |
| 143 | reg |= PRONTO_PMU_COMMON_CPU_CBCR_CLK_EN; |
| 144 | writel_relaxed(reg, base + PRONTO_PMU_COMMON_CPU_CBCR); |
| 145 | |
| 146 | /* Enable A2XB bridge */ |
| 147 | reg = readl_relaxed(base + PRONTO_PMU_COMMON_CSR); |
| 148 | reg |= PRONTO_PMU_COMMON_CSR_A2XB_CFG_EN; |
| 149 | writel_relaxed(reg, base + PRONTO_PMU_COMMON_CSR); |
| 150 | |
| 151 | /* Enable common_ss power */ |
| 152 | reg = readl_relaxed(base + PRONTO_PMU_COMMON_GDSCR); |
| 153 | reg &= ~PRONTO_PMU_COMMON_GDSCR_SW_COLLAPSE; |
| 154 | writel_relaxed(reg, base + PRONTO_PMU_COMMON_GDSCR); |
| 155 | |
| 156 | /* Wait for AHB clock to be on */ |
| 157 | rc = readl_tight_poll_timeout(base + PRONTO_PMU_COMMON_AHB_CBCR, |
| 158 | reg, |
| 159 | !(reg & PRONTO_PMU_COMMON_AHB_CLK_OFF), |
| 160 | CLK_UPDATE_TIMEOUT_US); |
| 161 | if (rc) { |
| 162 | dev_err(pil->dev, "pronto common ahb clk enable timeout\n"); |
| 163 | return rc; |
| 164 | } |
| 165 | |
| 166 | /* Wait for CPU clock to be on */ |
| 167 | rc = readl_tight_poll_timeout(base + PRONTO_PMU_COMMON_CPU_CBCR, |
| 168 | reg, |
| 169 | !(reg & PRONTO_PMU_COMMON_CPU_CLK_OFF), |
| 170 | CLK_UPDATE_TIMEOUT_US); |
| 171 | if (rc) { |
| 172 | dev_err(pil->dev, "pronto common cpu clk enable timeout\n"); |
| 173 | return rc; |
| 174 | } |
| 175 | |
| 176 | /* Deassert ARM9 software reset */ |
| 177 | reg = readl_relaxed(base + PRONTO_PMU_SOFT_RESET); |
| 178 | reg &= ~PRONTO_PMU_SOFT_RESET_CRCM_CCPU_SOFT_RESET; |
| 179 | writel_relaxed(reg, base + PRONTO_PMU_SOFT_RESET); |
| 180 | |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | static int pil_pronto_shutdown(struct pil_desc *pil) |
| 185 | { |
| 186 | struct pronto_data *drv = dev_get_drvdata(pil->dev); |
| 187 | int ret; |
| 188 | u32 reg, status; |
| 189 | |
| 190 | /* Halt A2XB */ |
| 191 | writel_relaxed(1, drv->axi_halt_base + AXI_HALTREQ); |
| 192 | ret = readl_poll_timeout(drv->axi_halt_base + AXI_HALTACK, |
| 193 | status, status, 50, HALT_ACK_TIMEOUT_US); |
| 194 | if (ret) |
| 195 | dev_err(pil->dev, "Port halt timeout\n"); |
| 196 | else if (!readl_relaxed(drv->axi_halt_base + AXI_IDLE)) |
| 197 | dev_err(pil->dev, "Port halt failed\n"); |
| 198 | |
| 199 | writel_relaxed(0, drv->axi_halt_base + AXI_HALTREQ); |
| 200 | |
| 201 | /* Assert reset to Pronto */ |
| 202 | reg = readl_relaxed(drv->reset_base); |
| 203 | reg |= CLK_CTL_WCNSS_RESTART_BIT; |
| 204 | writel_relaxed(reg, drv->reset_base); |
| 205 | |
| 206 | /* Wait for reset to complete */ |
| 207 | mb(); |
| 208 | usleep_range(1000, 2000); |
| 209 | |
Matt Wagantall | 44131df | 2012-08-03 18:29:47 -0700 | [diff] [blame^] | 210 | /* Deassert reset to subsystem and wait for propagation */ |
Tianyi Gou | c1e049f8 | 2011-11-23 14:20:16 -0800 | [diff] [blame] | 211 | reg = readl_relaxed(drv->reset_base); |
| 212 | reg &= ~CLK_CTL_WCNSS_RESTART_BIT; |
| 213 | writel_relaxed(reg, drv->reset_base); |
| 214 | mb(); |
Matt Wagantall | 44131df | 2012-08-03 18:29:47 -0700 | [diff] [blame^] | 215 | udelay(2); |
Tianyi Gou | c1e049f8 | 2011-11-23 14:20:16 -0800 | [diff] [blame] | 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static struct pil_reset_ops pil_pronto_ops = { |
| 221 | .init_image = pil_pronto_init_image, |
| 222 | .auth_and_reset = pil_pronto_reset, |
| 223 | .shutdown = pil_pronto_shutdown, |
| 224 | .proxy_vote = pil_pronto_make_proxy_vote, |
| 225 | .proxy_unvote = pil_pronto_remove_proxy_vote, |
| 226 | }; |
| 227 | |
| 228 | static int __devinit pil_pronto_probe(struct platform_device *pdev) |
| 229 | { |
| 230 | struct pronto_data *drv; |
| 231 | struct resource *res; |
| 232 | struct pil_desc *desc; |
| 233 | int ret; |
| 234 | uint32_t regval; |
| 235 | |
| 236 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 237 | if (!res) |
| 238 | return -EINVAL; |
| 239 | |
| 240 | drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); |
| 241 | if (!drv) |
| 242 | return -ENOMEM; |
| 243 | platform_set_drvdata(pdev, drv); |
| 244 | |
| 245 | drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
| 246 | if (!drv->base) |
| 247 | return -ENOMEM; |
| 248 | |
| 249 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 250 | if (!res) |
| 251 | return -EINVAL; |
| 252 | |
| 253 | drv->reset_base = devm_ioremap(&pdev->dev, res->start, |
| 254 | resource_size(res)); |
| 255 | |
| 256 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
| 257 | if (!res) |
| 258 | return -EINVAL; |
| 259 | |
| 260 | drv->axi_halt_base = devm_ioremap(&pdev->dev, res->start, |
| 261 | resource_size(res)); |
| 262 | |
| 263 | desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL); |
| 264 | if (!desc) |
| 265 | return -ENOMEM; |
| 266 | |
| 267 | ret = of_property_read_string(pdev->dev.of_node, "qcom,firmware-name", |
| 268 | &desc->name); |
| 269 | if (ret) |
| 270 | return ret; |
| 271 | |
| 272 | desc->dev = &pdev->dev; |
| 273 | desc->owner = THIS_MODULE; |
| 274 | desc->proxy_timeout = 10000; |
| 275 | |
| 276 | /* TODO: need to add secure boot when the support is available */ |
| 277 | desc->ops = &pil_pronto_ops; |
| 278 | dev_info(&pdev->dev, "using non-secure boot\n"); |
| 279 | |
| 280 | drv->vreg = devm_regulator_get(&pdev->dev, "vdd_pronto_pll"); |
| 281 | if (IS_ERR(drv->vreg)) { |
| 282 | dev_err(&pdev->dev, "failed to get pronto pll supply"); |
| 283 | return PTR_ERR(drv->vreg); |
| 284 | } |
| 285 | |
| 286 | ret = regulator_set_voltage(drv->vreg, 1800000, 1800000); |
| 287 | if (ret) { |
| 288 | dev_err(&pdev->dev, "failed to set pll supply voltage\n"); |
| 289 | return ret; |
| 290 | } |
| 291 | |
| 292 | ret = regulator_set_optimum_mode(drv->vreg, 18000); |
| 293 | if (ret < 0) { |
| 294 | dev_err(&pdev->dev, "failed to set pll supply mode\n"); |
| 295 | return ret; |
| 296 | } |
| 297 | |
| 298 | drv->cxo = devm_clk_get(&pdev->dev, "xo"); |
| 299 | if (IS_ERR(drv->cxo)) |
| 300 | return PTR_ERR(drv->cxo); |
| 301 | |
| 302 | drv->pil = msm_pil_register(desc); |
| 303 | if (IS_ERR(drv->pil)) |
| 304 | return PTR_ERR(drv->pil); |
| 305 | |
| 306 | /* Initialize common_ss GDSCR to wait 4 cycles between states */ |
| 307 | regval = readl_relaxed(drv->base + PRONTO_PMU_COMMON_GDSCR) |
| 308 | & PRONTO_PMU_COMMON_GDSCR_SW_COLLAPSE; |
| 309 | regval |= (2 << EN_REST_WAIT) | (2 << EN_FEW_WAIT) |
| 310 | | (2 << CLK_DIS_WAIT); |
| 311 | writel_relaxed(regval, drv->base + PRONTO_PMU_COMMON_GDSCR); |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static int __devexit pil_pronto_remove(struct platform_device *pdev) |
| 317 | { |
| 318 | struct pronto_data *drv = platform_get_drvdata(pdev); |
| 319 | msm_pil_unregister(drv->pil); |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | static struct of_device_id msm_pil_pronto_match[] = { |
| 324 | {.compatible = "qcom,pil-pronto"}, |
| 325 | {} |
| 326 | }; |
| 327 | |
| 328 | static struct platform_driver pil_pronto_driver = { |
| 329 | .probe = pil_pronto_probe, |
| 330 | .remove = __devexit_p(pil_pronto_remove), |
| 331 | .driver = { |
| 332 | .name = "pil_pronto", |
| 333 | .owner = THIS_MODULE, |
| 334 | .of_match_table = msm_pil_pronto_match, |
| 335 | }, |
| 336 | }; |
| 337 | |
| 338 | static int __init pil_pronto_init(void) |
| 339 | { |
| 340 | return platform_driver_register(&pil_pronto_driver); |
| 341 | } |
| 342 | module_init(pil_pronto_init); |
| 343 | |
| 344 | static void __exit pil_pronto_exit(void) |
| 345 | { |
| 346 | platform_driver_unregister(&pil_pronto_driver); |
| 347 | } |
| 348 | module_exit(pil_pronto_exit); |
| 349 | |
| 350 | MODULE_DESCRIPTION("Support for booting PRONTO (WCNSS) processors"); |
| 351 | MODULE_LICENSE("GPL v2"); |