Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1 | /* bnx2x.h: Broadcom Everest network driver. |
| 2 | * |
Dmitry Kravkov | 5de9240 | 2011-05-04 23:51:13 +0000 | [diff] [blame] | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
Eilon Greenstein | 24e3fce | 2008-06-12 14:30:28 -0700 | [diff] [blame] | 9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
| 10 | * Written by: Eliezer Tamir |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11 | * Based on code from Michael Chan's bnx2 driver |
| 12 | */ |
| 13 | |
| 14 | #ifndef BNX2X_H |
| 15 | #define BNX2X_H |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 16 | #include <linux/netdevice.h> |
| 17 | #include <linux/types.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 18 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 19 | /* compilation time flags */ |
| 20 | |
| 21 | /* define this to make the driver freeze on error to allow getting debug info |
| 22 | * (you will need to reboot afterwards) */ |
| 23 | /* #define BNX2X_STOP_ON_ERROR */ |
| 24 | |
Dmitry Kravkov | 5de9240 | 2011-05-04 23:51:13 +0000 | [diff] [blame] | 25 | #define DRV_MODULE_VERSION "1.62.12-0" |
| 26 | #define DRV_MODULE_RELDATE "2011/03/20" |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 27 | #define BNX2X_BC_VER 0x040200 |
| 28 | |
Eilon Greenstein | 555f6c7 | 2009-02-12 08:36:11 +0000 | [diff] [blame] | 29 | #define BNX2X_MULTI_QUEUE |
| 30 | |
| 31 | #define BNX2X_NEW_NAPI |
| 32 | |
Shmulik Ravid | 785b9b1 | 2010-12-30 06:27:03 +0000 | [diff] [blame] | 33 | #if defined(CONFIG_DCB) |
Shmulik Ravid | 9850767 | 2011-02-28 12:19:55 -0800 | [diff] [blame] | 34 | #define BCM_DCBNL |
Shmulik Ravid | 785b9b1 | 2010-12-30 06:27:03 +0000 | [diff] [blame] | 35 | #endif |
Vladislav Zolotarov | 1ac218c | 2010-04-19 01:14:18 +0000 | [diff] [blame] | 36 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
| 37 | #define BCM_CNIC 1 |
Dmitry Kravkov | 5d1e859 | 2010-07-27 12:31:10 +0000 | [diff] [blame] | 38 | #include "../cnic_if.h" |
Vladislav Zolotarov | 1ac218c | 2010-04-19 01:14:18 +0000 | [diff] [blame] | 39 | #endif |
| 40 | |
Vladislav Zolotarov | 1ac218c | 2010-04-19 01:14:18 +0000 | [diff] [blame] | 41 | #ifdef BCM_CNIC |
| 42 | #define BNX2X_MIN_MSIX_VEC_CNT 3 |
| 43 | #define BNX2X_MSIX_VEC_FP_START 2 |
| 44 | #else |
| 45 | #define BNX2X_MIN_MSIX_VEC_CNT 2 |
| 46 | #define BNX2X_MSIX_VEC_FP_START 1 |
| 47 | #endif |
| 48 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 49 | #include <linux/mdio.h> |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 50 | #include <linux/pci.h> |
Eilon Greenstein | 359d8b1 | 2009-02-12 08:38:25 +0000 | [diff] [blame] | 51 | #include "bnx2x_reg.h" |
| 52 | #include "bnx2x_fw_defs.h" |
| 53 | #include "bnx2x_hsi.h" |
| 54 | #include "bnx2x_link.h" |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 55 | #include "bnx2x_dcb.h" |
Dmitry Kravkov | 6c719d0 | 2010-07-27 12:36:15 +0000 | [diff] [blame] | 56 | #include "bnx2x_stats.h" |
Eilon Greenstein | 359d8b1 | 2009-02-12 08:38:25 +0000 | [diff] [blame] | 57 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 58 | /* error/debug prints */ |
| 59 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 60 | #define DRV_MODULE_NAME "bnx2x" |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 61 | |
| 62 | /* for messages that are currently off */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 63 | #define BNX2X_MSG_OFF 0 |
| 64 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ |
| 65 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ |
| 66 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ |
| 67 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 68 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
| 69 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 70 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 71 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 72 | |
| 73 | /* regular debug print */ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 74 | #define DP(__mask, __fmt, __args...) \ |
| 75 | do { \ |
| 76 | if (bp->msg_enable & (__mask)) \ |
| 77 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ |
| 78 | __func__, __LINE__, \ |
| 79 | bp->dev ? (bp->dev->name) : "?", \ |
| 80 | ##__args); \ |
| 81 | } while (0) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 82 | |
| 83 | /* errors debug print */ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 84 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
| 85 | do { \ |
| 86 | if (netif_msg_probe(bp)) \ |
| 87 | pr_err("[%s:%d(%s)]" __fmt, \ |
| 88 | __func__, __LINE__, \ |
| 89 | bp->dev ? (bp->dev->name) : "?", \ |
| 90 | ##__args); \ |
| 91 | } while (0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 92 | |
| 93 | /* for errors (never masked) */ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 94 | #define BNX2X_ERR(__fmt, __args...) \ |
| 95 | do { \ |
| 96 | pr_err("[%s:%d(%s)]" __fmt, \ |
| 97 | __func__, __LINE__, \ |
| 98 | bp->dev ? (bp->dev->name) : "?", \ |
| 99 | ##__args); \ |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 100 | } while (0) |
| 101 | |
| 102 | #define BNX2X_ERROR(__fmt, __args...) do { \ |
| 103 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ |
| 104 | } while (0) |
| 105 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 106 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 107 | /* before we have a dev->name use dev_info() */ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 108 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
| 109 | do { \ |
| 110 | if (netif_msg_probe(bp)) \ |
| 111 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ |
| 112 | } while (0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 113 | |
Dmitry Kravkov | 6c719d0 | 2010-07-27 12:36:15 +0000 | [diff] [blame] | 114 | void bnx2x_panic_dump(struct bnx2x *bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 115 | |
| 116 | #ifdef BNX2X_STOP_ON_ERROR |
| 117 | #define bnx2x_panic() do { \ |
| 118 | bp->panic = 1; \ |
| 119 | BNX2X_ERR("driver assert\n"); \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 120 | bnx2x_int_disable(bp); \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 121 | bnx2x_panic_dump(bp); \ |
| 122 | } while (0) |
| 123 | #else |
| 124 | #define bnx2x_panic() do { \ |
Eilon Greenstein | e3553b2 | 2009-08-12 08:23:31 +0000 | [diff] [blame] | 125 | bp->panic = 1; \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 126 | BNX2X_ERR("driver assert\n"); \ |
| 127 | bnx2x_panic_dump(bp); \ |
| 128 | } while (0) |
| 129 | #endif |
| 130 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 131 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 132 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 133 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 134 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
| 135 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) |
| 136 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 137 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 138 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 139 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 140 | |
| 141 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
| 142 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 143 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 144 | |
| 145 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 146 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 147 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 148 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 149 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
| 150 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 151 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 152 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
| 153 | do { \ |
| 154 | bnx2x_read_dmae(bp, offset, len32);\ |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 155 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 156 | } while (0) |
| 157 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 158 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 159 | do { \ |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 160 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 161 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
| 162 | offset, len32); \ |
| 163 | } while (0) |
| 164 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 165 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
| 166 | REG_WR_DMAE(bp, offset, valp, len32) |
| 167 | |
Vladislav Zolotarov | 3359fce | 2010-02-17 13:35:01 -0800 | [diff] [blame] | 168 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 169 | do { \ |
| 170 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ |
| 171 | bnx2x_write_big_buf_wb(bp, addr, len32); \ |
| 172 | } while (0) |
| 173 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 174 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
| 175 | offsetof(struct shmem_region, field)) |
| 176 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) |
| 177 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 178 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 179 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
| 180 | offsetof(struct shmem2_region, field)) |
| 181 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) |
| 182 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 183 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
| 184 | offsetof(struct mf_cfg, field)) |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 185 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 186 | offsetof(struct mf2_cfg, field)) |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 187 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 188 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
| 189 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ |
| 190 | MF_CFG_ADDR(bp, field), (val)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 191 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 192 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 193 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
| 194 | (SHMEM2_RD((bp), size) > \ |
| 195 | offsetof(struct shmem2_region, field))) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 196 | |
Eilon Greenstein | 345b5d5 | 2008-08-13 15:58:12 -0700 | [diff] [blame] | 197 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 198 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 199 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 200 | /* SP SB indices */ |
| 201 | |
| 202 | /* General SP events - stats query, cfc delete, etc */ |
| 203 | #define HC_SP_INDEX_ETH_DEF_CONS 3 |
| 204 | |
| 205 | /* EQ completions */ |
| 206 | #define HC_SP_INDEX_EQ_CONS 7 |
| 207 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 208 | /* FCoE L2 connection completions */ |
| 209 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 |
| 210 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 211 | /* iSCSI L2 */ |
| 212 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 |
| 213 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 |
| 214 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 215 | /* Special clients parameters */ |
| 216 | |
| 217 | /* SB indices */ |
| 218 | /* FCoE L2 */ |
| 219 | #define BNX2X_FCOE_L2_RX_INDEX \ |
| 220 | (&bp->def_status_blk->sp_sb.\ |
| 221 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) |
| 222 | |
| 223 | #define BNX2X_FCOE_L2_TX_INDEX \ |
| 224 | (&bp->def_status_blk->sp_sb.\ |
| 225 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) |
| 226 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 227 | /** |
| 228 | * CIDs and CLIDs: |
| 229 | * CLIDs below is a CLID for func 0, then the CLID for other |
| 230 | * functions will be calculated by the formula: |
| 231 | * |
| 232 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X |
| 233 | * |
| 234 | */ |
| 235 | /* iSCSI L2 */ |
| 236 | #define BNX2X_ISCSI_ETH_CL_ID 17 |
| 237 | #define BNX2X_ISCSI_ETH_CID 17 |
| 238 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 239 | /* FCoE L2 */ |
| 240 | #define BNX2X_FCOE_ETH_CL_ID 18 |
| 241 | #define BNX2X_FCOE_ETH_CID 18 |
| 242 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 243 | /** Additional rings budgeting */ |
| 244 | #ifdef BCM_CNIC |
| 245 | #define CNIC_CONTEXT_USE 1 |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 246 | #define FCOE_CONTEXT_USE 1 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 247 | #else |
| 248 | #define CNIC_CONTEXT_USE 0 |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 249 | #define FCOE_CONTEXT_USE 0 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 250 | #endif /* BCM_CNIC */ |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 251 | #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 252 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 253 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
| 254 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |
| 255 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 256 | #define SM_RX_ID 0 |
| 257 | #define SM_TX_ID 1 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 258 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 259 | /* fast path */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 260 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 261 | struct sw_rx_bd { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 262 | struct sk_buff *skb; |
FUJITA Tomonori | 1a98314 | 2010-04-04 01:51:03 +0000 | [diff] [blame] | 263 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | struct sw_tx_bd { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 267 | struct sk_buff *skb; |
| 268 | u16 first_bd; |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 269 | u8 flags; |
| 270 | /* Set on the first BD descriptor when there is a split BD */ |
| 271 | #define BNX2X_TSO_SPLIT_BD (1<<0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 272 | }; |
| 273 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 274 | struct sw_rx_page { |
| 275 | struct page *page; |
FUJITA Tomonori | 1a98314 | 2010-04-04 01:51:03 +0000 | [diff] [blame] | 276 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 277 | }; |
| 278 | |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 279 | union db_prod { |
| 280 | struct doorbell_set_prod data; |
| 281 | u32 raw; |
| 282 | }; |
| 283 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 284 | |
| 285 | /* MC hsi */ |
| 286 | #define BCM_PAGE_SHIFT 12 |
| 287 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
| 288 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) |
| 289 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
| 290 | |
| 291 | #define PAGES_PER_SGE_SHIFT 0 |
| 292 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
Eilon Greenstein | 4f40f2c | 2009-01-14 21:24:17 -0800 | [diff] [blame] | 293 | #define SGE_PAGE_SIZE PAGE_SIZE |
| 294 | #define SGE_PAGE_SHIFT PAGE_SHIFT |
Eilon Greenstein | 5b6402d | 2009-07-21 05:47:51 +0000 | [diff] [blame] | 295 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 296 | |
| 297 | /* SGE ring related macros */ |
| 298 | #define NUM_RX_SGE_PAGES 2 |
| 299 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
| 300 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 301 | /* RX_SGE_CNT is promised to be a power of 2 */ |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 302 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
| 303 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) |
| 304 | #define MAX_RX_SGE (NUM_RX_SGE - 1) |
| 305 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
| 306 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) |
| 307 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
| 308 | |
| 309 | /* SGE producer mask related macros */ |
| 310 | /* Number of bits in one sge_mask array element */ |
| 311 | #define RX_SGE_MASK_ELEM_SZ 64 |
| 312 | #define RX_SGE_MASK_ELEM_SHIFT 6 |
| 313 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) |
| 314 | |
| 315 | /* Creates a bitmask of all ones in less significant bits. |
| 316 | idx - index of the most significant bit in the created mask */ |
| 317 | #define RX_SGE_ONES_MASK(idx) \ |
| 318 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) |
| 319 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) |
| 320 | |
| 321 | /* Number of u64 elements in SGE mask array */ |
| 322 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ |
| 323 | RX_SGE_MASK_ELEM_SZ) |
| 324 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
| 325 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) |
| 326 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 327 | union host_hc_status_block { |
| 328 | /* pointer to fp status block e1x */ |
| 329 | struct host_hc_status_block_e1x *e1x_sb; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 330 | /* pointer to fp status block e2 */ |
| 331 | struct host_hc_status_block_e2 *e2_sb; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 332 | }; |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 333 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 334 | struct bnx2x_fastpath { |
| 335 | |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 336 | #define BNX2X_NAPI_WEIGHT 128 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 337 | struct napi_struct napi; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 338 | union host_hc_status_block status_blk; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 339 | /* chip independed shortcuts into sb structure */ |
| 340 | __le16 *sb_index_values; |
| 341 | __le16 *sb_running_index; |
| 342 | /* chip independed shortcut into rx_prods_offset memory */ |
| 343 | u32 ustorm_rx_prods_offset; |
| 344 | |
Vladislav Zolotarov | a8c94b9 | 2011-02-06 11:21:02 -0800 | [diff] [blame] | 345 | u32 rx_buf_size; |
| 346 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 347 | dma_addr_t status_blk_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 348 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 349 | struct sw_tx_bd *tx_buf_ring; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 350 | |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 351 | union eth_tx_bd_types *tx_desc_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 352 | dma_addr_t tx_desc_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 353 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 354 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
| 355 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 356 | |
| 357 | struct eth_rx_bd *rx_desc_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 358 | dma_addr_t rx_desc_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 359 | |
| 360 | union eth_rx_cqe *rx_comp_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 361 | dma_addr_t rx_comp_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 362 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 363 | /* SGE ring */ |
| 364 | struct eth_rx_sge *rx_sge_ring; |
| 365 | dma_addr_t rx_sge_mapping; |
| 366 | |
| 367 | u64 sge_mask[RX_SGE_MASK_LEN]; |
| 368 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 369 | int state; |
| 370 | #define BNX2X_FP_STATE_CLOSED 0 |
| 371 | #define BNX2X_FP_STATE_IRQ 0x80000 |
| 372 | #define BNX2X_FP_STATE_OPENING 0x90000 |
| 373 | #define BNX2X_FP_STATE_OPEN 0xa0000 |
| 374 | #define BNX2X_FP_STATE_HALTING 0xb0000 |
| 375 | #define BNX2X_FP_STATE_HALTED 0xc0000 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 376 | #define BNX2X_FP_STATE_TERMINATING 0xd0000 |
| 377 | #define BNX2X_FP_STATE_TERMINATED 0xe0000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 378 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 379 | u8 index; /* number in fp array */ |
| 380 | u8 cl_id; /* eth client id */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 381 | u8 cl_qzone_id; |
| 382 | u8 fw_sb_id; /* status block number in FW */ |
| 383 | u8 igu_sb_id; /* status block number in HW */ |
| 384 | u32 cid; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 385 | |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 386 | union db_prod tx_db; |
| 387 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 388 | u16 tx_pkt_prod; |
| 389 | u16 tx_pkt_cons; |
| 390 | u16 tx_bd_prod; |
| 391 | u16 tx_bd_cons; |
Eilon Greenstein | 4781bfa | 2009-02-12 08:38:17 +0000 | [diff] [blame] | 392 | __le16 *tx_cons_sb; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 393 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 394 | __le16 fp_hc_idx; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 395 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 396 | u16 rx_bd_prod; |
| 397 | u16 rx_bd_cons; |
| 398 | u16 rx_comp_prod; |
| 399 | u16 rx_comp_cons; |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 400 | u16 rx_sge_prod; |
| 401 | /* The last maximal completed SGE */ |
| 402 | u16 last_max_sge; |
Eilon Greenstein | 4781bfa | 2009-02-12 08:38:17 +0000 | [diff] [blame] | 403 | __le16 *rx_cons_sb; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 404 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 405 | unsigned long tx_pkt, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 406 | rx_pkt, |
Yitchak Gertner | 66e855f | 2008-08-13 15:49:05 -0700 | [diff] [blame] | 407 | rx_calls; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 408 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 409 | /* TPA related */ |
| 410 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; |
| 411 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; |
| 412 | #define BNX2X_TPA_START 1 |
| 413 | #define BNX2X_TPA_STOP 2 |
| 414 | u8 disable_tpa; |
| 415 | #ifdef BNX2X_STOP_ON_ERROR |
| 416 | u64 tpa_queue_used; |
| 417 | #endif |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 418 | |
Eilon Greenstein | de832a5 | 2009-02-12 08:36:33 +0000 | [diff] [blame] | 419 | struct tstorm_per_client_stats old_tclient; |
| 420 | struct ustorm_per_client_stats old_uclient; |
| 421 | struct xstorm_per_client_stats old_xclient; |
| 422 | struct bnx2x_eth_q_stats eth_q_stats; |
| 423 | |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 424 | /* The size is calculated using the following: |
| 425 | sizeof name field from netdev structure + |
| 426 | 4 ('-Xx-' string) + |
| 427 | 4 (for the digits and to make it DWORD aligned) */ |
| 428 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) |
| 429 | char name[FP_NAME_SIZE]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 430 | struct bnx2x *bp; /* parent */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 431 | }; |
| 432 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 433 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
Vladislav Zolotarov | a8c94b9 | 2011-02-06 11:21:02 -0800 | [diff] [blame] | 434 | |
| 435 | /* Use 2500 as a mini-jumbo MTU for FCoE */ |
| 436 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 |
| 437 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 438 | #ifdef BCM_CNIC |
| 439 | /* FCoE L2 `fastpath' is right after the eth entries */ |
| 440 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) |
| 441 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) |
| 442 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) |
| 443 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) |
| 444 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) |
| 445 | #else |
| 446 | #define IS_FCOE_FP(fp) false |
| 447 | #define IS_FCOE_IDX(idx) false |
| 448 | #endif |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 449 | |
| 450 | |
| 451 | /* MC hsi */ |
| 452 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ |
| 453 | #define RX_COPY_THRESH 92 |
| 454 | |
| 455 | #define NUM_TX_RINGS 16 |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 456 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 457 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
| 458 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
| 459 | #define MAX_TX_BD (NUM_TX_BD - 1) |
| 460 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 461 | #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL |
| 462 | #define INIT_TX_RING_SIZE MAX_TX_AVAIL |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 463 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
| 464 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 465 | #define TX_BD(x) ((x) & MAX_TX_BD) |
| 466 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) |
| 467 | |
| 468 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ |
| 469 | #define NUM_RX_RINGS 8 |
| 470 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
| 471 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) |
| 472 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
| 473 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) |
| 474 | #define MAX_RX_BD (NUM_RX_BD - 1) |
| 475 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) |
Dmitry Kravkov | b3b83c3 | 2011-05-04 23:50:33 +0000 | [diff] [blame] | 476 | #define MIN_RX_SIZE_TPA 72 |
| 477 | #define MIN_RX_SIZE_NONTPA 10 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 478 | #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL |
| 479 | #define INIT_RX_RING_SIZE MAX_RX_AVAIL |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 480 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
| 481 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) |
| 482 | #define RX_BD(x) ((x) & MAX_RX_BD) |
| 483 | |
| 484 | /* As long as CQE is 4 times bigger than BD entry we have to allocate |
| 485 | 4 times more pages for CQ ring in order to keep it balanced with |
| 486 | BD ring */ |
| 487 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) |
| 488 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
| 489 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) |
| 490 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
| 491 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) |
| 492 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) |
| 493 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
| 494 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 495 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
| 496 | |
| 497 | |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 498 | /* This is needed for determining of last_max */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 499 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
| 500 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 501 | #define __SGE_MASK_SET_BIT(el, bit) \ |
| 502 | do { \ |
| 503 | el = ((el) | ((u64)0x1 << (bit))); \ |
| 504 | } while (0) |
| 505 | |
| 506 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ |
| 507 | do { \ |
| 508 | el = ((el) & (~((u64)0x1 << (bit)))); \ |
| 509 | } while (0) |
| 510 | |
| 511 | #define SGE_MASK_SET_BIT(fp, idx) \ |
| 512 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ |
| 513 | ((idx) & RX_SGE_MASK_ELEM_MASK)) |
| 514 | |
| 515 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ |
| 516 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ |
| 517 | ((idx) & RX_SGE_MASK_ELEM_MASK)) |
| 518 | |
| 519 | |
| 520 | /* used on a CID received from the HW */ |
| 521 | #define SW_CID(x) (le32_to_cpu(x) & \ |
| 522 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) |
| 523 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
| 524 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) |
| 525 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 526 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
| 527 | le32_to_cpu((bd)->addr_lo)) |
| 528 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) |
| 529 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 530 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
| 531 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 532 | #define DPM_TRIGER_TYPE 0x40 |
| 533 | #define DOORBELL(bp, cid, val) \ |
| 534 | do { \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 535 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 536 | DPM_TRIGER_TYPE); \ |
| 537 | } while (0) |
| 538 | |
| 539 | |
| 540 | /* TX CSUM helpers */ |
| 541 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ |
| 542 | skb->csum_offset) |
| 543 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ |
| 544 | skb->csum_offset)) |
| 545 | |
| 546 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) |
| 547 | |
| 548 | #define XMIT_PLAIN 0 |
| 549 | #define XMIT_CSUM_V4 0x1 |
| 550 | #define XMIT_CSUM_V6 0x2 |
| 551 | #define XMIT_CSUM_TCP 0x4 |
| 552 | #define XMIT_GSO_V4 0x8 |
| 553 | #define XMIT_GSO_V6 0x10 |
| 554 | |
| 555 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) |
| 556 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) |
| 557 | |
| 558 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 559 | /* stuff added to make the code fit 80Col */ |
| 560 | |
| 561 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
| 562 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 563 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
| 564 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG |
| 565 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ |
| 566 | (TPA_TYPE_START | TPA_TYPE_END)) |
| 567 | |
Eilon Greenstein | 1adcd8b | 2008-08-13 15:48:29 -0700 | [diff] [blame] | 568 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
| 569 | |
| 570 | #define BNX2X_IP_CSUM_ERR(cqe) \ |
| 571 | (!((cqe)->fast_path_cqe.status_flags & \ |
| 572 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ |
| 573 | ((cqe)->fast_path_cqe.type_error_flags & \ |
| 574 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) |
| 575 | |
| 576 | #define BNX2X_L4_CSUM_ERR(cqe) \ |
| 577 | (!((cqe)->fast_path_cqe.status_flags & \ |
| 578 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ |
| 579 | ((cqe)->fast_path_cqe.type_error_flags & \ |
| 580 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) |
| 581 | |
| 582 | #define BNX2X_RX_CSUM_OK(cqe) \ |
| 583 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 584 | |
Eilon Greenstein | 052a38e | 2009-02-12 08:37:16 +0000 | [diff] [blame] | 585 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
| 586 | (((le16_to_cpu(flags) & \ |
| 587 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ |
| 588 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ |
| 589 | == PRS_FLAG_OVERETH_IPV4) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 590 | #define BNX2X_RX_SUM_FIX(cqe) \ |
Eilon Greenstein | 052a38e | 2009-02-12 08:37:16 +0000 | [diff] [blame] | 591 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 592 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 593 | #define U_SB_ETH_RX_CQ_INDEX 1 |
| 594 | #define U_SB_ETH_RX_BD_INDEX 2 |
| 595 | #define C_SB_ETH_TX_CQ_INDEX 5 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 596 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 597 | #define BNX2X_RX_SB_INDEX \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 598 | (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX]) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 599 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 600 | #define BNX2X_TX_SB_INDEX \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 601 | (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX]) |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 602 | |
| 603 | /* end of fast path */ |
| 604 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 605 | /* common */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 606 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 607 | struct bnx2x_common { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 608 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 609 | u32 chip_id; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 610 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 611 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 612 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 613 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 614 | #define CHIP_NUM_57710 0x164e |
| 615 | #define CHIP_NUM_57711 0x164f |
| 616 | #define CHIP_NUM_57711E 0x1650 |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 617 | #define CHIP_NUM_57712 0x1662 |
| 618 | #define CHIP_NUM_57712E 0x1663 |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 619 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
| 620 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) |
| 621 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 622 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
| 623 | #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 624 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
| 625 | CHIP_IS_57711E(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 626 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
| 627 | CHIP_IS_57712E(bp)) |
| 628 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
| 629 | #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 630 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 631 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 632 | #define CHIP_REV_Ax 0x00000000 |
| 633 | /* assume maximum 5 revisions */ |
| 634 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) |
| 635 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
| 636 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ |
| 637 | !(CHIP_REV(bp) & 0x00001000)) |
| 638 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
| 639 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ |
| 640 | (CHIP_REV(bp) & 0x00001000)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 641 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 642 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ |
| 643 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) |
| 644 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 645 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
| 646 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) |
Vladislav Zolotarov | 4a33bc0 | 2011-01-09 02:20:04 +0000 | [diff] [blame] | 647 | #define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 648 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 649 | int flash_size; |
| 650 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
| 651 | #define NVRAM_TIMEOUT_COUNT 30000 |
| 652 | #define NVRAM_PAGE_SIZE 256 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 653 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 654 | u32 shmem_base; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 655 | u32 shmem2_base; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 656 | u32 mf_cfg_base; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 657 | u32 mf2_cfg_base; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 658 | |
| 659 | u32 hw_config; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 660 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 661 | u32 bc_ver; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 662 | |
| 663 | u8 int_block; |
| 664 | #define INT_BLOCK_HC 0 |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 665 | #define INT_BLOCK_IGU 1 |
| 666 | #define INT_BLOCK_MODE_NORMAL 0 |
| 667 | #define INT_BLOCK_MODE_BW_COMP 2 |
| 668 | #define CHIP_INT_MODE_IS_NBC(bp) \ |
| 669 | (CHIP_IS_E2(bp) && \ |
| 670 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) |
| 671 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) |
| 672 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 673 | u8 chip_port_mode; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 674 | #define CHIP_4_PORT_MODE 0x0 |
| 675 | #define CHIP_2_PORT_MODE 0x1 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 676 | #define CHIP_PORT_MODE_NONE 0x2 |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 677 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
| 678 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 679 | }; |
| 680 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 681 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
| 682 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 |
| 683 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 684 | |
| 685 | /* end of common */ |
| 686 | |
| 687 | /* port */ |
| 688 | |
| 689 | struct bnx2x_port { |
| 690 | u32 pmf; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 691 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 692 | u32 link_config[LINK_CONFIG_SIZE]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 693 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 694 | u32 supported[LINK_CONFIG_SIZE]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 695 | /* link settings - missing defines */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 696 | #define SUPPORTED_2500baseX_Full (1 << 15) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 697 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 698 | u32 advertising[LINK_CONFIG_SIZE]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 699 | /* link settings - missing defines */ |
| 700 | #define ADVERTISED_2500baseX_Full (1 << 15) |
| 701 | |
| 702 | u32 phy_addr; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 703 | |
| 704 | /* used to synchronize phy accesses */ |
| 705 | struct mutex phy_mutex; |
Eilon Greenstein | 46c6a67 | 2009-02-12 08:36:58 +0000 | [diff] [blame] | 706 | int need_hw_lock; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 707 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 708 | u32 port_stx; |
| 709 | |
| 710 | struct nig_stats old_nig_stats; |
| 711 | }; |
| 712 | |
| 713 | /* end of port */ |
| 714 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 715 | /* e1h Classification CAM line allocations */ |
| 716 | enum { |
| 717 | CAM_ETH_LINE = 0, |
| 718 | CAM_ISCSI_ETH_LINE, |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 719 | CAM_FIP_ETH_LINE, |
| 720 | CAM_FIP_MCAST_LINE, |
| 721 | CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 722 | }; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 723 | /* number of MACs per function in NIG memory - used for SI mode */ |
| 724 | #define NIG_LLH_FUNC_MEM_SIZE 16 |
| 725 | /* number of entries in NIG_REG_LLHX_FUNC_MEM */ |
| 726 | #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8 |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 727 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 728 | #define BNX2X_VF_ID_INVALID 0xFF |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 729 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 730 | /* |
| 731 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is |
| 732 | * control by the number of fast-path status blocks supported by the |
| 733 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default |
| 734 | * status block represents an independent interrupts context that can |
| 735 | * serve a regular L2 networking queue. However special L2 queues such |
| 736 | * as the FCoE queue do not require a FP-SB and other components like |
| 737 | * the CNIC may consume FP-SB reducing the number of possible L2 queues |
| 738 | * |
| 739 | * If the maximum number of FP-SB available is X then: |
| 740 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of |
| 741 | * regular L2 queues is Y=X-1 |
| 742 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) |
| 743 | * c. If the FCoE L2 queue is supported the actual number of L2 queues |
| 744 | * is Y+1 |
| 745 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for |
| 746 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional |
| 747 | * FP interrupt context for the CNIC). |
| 748 | * e. The number of HW context (CID count) is always X or X+1 if FCoE |
| 749 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. |
| 750 | */ |
| 751 | |
| 752 | #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 753 | #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 754 | |
| 755 | /* |
| 756 | * cid_cnt paramter below refers to the value returned by |
| 757 | * 'bnx2x_get_l2_cid_count()' routine |
| 758 | */ |
| 759 | |
| 760 | /* |
| 761 | * The number of FP context allocated by the driver == max number of regular |
| 762 | * L2 queues + 1 for the FCoE L2 queue |
| 763 | */ |
| 764 | #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 765 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 766 | /* |
| 767 | * The number of FP-SB allocated by the driver == max number of regular L2 |
| 768 | * queues + 1 for the CNIC which also consumes an FP-SB |
| 769 | */ |
| 770 | #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE) |
| 771 | #define NUM_IGU_SB_REQUIRED(cid_cnt) \ |
| 772 | (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE) |
| 773 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 774 | union cdu_context { |
| 775 | struct eth_context eth; |
| 776 | char pad[1024]; |
| 777 | }; |
| 778 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 779 | /* CDU host DB constants */ |
| 780 | #define CDU_ILT_PAGE_SZ_HW 3 |
| 781 | #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */ |
| 782 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
| 783 | |
| 784 | #ifdef BCM_CNIC |
| 785 | #define CNIC_ISCSI_CID_MAX 256 |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 786 | #define CNIC_FCOE_CID_MAX 2048 |
| 787 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 788 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
| 789 | #endif |
| 790 | |
| 791 | #define QM_ILT_PAGE_SZ_HW 3 |
| 792 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */ |
| 793 | #define QM_CID_ROUND 1024 |
| 794 | |
| 795 | #ifdef BCM_CNIC |
| 796 | /* TM (timers) host DB constants */ |
| 797 | #define TM_ILT_PAGE_SZ_HW 2 |
| 798 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */ |
| 799 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ |
| 800 | #define TM_CONN_NUM 1024 |
| 801 | #define TM_ILT_SZ (8 * TM_CONN_NUM) |
| 802 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) |
| 803 | |
| 804 | /* SRC (Searcher) host DB constants */ |
| 805 | #define SRC_ILT_PAGE_SZ_HW 3 |
| 806 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */ |
| 807 | #define SRC_HASH_BITS 10 |
| 808 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ |
| 809 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) |
| 810 | #define SRC_T2_SZ SRC_ILT_SZ |
| 811 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) |
| 812 | #endif |
| 813 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 814 | #define MAX_DMAE_C 8 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 815 | |
| 816 | /* DMA memory not used in fastpath */ |
| 817 | struct bnx2x_slowpath { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 818 | struct eth_stats_query fw_stats; |
| 819 | struct mac_configuration_cmd mac_config; |
| 820 | struct mac_configuration_cmd mcast_config; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 821 | struct mac_configuration_cmd uc_mac_config; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 822 | struct client_init_ramrod_data client_init_data; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 823 | |
| 824 | /* used by dmae command executer */ |
| 825 | struct dmae_command dmae[MAX_DMAE_C]; |
| 826 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 827 | u32 stats_comp; |
| 828 | union mac_stats mac_stats; |
| 829 | struct nig_stats nig_stats; |
| 830 | struct host_port_stats port_stats; |
| 831 | struct host_func_stats func_stats; |
Eilon Greenstein | 6fe49bb | 2009-08-12 08:23:17 +0000 | [diff] [blame] | 832 | struct host_func_stats func_stats_base; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 833 | |
| 834 | u32 wb_comp; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 835 | u32 wb_data[4]; |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 836 | /* pfc configuration for DCBX ramrod */ |
| 837 | struct flow_control_configuration pfc_config; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 838 | }; |
| 839 | |
| 840 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) |
| 841 | #define bnx2x_sp_mapping(bp, var) \ |
| 842 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 843 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 844 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 845 | /* attn group wiring */ |
| 846 | #define MAX_DYNAMIC_ATTN_GRPS 8 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 847 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 848 | struct attn_route { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 849 | u32 sig[5]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 850 | }; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 851 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 852 | struct iro { |
| 853 | u32 base; |
| 854 | u16 m1; |
| 855 | u16 m2; |
| 856 | u16 m3; |
| 857 | u16 size; |
| 858 | }; |
| 859 | |
| 860 | struct hw_context { |
| 861 | union cdu_context *vcxt; |
| 862 | dma_addr_t cxt_mapping; |
| 863 | size_t size; |
| 864 | }; |
| 865 | |
| 866 | /* forward */ |
| 867 | struct bnx2x_ilt; |
| 868 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 869 | typedef enum { |
| 870 | BNX2X_RECOVERY_DONE, |
| 871 | BNX2X_RECOVERY_INIT, |
| 872 | BNX2X_RECOVERY_WAIT, |
| 873 | } bnx2x_recovery_state_t; |
| 874 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 875 | /** |
| 876 | * Event queue (EQ or event ring) MC hsi |
| 877 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 |
| 878 | */ |
| 879 | #define NUM_EQ_PAGES 1 |
| 880 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) |
| 881 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) |
| 882 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) |
| 883 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) |
| 884 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) |
| 885 | |
| 886 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ |
| 887 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ |
| 888 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) |
| 889 | |
| 890 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ |
| 891 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) |
| 892 | |
| 893 | #define BNX2X_EQ_INDEX \ |
| 894 | (&bp->def_status_blk->sp_sb.\ |
| 895 | index_values[HC_SP_INDEX_EQ_CONS]) |
| 896 | |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 897 | /* This is a data that will be used to create a link report message. |
| 898 | * We will keep the data used for the last link report in order |
| 899 | * to prevent reporting the same link parameters twice. |
| 900 | */ |
| 901 | struct bnx2x_link_report_data { |
| 902 | u16 line_speed; /* Effective line speed */ |
| 903 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ |
| 904 | }; |
| 905 | |
| 906 | enum { |
| 907 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ |
| 908 | BNX2X_LINK_REPORT_LINK_DOWN, |
| 909 | BNX2X_LINK_REPORT_RX_FC_ON, |
| 910 | BNX2X_LINK_REPORT_TX_FC_ON, |
| 911 | }; |
| 912 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 913 | struct bnx2x { |
| 914 | /* Fields used in the tx and intr/napi performance paths |
| 915 | * are grouped together in the beginning of the structure |
| 916 | */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 917 | struct bnx2x_fastpath *fp; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 918 | void __iomem *regview; |
| 919 | void __iomem *doorbells; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 920 | u16 db_size; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 921 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 922 | struct net_device *dev; |
| 923 | struct pci_dev *pdev; |
| 924 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 925 | struct iro *iro_arr; |
| 926 | #define IRO (bp->iro_arr) |
| 927 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 928 | atomic_t intr_sem; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 929 | |
| 930 | bnx2x_recovery_state_t recovery_state; |
| 931 | int is_leader; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 932 | struct msix_entry *msix_table; |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 933 | #define INT_MODE_INTx 1 |
| 934 | #define INT_MODE_MSI 2 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 935 | |
| 936 | int tx_ring_size; |
| 937 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 938 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
| 939 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 940 | #define ETH_MIN_PACKET_SIZE 60 |
| 941 | #define ETH_MAX_PACKET_SIZE 1500 |
| 942 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 |
| 943 | |
Eilon Greenstein | 0f00846 | 2009-02-12 08:36:18 +0000 | [diff] [blame] | 944 | /* Max supported alignment is 256 (8 shift) */ |
| 945 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ |
| 946 | L1_CACHE_SHIFT : 8) |
| 947 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 948 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
Eilon Greenstein | 0f00846 | 2009-02-12 08:36:18 +0000 | [diff] [blame] | 949 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 950 | struct host_sp_status_block *def_status_blk; |
| 951 | #define DEF_SB_IGU_ID 16 |
| 952 | #define DEF_SB_ID HC_SP_SB_ID |
| 953 | __le16 def_idx; |
Eilon Greenstein | 4781bfa | 2009-02-12 08:38:17 +0000 | [diff] [blame] | 954 | __le16 def_att_idx; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 955 | u32 attn_state; |
| 956 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 957 | |
| 958 | /* slow path ring */ |
| 959 | struct eth_spe *spq; |
| 960 | dma_addr_t spq_mapping; |
| 961 | u16 spq_prod_idx; |
| 962 | struct eth_spe *spq_prod_bd; |
| 963 | struct eth_spe *spq_last_bd; |
Eilon Greenstein | 4781bfa | 2009-02-12 08:38:17 +0000 | [diff] [blame] | 964 | __le16 *dsb_sp_prod; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 965 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 966 | /* used to synchronize spq accesses */ |
| 967 | spinlock_t spq_lock; |
| 968 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 969 | /* event queue */ |
| 970 | union event_ring_elem *eq_ring; |
| 971 | dma_addr_t eq_mapping; |
| 972 | u16 eq_prod; |
| 973 | u16 eq_cons; |
| 974 | __le16 *eq_cons_sb; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 975 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 976 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 977 | /* Flags for marking that there is a STAT_QUERY or |
| 978 | SET_MAC ramrod pending */ |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 979 | int stats_pending; |
| 980 | int set_mac_pending; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 981 | |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 982 | /* End of fields used in the performance code paths */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 983 | |
| 984 | int panic; |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 985 | int msg_enable; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 986 | |
| 987 | u32 flags; |
| 988 | #define PCIX_FLAG 1 |
| 989 | #define PCI_32BIT_FLAG 2 |
Eilon Greenstein | 1c06328 | 2009-02-12 08:36:43 +0000 | [diff] [blame] | 990 | #define ONE_PORT_FLAG 4 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 991 | #define NO_WOL_FLAG 8 |
| 992 | #define USING_DAC_FLAG 0x10 |
| 993 | #define USING_MSIX_FLAG 0x20 |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 994 | #define USING_MSI_FLAG 0x40 |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 995 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 996 | #define TPA_ENABLE_FLAG 0x80 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 997 | #define NO_MCP_FLAG 0x100 |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 998 | #define DISABLE_MSI_FLAG 0x200 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 999 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 1000 | #define MF_FUNC_DIS 0x1000 |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1001 | #define FCOE_MACS_SET 0x2000 |
| 1002 | #define NO_FCOE_FLAG 0x4000 |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 1003 | #define NO_ISCSI_OOO_FLAG 0x8000 |
| 1004 | #define NO_ISCSI_FLAG 0x10000 |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1005 | |
| 1006 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 1007 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
| 1008 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1009 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1010 | int pf_num; /* absolute PF number */ |
| 1011 | int pfid; /* per-path PF number */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1012 | int base_fw_ndsb; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1013 | #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \ |
| 1014 | 0 : (bp->pf_num & 1)) |
| 1015 | #define BP_PORT(bp) (bp->pfid & 1) |
| 1016 | #define BP_FUNC(bp) (bp->pfid) |
| 1017 | #define BP_ABS_FUNC(bp) (bp->pf_num) |
| 1018 | #define BP_E1HVN(bp) (bp->pfid >> 1) |
| 1019 | #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \ |
| 1020 | 0 : BP_E1HVN(bp)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1021 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1022 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ |
| 1023 | BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1024 | |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1025 | #ifdef BCM_CNIC |
| 1026 | #define BCM_CNIC_CID_START 16 |
| 1027 | #define BCM_ISCSI_ETH_CL_ID 17 |
| 1028 | #endif |
| 1029 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1030 | int pm_cap; |
| 1031 | int pcie_cap; |
Eilon Greenstein | 8d5726c | 2009-02-12 08:37:19 +0000 | [diff] [blame] | 1032 | int mrrs; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1033 | |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 1034 | struct delayed_work sp_task; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1035 | struct delayed_work reset_task; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1036 | struct timer_list timer; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1037 | int current_interval; |
| 1038 | |
| 1039 | u16 fw_seq; |
| 1040 | u16 fw_drv_pulse_wr_seq; |
| 1041 | u32 func_stx; |
| 1042 | |
| 1043 | struct link_params link_params; |
| 1044 | struct link_vars link_vars; |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 1045 | u32 link_cnt; |
| 1046 | struct bnx2x_link_report_data last_reported_link; |
| 1047 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 1048 | struct mdio_if_info mdio; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1049 | |
| 1050 | struct bnx2x_common common; |
| 1051 | struct bnx2x_port port; |
| 1052 | |
Eilon Greenstein | 8a1c38d | 2009-02-12 08:36:40 +0000 | [diff] [blame] | 1053 | struct cmng_struct_per_port cmng; |
| 1054 | u32 vn_weight_sum; |
| 1055 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1056 | u32 mf_config[E1HVN_MAX]; |
| 1057 | u32 mf2_config[E2_FUNC_MAX]; |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 1058 | u16 mf_ov; |
| 1059 | u8 mf_mode; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1060 | #define IS_MF(bp) (bp->mf_mode != 0) |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 1061 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
| 1062 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1063 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1064 | u8 wol; |
| 1065 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1066 | int rx_ring_size; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1067 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1068 | u16 tx_quick_cons_trip_int; |
| 1069 | u16 tx_quick_cons_trip; |
| 1070 | u16 tx_ticks_int; |
| 1071 | u16 tx_ticks; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1072 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1073 | u16 rx_quick_cons_trip_int; |
| 1074 | u16 rx_quick_cons_trip; |
| 1075 | u16 rx_ticks_int; |
| 1076 | u16 rx_ticks; |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 1077 | /* Maximal coalescing timeout in us */ |
| 1078 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1079 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1080 | u32 lin_cnt; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1081 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1082 | int state; |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 1083 | #define BNX2X_STATE_CLOSED 0 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1084 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
| 1085 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1086 | #define BNX2X_STATE_OPEN 0x3000 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1087 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1088 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
| 1089 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1090 | #define BNX2X_STATE_FUNC_STARTED 0x7000 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1091 | #define BNX2X_STATE_DIAG 0xe000 |
| 1092 | #define BNX2X_STATE_ERROR 0xf000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1093 | |
Eilon Greenstein | 555f6c7 | 2009-02-12 08:36:11 +0000 | [diff] [blame] | 1094 | int multi_mode; |
Vladislav Zolotarov | 54b9dda | 2009-11-16 06:05:58 +0000 | [diff] [blame] | 1095 | int num_queues; |
Dmitry Kravkov | 5d7cd49 | 2010-07-27 12:32:19 +0000 | [diff] [blame] | 1096 | int disable_tpa; |
| 1097 | int int_mode; |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 1098 | u32 *rx_indir_table; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1099 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1100 | struct tstorm_eth_mac_filter_config mac_filters; |
| 1101 | #define BNX2X_ACCEPT_NONE 0x0000 |
| 1102 | #define BNX2X_ACCEPT_UNICAST 0x0001 |
| 1103 | #define BNX2X_ACCEPT_MULTICAST 0x0002 |
| 1104 | #define BNX2X_ACCEPT_ALL_UNICAST 0x0004 |
| 1105 | #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008 |
| 1106 | #define BNX2X_ACCEPT_BROADCAST 0x0010 |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 1107 | #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1108 | #define BNX2X_PROMISCUOUS_MODE 0x10000 |
| 1109 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1110 | u32 rx_mode; |
| 1111 | #define BNX2X_RX_MODE_NONE 0 |
| 1112 | #define BNX2X_RX_MODE_NORMAL 1 |
| 1113 | #define BNX2X_RX_MODE_ALLMULTI 2 |
| 1114 | #define BNX2X_RX_MODE_PROMISC 3 |
| 1115 | #define BNX2X_MAX_MULTICAST 64 |
| 1116 | #define BNX2X_MAX_EMUL_MULTI 16 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1117 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1118 | u8 igu_dsb_id; |
| 1119 | u8 igu_base_sb; |
| 1120 | u8 igu_sb_cnt; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1121 | dma_addr_t def_status_blk_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1122 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1123 | struct bnx2x_slowpath *slowpath; |
| 1124 | dma_addr_t slowpath_mapping; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1125 | struct hw_context context; |
| 1126 | |
| 1127 | struct bnx2x_ilt *ilt; |
| 1128 | #define BP_ILT(bp) ((bp)->ilt) |
| 1129 | #define ILT_MAX_LINES 128 |
| 1130 | |
| 1131 | int l2_cid_count; |
| 1132 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \ |
| 1133 | ILT_PAGE_CIDS)) |
| 1134 | #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT)) |
| 1135 | |
| 1136 | int qm_cid_count; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1137 | |
Eilon Greenstein | a18f512 | 2009-08-12 08:23:26 +0000 | [diff] [blame] | 1138 | int dropless_fc; |
| 1139 | |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1140 | #ifdef BCM_CNIC |
| 1141 | u32 cnic_flags; |
| 1142 | #define BNX2X_CNIC_FLAG_MAC_SET 1 |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1143 | void *t2; |
| 1144 | dma_addr_t t2_mapping; |
Eric Dumazet | 13707f9 | 2011-01-26 19:28:23 +0000 | [diff] [blame] | 1145 | struct cnic_ops __rcu *cnic_ops; |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1146 | void *cnic_data; |
| 1147 | u32 cnic_tag; |
| 1148 | struct cnic_eth_dev cnic_eth_dev; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1149 | union host_hc_status_block cnic_sb; |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1150 | dma_addr_t cnic_sb_mapping; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1151 | #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp)) |
| 1152 | #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb) |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1153 | struct eth_spe *cnic_kwq; |
| 1154 | struct eth_spe *cnic_kwq_prod; |
| 1155 | struct eth_spe *cnic_kwq_cons; |
| 1156 | struct eth_spe *cnic_kwq_last; |
| 1157 | u16 cnic_kwq_pending; |
| 1158 | u16 cnic_spq_pending; |
| 1159 | struct mutex cnic_mutex; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1160 | u8 fip_mac[ETH_ALEN]; |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 1161 | #endif |
| 1162 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1163 | int dmae_ready; |
| 1164 | /* used to synchronize dmae accesses */ |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 1165 | spinlock_t dmae_lock; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1166 | |
Eilon Greenstein | c4ff7cb | 2009-10-15 00:18:27 -0700 | [diff] [blame] | 1167 | /* used to protect the FW mail box */ |
| 1168 | struct mutex fw_mb_mutex; |
| 1169 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1170 | /* used to synchronize stats collecting */ |
| 1171 | int stats_state; |
Vladislav Zolotarov | a13773a | 2010-07-21 05:59:01 +0000 | [diff] [blame] | 1172 | |
| 1173 | /* used for synchronization of concurrent threads statistics handling */ |
| 1174 | spinlock_t stats_lock; |
| 1175 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1176 | /* used by dmae command loader */ |
| 1177 | struct dmae_command stats_dmae; |
| 1178 | int executer_idx; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1179 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1180 | u16 stats_counter; |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1181 | struct bnx2x_eth_stats eth_stats; |
| 1182 | |
| 1183 | struct z_stream_s *strm; |
| 1184 | void *gunzip_buf; |
| 1185 | dma_addr_t gunzip_mapping; |
| 1186 | int gunzip_outlen; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1187 | #define FW_BUF_SIZE 0x8000 |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 1188 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
| 1189 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) |
| 1190 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1191 | |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1192 | struct raw_op *init_ops; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 1193 | /* Init blocks offsets inside init_ops */ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1194 | u16 *init_ops_offsets; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 1195 | /* Data blob - has 32 bit granularity */ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1196 | u32 *init_data; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 1197 | /* Zipped PRAM blobs - raw data */ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1198 | const u8 *tsem_int_table_data; |
| 1199 | const u8 *tsem_pram_data; |
| 1200 | const u8 *usem_int_table_data; |
| 1201 | const u8 *usem_pram_data; |
| 1202 | const u8 *xsem_int_table_data; |
| 1203 | const u8 *xsem_pram_data; |
| 1204 | const u8 *csem_int_table_data; |
| 1205 | const u8 *csem_pram_data; |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 1206 | #define INIT_OPS(bp) (bp->init_ops) |
| 1207 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) |
| 1208 | #define INIT_DATA(bp) (bp->init_data) |
| 1209 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) |
| 1210 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) |
| 1211 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) |
| 1212 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) |
| 1213 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) |
| 1214 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) |
| 1215 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) |
| 1216 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) |
| 1217 | |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 1218 | char fw_ver[32]; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1219 | const struct firmware *firmware; |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 1220 | /* LLDP params */ |
| 1221 | struct bnx2x_config_lldp_params lldp_config_params; |
| 1222 | |
Shmulik Ravid | 785b9b1 | 2010-12-30 06:27:03 +0000 | [diff] [blame] | 1223 | /* DCB support on/off */ |
| 1224 | u16 dcb_state; |
| 1225 | #define BNX2X_DCB_STATE_OFF 0 |
| 1226 | #define BNX2X_DCB_STATE_ON 1 |
| 1227 | |
| 1228 | /* DCBX engine mode */ |
| 1229 | int dcbx_enabled; |
| 1230 | #define BNX2X_DCBX_ENABLED_OFF 0 |
| 1231 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 |
| 1232 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 |
| 1233 | #define BNX2X_DCBX_ENABLED_INVALID (-1) |
| 1234 | |
| 1235 | bool dcbx_mode_uset; |
| 1236 | |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 1237 | struct bnx2x_config_dcbx_params dcbx_config_params; |
| 1238 | |
| 1239 | struct bnx2x_dcbx_port_params dcbx_port_params; |
| 1240 | int dcb_version; |
| 1241 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1242 | /* DCBX Negotiation results */ |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 1243 | struct dcbx_features dcbx_local_feat; |
| 1244 | u32 dcbx_error; |
Shmulik Ravid | 0be6bc6 | 2011-05-18 02:55:31 +0000 | [diff] [blame] | 1245 | #ifdef BCM_DCBNL |
| 1246 | struct dcbx_features dcbx_remote_feat; |
| 1247 | u32 dcbx_remote_flags; |
| 1248 | #endif |
Dmitry Kravkov | e3835b9 | 2011-03-06 10:50:44 +0000 | [diff] [blame] | 1249 | u32 pending_max; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1250 | }; |
| 1251 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1252 | /** |
| 1253 | * Init queue/func interface |
| 1254 | */ |
| 1255 | /* queue init flags */ |
| 1256 | #define QUEUE_FLG_TPA 0x0001 |
| 1257 | #define QUEUE_FLG_CACHE_ALIGN 0x0002 |
| 1258 | #define QUEUE_FLG_STATS 0x0004 |
| 1259 | #define QUEUE_FLG_OV 0x0008 |
| 1260 | #define QUEUE_FLG_VLAN 0x0010 |
| 1261 | #define QUEUE_FLG_COS 0x0020 |
| 1262 | #define QUEUE_FLG_HC 0x0040 |
| 1263 | #define QUEUE_FLG_DHC 0x0080 |
| 1264 | #define QUEUE_FLG_OOO 0x0100 |
| 1265 | |
| 1266 | #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR |
| 1267 | #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR |
| 1268 | #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 |
| 1269 | #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR |
| 1270 | |
| 1271 | |
| 1272 | |
| 1273 | /* rss capabilities */ |
| 1274 | #define RSS_IPV4_CAP 0x0001 |
| 1275 | #define RSS_IPV4_TCP_CAP 0x0002 |
| 1276 | #define RSS_IPV6_CAP 0x0004 |
| 1277 | #define RSS_IPV6_TCP_CAP 0x0008 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1278 | |
Vladislav Zolotarov | 54b9dda | 2009-11-16 06:05:58 +0000 | [diff] [blame] | 1279 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1280 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE) |
| 1281 | |
| 1282 | /* ethtool statistics are displayed for all regular ethernet queues and the |
| 1283 | * fcoe L2 queue if not disabled |
| 1284 | */ |
| 1285 | #define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \ |
| 1286 | (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE)) |
| 1287 | |
Vladislav Zolotarov | 54b9dda | 2009-11-16 06:05:58 +0000 | [diff] [blame] | 1288 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1289 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1290 | #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1291 | |
| 1292 | #define RSS_IPV4_CAP_MASK \ |
| 1293 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY |
| 1294 | |
| 1295 | #define RSS_IPV4_TCP_CAP_MASK \ |
| 1296 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY |
| 1297 | |
| 1298 | #define RSS_IPV6_CAP_MASK \ |
| 1299 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY |
| 1300 | |
| 1301 | #define RSS_IPV6_TCP_CAP_MASK \ |
| 1302 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY |
| 1303 | |
| 1304 | /* func init flags */ |
Dmitry Kravkov | 030f335 | 2010-10-17 23:08:53 +0000 | [diff] [blame] | 1305 | #define FUNC_FLG_STATS 0x0001 |
| 1306 | #define FUNC_FLG_TPA 0x0002 |
| 1307 | #define FUNC_FLG_SPQ 0x0004 |
| 1308 | #define FUNC_FLG_LEADING 0x0008 /* PF only */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1309 | |
| 1310 | struct rxq_pause_params { |
| 1311 | u16 bd_th_lo; |
| 1312 | u16 bd_th_hi; |
| 1313 | u16 rcq_th_lo; |
| 1314 | u16 rcq_th_hi; |
| 1315 | u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */ |
| 1316 | u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */ |
| 1317 | u16 pri_map; |
| 1318 | }; |
| 1319 | |
| 1320 | struct bnx2x_rxq_init_params { |
| 1321 | /* cxt*/ |
| 1322 | struct eth_context *cxt; |
| 1323 | |
| 1324 | /* dma */ |
| 1325 | dma_addr_t dscr_map; |
| 1326 | dma_addr_t sge_map; |
| 1327 | dma_addr_t rcq_map; |
| 1328 | dma_addr_t rcq_np_map; |
| 1329 | |
| 1330 | u16 flags; |
| 1331 | u16 drop_flags; |
| 1332 | u16 mtu; |
| 1333 | u16 buf_sz; |
| 1334 | u16 fw_sb_id; |
| 1335 | u16 cl_id; |
| 1336 | u16 spcl_id; |
| 1337 | u16 cl_qzone_id; |
| 1338 | |
| 1339 | /* valid iff QUEUE_FLG_STATS */ |
| 1340 | u16 stat_id; |
| 1341 | |
| 1342 | /* valid iff QUEUE_FLG_TPA */ |
| 1343 | u16 tpa_agg_sz; |
| 1344 | u16 sge_buf_sz; |
| 1345 | u16 max_sges_pkt; |
| 1346 | |
| 1347 | /* valid iff QUEUE_FLG_CACHE_ALIGN */ |
| 1348 | u8 cache_line_log; |
| 1349 | |
| 1350 | u8 sb_cq_index; |
| 1351 | u32 cid; |
| 1352 | |
| 1353 | /* desired interrupts per sec. valid iff QUEUE_FLG_HC */ |
| 1354 | u32 hc_rate; |
| 1355 | }; |
| 1356 | |
| 1357 | struct bnx2x_txq_init_params { |
| 1358 | /* cxt*/ |
| 1359 | struct eth_context *cxt; |
| 1360 | |
| 1361 | /* dma */ |
| 1362 | dma_addr_t dscr_map; |
| 1363 | |
| 1364 | u16 flags; |
| 1365 | u16 fw_sb_id; |
| 1366 | u8 sb_cq_index; |
| 1367 | u8 cos; /* valid iff QUEUE_FLG_COS */ |
| 1368 | u16 stat_id; /* valid iff QUEUE_FLG_STATS */ |
| 1369 | u16 traffic_type; |
| 1370 | u32 cid; |
| 1371 | u16 hc_rate; /* desired interrupts per sec.*/ |
| 1372 | /* valid iff QUEUE_FLG_HC */ |
| 1373 | |
| 1374 | }; |
| 1375 | |
| 1376 | struct bnx2x_client_ramrod_params { |
| 1377 | int *pstate; |
| 1378 | int state; |
| 1379 | u16 index; |
| 1380 | u16 cl_id; |
| 1381 | u32 cid; |
| 1382 | u8 poll; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1383 | #define CLIENT_IS_FCOE 0x01 |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1384 | #define CLIENT_IS_LEADING_RSS 0x02 |
| 1385 | u8 flags; |
| 1386 | }; |
| 1387 | |
| 1388 | struct bnx2x_client_init_params { |
| 1389 | struct rxq_pause_params pause; |
| 1390 | struct bnx2x_rxq_init_params rxq_params; |
| 1391 | struct bnx2x_txq_init_params txq_params; |
| 1392 | struct bnx2x_client_ramrod_params ramrod_params; |
| 1393 | }; |
| 1394 | |
| 1395 | struct bnx2x_rss_params { |
| 1396 | int mode; |
| 1397 | u16 cap; |
| 1398 | u16 result_mask; |
| 1399 | }; |
| 1400 | |
| 1401 | struct bnx2x_func_init_params { |
| 1402 | |
| 1403 | /* rss */ |
| 1404 | struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */ |
| 1405 | |
| 1406 | /* dma */ |
| 1407 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ |
| 1408 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ |
| 1409 | |
| 1410 | u16 func_flgs; |
| 1411 | u16 func_id; /* abs fid */ |
| 1412 | u16 pf_id; |
| 1413 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ |
| 1414 | }; |
| 1415 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1416 | #define for_each_eth_queue(bp, var) \ |
| 1417 | for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++) |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1418 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1419 | #define for_each_nondefault_eth_queue(bp, var) \ |
| 1420 | for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++) |
| 1421 | |
| 1422 | #define for_each_napi_queue(bp, var) \ |
| 1423 | for (var = 0; \ |
| 1424 | var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \ |
| 1425 | if (skip_queue(bp, var)) \ |
| 1426 | continue; \ |
| 1427 | else |
| 1428 | |
| 1429 | #define for_each_queue(bp, var) \ |
| 1430 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ |
| 1431 | if (skip_queue(bp, var)) \ |
| 1432 | continue; \ |
| 1433 | else |
| 1434 | |
| 1435 | #define for_each_rx_queue(bp, var) \ |
| 1436 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ |
| 1437 | if (skip_rx_queue(bp, var)) \ |
| 1438 | continue; \ |
| 1439 | else |
| 1440 | |
| 1441 | #define for_each_tx_queue(bp, var) \ |
| 1442 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ |
| 1443 | if (skip_tx_queue(bp, var)) \ |
| 1444 | continue; \ |
| 1445 | else |
| 1446 | |
| 1447 | #define for_each_nondefault_queue(bp, var) \ |
| 1448 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \ |
| 1449 | if (skip_queue(bp, var)) \ |
| 1450 | continue; \ |
| 1451 | else |
| 1452 | |
| 1453 | /* skip rx queue |
Linus Torvalds | 008d23e | 2011-01-13 10:05:56 -0800 | [diff] [blame] | 1454 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1455 | */ |
| 1456 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
| 1457 | |
| 1458 | /* skip tx queue |
Linus Torvalds | 008d23e | 2011-01-13 10:05:56 -0800 | [diff] [blame] | 1459 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1460 | */ |
| 1461 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
| 1462 | |
| 1463 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1464 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1465 | #define WAIT_RAMROD_POLL 0x01 |
| 1466 | #define WAIT_RAMROD_COMMON 0x02 |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1467 | |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 1468 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
| 1469 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1470 | /* dmae */ |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 1471 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
| 1472 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, |
| 1473 | u32 len32); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1474 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
| 1475 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); |
| 1476 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); |
| 1477 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
| 1478 | bool with_comp, u8 comp_type); |
| 1479 | |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 1480 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
Eilon Greenstein | 17de50b | 2008-08-13 15:56:59 -0700 | [diff] [blame] | 1481 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 1482 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 1483 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1484 | |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 1485 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
| 1486 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
| 1487 | u32 data_hi, u32 data_lo, int common); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 1488 | |
| 1489 | /* Clears multicast and unicast list configuration in the chip. */ |
| 1490 | void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp); |
| 1491 | void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp); |
| 1492 | void bnx2x_invalidate_uc_list(struct bnx2x *bp); |
| 1493 | |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 1494 | void bnx2x_update_coalesce(struct bnx2x *bp); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 1495 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1496 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1497 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
| 1498 | int wait) |
| 1499 | { |
| 1500 | u32 val; |
| 1501 | |
| 1502 | do { |
| 1503 | val = REG_RD(bp, reg); |
| 1504 | if (val == expected) |
| 1505 | break; |
| 1506 | ms -= wait; |
| 1507 | msleep(wait); |
| 1508 | |
| 1509 | } while (ms > 0); |
| 1510 | |
| 1511 | return val; |
| 1512 | } |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1513 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1514 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
| 1515 | do { \ |
Vladislav Zolotarov | d245a11 | 2010-12-08 01:43:17 +0000 | [diff] [blame] | 1516 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1517 | if (x) \ |
| 1518 | memset(x, 0, size); \ |
| 1519 | } while (0) |
| 1520 | |
| 1521 | #define BNX2X_ILT_FREE(x, y, size) \ |
| 1522 | do { \ |
| 1523 | if (x) { \ |
Vladislav Zolotarov | d245a11 | 2010-12-08 01:43:17 +0000 | [diff] [blame] | 1524 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1525 | x = NULL; \ |
| 1526 | y = 0; \ |
| 1527 | } \ |
| 1528 | } while (0) |
| 1529 | |
| 1530 | #define ILOG2(x) (ilog2((x))) |
| 1531 | |
| 1532 | #define ILT_NUM_PAGE_ENTRIES (3072) |
| 1533 | /* In 57710/11 we use whole table since we have 8 func |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1534 | * In 57712 we have only 4 func, but use same size per func, then only half of |
| 1535 | * the table in use |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1536 | */ |
| 1537 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) |
| 1538 | |
| 1539 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) |
| 1540 | /* |
| 1541 | * the phys address is shifted right 12 bits and has an added |
| 1542 | * 1=valid bit added to the 53rd bit |
| 1543 | * then since this is a wide register(TM) |
| 1544 | * we split it into two 32 bit writes |
| 1545 | */ |
| 1546 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) |
| 1547 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1548 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1549 | /* load/unload mode */ |
| 1550 | #define LOAD_NORMAL 0 |
| 1551 | #define LOAD_OPEN 1 |
| 1552 | #define LOAD_DIAG 2 |
| 1553 | #define UNLOAD_NORMAL 0 |
| 1554 | #define UNLOAD_CLOSE 1 |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1555 | #define UNLOAD_RECOVERY 2 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1556 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1557 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1558 | /* DMAE command defines */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1559 | #define DMAE_TIMEOUT -1 |
| 1560 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ |
| 1561 | #define DMAE_NOT_RDY -3 |
| 1562 | #define DMAE_PCI_ERR_FLAG 0x80000000 |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1563 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1564 | #define DMAE_SRC_PCI 0 |
| 1565 | #define DMAE_SRC_GRC 1 |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1566 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1567 | #define DMAE_DST_NONE 0 |
| 1568 | #define DMAE_DST_PCI 1 |
| 1569 | #define DMAE_DST_GRC 2 |
| 1570 | |
| 1571 | #define DMAE_COMP_PCI 0 |
| 1572 | #define DMAE_COMP_GRC 1 |
| 1573 | |
| 1574 | /* E2 and onward - PCI error handling in the completion */ |
| 1575 | |
| 1576 | #define DMAE_COMP_REGULAR 0 |
| 1577 | #define DMAE_COM_SET_ERR 1 |
| 1578 | |
| 1579 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
| 1580 | DMAE_COMMAND_SRC_SHIFT) |
| 1581 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ |
| 1582 | DMAE_COMMAND_SRC_SHIFT) |
| 1583 | |
| 1584 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
| 1585 | DMAE_COMMAND_DST_SHIFT) |
| 1586 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ |
| 1587 | DMAE_COMMAND_DST_SHIFT) |
| 1588 | |
| 1589 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ |
| 1590 | DMAE_COMMAND_C_DST_SHIFT) |
| 1591 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ |
| 1592 | DMAE_COMMAND_C_DST_SHIFT) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1593 | |
| 1594 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE |
| 1595 | |
| 1596 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 1597 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 1598 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 1599 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 1600 | |
| 1601 | #define DMAE_CMD_PORT_0 0 |
| 1602 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT |
| 1603 | |
| 1604 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET |
| 1605 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET |
| 1606 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT |
| 1607 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1608 | #define DMAE_SRC_PF 0 |
| 1609 | #define DMAE_SRC_VF 1 |
| 1610 | |
| 1611 | #define DMAE_DST_PF 0 |
| 1612 | #define DMAE_DST_VF 1 |
| 1613 | |
| 1614 | #define DMAE_C_SRC 0 |
| 1615 | #define DMAE_C_DST 1 |
| 1616 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1617 | #define DMAE_LEN32_RD_MAX 0x80 |
Vladislav Zolotarov | 02e3c6c | 2010-04-19 01:13:33 +0000 | [diff] [blame] | 1618 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1619 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1620 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
| 1621 | indicates eror */ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1622 | |
| 1623 | #define MAX_DMAE_C_PER_PORT 8 |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1624 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1625 | BP_E1HVN(bp)) |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1626 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 1627 | E1HVN_MAX) |
| 1628 | |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 1629 | /* PCIE link and speed */ |
| 1630 | #define PCICFG_LINK_WIDTH 0x1f00000 |
| 1631 | #define PCICFG_LINK_WIDTH_SHIFT 20 |
| 1632 | #define PCICFG_LINK_SPEED 0xf0000 |
| 1633 | #define PCICFG_LINK_SPEED_SHIFT 16 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1634 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1635 | |
Eilon Greenstein | d3d4f49 | 2009-02-12 08:36:27 +0000 | [diff] [blame] | 1636 | #define BNX2X_NUM_TESTS 7 |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1637 | |
Eilon Greenstein | b5bf906 | 2009-02-12 08:38:08 +0000 | [diff] [blame] | 1638 | #define BNX2X_PHY_LOOPBACK 0 |
| 1639 | #define BNX2X_MAC_LOOPBACK 1 |
| 1640 | #define BNX2X_PHY_LOOPBACK_FAILED 1 |
| 1641 | #define BNX2X_MAC_LOOPBACK_FAILED 2 |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 1642 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
| 1643 | BNX2X_PHY_LOOPBACK_FAILED) |
Eliezer Tamir | 96fc178 | 2008-02-28 11:57:55 -0800 | [diff] [blame] | 1644 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 1645 | |
| 1646 | #define STROM_ASSERT_ARRAY_SIZE 50 |
| 1647 | |
Eliezer Tamir | 96fc178 | 2008-02-28 11:57:55 -0800 | [diff] [blame] | 1648 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1649 | /* must be used on a CID before placing it on a HW ring */ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1650 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
| 1651 | (BP_E1HVN(bp) << 17) | (x)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1652 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 1653 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
| 1654 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
| 1655 | |
| 1656 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1657 | #define BNX2X_BTR 4 |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 1658 | #define MAX_SPQ_PENDING 8 |
| 1659 | |
Dmitry Kravkov | ff80ee0 | 2011-02-28 03:37:11 +0000 | [diff] [blame] | 1660 | /* CMNG constants, as derived from system spec calculations */ |
| 1661 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ |
| 1662 | #define DEF_MIN_RATE 100 |
Dmitry Kravkov | 9b3de1e | 2011-03-06 10:51:37 +0000 | [diff] [blame] | 1663 | /* resolution of the rate shaping timer - 400 usec */ |
| 1664 | #define RS_PERIODIC_TIMEOUT_USEC 400 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1665 | /* number of bytes in single QM arbitration cycle - |
Dmitry Kravkov | ff80ee0 | 2011-02-28 03:37:11 +0000 | [diff] [blame] | 1666 | * coefficient for calculating the fairness timer */ |
| 1667 | #define QM_ARB_BYTES 160000 |
| 1668 | /* resolution of Min algorithm 1:100 */ |
| 1669 | #define MIN_RES 100 |
| 1670 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ |
| 1671 | #define MIN_ABOVE_THRESH 32768 |
| 1672 | /* Fairness algorithm integration time coefficient - |
| 1673 | * for calculating the actual Tfair */ |
| 1674 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) |
| 1675 | /* Memory of fairness algorithm . 2 cycles */ |
| 1676 | #define FAIR_MEM 2 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1677 | |
| 1678 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1679 | #define ATTN_NIG_FOR_FUNC (1L << 8) |
| 1680 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) |
| 1681 | #define GPIO_2_FUNC (1L << 10) |
| 1682 | #define GPIO_3_FUNC (1L << 11) |
| 1683 | #define GPIO_4_FUNC (1L << 12) |
| 1684 | #define ATTN_GENERAL_ATTN_1 (1L << 13) |
| 1685 | #define ATTN_GENERAL_ATTN_2 (1L << 14) |
| 1686 | #define ATTN_GENERAL_ATTN_3 (1L << 15) |
| 1687 | #define ATTN_GENERAL_ATTN_4 (1L << 13) |
| 1688 | #define ATTN_GENERAL_ATTN_5 (1L << 14) |
| 1689 | #define ATTN_GENERAL_ATTN_6 (1L << 15) |
| 1690 | |
| 1691 | #define ATTN_HARD_WIRED_MASK 0xff00 |
| 1692 | #define ATTENTION_ID 4 |
| 1693 | |
| 1694 | |
| 1695 | /* stuff added to make the code fit 80Col */ |
| 1696 | |
| 1697 | #define BNX2X_PMF_LINK_ASSERT \ |
| 1698 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) |
| 1699 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1700 | #define BNX2X_MC_ASSERT_BITS \ |
| 1701 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 1702 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 1703 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 1704 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) |
| 1705 | |
| 1706 | #define BNX2X_MCP_ASSERT \ |
| 1707 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
| 1708 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1709 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
| 1710 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ |
| 1711 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ |
| 1712 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ |
| 1713 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ |
| 1714 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ |
| 1715 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) |
| 1716 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1717 | #define HW_INTERRUT_ASSERT_SET_0 \ |
| 1718 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ |
| 1719 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ |
| 1720 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ |
| 1721 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1722 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1723 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
| 1724 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ |
| 1725 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ |
| 1726 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) |
| 1727 | #define HW_INTERRUT_ASSERT_SET_1 \ |
| 1728 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ |
| 1729 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ |
| 1730 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ |
| 1731 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ |
| 1732 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ |
| 1733 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ |
| 1734 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ |
| 1735 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ |
| 1736 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ |
| 1737 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ |
| 1738 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1739 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1740 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
| 1741 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
| 1742 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 1743 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
| 1744 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1745 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
| 1746 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ |
| 1747 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
| 1748 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ |
| 1749 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) |
| 1750 | #define HW_INTERRUT_ASSERT_SET_2 \ |
| 1751 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ |
| 1752 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ |
| 1753 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ |
| 1754 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ |
| 1755 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1756 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1757 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
| 1758 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ |
| 1759 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ |
| 1760 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ |
| 1761 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
| 1762 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) |
| 1763 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1764 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
| 1765 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ |
| 1766 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ |
| 1767 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1768 | |
Tom Herbert | c68ed25 | 2010-04-23 00:10:52 -0700 | [diff] [blame] | 1769 | #define RSS_FLAGS(bp) \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1770 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
| 1771 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ |
| 1772 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ |
| 1773 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ |
Eilon Greenstein | 555f6c7 | 2009-02-12 08:36:11 +0000 | [diff] [blame] | 1774 | (bp->multi_mode << \ |
| 1775 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1776 | #define MULTI_MASK 0x7f |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1777 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1778 | #define BNX2X_SP_DSB_INDEX \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1779 | (&bp->def_status_blk->sp_sb.\ |
| 1780 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1781 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1782 | #define SET_FLAG(value, mask, flag) \ |
| 1783 | do {\ |
| 1784 | (value) &= ~(mask);\ |
| 1785 | (value) |= ((flag) << (mask##_SHIFT));\ |
| 1786 | } while (0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1787 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1788 | #define GET_FLAG(value, mask) \ |
| 1789 | (((value) &= (mask)) >> (mask##_SHIFT)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1790 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1791 | #define GET_FIELD(value, fname) \ |
| 1792 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) |
| 1793 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1794 | #define CAM_IS_INVALID(x) \ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1795 | (GET_FLAG(x.flags, \ |
| 1796 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ |
| 1797 | (T_ETH_MAC_COMMAND_INVALIDATE)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1798 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1799 | /* Number of u32 elements in MC hash array */ |
| 1800 | #define MC_HASH_SIZE 8 |
| 1801 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ |
| 1802 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) |
| 1803 | |
| 1804 | |
| 1805 | #ifndef PXP2_REG_PXP2_INT_STS |
| 1806 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 |
| 1807 | #endif |
| 1808 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1809 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
| 1810 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H |
| 1811 | #endif |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 1812 | |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 1813 | #define BNX2X_VPD_LEN 128 |
| 1814 | #define VENDOR_ID_LEN 4 |
| 1815 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1816 | /* Congestion management fairness mode */ |
| 1817 | #define CMNG_FNS_NONE 0 |
| 1818 | #define CMNG_FNS_MINMAX 1 |
| 1819 | |
| 1820 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ |
| 1821 | #define HC_SEG_ACCESS_ATTN 4 |
| 1822 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ |
| 1823 | |
Dmitry Kravkov | b0efbb9 | 2010-07-27 12:33:43 +0000 | [diff] [blame] | 1824 | #ifdef BNX2X_MAIN |
| 1825 | #define BNX2X_EXTERN |
| 1826 | #else |
| 1827 | #define BNX2X_EXTERN extern |
| 1828 | #endif |
| 1829 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1830 | BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */ |
Dmitry Kravkov | b0efbb9 | 2010-07-27 12:33:43 +0000 | [diff] [blame] | 1831 | |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 1832 | extern void bnx2x_set_ethtool_ops(struct net_device *netdev); |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 1833 | void bnx2x_push_indir_table(struct bnx2x *bp); |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 1834 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1835 | #endif /* bnx2x.h */ |