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Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/bitops.h>
19#include <linux/io.h>
20#include <linux/spinlock.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/clkdev.h>
24#include <linux/string.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28
29#include "clock.h"
30#include "clock-local.h"
31#include "clock-pcom.h"
32#include "clock-voter.h"
33#include "proc_comm.h"
34
35#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
36#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
37
38/* Shadow-region 2 (SH2) registers. */
39#define QUP_I2C_NS_REG REG(0x04F0)
40#define CAM_NS_REG REG(0x0374)
41#define CAM_VFE_NS_REG REG(0x0044)
42#define CLK_HALT_STATEA_REG REG(0x0108)
43#define CLK_HALT_STATEB_REG REG(0x010C)
44#define CLK_HALT_STATEC_REG REG(0x02D4)
45#define CSI_NS_REG REG(0x0174)
46#define EMDH_NS_REG REG(0x0050)
47#define GLBL_CLK_ENA_2_SC_REG REG(0x03C0)
48#define GLBL_CLK_ENA_SC_REG REG(0x03BC)
49#define GLBL_CLK_STATE_2_REG REG(0x037C)
50#define GLBL_CLK_STATE_REG REG(0x0004)
51#define GRP_2D_NS_REG REG(0x0034)
52#define GRP_NS_REG REG(0x0084)
53#define HDMI_NS_REG REG(0x0484)
54#define I2C_2_NS_REG REG(0x02D8)
55#define I2C_NS_REG REG(0x0068)
56#define JPEG_NS_REG REG(0x0164)
57#define LPA_CORE_CLK_MA0_REG REG(0x04F4)
58#define LPA_CORE_CLK_MA2_REG REG(0x04FC)
59#define LPA_NS_REG REG(0x02E8)
60#define MDC_NS_REG REG(0x007C)
61#define MDP_LCDC_NS_REG REG(0x0390)
62#define MDP_NS_REG REG(0x014C)
63#define MDP_VSYNC_REG REG(0x0460)
64#define MFC_NS_REG REG(0x0154)
65#define MI2S_CODEC_RX_DIV_REG REG(0x02EC)
66#define MI2S_CODEC_TX_DIV_REG REG(0x02F0)
67#define MI2S_DIV_REG REG(0x02E4)
68#define MI2S_NS_REG REG(0x02E0)
69#define MI2S_RX_NS_REG REG(0x0070)
70#define MI2S_TX_NS_REG REG(0x0078)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#define PLL_ENA_REG REG(0x0264)
72#define PMDH_NS_REG REG(0x008C)
73#define SDAC_NS_REG REG(0x009C)
74#define SDCn_NS_REG(n) REG(0x00A4+(0x8*((n)-1)))
75#define SPI_NS_REG REG(0x02C8)
76#define TSIF_NS_REG REG(0x00C4)
77#define TV_NS_REG REG(0x00CC)
78#define UART1DM_NS_REG REG(0x00D4)
79#define UART2DM_NS_REG REG(0x00DC)
80#define UART2_NS_REG REG(0x0464)
81#define UART_NS_REG REG(0x00E0)
82#define USBH2_NS_REG REG(0x046C)
83#define USBH3_NS_REG REG(0x0470)
84#define USBH_MD_REG REG(0x02BC)
85#define USBH_NS_REG REG(0x02C0)
86#define VPE_NS_REG REG(0x015C)
87
88/* Registers in the base (non-shadow) region. */
89#define CLK_TEST_BASE_REG REG_BASE(0x011C)
90#define CLK_TEST_2_BASE_REG REG_BASE(0x0384)
91#define MISC_CLK_CTL_BASE_REG REG_BASE(0x0110)
92#define PRPH_WEB_NS_BASE_REG REG_BASE(0x0080)
93#define PLL0_STATUS_BASE_REG REG_BASE(0x0318)
94#define PLL1_STATUS_BASE_REG REG_BASE(0x0334)
95#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
96#define PLL3_STATUS_BASE_REG REG_BASE(0x036C)
97#define PLL4_STATUS_BASE_REG REG_BASE(0x0254)
98#define PLL5_STATUS_BASE_REG REG_BASE(0x0258)
99#define PLL6_STATUS_BASE_REG REG_BASE(0x04EC)
100#define RINGOSC_CNT_BASE_REG REG_BASE(0x00FC)
101#define SH2_OWN_APPS1_BASE_REG REG_BASE(0x040C)
102#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414)
103#define SH2_OWN_APPS3_BASE_REG REG_BASE(0x0444)
104#define SH2_OWN_GLBL_BASE_REG REG_BASE(0x0404)
105#define SH2_OWN_ROW1_BASE_REG REG_BASE(0x041C)
106#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
107#define TCXO_CNT_BASE_REG REG_BASE(0x00F8)
108#define TCXO_CNT_DONE_BASE_REG REG_BASE(0x00F8)
109
110
111/* MUX source input identifiers. */
112#define SRC_SEL_pll0 4 /* Modem PLL */
113#define SRC_SEL_pll1 1 /* Global PLL */
114#define SRC_SEL_pll3 3 /* Multimedia/Peripheral PLL or Backup PLL1 */
115#define SRC_SEL_pll4 2 /* Display PLL */
116#define SRC_SEL_SDAC_lpxo 5 /* Low-power XO for SDAC */
117#define SRC_SEL_lpxo 6 /* Low-power XO */
118#define SRC_SEL_tcxo 0 /* Used for rates from TCXO */
119#define SRC_SEL_axi 0 /* Used for rates that sync to AXI */
120#define SRC_SEL_gnd 7 /* No clock */
121
122/* Clock declaration macros. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700123#define N8(msb, lsb, m, n) (BVAL(msb, lsb, ~(n-m)) | BVAL(6, 5, \
124 (MN_MODE_DUAL_EDGE * !!(n))))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700125#define N16(m, n) (BVAL(31, 16, ~(n-m)) | BVAL(6, 5, \
126 (MN_MODE_DUAL_EDGE * !!(n))))
127#define SPDIV(s, d) (BVAL(4, 3, d-1) | BVAL(2, 0, s))
128#define SDIV(s, d) (BVAL(6, 3, d-1) | BVAL(2, 0, s))
129#define F_MASK_BASIC (BM(6, 3)|BM(2, 0))
130#define F_MASK_MND16 (BM(31, 16)|BM(6, 5)|BM(4, 3)|BM(2, 0))
131#define F_MASK_MND8(m, l) (BM(m, l)|BM(6, 5)|BM(4, 3)|BM(2, 0))
132
133/*
134 * Clock frequency definitions and macros
135 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700136#define F_BASIC(f, s, div) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700137 { \
138 .freq_hz = f, \
139 .src_clk = &s##_clk.c, \
140 .ns_val = SDIV(SRC_SEL_##s, div), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141 }
142
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700143#define F_MND16(f, s, div, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700144 { \
145 .freq_hz = f, \
146 .src_clk = &s##_clk.c, \
147 .md_val = MD16(m, n), \
148 .ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700149 }
150
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700151#define F_MND8(f, nmsb, nlsb, s, div, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700152 { \
153 .freq_hz = f, \
154 .src_clk = &s##_clk.c, \
Stephen Boydd10d2642012-01-23 18:09:00 -0800155 .md_val = MD8(8, m, 0, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700156 .ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700157 }
158
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700159static struct clk_ops clk_ops_rcg_7x30;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700160
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700161enum vdd_dig_levels {
162 VDD_DIG_NONE,
163 VDD_DIG_LOW,
164 VDD_DIG_NOMINAL,
165 VDD_DIG_HIGH
166};
167
168static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
169{
170 int rc, target_mv;
171
172 static const int mv[] = {
173 [VDD_DIG_NONE] = 1000,
174 [VDD_DIG_LOW] = 1000,
175 [VDD_DIG_NOMINAL] = 1100,
176 [VDD_DIG_HIGH] = 1200
177 };
178
179 target_mv = mv[level];
180 rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
181 if (rc)
182 return rc;
183 if (target_mv)
184 rc = -EINVAL;
185
186 return rc;
187}
188
189static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
190
191#define VDD_DIG_FMAX_MAP1(l1, f1) \
192 .vdd_class = &vdd_dig, \
193 .fmax[VDD_DIG_##l1] = (f1)
194#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
195 .vdd_class = &vdd_dig, \
196 .fmax[VDD_DIG_##l1] = (f1), \
197 .fmax[VDD_DIG_##l2] = (f2)
198
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700199#define PCOM_XO_DISABLE 0
200#define PCOM_XO_ENABLE 1
201#define PCOM_XO_TCXO 0
202#define PCOM_XO_LPXO 1
203
204static bool pcom_is_local(struct clk *clk)
205{
206 return false;
207}
208
209static int pcom_xo_enable(unsigned pcom_id, unsigned enable)
210{
211 /* TODO: Check return code in pcom_id */
212 return msm_proc_comm(PCOM_CLKCTL_RPC_SRC_REQUEST, &pcom_id, &enable);
213}
214
215static int tcxo_clk_enable(struct clk *clk)
216{
217 return pcom_xo_enable(PCOM_XO_TCXO, PCOM_XO_ENABLE);
218}
219
220static void tcxo_clk_disable(struct clk *clk)
221{
222 pcom_xo_enable(PCOM_XO_TCXO, PCOM_XO_DISABLE);
223}
224
225static struct clk_ops clk_ops_tcxo = {
226 .enable = tcxo_clk_enable,
227 .disable = tcxo_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700228 .is_local = pcom_is_local,
229};
230
231static struct fixed_clk tcxo_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232 .c = {
233 .dbg_name = "tcxo_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800234 .rate = 19200000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700235 .ops = &clk_ops_tcxo,
236 CLK_INIT(tcxo_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800237 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700238 },
239};
240
241static int lpxo_clk_enable(struct clk *clk)
242{
243 return pcom_xo_enable(PCOM_XO_LPXO, PCOM_XO_ENABLE);
244}
245
246static void lpxo_clk_disable(struct clk *clk)
247{
248 pcom_xo_enable(PCOM_XO_LPXO, PCOM_XO_DISABLE);
249}
250
251static struct clk_ops clk_ops_lpxo = {
252 .enable = lpxo_clk_enable,
253 .disable = lpxo_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700254 .is_local = pcom_is_local,
255};
256
257static struct fixed_clk lpxo_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700258 .c = {
259 .dbg_name = "lpxo_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800260 .rate = 24576000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700261 .ops = &clk_ops_lpxo,
262 CLK_INIT(lpxo_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800263 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700264 },
265};
266
267static struct pll_vote_clk pll1_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700268 .en_reg = PLL_ENA_REG,
269 .en_mask = BIT(1),
270 .status_reg = PLL1_STATUS_BASE_REG,
271 .parent = &tcxo_clk.c,
272 .c = {
273 .dbg_name = "pll1_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800274 .rate = 768000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700275 .ops = &clk_ops_pll_vote,
276 CLK_INIT(pll1_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800277 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700278 },
279};
280
281static struct pll_vote_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700282 .en_reg = PLL_ENA_REG,
283 .en_mask = BIT(2),
284 .status_reg = PLL2_STATUS_BASE_REG,
285 .parent = &tcxo_clk.c,
286 .c = {
287 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800288 .rate = 806400000, /* TODO: Support scaling */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700289 .ops = &clk_ops_pll_vote,
290 CLK_INIT(pll2_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800291 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700292 },
293};
294
295static struct pll_vote_clk pll3_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700296 .en_reg = PLL_ENA_REG,
297 .en_mask = BIT(3),
298 .status_reg = PLL3_STATUS_BASE_REG,
299 .parent = &lpxo_clk.c,
300 .c = {
301 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800302 .rate = 737280000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700303 .ops = &clk_ops_pll_vote,
304 CLK_INIT(pll3_clk.c),
305 },
306};
307
308static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700309 .en_reg = PLL_ENA_REG,
310 .en_mask = BIT(4),
311 .status_reg = PLL4_STATUS_BASE_REG,
312 .parent = &lpxo_clk.c,
313 .c = {
314 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800315 .rate = 891000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700316 .ops = &clk_ops_pll_vote,
317 CLK_INIT(pll4_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800318 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700319 },
320};
321
322static struct clk_ops clk_ops_branch;
323
324static struct clk_freq_tbl clk_tbl_axi[] = {
Matt Wagantall07c45472012-02-10 23:27:24 -0800325 F_RAW(1, &lpxo_clk.c, 0, 0, 0, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700326 F_END,
327};
328
329/* For global clocks to be on we must have GLBL_ROOT_ENA set */
330static struct rcg_clk glbl_root_clk = {
331 .b = {
332 .ctl_reg = GLBL_CLK_ENA_SC_REG,
333 .en_mask = BIT(29),
334 .halt_check = NOCHECK,
335 },
336 .freq_tbl = clk_tbl_axi,
337 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700338 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700339 .set_rate = set_rate_nop,
340 .c = {
341 .dbg_name = "glbl_root_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700342 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700343 VDD_DIG_FMAX_MAP1(NOMINAL, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700344 CLK_INIT(glbl_root_clk.c),
345 },
346};
347
348/* AXI bridge clocks. */
349static struct branch_clk axi_li_apps_clk = {
350 .b = {
351 .ctl_reg = GLBL_CLK_ENA_SC_REG,
352 .en_mask = BIT(2),
353 .halt_reg = GLBL_CLK_STATE_REG,
354 .halt_check = HALT_VOTED,
355 .halt_bit = 2,
356 },
357 .parent = &glbl_root_clk.c,
358 .c = {
359 .dbg_name = "axi_li_apps_clk",
360 .ops = &clk_ops_branch,
361 CLK_INIT(axi_li_apps_clk.c),
362 },
363};
364
365static struct branch_clk axi_li_adsp_a_clk = {
366 .b = {
367 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
368 .en_mask = BIT(14),
369 .halt_reg = GLBL_CLK_STATE_2_REG,
370 .halt_check = HALT_VOTED,
371 .halt_bit = 14,
372 },
373 .parent = &axi_li_apps_clk.c,
374 .c = {
375 .dbg_name = "axi_li_adsp_a_clk",
376 .ops = &clk_ops_branch,
377 CLK_INIT(axi_li_adsp_a_clk.c),
378 },
379};
380
381static struct branch_clk axi_li_jpeg_clk = {
382 .b = {
383 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
384 .en_mask = BIT(19),
385 .halt_reg = GLBL_CLK_STATE_2_REG,
386 .halt_check = HALT_VOTED,
387 .halt_bit = 19,
388 },
389 .parent = &axi_li_apps_clk.c,
390 .c = {
391 .dbg_name = "axi_li_jpeg_clk",
392 .ops = &clk_ops_branch,
393 CLK_INIT(axi_li_jpeg_clk.c),
394 },
395};
396
397static struct branch_clk axi_li_vfe_clk = {
398 .b = {
399 .ctl_reg = GLBL_CLK_ENA_SC_REG,
400 .en_mask = BIT(23),
401 .halt_reg = GLBL_CLK_STATE_REG,
402 .halt_check = HALT_VOTED,
403 .halt_bit = 23,
404 },
405 .parent = &axi_li_apps_clk.c,
406 .c = {
407 .dbg_name = "axi_li_vfe_clk",
408 .ops = &clk_ops_branch,
409 CLK_INIT(axi_li_vfe_clk.c),
410 },
411};
412
413static struct branch_clk axi_mdp_clk = {
414 .b = {
415 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
416 .en_mask = BIT(29),
417 .halt_reg = GLBL_CLK_STATE_2_REG,
418 .halt_check = HALT_VOTED,
419 .halt_bit = 29,
420 },
421 .parent = &axi_li_apps_clk.c,
422 .c = {
423 .dbg_name = "axi_mdp_clk",
424 .ops = &clk_ops_branch,
425 CLK_INIT(axi_mdp_clk.c),
426 },
427};
428
429static struct branch_clk axi_li_vg_clk = {
430 .b = {
431 .ctl_reg = GLBL_CLK_ENA_SC_REG,
432 .en_mask = BIT(3),
433 .halt_reg = GLBL_CLK_STATE_REG,
434 .halt_check = HALT_VOTED,
435 .halt_bit = 3,
436 },
437 .parent = &glbl_root_clk.c,
438 .c = {
439 .dbg_name = "axi_li_vg_clk",
440 .ops = &clk_ops_branch,
441 CLK_INIT(axi_li_vg_clk.c),
442 },
443};
444
445static struct branch_clk axi_grp_2d_clk = {
446 .b = {
447 .ctl_reg = GLBL_CLK_ENA_SC_REG,
448 .en_mask = BIT(21),
449 .halt_reg = GLBL_CLK_STATE_REG,
450 .halt_check = HALT_VOTED,
451 .halt_bit = 21,
452 },
453 .parent = &axi_li_vg_clk.c,
454 .c = {
455 .dbg_name = "axi_grp_2d_clk",
456 .ops = &clk_ops_branch,
457 CLK_INIT(axi_grp_2d_clk.c),
458 },
459};
460
461static struct branch_clk axi_li_grp_clk = {
462 .b = {
463 .ctl_reg = GLBL_CLK_ENA_SC_REG,
464 .en_mask = BIT(22),
465 .halt_reg = GLBL_CLK_STATE_REG,
466 .halt_check = HALT_VOTED,
467 .halt_bit = 22,
468 },
469 .parent = &axi_li_vg_clk.c,
470 .c = {
471 .dbg_name = "axi_li_grp_clk",
472 .ops = &clk_ops_branch,
473 CLK_INIT(axi_li_grp_clk.c),
474 },
475};
476
477static struct branch_clk axi_mfc_clk = {
478 .b = {
479 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
480 .en_mask = BIT(20),
481 .halt_reg = GLBL_CLK_STATE_2_REG,
482 .halt_check = HALT_VOTED,
483 .halt_bit = 20,
484 },
485 .parent = &axi_li_vg_clk.c,
486 .c = {
487 .dbg_name = "axi_mfc_clk",
488 .ops = &clk_ops_branch,
489 CLK_INIT(axi_mfc_clk.c),
490 },
491};
492
493static struct branch_clk axi_rotator_clk = {
494 .b = {
495 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
496 .en_mask = BIT(22),
497 .halt_reg = GLBL_CLK_STATE_2_REG,
498 .halt_check = HALT_VOTED,
499 .halt_bit = 22,
500 .reset_mask = P_AXI_ROTATOR_CLK,
501 },
502 .parent = &axi_li_vg_clk.c,
503 .c = {
504 .dbg_name = "axi_rotator_clk",
505 .ops = &clk_ops_branch,
506 CLK_INIT(axi_rotator_clk.c),
507 },
508};
509
510static struct branch_clk axi_vpe_clk = {
511 .b = {
512 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
513 .en_mask = BIT(21),
514 .halt_reg = GLBL_CLK_STATE_2_REG,
515 .halt_check = HALT_VOTED,
516 .halt_bit = 21,
517 },
518 .parent = &axi_li_vg_clk.c,
519 .c = {
520 .dbg_name = "axi_vpe_clk",
521 .ops = &clk_ops_branch,
522 CLK_INIT(axi_vpe_clk.c),
523 },
524};
525
526/* Peripheral bus clocks. */
527static struct branch_clk adm_clk = {
528 .b = {
529 .ctl_reg = GLBL_CLK_ENA_SC_REG,
530 .en_mask = BIT(5),
531 .halt_reg = GLBL_CLK_STATE_REG,
532 .halt_check = HALT_VOTED,
533 .halt_bit = 5,
534 .reset_mask = P_ADM_CLK,
535 },
536 .parent = &axi_li_apps_clk.c,
537 .c = {
538 .dbg_name = "adm_clk",
539 .ops = &clk_ops_branch,
540 CLK_INIT(adm_clk.c),
541 },
542};
543
544static struct branch_clk adm_p_clk = {
545 .b = {
546 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
547 .en_mask = BIT(15),
548 .halt_reg = GLBL_CLK_STATE_2_REG,
549 .halt_check = HALT_VOTED,
550 .halt_bit = 15,
551 },
552 .parent = &glbl_root_clk.c,
553 .c = {
554 .dbg_name = "adm_p_clk",
555 .ops = &clk_ops_branch,
556 CLK_INIT(adm_p_clk.c),
557 },
558};
559
560static struct branch_clk ce_clk = {
561 .b = {
562 .ctl_reg = GLBL_CLK_ENA_SC_REG,
563 .en_mask = BIT(6),
564 .halt_reg = GLBL_CLK_STATE_REG,
565 .halt_check = HALT_VOTED,
566 .halt_bit = 6,
567 .reset_mask = P_CE_CLK,
568 },
569 .parent = &glbl_root_clk.c,
570 .c = {
571 .dbg_name = "ce_clk",
572 .ops = &clk_ops_branch,
573 CLK_INIT(ce_clk.c),
574 },
575};
576
577static struct branch_clk camif_pad_p_clk = {
578 .b = {
579 .ctl_reg = GLBL_CLK_ENA_SC_REG,
580 .en_mask = BIT(9),
581 .halt_reg = GLBL_CLK_STATE_REG,
582 .halt_check = HALT_VOTED,
583 .halt_bit = 9,
584 .reset_mask = P_CAMIF_PAD_P_CLK,
585 },
586 .parent = &glbl_root_clk.c,
587 .c = {
588 .dbg_name = "camif_pad_p_clk",
589 .ops = &clk_ops_branch,
590 CLK_INIT(camif_pad_p_clk.c),
591 },
592};
593
594static struct branch_clk csi0_p_clk = {
595 .b = {
596 .ctl_reg = GLBL_CLK_ENA_SC_REG,
597 .en_mask = BIT(30),
598 .halt_reg = GLBL_CLK_STATE_REG,
599 .halt_check = HALT_VOTED,
600 .halt_bit = 30,
601 .reset_mask = P_CSI0_P_CLK,
602 },
603 .parent = &glbl_root_clk.c,
604 .c = {
605 .dbg_name = "csi0_p_clk",
606 .ops = &clk_ops_branch,
607 CLK_INIT(csi0_p_clk.c),
608 },
609};
610
611static struct branch_clk emdh_p_clk = {
612 .b = {
613 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
614 .en_mask = BIT(3),
615 .halt_reg = GLBL_CLK_STATE_2_REG,
616 .halt_check = HALT_VOTED,
617 .halt_bit = 3,
618 .reset_mask = P_EMDH_P_CLK,
619 },
620 .parent = &glbl_root_clk.c,
621 .c = {
622 .dbg_name = "emdh_p_clk",
623 .ops = &clk_ops_branch,
624 CLK_INIT(emdh_p_clk.c),
625 },
626};
627
628static struct branch_clk grp_2d_p_clk = {
629 .b = {
630 .ctl_reg = GLBL_CLK_ENA_SC_REG,
631 .en_mask = BIT(24),
632 .halt_reg = GLBL_CLK_STATE_REG,
633 .halt_check = HALT_VOTED,
634 .halt_bit = 24,
635 .reset_mask = P_GRP_2D_P_CLK,
636 },
637 .parent = &glbl_root_clk.c,
638 .c = {
639 .dbg_name = "grp_2d_p_clk",
640 .ops = &clk_ops_branch,
641 CLK_INIT(grp_2d_p_clk.c),
642 },
643};
644
645static struct branch_clk grp_3d_p_clk = {
646 .b = {
647 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
648 .en_mask = BIT(17),
649 .halt_reg = GLBL_CLK_STATE_2_REG,
650 .halt_check = HALT_VOTED,
651 .halt_bit = 17,
652 .reset_mask = P_GRP_3D_P_CLK,
653 },
654 .parent = &glbl_root_clk.c,
655 .c = {
656 .dbg_name = "grp_3d_p_clk",
657 .ops = &clk_ops_branch,
658 CLK_INIT(grp_3d_p_clk.c),
659 },
660};
661
662static struct branch_clk jpeg_p_clk = {
663 .b = {
664 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
665 .en_mask = BIT(24),
666 .halt_reg = GLBL_CLK_STATE_2_REG,
667 .halt_check = HALT_VOTED,
668 .halt_bit = 24,
669 .reset_mask = P_JPEG_P_CLK,
670 },
671 .parent = &glbl_root_clk.c,
672 .c = {
673 .dbg_name = "jpeg_p_clk",
674 .ops = &clk_ops_branch,
675 CLK_INIT(jpeg_p_clk.c),
676 },
677};
678
679static struct branch_clk lpa_p_clk = {
680 .b = {
681 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
682 .en_mask = BIT(7),
683 .halt_reg = GLBL_CLK_STATE_2_REG,
684 .halt_check = HALT_VOTED,
685 .halt_bit = 7,
686 .reset_mask = P_LPA_P_CLK,
687 },
688 .parent = &glbl_root_clk.c,
689 .c = {
690 .dbg_name = "lpa_p_clk",
691 .ops = &clk_ops_branch,
692 CLK_INIT(lpa_p_clk.c),
693 },
694};
695
696static struct branch_clk mdp_p_clk = {
697 .b = {
698 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
699 .en_mask = BIT(6),
700 .halt_reg = GLBL_CLK_STATE_2_REG,
701 .halt_check = HALT_VOTED,
702 .halt_bit = 6,
703 .reset_mask = P_MDP_P_CLK,
704 },
705 .parent = &glbl_root_clk.c,
706 .c = {
707 .dbg_name = "mdp_p_clk",
708 .ops = &clk_ops_branch,
709 CLK_INIT(mdp_p_clk.c),
710 },
711};
712
713static struct branch_clk mfc_p_clk = {
714 .b = {
715 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
716 .en_mask = BIT(26),
717 .halt_reg = GLBL_CLK_STATE_2_REG,
718 .halt_check = HALT_VOTED,
719 .halt_bit = 26,
720 .reset_mask = P_MFC_P_CLK,
721 },
722 .parent = &glbl_root_clk.c,
723 .c = {
724 .dbg_name = "mfc_p_clk",
725 .ops = &clk_ops_branch,
726 CLK_INIT(mfc_p_clk.c),
727 },
728};
729
730static struct branch_clk pmdh_p_clk = {
731 .b = {
732 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
733 .en_mask = BIT(4),
734 .halt_reg = GLBL_CLK_STATE_2_REG,
735 .halt_check = HALT_VOTED,
736 .halt_bit = 4,
737 .reset_mask = P_PMDH_P_CLK,
738 },
739 .parent = &glbl_root_clk.c,
740 .c = {
741 .dbg_name = "pmdh_p_clk",
742 .ops = &clk_ops_branch,
743 CLK_INIT(pmdh_p_clk.c),
744 },
745};
746
747static struct branch_clk rotator_imem_clk = {
748 .b = {
749 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
750 .en_mask = BIT(23),
751 .halt_reg = GLBL_CLK_STATE_2_REG,
752 .halt_check = HALT_VOTED,
753 .halt_bit = 23,
754 .reset_mask = P_ROTATOR_IMEM_CLK,
755 },
756 .parent = &glbl_root_clk.c,
757 .c = {
758 .dbg_name = "rotator_imem_clk",
759 .ops = &clk_ops_branch,
760 CLK_INIT(rotator_imem_clk.c),
761 },
762};
763
764static struct branch_clk rotator_p_clk = {
765 .b = {
766 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
767 .en_mask = BIT(25),
768 .halt_reg = GLBL_CLK_STATE_2_REG,
769 .halt_check = HALT_VOTED,
770 .halt_bit = 25,
771 .reset_mask = P_ROTATOR_P_CLK,
772 },
773 .parent = &glbl_root_clk.c,
774 .c = {
775 .dbg_name = "rotator_p_clk",
776 .ops = &clk_ops_branch,
777 CLK_INIT(rotator_p_clk.c),
778 },
779};
780
781static struct branch_clk sdc1_p_clk = {
782 .b = {
783 .ctl_reg = GLBL_CLK_ENA_SC_REG,
784 .en_mask = BIT(7),
785 .halt_reg = GLBL_CLK_STATE_REG,
786 .halt_check = HALT_VOTED,
787 .halt_bit = 7,
788 .reset_mask = P_SDC1_P_CLK,
789 },
790 .parent = &glbl_root_clk.c,
791 .c = {
792 .dbg_name = "sdc1_p_clk",
793 .ops = &clk_ops_branch,
794 CLK_INIT(sdc1_p_clk.c),
795 },
796};
797
798static struct branch_clk sdc2_p_clk = {
799 .b = {
800 .ctl_reg = GLBL_CLK_ENA_SC_REG,
801 .en_mask = BIT(8),
802 .halt_reg = GLBL_CLK_STATE_REG,
803 .halt_check = HALT_VOTED,
804 .halt_bit = 8,
805 .reset_mask = P_SDC2_P_CLK,
806 },
807 .parent = &glbl_root_clk.c,
808 .c = {
809 .dbg_name = "sdc2_p_clk",
810 .ops = &clk_ops_branch,
811 CLK_INIT(sdc2_p_clk.c),
812 },
813};
814
815static struct branch_clk sdc3_p_clk = {
816 .b = {
817 .ctl_reg = GLBL_CLK_ENA_SC_REG,
818 .en_mask = BIT(27),
819 .halt_reg = GLBL_CLK_STATE_REG,
820 .halt_check = HALT_VOTED,
821 .halt_bit = 27,
822 .reset_mask = P_SDC3_P_CLK,
823 },
824 .parent = &glbl_root_clk.c,
825 .c = {
826 .dbg_name = "sdc3_p_clk",
827 .ops = &clk_ops_branch,
828 CLK_INIT(sdc3_p_clk.c),
829 },
830};
831
832static struct branch_clk sdc4_p_clk = {
833 .b = {
834 .ctl_reg = GLBL_CLK_ENA_SC_REG,
835 .en_mask = BIT(28),
836 .halt_reg = GLBL_CLK_STATE_REG,
837 .halt_check = HALT_VOTED,
838 .halt_bit = 28,
839 .reset_mask = P_SDC4_P_CLK,
840 },
841 .parent = &glbl_root_clk.c,
842 .c = {
843 .dbg_name = "sdc4_p_clk",
844 .ops = &clk_ops_branch,
845 CLK_INIT(sdc4_p_clk.c),
846 },
847};
848
849static struct branch_clk spi_p_clk = {
850 .b = {
851 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
852 .en_mask = BIT(10),
853 .halt_reg = GLBL_CLK_STATE_2_REG,
854 .halt_check = HALT_VOTED,
855 .halt_bit = 10,
856 .reset_mask = P_SPI_P_CLK,
857 },
858 .parent = &glbl_root_clk.c,
859 .c = {
860 .dbg_name = "spi_p_clk",
861 .ops = &clk_ops_branch,
862 CLK_INIT(spi_p_clk.c),
863 },
864};
865
866static struct branch_clk tsif_p_clk = {
867 .b = {
868 .ctl_reg = GLBL_CLK_ENA_SC_REG,
869 .en_mask = BIT(18),
870 .halt_reg = GLBL_CLK_STATE_REG,
871 .halt_check = HALT_VOTED,
872 .halt_bit = 18,
873 .reset_mask = P_TSIF_P_CLK,
874 },
875 .parent = &glbl_root_clk.c,
876 .c = {
877 .dbg_name = "tsif_p_clk",
878 .ops = &clk_ops_branch,
879 CLK_INIT(tsif_p_clk.c),
880 },
881};
882
883static struct branch_clk uart1dm_p_clk = {
884 .b = {
885 .ctl_reg = GLBL_CLK_ENA_SC_REG,
886 .en_mask = BIT(17),
887 .halt_reg = GLBL_CLK_STATE_REG,
888 .halt_check = HALT_VOTED,
889 .halt_bit = 17,
890 },
891 .parent = &glbl_root_clk.c,
892 .c = {
893 .dbg_name = "uart1dm_p_clk",
894 .ops = &clk_ops_branch,
895 CLK_INIT(uart1dm_p_clk.c),
896 },
897};
898
899static struct branch_clk uart2dm_p_clk = {
900 .b = {
901 .ctl_reg = GLBL_CLK_ENA_SC_REG,
902 .en_mask = BIT(26),
903 .halt_reg = GLBL_CLK_STATE_REG,
904 .halt_check = HALT_VOTED,
905 .halt_bit = 26,
906 },
907 .parent = &glbl_root_clk.c,
908 .c = {
909 .dbg_name = "uart2dm_p_clk",
910 .ops = &clk_ops_branch,
911 CLK_INIT(uart2dm_p_clk.c),
912 },
913};
914
915static struct branch_clk usb_hs2_p_clk = {
916 .b = {
917 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
918 .en_mask = BIT(8),
919 .halt_reg = GLBL_CLK_STATE_2_REG,
920 .halt_check = HALT_VOTED,
921 .halt_bit = 8,
922 .reset_mask = P_USB_HS2_P_CLK,
923 },
924 .parent = &glbl_root_clk.c,
925 .c = {
926 .dbg_name = "usb_hs2_p_clk",
927 .ops = &clk_ops_branch,
928 CLK_INIT(usb_hs2_p_clk.c),
929 },
930};
931
932static struct branch_clk usb_hs3_p_clk = {
933 .b = {
934 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
935 .en_mask = BIT(9),
936 .halt_reg = GLBL_CLK_STATE_2_REG,
937 .halt_check = HALT_VOTED,
938 .halt_bit = 9,
939 .reset_mask = P_USB_HS3_P_CLK,
940 },
941 .parent = &glbl_root_clk.c,
942 .c = {
943 .dbg_name = "usb_hs3_p_clk",
944 .ops = &clk_ops_branch,
945 CLK_INIT(usb_hs3_p_clk.c),
946 },
947};
948
949static struct branch_clk usb_hs_p_clk = {
950 .b = {
951 .ctl_reg = GLBL_CLK_ENA_SC_REG,
952 .en_mask = BIT(25),
953 .halt_reg = GLBL_CLK_STATE_REG,
954 .halt_check = HALT_VOTED,
955 .halt_bit = 25,
956 .reset_mask = P_USB_HS_P_CLK,
957 },
958 .parent = &glbl_root_clk.c,
959 .c = {
960 .dbg_name = "usb_hs_p_clk",
961 .ops = &clk_ops_branch,
962 CLK_INIT(usb_hs_p_clk.c),
963 },
964};
965
966static struct branch_clk vfe_p_clk = {
967 .b = {
968 .ctl_reg = GLBL_CLK_ENA_2_SC_REG,
969 .en_mask = BIT(27),
970 .halt_reg = GLBL_CLK_STATE_2_REG,
971 .halt_check = HALT_VOTED,
972 .halt_bit = 27,
973 .reset_mask = P_VFE_P_CLK,
974 },
975 .parent = &glbl_root_clk.c,
976 .c = {
977 .dbg_name = "vfe_p_clk",
978 .ops = &clk_ops_branch,
979 CLK_INIT(vfe_p_clk.c),
980 },
981};
982
983static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700984 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
985 F_MND8(153600000, 24, 17, pll1, 2, 2, 5),
986 F_MND8(192000000, 24, 17, pll1, 4, 0, 0),
987 F_MND8(384000000, 24, 17, pll1, 2, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700988 F_END,
989};
990
991static struct rcg_clk csi0_clk = {
992 .b = {
993 .ctl_reg = CSI_NS_REG,
994 .en_mask = BIT(9),
995 .halt_reg = CLK_HALT_STATEC_REG,
996 .halt_bit = 17,
997 .reset_mask = P_CSI0_CLK,
998 },
999 .ns_reg = CSI_NS_REG,
1000 .md_reg = CSI_NS_REG - 4,
1001 .ns_mask = F_MASK_MND8(24, 17),
Matt Wagantall07c45472012-02-10 23:27:24 -08001002 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001003 .root_en_mask = BIT(11),
1004 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001005 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001006 .set_rate = set_rate_mnd,
1007 .c = {
1008 .dbg_name = "csi0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001009 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001010 VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001011 CLK_INIT(csi0_clk.c),
1012 },
1013};
1014
1015static struct clk_freq_tbl clk_tbl_tcxo[] = {
Matt Wagantall07c45472012-02-10 23:27:24 -08001016 F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001017 F_END,
1018};
1019
1020static struct rcg_clk i2c_clk = {
1021 .b = {
1022 .ctl_reg = I2C_NS_REG,
1023 .en_mask = BIT(9),
1024 .halt_reg = CLK_HALT_STATEA_REG,
1025 .halt_bit = 15,
1026 .reset_mask = P_I2C_CLK,
1027 },
1028 .set_rate = set_rate_nop,
1029 .freq_tbl = clk_tbl_tcxo,
1030 .root_en_mask = BIT(11),
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001031 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001032 .c = {
1033 .dbg_name = "i2c_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001034 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001035 VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001036 CLK_INIT(i2c_clk.c),
1037 },
1038};
1039
1040static struct rcg_clk i2c_2_clk = {
1041 .b = {
1042 .ctl_reg = I2C_2_NS_REG,
1043 .en_mask = BIT(0),
1044 .halt_reg = CLK_HALT_STATEC_REG,
1045 .halt_bit = 2,
1046 .reset_mask = P_I2C_2_CLK,
1047 },
1048 .root_en_mask = BIT(2),
1049 .freq_tbl = clk_tbl_tcxo,
1050 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001051 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001052 .c = {
1053 .dbg_name = "i2c_2_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001054 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001055 VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001056 CLK_INIT(i2c_2_clk.c),
1057 },
1058};
1059
1060static struct rcg_clk qup_i2c_clk = {
1061 .b = {
1062 .ctl_reg = QUP_I2C_NS_REG,
1063 .en_mask = BIT(0),
1064 .halt_reg = CLK_HALT_STATEB_REG,
1065 .halt_bit = 31,
1066 .reset_mask = P_QUP_I2C_CLK,
1067 },
1068 .root_en_mask = BIT(2),
1069 .freq_tbl = clk_tbl_tcxo,
1070 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001071 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001072 .c = {
1073 .dbg_name = "qup_i2c_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001074 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001075 VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001076 CLK_INIT(qup_i2c_clk.c),
1077 },
1078};
1079
1080static struct rcg_clk uart1_clk = {
1081 .b = {
1082 .ctl_reg = UART_NS_REG,
1083 .en_mask = BIT(5),
1084 .halt_reg = CLK_HALT_STATEB_REG,
1085 .halt_bit = 7,
1086 .reset_mask = P_UART1_CLK,
1087 },
1088 .root_en_mask = BIT(4),
1089 .freq_tbl = clk_tbl_tcxo,
1090 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001091 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001092 .c = {
1093 .dbg_name = "uart1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001094 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001095 VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001096 CLK_INIT(uart1_clk.c),
1097 },
1098};
1099
1100static struct rcg_clk uart2_clk = {
1101 .b = {
1102 .ctl_reg = UART2_NS_REG,
1103 .en_mask = BIT(5),
1104 .halt_reg = CLK_HALT_STATEB_REG,
1105 .halt_bit = 5,
1106 .reset_mask = P_UART2_CLK,
1107 },
1108 .root_en_mask = BIT(4),
1109 .freq_tbl = clk_tbl_tcxo,
1110 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001111 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001112 .c = {
1113 .dbg_name = "uart2_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001114 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001115 VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001116 CLK_INIT(uart2_clk.c),
1117 },
1118};
1119
1120static struct clk_freq_tbl clk_tbl_uartdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001121 F_MND16( 0, gnd, 1, 0, 0),
1122 F_MND16( 3686400, pll3, 3, 3, 200),
1123 F_MND16( 7372800, pll3, 3, 3, 100),
1124 F_MND16(14745600, pll3, 3, 3, 50),
1125 F_MND16(32000000, pll3, 3, 25, 192),
1126 F_MND16(40000000, pll3, 3, 125, 768),
1127 F_MND16(46400000, pll3, 3, 145, 768),
1128 F_MND16(48000000, pll3, 3, 25, 128),
1129 F_MND16(51200000, pll3, 3, 5, 24),
1130 F_MND16(56000000, pll3, 3, 175, 768),
1131 F_MND16(58982400, pll3, 3, 6, 25),
1132 F_MND16(64000000, pll1, 4, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001133 F_END,
1134};
1135
1136static struct rcg_clk uart1dm_clk = {
1137 .b = {
1138 .ctl_reg = UART1DM_NS_REG,
1139 .en_mask = BIT(9),
1140 .halt_reg = CLK_HALT_STATEB_REG,
1141 .halt_bit = 6,
1142 .reset_mask = P_UART1DM_CLK,
1143 },
1144 .ns_reg = UART1DM_NS_REG,
1145 .md_reg = UART1DM_NS_REG - 4,
1146 .root_en_mask = BIT(11),
Matt Wagantall07c45472012-02-10 23:27:24 -08001147 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001148 .freq_tbl = clk_tbl_uartdm,
1149 .ns_mask = F_MASK_MND16,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001150 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001151 .set_rate = set_rate_mnd,
1152 .c = {
1153 .dbg_name = "uart1dm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001154 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001155 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001156 CLK_INIT(uart1dm_clk.c),
1157 },
1158};
1159
1160static struct rcg_clk uart2dm_clk = {
1161 .b = {
1162 .ctl_reg = UART2DM_NS_REG,
1163 .en_mask = BIT(9),
1164 .halt_reg = CLK_HALT_STATEB_REG,
1165 .halt_bit = 23,
1166 .reset_mask = P_UART2DM_CLK,
1167 },
1168 .ns_reg = UART2DM_NS_REG,
1169 .md_reg = UART2DM_NS_REG - 4,
1170 .root_en_mask = BIT(11),
1171 .freq_tbl = clk_tbl_uartdm,
1172 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08001173 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001174 .set_rate = set_rate_mnd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001175 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001176 .c = {
1177 .dbg_name = "uart2dm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001178 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001179 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001180 CLK_INIT(uart2dm_clk.c),
1181 },
1182};
1183
1184static struct clk_freq_tbl clk_tbl_mdh[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001185 F_BASIC( 0, gnd, 1),
1186 F_BASIC( 49150000, pll3, 15),
1187 F_BASIC( 92160000, pll3, 8),
1188 F_BASIC(122880000, pll3, 6),
1189 F_BASIC(184320000, pll3, 4),
1190 F_BASIC(245760000, pll3, 3),
1191 F_BASIC(368640000, pll3, 2),
1192 F_BASIC(384000000, pll1, 2),
1193 F_BASIC(445500000, pll4, 2),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001194 F_END,
1195};
1196
1197static struct rcg_clk emdh_clk = {
1198 .b = {
1199 .ctl_reg = EMDH_NS_REG,
1200 .halt_check = DELAY,
1201 .reset_mask = P_EMDH_CLK,
1202 },
1203 .root_en_mask = BIT(11),
1204 .ns_reg = EMDH_NS_REG,
1205 .ns_mask = F_MASK_BASIC,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001206 .set_rate = set_rate_nop,
1207 .freq_tbl = clk_tbl_mdh,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001208 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001209 .c = {
1210 .dbg_name = "emdh_clk",
1211 .flags = CLKFLAG_MIN | CLKFLAG_MAX,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001212 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001213 VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001214 CLK_INIT(emdh_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001215 .depends = &axi_li_adsp_a_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001216 },
1217};
1218
1219static struct rcg_clk pmdh_clk = {
1220 .b = {
1221 .ctl_reg = PMDH_NS_REG,
1222 .halt_check = DELAY,
1223 .reset_mask = P_PMDH_CLK,
1224 },
1225 .root_en_mask = BIT(11),
1226 .ns_reg = PMDH_NS_REG,
1227 .ns_mask = F_MASK_BASIC,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001228 .set_rate = set_rate_nop,
1229 .freq_tbl = clk_tbl_mdh,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001230 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001231 .c = {
1232 .dbg_name = "pmdh_clk",
1233 .flags = CLKFLAG_MIN | CLKFLAG_MAX,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001234 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001235 VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001236 CLK_INIT(pmdh_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001237 .depends = &axi_li_adsp_a_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001238 },
1239};
1240
1241static struct clk_freq_tbl clk_tbl_grp[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001242 F_BASIC( 24576000, lpxo, 1),
1243 F_BASIC( 46080000, pll3, 16),
1244 F_BASIC( 49152000, pll3, 15),
1245 F_BASIC( 52662875, pll3, 14),
1246 F_BASIC( 56713846, pll3, 13),
1247 F_BASIC( 61440000, pll3, 12),
1248 F_BASIC( 67025454, pll3, 11),
1249 F_BASIC( 73728000, pll3, 10),
1250 F_BASIC( 81920000, pll3, 9),
1251 F_BASIC( 92160000, pll3, 8),
1252 F_BASIC(105325714, pll3, 7),
1253 F_BASIC(122880000, pll3, 6),
1254 F_BASIC(147456000, pll3, 5),
1255 F_BASIC(184320000, pll3, 4),
1256 F_BASIC(192000000, pll1, 4),
1257 F_BASIC(245760000, pll3, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001258 /* Sync to AXI. Hence this "rate" is not fixed. */
Matt Wagantall07c45472012-02-10 23:27:24 -08001259 F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001260 F_END,
1261};
1262
1263static struct rcg_clk grp_2d_clk = {
1264 .b = {
1265 .ctl_reg = GRP_2D_NS_REG,
1266 .en_mask = BIT(7),
1267 .halt_reg = CLK_HALT_STATEA_REG,
1268 .halt_bit = 31,
1269 .reset_mask = P_GRP_2D_CLK,
1270 },
1271 .ns_reg = GRP_2D_NS_REG,
1272 .root_en_mask = BIT(11),
1273 .ns_mask = F_MASK_BASIC | (7 << 12),
1274 .set_rate = set_rate_nop,
1275 .freq_tbl = clk_tbl_grp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001276 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001277 .c = {
1278 .dbg_name = "grp_2d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001279 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001280 VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001281 CLK_INIT(grp_2d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001282 .depends = &axi_grp_2d_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001283 },
1284};
1285
1286static struct rcg_clk grp_3d_src_clk = {
1287 .ns_reg = GRP_NS_REG,
1288 .b = {
1289 .ctl_reg = GRP_NS_REG,
1290 .halt_check = NOCHECK,
1291 },
1292 .root_en_mask = BIT(11),
1293 .ns_mask = F_MASK_BASIC | (7 << 12),
1294 .set_rate = set_rate_nop,
1295 .freq_tbl = clk_tbl_grp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001296 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001297 .c = {
1298 .dbg_name = "grp_3d_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001299 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001300 VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001301 CLK_INIT(grp_3d_src_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001302 .depends = &axi_li_grp_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001303 },
1304};
1305
1306static struct branch_clk grp_3d_clk = {
1307 .b = {
1308 .ctl_reg = GRP_NS_REG,
1309 .en_mask = BIT(7),
1310 .halt_reg = CLK_HALT_STATEB_REG,
1311 .halt_bit = 18,
1312 .reset_mask = P_GRP_3D_CLK,
1313 },
1314 .parent = &grp_3d_src_clk.c,
1315 .c = {
1316 .dbg_name = "grp_3d_clk",
1317 .ops = &clk_ops_branch,
1318 CLK_INIT(grp_3d_clk.c),
1319 },
1320};
1321
1322static struct branch_clk imem_clk = {
1323 .b = {
1324 .ctl_reg = GRP_NS_REG,
1325 .en_mask = BIT(9),
1326 .halt_reg = CLK_HALT_STATEB_REG,
1327 .halt_bit = 19,
1328 .reset_mask = P_IMEM_CLK,
1329 },
1330 .parent = &grp_3d_src_clk.c,
1331 .c = {
1332 .dbg_name = "imem_clk",
1333 .ops = &clk_ops_branch,
1334 CLK_INIT(imem_clk.c),
1335 },
1336};
1337
1338static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001339 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
1340 F_MND8( 144000, 19, 12, lpxo, 1, 1, 171),
1341 F_MND8( 400000, 19, 12, lpxo, 1, 2, 123),
1342 F_MND8(16027000, 19, 12, pll3, 3, 14, 215),
1343 F_MND8(17000000, 19, 12, pll3, 4, 19, 206),
1344 F_MND8(20480000, 19, 12, pll3, 4, 23, 212),
1345 F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
1346 F_MND8(49152000, 19, 12, pll3, 3, 1, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001347 F_END,
1348};
1349
1350static struct rcg_clk sdc1_clk = {
1351 .b = {
1352 .ctl_reg = SDCn_NS_REG(1),
1353 .en_mask = BIT(9),
1354 .halt_reg = CLK_HALT_STATEA_REG,
1355 .halt_bit = 1,
1356 .reset_mask = P_SDC1_CLK,
1357 },
1358 .ns_reg = SDCn_NS_REG(1),
1359 .md_reg = SDCn_NS_REG(1) - 4,
1360 .ns_mask = F_MASK_MND8(19, 12),
Matt Wagantall07c45472012-02-10 23:27:24 -08001361 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001362 .root_en_mask = BIT(11),
1363 .freq_tbl = clk_tbl_sdc1_3,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001364 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001365 .set_rate = set_rate_mnd,
1366 .c = {
1367 .dbg_name = "sdc1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001368 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001369 VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001370 CLK_INIT(sdc1_clk.c),
1371 },
1372};
1373
1374static struct rcg_clk sdc3_clk = {
1375 .b = {
1376 .ctl_reg = SDCn_NS_REG(3),
1377 .en_mask = BIT(9),
1378 .halt_reg = CLK_HALT_STATEB_REG,
1379 .halt_bit = 24,
1380 .reset_mask = P_SDC3_CLK,
1381 },
1382 .ns_reg = SDCn_NS_REG(3),
1383 .md_reg = SDCn_NS_REG(3) - 4,
1384 .ns_mask = F_MASK_MND8(19, 12),
Matt Wagantall07c45472012-02-10 23:27:24 -08001385 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001386 .root_en_mask = BIT(11),
1387 .freq_tbl = clk_tbl_sdc1_3,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001388 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001389 .set_rate = set_rate_mnd,
1390 .c = {
1391 .dbg_name = "sdc3_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001392 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001393 VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001394 CLK_INIT(sdc3_clk.c),
1395 },
1396};
1397
1398static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001399 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
1400 F_MND8( 144000, 20, 13, lpxo, 1, 1, 171),
1401 F_MND8( 400000, 20, 13, lpxo, 1, 2, 123),
1402 F_MND8(16027000, 20, 13, pll3, 3, 14, 215),
1403 F_MND8(17000000, 20, 13, pll3, 4, 19, 206),
1404 F_MND8(20480000, 20, 13, pll3, 4, 23, 212),
1405 F_MND8(24576000, 20, 13, lpxo, 1, 0, 0),
1406 F_MND8(49152000, 20, 13, pll3, 3, 1, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001407 F_END,
1408};
1409
1410static struct rcg_clk sdc2_clk = {
1411 .b = {
1412 .ctl_reg = SDCn_NS_REG(2),
1413 .en_mask = BIT(9),
1414 .halt_reg = CLK_HALT_STATEA_REG,
1415 .halt_bit = 0,
1416 .reset_mask = P_SDC2_CLK,
1417 },
1418 .ns_reg = SDCn_NS_REG(2),
1419 .md_reg = SDCn_NS_REG(2) - 4,
1420 .ns_mask = F_MASK_MND8(20, 13),
Matt Wagantall07c45472012-02-10 23:27:24 -08001421 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001422 .root_en_mask = BIT(11),
1423 .freq_tbl = clk_tbl_sdc2_4,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001424 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001425 .set_rate = set_rate_mnd,
1426 .c = {
1427 .dbg_name = "sdc2_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001428 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001429 VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001430 CLK_INIT(sdc2_clk.c),
1431 },
1432};
1433
1434static struct rcg_clk sdc4_clk = {
1435 .b = {
1436 .ctl_reg = SDCn_NS_REG(4),
1437 .en_mask = BIT(9),
1438 .halt_reg = CLK_HALT_STATEB_REG,
1439 .halt_bit = 25,
1440 .reset_mask = P_SDC4_CLK,
1441 },
1442 .ns_reg = SDCn_NS_REG(4),
1443 .md_reg = SDCn_NS_REG(4) - 4,
1444 .ns_mask = F_MASK_MND8(20, 13),
Matt Wagantall07c45472012-02-10 23:27:24 -08001445 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001446 .root_en_mask = BIT(11),
1447 .freq_tbl = clk_tbl_sdc2_4,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001448 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001449 .set_rate = set_rate_mnd,
1450 .c = {
1451 .dbg_name = "sdc4_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001452 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001453 VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001454 CLK_INIT(sdc4_clk.c),
1455 },
1456};
1457
1458static struct clk_freq_tbl clk_tbl_mdp_core[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001459 F_BASIC( 24576000, lpxo, 1),
1460 F_BASIC( 46080000, pll3, 16),
1461 F_BASIC( 49152000, pll3, 15),
1462 F_BASIC( 52663000, pll3, 14),
1463 F_BASIC( 92160000, pll3, 8),
1464 F_BASIC(122880000, pll3, 6),
1465 F_BASIC(147456000, pll3, 5),
1466 F_BASIC(153600000, pll1, 5),
1467 F_BASIC(192000000, pll1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001468 F_END,
1469};
1470
1471static struct rcg_clk mdp_clk = {
1472 .b = {
1473 .ctl_reg = MDP_NS_REG,
1474 .en_mask = BIT(9),
1475 .halt_reg = CLK_HALT_STATEB_REG,
1476 .halt_bit = 16,
1477 .reset_mask = P_MDP_CLK,
1478 },
1479 .ns_reg = MDP_NS_REG,
1480 .root_en_mask = BIT(11),
1481 .ns_mask = F_MASK_BASIC,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001482 .set_rate = set_rate_nop,
1483 .freq_tbl = clk_tbl_mdp_core,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001484 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001485 .c = {
1486 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001487 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001488 VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001489 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001490 .depends = &axi_mdp_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001491 },
1492};
1493
1494static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001495 F_MND16( 0, gnd, 1, 0, 0),
1496 F_MND16(24576000, lpxo, 1, 0, 0),
1497 F_MND16(30720000, pll3, 4, 1, 6),
1498 F_MND16(32768000, pll3, 3, 2, 15),
1499 F_MND16(40960000, pll3, 2, 1, 9),
1500 F_MND16(73728000, pll3, 2, 1, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001501 F_END,
1502};
1503
1504static struct rcg_clk mdp_lcdc_pclk_clk = {
1505 .b = {
1506 .ctl_reg = MDP_LCDC_NS_REG,
1507 .en_mask = BIT(9),
1508 .halt_reg = CLK_HALT_STATEB_REG,
1509 .halt_bit = 28,
1510 .reset_mask = P_MDP_LCDC_PCLK_CLK,
1511 },
1512 .ns_reg = MDP_LCDC_NS_REG,
1513 .md_reg = MDP_LCDC_NS_REG - 4,
1514 .root_en_mask = BIT(11),
1515 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08001516 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001517 .set_rate = set_rate_mnd,
1518 .freq_tbl = clk_tbl_mdp_lcdc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001519 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001520 .c = {
1521 .dbg_name = "mdp_lcdc_pclk_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001522 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001523 VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001524 CLK_INIT(mdp_lcdc_pclk_clk.c),
1525 },
1526};
1527
1528static struct branch_clk mdp_lcdc_pad_pclk_clk = {
1529 .b = {
1530 .ctl_reg = MDP_LCDC_NS_REG,
1531 .en_mask = BIT(12),
1532 .halt_reg = CLK_HALT_STATEB_REG,
1533 .halt_bit = 29,
1534 .reset_mask = P_MDP_LCDC_PAD_PCLK_CLK,
1535 },
1536 .parent = &mdp_lcdc_pclk_clk.c,
1537 .c = {
1538 .dbg_name = "mdp_lcdc_pad_pclk_clk",
1539 .ops = &clk_ops_branch,
1540 CLK_INIT(mdp_lcdc_pad_pclk_clk.c),
1541 },
1542};
1543
1544static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantall07c45472012-02-10 23:27:24 -08001545 F_RAW( 0, &gnd_clk.c, 0, (0x3<<2), 0, NULL),
1546 F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001547 F_END,
1548};
1549
1550static struct rcg_clk mdp_vsync_clk = {
1551 .b = {
1552 .ctl_reg = MDP_VSYNC_REG,
1553 .en_mask = BIT(0),
1554 .halt_reg = CLK_HALT_STATEB_REG,
1555 .halt_bit = 30,
1556 .reset_mask = P_MDP_VSYNC_CLK,
1557 },
1558 .ns_reg = MDP_VSYNC_REG,
1559 .ns_mask = BM(3, 2),
1560 .freq_tbl = clk_tbl_mdp_vsync,
1561 .set_rate = set_rate_nop,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001562 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001563 .c = {
1564 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001565 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001566 VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001567 CLK_INIT(mdp_vsync_clk.c),
1568 },
1569};
1570
1571static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001572 F_MND16( 0, gnd, 1, 0, 0),
1573 F_MND16( 2048000, lpxo, 4, 1, 3),
1574 F_MND16(12288000, lpxo, 2, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001575 F_END,
1576};
1577
1578static struct rcg_clk mi2s_codec_rx_m_clk = {
1579 .b = {
1580 .ctl_reg = MI2S_RX_NS_REG,
1581 .en_mask = BIT(12),
1582 .halt_reg = CLK_HALT_STATEA_REG,
1583 .halt_bit = 12,
1584 .reset_mask = P_MI2S_CODEC_RX_M_CLK,
1585 },
1586 .ns_reg = MI2S_RX_NS_REG,
1587 .md_reg = MI2S_RX_NS_REG - 4,
1588 .root_en_mask = BIT(11),
1589 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08001590 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001591 .set_rate = set_rate_mnd,
1592 .freq_tbl = clk_tbl_mi2s_codec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001593 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001594 .c = {
1595 .dbg_name = "mi2s_codec_rx_m_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001596 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001597 VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001598 CLK_INIT(mi2s_codec_rx_m_clk.c),
1599 },
1600};
1601
1602static struct branch_clk mi2s_codec_rx_s_clk = {
1603 .b = {
1604 .ctl_reg = MI2S_RX_NS_REG,
1605 .en_mask = BIT(9),
1606 .halt_reg = CLK_HALT_STATEA_REG,
1607 .halt_bit = 13,
1608 .reset_mask = P_MI2S_CODEC_RX_S_CLK,
1609 },
1610 .parent = &mi2s_codec_rx_m_clk.c,
1611 .c = {
1612 .dbg_name = "mi2s_codec_rx_s_clk",
1613 .ops = &clk_ops_branch,
1614 CLK_INIT(mi2s_codec_rx_s_clk.c),
1615 },
1616};
1617
1618static struct rcg_clk mi2s_codec_tx_m_clk = {
1619 .b = {
1620 .ctl_reg = MI2S_TX_NS_REG,
1621 .en_mask = BIT(12),
1622 .halt_reg = CLK_HALT_STATEC_REG,
1623 .halt_bit = 8,
1624 .reset_mask = P_MI2S_CODEC_TX_M_CLK,
1625 },
1626 .ns_reg = MI2S_TX_NS_REG,
1627 .md_reg = MI2S_TX_NS_REG - 4,
1628 .root_en_mask = BIT(11),
1629 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08001630 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001631 .set_rate = set_rate_mnd,
1632 .freq_tbl = clk_tbl_mi2s_codec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001633 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001634 .c = {
1635 .dbg_name = "mi2s_codec_tx_m_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001636 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001637 VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001638 CLK_INIT(mi2s_codec_tx_m_clk.c),
1639 },
1640};
1641
1642static struct branch_clk mi2s_codec_tx_s_clk = {
1643 .b = {
1644 .ctl_reg = MI2S_TX_NS_REG,
1645 .en_mask = BIT(9),
1646 .halt_reg = CLK_HALT_STATEA_REG,
1647 .halt_bit = 11,
1648 .reset_mask = P_MI2S_CODEC_TX_S_CLK,
1649 },
1650 .parent = &mi2s_codec_tx_m_clk.c,
1651 .c = {
1652 .dbg_name = "mi2s_codec_tx_s_clk",
1653 .ops = &clk_ops_branch,
1654 CLK_INIT(mi2s_codec_tx_s_clk.c),
1655 },
1656};
1657
1658static struct clk_freq_tbl clk_tbl_mi2s[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001659 F_MND16( 0, gnd, 1, 0, 0),
1660 F_MND16(12288000, lpxo, 2, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001661 F_END,
1662};
1663
1664static struct rcg_clk mi2s_m_clk = {
1665 .b = {
1666 .ctl_reg = MI2S_NS_REG,
1667 .en_mask = BIT(12),
1668 .halt_reg = CLK_HALT_STATEC_REG,
1669 .halt_bit = 4,
1670 .reset_mask = P_MI2S_M_CLK,
1671 },
1672 .ns_reg = MI2S_NS_REG,
1673 .md_reg = MI2S_NS_REG - 4,
1674 .root_en_mask = BIT(11),
1675 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08001676 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001677 .set_rate = set_rate_mnd,
1678 .freq_tbl = clk_tbl_mi2s,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001679 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001680 .c = {
1681 .dbg_name = "mi2s_m_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001682 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001683 VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001684 CLK_INIT(mi2s_m_clk.c),
1685 },
1686};
1687
1688static struct branch_clk mi2s_s_clk = {
1689 .b = {
1690 .ctl_reg = MI2S_NS_REG,
1691 .en_mask = BIT(9),
1692 .halt_reg = CLK_HALT_STATEC_REG,
1693 .halt_bit = 3,
1694 .reset_mask = P_MI2S_S_CLK,
1695 },
1696 .parent = &mi2s_m_clk.c,
1697 .c = {
1698 .dbg_name = "mi2s_s_clk",
1699 .ops = &clk_ops_branch,
1700 CLK_INIT(mi2s_s_clk.c),
1701 },
1702};
1703
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001704#define F_SDAC(f, s, div, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001705 { \
1706 .freq_hz = f, \
1707 .md_val = MD16(m, n), \
1708 .ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001709 .src_clk = &s##_clk.c, \
1710 }
1711
1712static struct clk_freq_tbl clk_tbl_sdac[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001713 F_SDAC( 256000, lpxo, 4, 1, 24),
1714 F_SDAC( 352800, lpxo, 1, 147, 10240),
1715 F_SDAC( 384000, lpxo, 4, 1, 16),
1716 F_SDAC( 512000, lpxo, 4, 1, 12),
1717 F_SDAC( 705600, lpxo, 1, 147, 5120),
1718 F_SDAC( 768000, lpxo, 4, 1, 8),
1719 F_SDAC(1024000, lpxo, 4, 1, 6),
1720 F_SDAC(1411200, lpxo, 1, 147, 2560),
1721 F_SDAC(1536000, lpxo, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001722 F_END,
1723};
1724
1725static struct rcg_clk sdac_clk = {
1726 .b = {
1727 .ctl_reg = SDAC_NS_REG,
1728 .en_mask = BIT(9),
1729 .halt_reg = CLK_HALT_STATEA_REG,
1730 .halt_bit = 2,
1731 .reset_mask = P_SDAC_CLK,
1732 },
1733 .ns_reg = SDAC_NS_REG,
1734 .md_reg = SDAC_NS_REG - 4,
1735 .root_en_mask = BIT(11),
Matt Wagantall07c45472012-02-10 23:27:24 -08001736 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001737 .freq_tbl = clk_tbl_sdac,
1738 .ns_mask = F_MASK_MND16,
1739 .set_rate = set_rate_mnd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001740 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001741 .c = {
1742 .dbg_name = "sdac_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001743 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001744 VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001745 CLK_INIT(sdac_clk.c),
1746 },
1747};
1748
1749static struct branch_clk sdac_m_clk = {
1750 .b = {
1751 .ctl_reg = SDAC_NS_REG,
1752 .en_mask = BIT(12),
1753 .halt_reg = CLK_HALT_STATEB_REG,
1754 .halt_bit = 17,
1755 .reset_mask = P_SDAC_M_CLK,
1756 },
1757 .parent = &sdac_clk.c,
1758 .c = {
1759 .dbg_name = "sdac_m_clk",
1760 .ops = &clk_ops_branch,
1761 CLK_INIT(sdac_m_clk.c),
1762 },
1763};
1764
1765static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001766 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
1767 F_MND8(27000000, 23, 16, pll4, 2, 2, 33),
1768 F_MND8(74250000, 23, 16, pll4, 2, 1, 6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001769 F_END,
1770};
1771
1772static struct rcg_clk tv_clk = {
1773 .ns_reg = TV_NS_REG,
1774 .b = {
1775 .ctl_reg = TV_NS_REG,
1776 .halt_check = NOCHECK,
1777 },
1778 .md_reg = TV_NS_REG - 4,
1779 .ns_mask = F_MASK_MND8(23, 16),
Matt Wagantall07c45472012-02-10 23:27:24 -08001780 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001781 .root_en_mask = BIT(11),
1782 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001783 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001784 .set_rate = set_rate_mnd,
1785 .c = {
1786 .dbg_name = "tv_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001787 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001788 VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001789 CLK_INIT(tv_clk.c),
1790 },
1791};
1792
1793static struct branch_clk hdmi_clk = {
1794 .b = {
1795 .ctl_reg = HDMI_NS_REG,
1796 .en_mask = BIT(9),
1797 .halt_reg = CLK_HALT_STATEC_REG,
1798 .halt_bit = 7,
1799 .reset_mask = P_HDMI_CLK,
1800 },
1801 .parent = &tv_clk.c,
1802 .c = {
1803 .dbg_name = "hdmi_clk",
1804 .ops = &clk_ops_branch,
1805 CLK_INIT(hdmi_clk.c),
1806 },
1807};
1808
1809static struct branch_clk tv_dac_clk = {
1810 .b = {
1811 .ctl_reg = TV_NS_REG,
1812 .en_mask = BIT(12),
1813 .halt_reg = CLK_HALT_STATEB_REG,
1814 .halt_bit = 27,
1815 .reset_mask = P_TV_DAC_CLK,
1816 },
1817 .parent = &tv_clk.c,
1818 .c = {
1819 .dbg_name = "tv_dac_clk",
1820 .ops = &clk_ops_branch,
1821 CLK_INIT(tv_dac_clk.c),
1822 },
1823};
1824
1825static struct branch_clk tv_enc_clk = {
1826 .b = {
1827 .ctl_reg = TV_NS_REG,
1828 .en_mask = BIT(9),
1829 .halt_reg = CLK_HALT_STATEB_REG,
1830 .halt_bit = 10,
1831 .reset_mask = P_TV_ENC_CLK,
1832 },
1833 .parent = &tv_clk.c,
1834 .c = {
1835 .dbg_name = "tv_enc_clk",
1836 .ops = &clk_ops_branch,
1837 CLK_INIT(tv_enc_clk.c),
1838 },
1839};
1840
1841/* Hacking root & branch into one param. */
1842static struct branch_clk tsif_ref_clk = {
1843 .b = {
1844 .ctl_reg = TSIF_NS_REG,
1845 .en_mask = BIT(9)|BIT(11),
1846 .halt_reg = CLK_HALT_STATEB_REG,
1847 .halt_bit = 11,
1848 .reset_mask = P_TSIF_REF_CLK,
1849 },
1850 .parent = &tv_clk.c,
1851 .c = {
1852 .dbg_name = "tsif_ref_clk",
1853 .ops = &clk_ops_branch,
1854 CLK_INIT(tsif_ref_clk.c),
1855 },
1856};
1857
1858static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001859 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
1860 F_MND8(60000000, 23, 16, pll1, 2, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001861 F_END,
1862};
1863
1864static struct rcg_clk usb_hs_src_clk = {
1865 .ns_reg = USBH_NS_REG,
1866 .b = {
1867 .ctl_reg = USBH_NS_REG,
1868 .halt_check = NOCHECK,
1869 },
1870 .md_reg = USBH_NS_REG - 4,
1871 .ns_mask = F_MASK_MND8(23, 16),
Matt Wagantall07c45472012-02-10 23:27:24 -08001872 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001873 .root_en_mask = BIT(11),
1874 .freq_tbl = clk_tbl_usb,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001875 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001876 .set_rate = set_rate_mnd,
1877 .c = {
1878 .dbg_name = "usb_hs_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001879 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001880 VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001881 CLK_INIT(usb_hs_src_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07001882 .depends = &axi_li_adsp_a_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001883 },
1884};
1885
1886static struct branch_clk usb_hs_clk = {
1887 .b = {
1888 .ctl_reg = USBH_NS_REG,
1889 .en_mask = BIT(9),
1890 .halt_reg = CLK_HALT_STATEB_REG,
1891 .halt_bit = 26,
1892 .reset_mask = P_USB_HS_CLK,
1893 },
1894 .c = {
1895 .dbg_name = "usb_hs_clk",
1896 .ops = &clk_ops_branch,
1897 CLK_INIT(usb_hs_clk.c),
1898 },
1899};
1900
1901static struct branch_clk usb_hs_core_clk = {
1902 .b = {
1903 .ctl_reg = USBH_NS_REG,
1904 .en_mask = BIT(13),
1905 .halt_reg = CLK_HALT_STATEA_REG,
1906 .halt_bit = 27,
1907 .reset_mask = P_USB_HS_CORE_CLK,
1908 },
1909 .parent = &usb_hs_src_clk.c,
1910 .c = {
1911 .dbg_name = "usb_hs_core_clk",
1912 .ops = &clk_ops_branch,
1913 CLK_INIT(usb_hs_core_clk.c),
1914 },
1915};
1916
1917static struct branch_clk usb_hs2_clk = {
1918 .b = {
1919 .ctl_reg = USBH2_NS_REG,
1920 .en_mask = BIT(9),
1921 .halt_reg = CLK_HALT_STATEB_REG,
1922 .halt_bit = 3,
1923 .reset_mask = P_USB_HS2_CLK,
1924 },
1925 .parent = &usb_hs_src_clk.c,
1926 .c = {
1927 .dbg_name = "usb_hs2_clk",
1928 .ops = &clk_ops_branch,
1929 CLK_INIT(usb_hs2_clk.c),
1930 },
1931};
1932
1933static struct branch_clk usb_hs2_core_clk = {
1934 .b = {
1935 .ctl_reg = USBH2_NS_REG,
1936 .en_mask = BIT(4),
1937 .halt_reg = CLK_HALT_STATEA_REG,
1938 .halt_bit = 28,
1939 .reset_mask = P_USB_HS2_CORE_CLK,
1940 },
1941 .parent = &usb_hs_src_clk.c,
1942 .c = {
1943 .dbg_name = "usb_hs2_core_clk",
1944 .ops = &clk_ops_branch,
1945 CLK_INIT(usb_hs2_core_clk.c),
1946 },
1947};
1948
1949static struct branch_clk usb_hs3_clk = {
1950 .b = {
1951 .ctl_reg = USBH3_NS_REG,
1952 .en_mask = BIT(9),
1953 .halt_reg = CLK_HALT_STATEB_REG,
1954 .halt_bit = 2,
1955 .reset_mask = P_USB_HS3_CLK,
1956 },
1957 .parent = &usb_hs_src_clk.c,
1958 .c = {
1959 .dbg_name = "usb_hs3_clk",
1960 .ops = &clk_ops_branch,
1961 CLK_INIT(usb_hs3_clk.c),
1962 },
1963};
1964
1965static struct branch_clk usb_hs3_core_clk = {
1966 .b = {
1967 .ctl_reg = USBH3_NS_REG,
1968 .en_mask = BIT(4),
1969 .halt_reg = CLK_HALT_STATEA_REG,
1970 .halt_bit = 29,
1971 .reset_mask = P_USB_HS3_CORE_CLK,
1972 },
1973 .parent = &usb_hs_src_clk.c,
1974 .c = {
1975 .dbg_name = "usb_hs3_core_clk",
1976 .ops = &clk_ops_branch,
1977 CLK_INIT(usb_hs3_core_clk.c),
1978 },
1979};
1980
1981static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001982 F_MND16( 24576000, lpxo, 1, 0, 0),
1983 F_MND16( 36864000, pll3, 4, 1, 5),
1984 F_MND16( 46080000, pll3, 4, 1, 4),
1985 F_MND16( 61440000, pll3, 4, 1, 3),
1986 F_MND16( 73728000, pll3, 2, 1, 5),
1987 F_MND16( 81920000, pll3, 3, 1, 3),
1988 F_MND16( 92160000, pll3, 4, 1, 2),
1989 F_MND16( 98304000, pll3, 3, 2, 5),
1990 F_MND16(105326000, pll3, 2, 2, 7),
1991 F_MND16(122880000, pll3, 2, 1, 3),
1992 F_MND16(147456000, pll3, 2, 2, 5),
1993 F_MND16(153600000, pll1, 2, 2, 5),
1994 F_MND16(192000000, pll1, 4, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001995 F_END,
1996};
1997
1998static struct rcg_clk jpeg_clk = {
1999 .b = {
2000 .ctl_reg = JPEG_NS_REG,
2001 .en_mask = BIT(9),
2002 .halt_reg = CLK_HALT_STATEB_REG,
2003 .halt_bit = 1,
2004 .reset_mask = P_JPEG_CLK,
2005 },
2006 .ns_reg = JPEG_NS_REG,
2007 .md_reg = JPEG_NS_REG - 4,
2008 .root_en_mask = BIT(11),
2009 .freq_tbl = clk_tbl_vfe_jpeg,
2010 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08002011 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002012 .set_rate = set_rate_mnd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002013 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002014 .c = {
2015 .dbg_name = "jpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002016 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002017 VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002018 CLK_INIT(jpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002019 .depends = &axi_li_jpeg_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002020 },
2021};
2022
2023static struct rcg_clk vfe_clk = {
2024 .b = {
2025 .ctl_reg = CAM_VFE_NS_REG,
2026 .en_mask = BIT(9),
2027 .halt_reg = CLK_HALT_STATEB_REG,
2028 .halt_bit = 0,
2029 .reset_mask = P_VFE_CLK,
2030 },
2031 .ns_reg = CAM_VFE_NS_REG,
2032 .md_reg = CAM_VFE_NS_REG - 4,
2033 .root_en_mask = BIT(13),
2034 .freq_tbl = clk_tbl_vfe_jpeg,
2035 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08002036 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002037 .set_rate = set_rate_mnd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002038 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002039 .c = {
2040 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002041 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002042 VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002043 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002044 .depends = &axi_li_vfe_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002045 },
2046};
2047
2048static struct branch_clk vfe_mdc_clk = {
2049 .b = {
2050 .ctl_reg = CAM_VFE_NS_REG,
2051 .en_mask = BIT(11),
2052 .halt_reg = CLK_HALT_STATEA_REG,
2053 .halt_bit = 9,
2054 .reset_mask = P_VFE_MDC_CLK,
2055 },
2056 .parent = &vfe_clk.c,
2057 .c = {
2058 .dbg_name = "vfe_mdc_clk",
2059 .ops = &clk_ops_branch,
2060 CLK_INIT(vfe_mdc_clk.c),
2061 },
2062};
2063
2064static struct branch_clk vfe_camif_clk = {
2065 .b = {
2066 .ctl_reg = CAM_VFE_NS_REG,
2067 .en_mask = BIT(15),
2068 .halt_reg = CLK_HALT_STATEC_REG,
2069 .halt_bit = 13,
2070 .reset_mask = P_VFE_CAMIF_CLK,
2071 },
2072 .parent = &vfe_clk.c,
2073 .c = {
2074 .dbg_name = "vfe_camif_clk",
2075 .ops = &clk_ops_branch,
2076 CLK_INIT(vfe_camif_clk.c),
2077 },
2078};
2079
2080static struct branch_clk csi0_vfe_clk = {
2081 .b = {
2082 .ctl_reg = CSI_NS_REG,
2083 .en_mask = BIT(15),
2084 .halt_reg = CLK_HALT_STATEC_REG,
2085 .halt_bit = 16,
2086 .reset_mask = P_CSI0_VFE_CLK,
2087 },
2088 .parent = &vfe_clk.c,
2089 .c = {
2090 .dbg_name = "csi0_vfe_clk",
2091 .ops = &clk_ops_branch,
2092 CLK_INIT(csi0_vfe_clk.c),
2093 },
2094};
2095
2096static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002097 F_MND16( 0, gnd, 1, 0, 0),
2098 F_MND16( 6000000, pll1, 4, 1, 32),
2099 F_MND16( 8000000, pll1, 4, 1, 24),
2100 F_MND16(12000000, pll1, 4, 1, 16),
2101 F_MND16(16000000, pll1, 4, 1, 12),
2102 F_MND16(19200000, pll1, 4, 1, 10),
2103 F_MND16(24000000, pll1, 4, 1, 8),
2104 F_MND16(32000000, pll1, 4, 1, 6),
2105 F_MND16(48000000, pll1, 4, 1, 4),
2106 F_MND16(64000000, pll1, 4, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002107 F_END,
2108};
2109
2110static struct rcg_clk cam_m_clk = {
2111 .b = {
2112 .ctl_reg = CAM_NS_REG,
2113 .halt_check = DELAY,
2114 .reset_mask = P_CAM_M_CLK,
2115 },
2116 .ns_reg = CAM_NS_REG,
2117 .md_reg = CAM_NS_REG - 4,
2118 .root_en_mask = BIT(9),
2119 .freq_tbl = clk_tbl_cam,
2120 .ns_mask = F_MASK_MND16,
Matt Wagantall07c45472012-02-10 23:27:24 -08002121 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002122 .set_rate = set_rate_mnd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002123 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002124 .c = {
2125 .dbg_name = "cam_m_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002126 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002127 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002128 CLK_INIT(cam_m_clk.c),
2129 },
2130};
2131
2132static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002133 F_MND8( 24576000, 22, 15, lpxo, 1, 0, 0),
2134 F_MND8( 30720000, 22, 15, pll3, 4, 1, 6),
2135 F_MND8( 61440000, 22, 15, pll3, 4, 1, 3),
2136 F_MND8( 81920000, 22, 15, pll3, 3, 1, 3),
2137 F_MND8(122880000, 22, 15, pll3, 3, 1, 2),
2138 F_MND8(147456000, 22, 15, pll3, 1, 1, 5),
2139 F_MND8(153600000, 22, 15, pll1, 1, 1, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002140 F_END,
2141};
2142
2143static struct rcg_clk vpe_clk = {
2144 .b = {
2145 .ctl_reg = VPE_NS_REG,
2146 .en_mask = BIT(9),
2147 .halt_reg = CLK_HALT_STATEC_REG,
2148 .halt_bit = 10,
2149 .reset_mask = P_VPE_CLK,
2150 },
2151 .ns_reg = VPE_NS_REG,
2152 .md_reg = VPE_NS_REG - 4,
2153 .ns_mask = F_MASK_MND8(22, 15),
Matt Wagantall07c45472012-02-10 23:27:24 -08002154 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002155 .root_en_mask = BIT(11),
2156 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002157 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002158 .set_rate = set_rate_mnd,
2159 .c = {
2160 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002161 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002162 VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002163 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002164 .depends = &axi_vpe_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002165 },
2166};
2167
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002168static struct clk_freq_tbl clk_tbl_mfc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002169 F_MND8( 24576000, 24, 17, lpxo, 1, 0, 0),
2170 F_MND8( 30720000, 24, 17, pll3, 4, 1, 6),
2171 F_MND8( 61440000, 24, 17, pll3, 4, 1, 3),
2172 F_MND8( 81920000, 24, 17, pll3, 3, 1, 3),
2173 F_MND8(122880000, 24, 17, pll3, 3, 1, 2),
2174 F_MND8(147456000, 24, 17, pll3, 1, 1, 5),
2175 F_MND8(153600000, 24, 17, pll1, 1, 1, 5),
2176 F_MND8(170667000, 24, 17, pll1, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002177 F_END,
2178};
2179
2180static struct rcg_clk mfc_clk = {
2181 .b = {
2182 .ctl_reg = MFC_NS_REG,
2183 .en_mask = BIT(9),
2184 .halt_reg = CLK_HALT_STATEC_REG,
2185 .halt_bit = 12,
2186 .reset_mask = P_MFC_CLK,
2187 },
2188 .ns_reg = MFC_NS_REG,
2189 .md_reg = MFC_NS_REG - 4,
2190 .ns_mask = F_MASK_MND8(24, 17),
Matt Wagantall07c45472012-02-10 23:27:24 -08002191 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002192 .root_en_mask = BIT(11),
2193 .freq_tbl = clk_tbl_mfc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002194 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002195 .set_rate = set_rate_mnd,
2196 .c = {
2197 .dbg_name = "mfc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002198 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002199 VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002200 CLK_INIT(mfc_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002201 .depends = &axi_mfc_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002202 },
2203};
2204
2205static struct branch_clk mfc_div2_clk = {
2206 .b = {
2207 .ctl_reg = MFC_NS_REG,
2208 .en_mask = BIT(15),
2209 .halt_reg = CLK_HALT_STATEC_REG,
2210 .halt_bit = 11,
2211 .reset_mask = P_MFC_DIV2_CLK,
2212 },
2213 .parent = &mfc_clk.c,
2214 .c = {
2215 .dbg_name = "mfc_div2_clk",
2216 .ops = &clk_ops_branch,
2217 CLK_INIT(mfc_div2_clk.c),
2218 },
2219};
2220
2221static struct clk_freq_tbl clk_tbl_spi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002222 F_MND8( 0, 0, 0, gnd, 1, 0, 0),
2223 F_MND8( 9963243, 19, 12, pll3, 4, 2, 37),
Matt Wagantalla7df37f2011-11-11 11:28:11 -08002224 F_MND8(24576000, 19, 12, lpxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002225 F_MND8(26331429, 19, 12, pll3, 4, 1, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002226 F_END,
2227};
2228
2229static struct rcg_clk spi_clk = {
2230 .b = {
2231 .ctl_reg = SPI_NS_REG,
2232 .en_mask = BIT(9),
2233 .halt_reg = CLK_HALT_STATEC_REG,
2234 .halt_bit = 0,
2235 .reset_mask = P_SPI_CLK,
2236 },
2237 .ns_reg = SPI_NS_REG,
2238 .md_reg = SPI_NS_REG - 4,
2239 .ns_mask = F_MASK_MND8(19, 12),
Matt Wagantall07c45472012-02-10 23:27:24 -08002240 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002241 .root_en_mask = BIT(11),
2242 .freq_tbl = clk_tbl_spi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002243 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002244 .set_rate = set_rate_mnd,
2245 .c = {
2246 .dbg_name = "spi_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002247 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002248 VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002249 CLK_INIT(spi_clk.c),
2250 },
2251};
2252
2253static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
Matt Wagantall07c45472012-02-10 23:27:24 -08002254 F_RAW(1, NULL, 0, 0, 0, NULL), /* src MI2S_CODEC_RX */
2255 F_RAW(2, NULL, 0, 1, 0, NULL), /* src ECODEC_CIF */
2256 F_RAW(3, NULL, 0, 2, 0, NULL), /* src MI2S */
2257 F_RAW(4, NULL, 0, 3, 0, NULL), /* src SDAC */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002258 F_END,
2259};
2260
2261static struct rcg_clk lpa_codec_clk = {
2262 .b = {
2263 .ctl_reg = LPA_NS_REG,
2264 .en_mask = BIT(9),
2265 .halt_reg = CLK_HALT_STATEC_REG,
2266 .halt_bit = 6,
2267 .reset_mask = P_LPA_CODEC_CLK,
2268 },
2269 .ns_reg = LPA_NS_REG,
2270 .ns_mask = BM(1, 0),
2271 .set_rate = set_rate_nop,
2272 .freq_tbl = clk_tbl_lpa_codec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002273 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002274 .c = {
2275 .dbg_name = "lpa_codec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002276 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002277 VDD_DIG_FMAX_MAP1(LOW, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002278 CLK_INIT(lpa_codec_clk.c),
2279 },
2280};
2281
2282static struct clk_freq_tbl clk_tbl_mdc[] = {
Matt Wagantall07c45472012-02-10 23:27:24 -08002283 F_RAW(1, NULL, 0, 0, 0, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002284 F_END
2285};
2286
2287static struct rcg_clk mdc_clk = {
2288 .b = {
2289 .ctl_reg = MDC_NS_REG,
2290 .en_mask = BIT(9),
2291 .halt_reg = CLK_HALT_STATEA_REG,
2292 .halt_bit = 10,
2293 .reset_mask = P_MDC_CLK,
2294 },
2295 .ns_reg = MDC_NS_REG,
2296 .root_en_mask = BIT(11),
2297 .freq_tbl = clk_tbl_mdc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002298 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002299 .set_rate = set_rate_nop,
2300 .c = {
2301 .dbg_name = "mdc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002302 .ops = &clk_ops_rcg_7x30,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002303 VDD_DIG_FMAX_MAP1(LOW, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002304 CLK_INIT(mdc_clk.c),
2305 },
2306};
2307
2308static struct branch_clk lpa_core_clk = {
2309 .b = {
2310 .ctl_reg = LPA_NS_REG,
2311 .en_mask = BIT(5),
2312 .halt_reg = CLK_HALT_STATEC_REG,
2313 .halt_bit = 5,
2314 .reset_mask = P_LPA_CORE_CLK,
2315 },
2316 .c = {
2317 .dbg_name = "lpa_core_clk",
2318 .ops = &clk_ops_branch,
2319 CLK_INIT(lpa_core_clk.c),
2320 },
2321};
2322
2323static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, CLKFLAG_SKIP_AUTO_OFF);
2324static DEFINE_CLK_PCOM(codec_ssbi_clk, CODEC_SSBI_CLK, CLKFLAG_SKIP_AUTO_OFF);
2325static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
2326static DEFINE_CLK_PCOM(ebi1_fixed_clk, EBI1_FIXED_CLK, CLKFLAG_MIN |
2327 CLKFLAG_SKIP_AUTO_OFF);
2328static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2329static DEFINE_CLK_PCOM(gp_clk, GP_CLK, CLKFLAG_SKIP_AUTO_OFF);
2330static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, 0);
2331static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLKFLAG_MIN);
2332
2333static DEFINE_CLK_PCOM(p_grp_2d_clk, GRP_2D_CLK, CLKFLAG_SKIP_AUTO_OFF);
2334static DEFINE_CLK_PCOM(p_grp_2d_p_clk, GRP_2D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2335static DEFINE_CLK_PCOM(p_hdmi_clk, HDMI_CLK, CLKFLAG_SKIP_AUTO_OFF);
Matt Wagantall2eedd222011-11-16 12:55:21 -08002336static DEFINE_CLK_PCOM(p_jpeg_clk, JPEG_CLK, CLKFLAG_MIN);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002337static DEFINE_CLK_PCOM(p_jpeg_p_clk, JPEG_P_CLK, 0);
2338static DEFINE_CLK_PCOM(p_lpa_codec_clk, LPA_CODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2339static DEFINE_CLK_PCOM(p_lpa_core_clk, LPA_CORE_CLK, CLKFLAG_SKIP_AUTO_OFF);
2340static DEFINE_CLK_PCOM(p_lpa_p_clk, LPA_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2341static DEFINE_CLK_PCOM(p_mi2s_m_clk, MI2S_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
2342static DEFINE_CLK_PCOM(p_mi2s_s_clk, MI2S_S_CLK, CLKFLAG_SKIP_AUTO_OFF);
2343static DEFINE_CLK_PCOM(p_mi2s_codec_rx_m_clk, MI2S_CODEC_RX_M_CLK,
2344 CLKFLAG_SKIP_AUTO_OFF);
2345static DEFINE_CLK_PCOM(p_mi2s_codec_rx_s_clk, MI2S_CODEC_RX_S_CLK,
2346 CLKFLAG_SKIP_AUTO_OFF);
2347static DEFINE_CLK_PCOM(p_mi2s_codec_tx_m_clk, MI2S_CODEC_TX_M_CLK,
2348 CLKFLAG_SKIP_AUTO_OFF);
2349static DEFINE_CLK_PCOM(p_mi2s_codec_tx_s_clk, MI2S_CODEC_TX_S_CLK,
2350 CLKFLAG_SKIP_AUTO_OFF);
2351static DEFINE_CLK_PCOM(p_sdac_clk, SDAC_CLK, 0);
2352static DEFINE_CLK_PCOM(p_sdac_m_clk, SDAC_M_CLK, 0);
2353static DEFINE_CLK_PCOM(p_vfe_clk, VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
2354static DEFINE_CLK_PCOM(p_vfe_camif_clk, VFE_CAMIF_CLK, CLKFLAG_SKIP_AUTO_OFF);
2355static DEFINE_CLK_PCOM(p_vfe_mdc_clk, VFE_MDC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2356static DEFINE_CLK_PCOM(p_vfe_p_clk, VFE_P_CLK, 0);
2357static DEFINE_CLK_PCOM(p_grp_3d_clk, GRP_3D_CLK, CLKFLAG_SKIP_AUTO_OFF);
2358static DEFINE_CLK_PCOM(p_grp_3d_p_clk, GRP_3D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2359static DEFINE_CLK_PCOM(p_imem_clk, IMEM_CLK, 0);
2360static DEFINE_CLK_PCOM(p_mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK,
2361 CLKFLAG_SKIP_AUTO_OFF);
2362static DEFINE_CLK_PCOM(p_mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
2363 CLKFLAG_SKIP_AUTO_OFF);
2364static DEFINE_CLK_PCOM(p_mdp_p_clk, MDP_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2365static DEFINE_CLK_PCOM(p_mdp_vsync_clk, MDP_VSYNC_CLK, 0);
2366static DEFINE_CLK_PCOM(p_tsif_ref_clk, TSIF_REF_CLK, CLKFLAG_SKIP_AUTO_OFF);
2367static DEFINE_CLK_PCOM(p_tsif_p_clk, TSIF_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2368static DEFINE_CLK_PCOM(p_tv_dac_clk, TV_DAC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2369static DEFINE_CLK_PCOM(p_tv_enc_clk, TV_ENC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2370static DEFINE_CLK_PCOM(p_emdh_clk, EMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
2371static DEFINE_CLK_PCOM(p_emdh_p_clk, EMDH_P_CLK, 0);
2372static DEFINE_CLK_PCOM(p_i2c_clk, I2C_CLK, CLKFLAG_SKIP_AUTO_OFF);
2373static DEFINE_CLK_PCOM(p_i2c_2_clk, I2C_2_CLK, CLKFLAG_SKIP_AUTO_OFF);
2374static DEFINE_CLK_PCOM(p_mdc_clk, MDC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2375static DEFINE_CLK_PCOM(p_pmdh_clk, PMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
2376static DEFINE_CLK_PCOM(p_pmdh_p_clk, PMDH_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2377static DEFINE_CLK_PCOM(p_sdc1_clk, SDC1_CLK, 0);
2378static DEFINE_CLK_PCOM(p_sdc1_p_clk, SDC1_P_CLK, 0);
2379static DEFINE_CLK_PCOM(p_sdc2_clk, SDC2_CLK, 0);
2380static DEFINE_CLK_PCOM(p_sdc2_p_clk, SDC2_P_CLK, 0);
2381static DEFINE_CLK_PCOM(p_sdc3_clk, SDC3_CLK, 0);
2382static DEFINE_CLK_PCOM(p_sdc3_p_clk, SDC3_P_CLK, 0);
2383static DEFINE_CLK_PCOM(p_sdc4_clk, SDC4_CLK, 0);
2384static DEFINE_CLK_PCOM(p_sdc4_p_clk, SDC4_P_CLK, 0);
2385static DEFINE_CLK_PCOM(p_uart2_clk, UART2_CLK, CLKFLAG_SKIP_AUTO_OFF);
2386static DEFINE_CLK_PCOM(p_usb_hs2_clk, USB_HS2_CLK, 0);
2387static DEFINE_CLK_PCOM(p_usb_hs2_core_clk, USB_HS2_CORE_CLK, 0);
2388static DEFINE_CLK_PCOM(p_usb_hs2_p_clk, USB_HS2_P_CLK, 0);
2389static DEFINE_CLK_PCOM(p_usb_hs3_clk, USB_HS3_CLK, 0);
2390static DEFINE_CLK_PCOM(p_usb_hs3_core_clk, USB_HS3_CORE_CLK, 0);
2391static DEFINE_CLK_PCOM(p_usb_hs3_p_clk, USB_HS3_P_CLK, 0);
2392static DEFINE_CLK_PCOM(p_qup_i2c_clk, QUP_I2C_CLK, CLKFLAG_SKIP_AUTO_OFF);
2393static DEFINE_CLK_PCOM(p_spi_clk, SPI_CLK, CLKFLAG_SKIP_AUTO_OFF);
2394static DEFINE_CLK_PCOM(p_spi_p_clk, SPI_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2395static DEFINE_CLK_PCOM(p_uart1_clk, UART1_CLK, 0);
2396static DEFINE_CLK_PCOM(p_uart1dm_clk, UART1DM_CLK, 0);
2397static DEFINE_CLK_PCOM(p_uart2dm_clk, UART2DM_CLK, CLKFLAG_SKIP_AUTO_OFF);
2398static DEFINE_CLK_PCOM(p_usb_hs_clk, USB_HS_CLK, 0);
2399static DEFINE_CLK_PCOM(p_usb_hs_core_clk, USB_HS_CORE_CLK, 0);
2400static DEFINE_CLK_PCOM(p_usb_hs_p_clk, USB_HS_P_CLK, 0);
2401static DEFINE_CLK_PCOM(p_cam_m_clk, CAM_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
2402static DEFINE_CLK_PCOM(p_camif_pad_p_clk, CAMIF_PAD_P_CLK, 0);
2403static DEFINE_CLK_PCOM(p_csi0_clk, CSI0_CLK, CLKFLAG_SKIP_AUTO_OFF);
2404static DEFINE_CLK_PCOM(p_csi0_vfe_clk, CSI0_VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
2405static DEFINE_CLK_PCOM(p_csi0_p_clk, CSI0_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
Matt Wagantalla12cc952011-11-08 18:14:50 -08002406static DEFINE_CLK_PCOM(p_mdp_clk, MDP_CLK, CLKFLAG_MIN);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002407static DEFINE_CLK_PCOM(p_mfc_clk, MFC_CLK, CLKFLAG_SKIP_AUTO_OFF);
2408static DEFINE_CLK_PCOM(p_mfc_div2_clk, MFC_DIV2_CLK, CLKFLAG_SKIP_AUTO_OFF);
2409static DEFINE_CLK_PCOM(p_mfc_p_clk, MFC_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
2410static DEFINE_CLK_PCOM(p_vpe_clk, VPE_CLK, CLKFLAG_SKIP_AUTO_OFF);
2411static DEFINE_CLK_PCOM(p_adm_clk, ADM_CLK, CLKFLAG_SKIP_AUTO_OFF);
2412static DEFINE_CLK_PCOM(p_ce_clk, CE_CLK, CLKFLAG_SKIP_AUTO_OFF);
2413static DEFINE_CLK_PCOM(p_axi_rotator_clk, AXI_ROTATOR_CLK,
2414 CLKFLAG_SKIP_AUTO_OFF);
2415static DEFINE_CLK_PCOM(p_rotator_imem_clk, ROTATOR_IMEM_CLK, 0);
2416static DEFINE_CLK_PCOM(p_rotator_p_clk, ROTATOR_P_CLK, 0);
2417
2418static DEFINE_CLK_VOTER(ebi_dtv_clk, &ebi1_fixed_clk.c);
Matt Wagantall9dc01632011-08-17 18:55:04 -07002419static DEFINE_CLK_VOTER(ebi_grp_3d_clk, &ebi1_fixed_clk.c);
2420static DEFINE_CLK_VOTER(ebi_grp_2d_clk, &ebi1_fixed_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002421static DEFINE_CLK_VOTER(ebi_lcdc_clk, &ebi1_fixed_clk.c);
2422static DEFINE_CLK_VOTER(ebi_mddi_clk, &ebi1_fixed_clk.c);
2423static DEFINE_CLK_VOTER(ebi_tv_clk, &ebi1_fixed_clk.c);
2424static DEFINE_CLK_VOTER(ebi_vcd_clk, &ebi1_fixed_clk.c);
2425static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_fixed_clk.c);
2426static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_fixed_clk.c);
2427
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002428#ifdef CONFIG_DEBUG_FS
2429
2430#define CLK_TEST_2(s) (s)
2431#define CLK_TEST_HS(s) (0x4000 | ((s) << 8))
2432#define CLK_TEST_LS(s) (0x4D40 | (s))
2433
2434struct measure_sel {
2435 u32 test_vector;
2436 struct clk *clk;
2437};
2438
2439static struct measure_sel measure_mux[] = {
2440 { CLK_TEST_2(0x03), &emdh_p_clk.c },
2441 { CLK_TEST_2(0x04), &pmdh_p_clk.c },
2442 { CLK_TEST_2(0x06), &mdp_p_clk.c },
2443 { CLK_TEST_2(0x07), &lpa_p_clk.c },
2444 { CLK_TEST_2(0x08), &usb_hs2_p_clk.c },
2445 { CLK_TEST_2(0x09), &spi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002446 { CLK_TEST_2(0x0B), &i2c_2_clk.c },
2447 { CLK_TEST_2(0x0D), &mi2s_m_clk.c },
2448 { CLK_TEST_2(0x0E), &lpa_core_clk.c },
2449 { CLK_TEST_2(0x0F), &lpa_codec_clk.c },
2450 { CLK_TEST_2(0x10), &usb_hs3_p_clk.c },
2451 { CLK_TEST_2(0x11), &adm_p_clk.c },
2452 { CLK_TEST_2(0x13), &hdmi_clk.c },
2453 { CLK_TEST_2(0x14), &usb_hs_core_clk.c },
2454 { CLK_TEST_2(0x15), &usb_hs2_core_clk.c },
2455 { CLK_TEST_2(0x16), &usb_hs3_core_clk.c },
2456 { CLK_TEST_2(0x17), &mi2s_codec_tx_s_clk.c },
2457 { CLK_TEST_2(0x18), &spi_p_clk.c },
2458 { CLK_TEST_2(0x1A), &camif_pad_p_clk.c },
2459 { CLK_TEST_2(0x1C), &qup_i2c_clk.c },
2460 { CLK_TEST_2(0x1F), &mfc_div2_clk.c },
2461 { CLK_TEST_2(0x38), &mfc_clk.c },
2462
2463 { CLK_TEST_HS(0x00), &adm_clk.c },
2464 { CLK_TEST_HS(0x01), &mdp_lcdc_pad_pclk_clk.c },
2465 { CLK_TEST_HS(0x02), &mdp_lcdc_pclk_clk.c },
2466 { CLK_TEST_HS(0x03), &axi_rotator_clk.c },
2467 { CLK_TEST_HS(0x07), &axi_li_vg_clk.c },
2468 { CLK_TEST_HS(0x09), &axi_li_apps_clk.c },
2469 { CLK_TEST_HS(0x0E), &axi_li_jpeg_clk.c },
2470 { CLK_TEST_HS(0x0F), &emdh_clk.c },
2471 { CLK_TEST_HS(0x14), &mdp_clk.c },
2472 { CLK_TEST_HS(0x15), &pmdh_clk.c },
2473 { CLK_TEST_HS(0x19), &axi_grp_2d_clk.c },
2474 { CLK_TEST_HS(0x1A), &axi_li_grp_clk.c },
2475 { CLK_TEST_HS(0x1B), &axi_li_vfe_clk.c },
2476 { CLK_TEST_HS(0x1C), &grp_2d_clk.c },
2477 { CLK_TEST_HS(0x1E), &grp_3d_clk.c },
2478 { CLK_TEST_HS(0x1F), &imem_clk.c },
2479 { CLK_TEST_HS(0x20), &jpeg_clk.c },
2480 { CLK_TEST_HS(0x24), &axi_li_adsp_a_clk.c },
2481 { CLK_TEST_HS(0x26), &rotator_imem_clk.c },
2482 { CLK_TEST_HS(0x27), &axi_vpe_clk.c },
2483 { CLK_TEST_HS(0x2A), &axi_mfc_clk.c },
2484 { CLK_TEST_HS(0x2B), &axi_mdp_clk.c },
2485 { CLK_TEST_HS(0x2C), &vpe_clk.c },
2486 { CLK_TEST_HS(0x30), &vfe_camif_clk.c },
2487 { CLK_TEST_HS(0x31), &csi0_clk.c },
2488 { CLK_TEST_HS(0x32), &csi0_vfe_clk.c },
2489 { CLK_TEST_HS(0x33), &csi0_p_clk.c },
2490
2491 { CLK_TEST_LS(0x03), &ce_clk.c },
2492 { CLK_TEST_LS(0x04), &cam_m_clk.c },
2493 { CLK_TEST_LS(0x0C), &grp_2d_p_clk.c },
2494 { CLK_TEST_LS(0x0D), &i2c_clk.c },
2495 { CLK_TEST_LS(0x0E), &mi2s_codec_rx_m_clk.c },
2496 { CLK_TEST_LS(0x0F), &mi2s_codec_rx_s_clk.c },
2497 { CLK_TEST_LS(0x10), &mi2s_codec_tx_m_clk.c },
2498 { CLK_TEST_LS(0x13), &mdp_vsync_clk.c },
2499 { CLK_TEST_LS(0x15), &vfe_p_clk.c },
2500 { CLK_TEST_LS(0x16), &mdc_clk.c },
2501 { CLK_TEST_LS(0x17), &vfe_mdc_clk.c },
2502 { CLK_TEST_LS(0x18), &usb_hs_p_clk.c },
2503 { CLK_TEST_LS(0x1C), &uart1dm_p_clk.c },
2504 { CLK_TEST_LS(0x1E), &jpeg_p_clk.c },
2505 { CLK_TEST_LS(0x20), &sdac_clk.c },
2506 { CLK_TEST_LS(0x21), &sdc1_p_clk.c },
2507 { CLK_TEST_LS(0x22), &sdc1_clk.c },
2508 { CLK_TEST_LS(0x23), &sdc2_p_clk.c },
2509 { CLK_TEST_LS(0x24), &sdc2_clk.c },
2510 { CLK_TEST_LS(0x25), &tsif_p_clk.c },
2511 { CLK_TEST_LS(0x26), &sdac_m_clk.c },
2512 { CLK_TEST_LS(0x27), &grp_3d_p_clk.c },
2513 { CLK_TEST_LS(0x2A), &tsif_ref_clk.c },
2514 { CLK_TEST_LS(0x2B), &tv_enc_clk.c },
2515 { CLK_TEST_LS(0x2C), &tv_dac_clk.c },
2516 { CLK_TEST_LS(0x2D), &rotator_p_clk.c },
2517 { CLK_TEST_LS(0x2F), &uart1_clk.c },
2518 { CLK_TEST_LS(0x30), &uart1dm_clk.c },
2519 { CLK_TEST_LS(0x31), &uart2_clk.c },
2520 { CLK_TEST_LS(0x33), &usb_hs2_clk.c },
2521 { CLK_TEST_LS(0x34), &usb_hs3_clk.c },
2522 { CLK_TEST_LS(0x35), &mfc_p_clk.c },
2523 { CLK_TEST_LS(0x36), &vfe_clk.c },
2524 { CLK_TEST_LS(0x39), &sdc3_p_clk.c },
2525 { CLK_TEST_LS(0x3A), &sdc3_clk.c },
2526 { CLK_TEST_LS(0x3B), &sdc4_p_clk.c },
2527 { CLK_TEST_LS(0x3C), &sdc4_clk.c },
2528 { CLK_TEST_LS(0x3D), &uart2dm_clk.c },
2529 { CLK_TEST_LS(0x3E), &uart2dm_p_clk.c },
2530 { CLK_TEST_LS(0x3F), &usb_hs_clk.c },
2531};
2532
2533static struct measure_sel *find_measure_sel(struct clk *clk)
2534{
2535 int i;
2536
2537 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
2538 if (measure_mux[i].clk == clk)
2539 return &measure_mux[i];
2540 return NULL;
2541}
2542
2543static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
2544{
2545 struct measure_sel *p;
2546 unsigned long flags;
2547
2548 if (!parent)
2549 return -EINVAL;
2550
2551 p = find_measure_sel(parent);
2552 if (!p)
2553 return -EINVAL;
2554
2555 spin_lock_irqsave(&local_clock_reg_lock, flags);
2556
2557 /* Program test vector. */
2558 if (p->test_vector <= 0xFF) {
2559 /* Select CLK_TEST_2 */
2560 writel_relaxed(0x4D40, CLK_TEST_BASE_REG);
2561 writel_relaxed(p->test_vector, CLK_TEST_2_BASE_REG);
2562 } else
2563 writel_relaxed(p->test_vector, CLK_TEST_BASE_REG);
2564
2565 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2566
2567 return 0;
2568}
2569
2570/* Sample clock for 'tcxo4_ticks' reference clock ticks. */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002571static unsigned long run_measurement(unsigned tcxo4_ticks)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002572{
2573 /* TCXO4_CNT_EN and RINGOSC_CNT_EN register values. */
2574 u32 reg_val_enable = readl_relaxed(MISC_CLK_CTL_BASE_REG) | 0x3;
2575 u32 reg_val_disable = reg_val_enable & ~0x3;
2576
2577 /* Stop counters and set the TCXO4 counter start value. */
2578 writel_relaxed(reg_val_disable, MISC_CLK_CTL_BASE_REG);
2579 writel_relaxed(tcxo4_ticks, TCXO_CNT_BASE_REG);
2580
2581 /* Run measurement and wait for completion. */
2582 writel_relaxed(reg_val_enable, MISC_CLK_CTL_BASE_REG);
2583 while (readl_relaxed(TCXO_CNT_DONE_BASE_REG) == 0)
2584 cpu_relax();
2585
2586 /* Stop counters. */
2587 writel_relaxed(reg_val_disable, MISC_CLK_CTL_BASE_REG);
2588
2589 return readl_relaxed(RINGOSC_CNT_BASE_REG);
2590}
2591
2592/* Perform a hardware rate measurement for a given clock.
2593 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002594static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002595{
2596 unsigned long flags;
2597 u32 regval, prph_web_reg_old;
2598 u64 raw_count_short, raw_count_full;
2599 unsigned ret;
2600
Stephen Boyde334aeb2012-01-24 12:17:29 -08002601 clk_prepare_enable(&tcxo_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002602
2603 spin_lock_irqsave(&local_clock_reg_lock, flags);
2604
2605 /* Enable TCXO4 clock branch and root. */
2606 prph_web_reg_old = readl_relaxed(PRPH_WEB_NS_BASE_REG);
2607 regval = prph_web_reg_old | BIT(9) | BIT(11);
2608 writel_relaxed(regval, PRPH_WEB_NS_BASE_REG);
2609
2610 /*
2611 * The ring oscillator counter will not reset if the measured clock
2612 * is not running. To detect this, run a short measurement before
2613 * the full measurement. If the raw results of the two are the same
2614 * then the clock must be off.
2615 */
2616
2617 /* Run a short measurement. (~1 ms) */
2618 raw_count_short = run_measurement(0x1000);
2619 /* Run a full measurement. (~14 ms) */
2620 raw_count_full = run_measurement(0x10000);
2621
2622 /* Disable TCXO4 clock branch and root. */
2623 writel_relaxed(prph_web_reg_old, PRPH_WEB_NS_BASE_REG);
2624
2625 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2626
2627 /* Return 0 if the clock is off. */
2628 if (raw_count_full == raw_count_short)
2629 ret = 0;
2630 else {
2631 /* Compute rate in Hz. */
2632 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
2633 do_div(raw_count_full, ((0x10000 * 10) + 35));
2634 ret = raw_count_full;
2635 }
2636
Stephen Boyde334aeb2012-01-24 12:17:29 -08002637 clk_disable_unprepare(&tcxo_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002638
2639 return ret;
2640}
2641#else /* !CONFIG_DEBUG_FS */
2642static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
2643{
2644 return -EINVAL;
2645}
2646
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002647static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002648{
2649 return 0;
2650}
2651#endif /* CONFIG_DEBUG_FS */
2652
2653static struct clk_ops measure_clk_ops = {
2654 .set_parent = measure_clk_set_parent,
2655 .get_rate = measure_clk_get_rate,
2656 .is_local = local_clk_is_local,
2657};
2658
2659static struct clk measure_clk = {
2660 .dbg_name = "measure_clk",
2661 .ops = &measure_clk_ops,
2662 CLK_INIT(measure_clk),
2663};
2664
2665/* Implementation for clk_set_flags(). */
2666int soc_clk_set_flags(struct clk *clk, unsigned clk_flags)
2667{
2668 uint32_t regval, ret = 0;
2669 unsigned long flags;
2670
2671 spin_lock_irqsave(&local_clock_reg_lock, flags);
2672
2673 if (clk == &vfe_clk.c) {
2674 regval = readl_relaxed(CAM_VFE_NS_REG);
2675 /* Flag values chosen for backward compatibility
2676 * with proc_comm remote clock control. */
2677 if (clk_flags == 0x00000100) {
2678 /* Select external source. */
2679 regval |= BIT(14);
2680 } else if (clk_flags == 0x00000200) {
2681 /* Select internal source. */
2682 regval &= ~BIT(14);
2683 } else
2684 ret = -EINVAL;
2685
2686 writel_relaxed(regval, CAM_VFE_NS_REG);
2687 /* Make sure write is issued before returning. */
2688 mb();
2689 } else
2690 ret = -EPERM;
2691
2692 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2693
2694 return ret;
2695}
2696
2697static int msm7x30_clk_reset(struct clk *clk, enum clk_reset_action action)
2698{
2699 /* reset_mask is actually a proc_comm id */
2700 unsigned id = to_rcg_clk(clk)->b.reset_mask;
2701 return pc_clk_reset(id, action);
2702}
2703
2704static int soc_branch_clk_reset(struct clk *clk, enum clk_reset_action action)
2705{
2706 unsigned id = to_branch_clk(clk)->b.reset_mask;
2707 return pc_clk_reset(id, action);
2708}
2709
2710/*
2711 * Clock ownership detection code
2712 */
2713
2714enum {
2715 SH2_OWN_GLBL,
2716 SH2_OWN_APPS1,
2717 SH2_OWN_APPS2,
2718 SH2_OWN_ROW1,
2719 SH2_OWN_ROW2,
2720 SH2_OWN_APPS3,
2721 NUM_OWNERSHIP
2722};
2723static __initdata uint32_t ownership_regs[NUM_OWNERSHIP];
2724
2725static void __init cache_ownership(void)
2726{
2727 ownership_regs[SH2_OWN_GLBL] = readl_relaxed(SH2_OWN_GLBL_BASE_REG);
2728 ownership_regs[SH2_OWN_APPS1] = readl_relaxed(SH2_OWN_APPS1_BASE_REG);
2729 ownership_regs[SH2_OWN_APPS2] = readl_relaxed(SH2_OWN_APPS2_BASE_REG);
2730 ownership_regs[SH2_OWN_ROW1] = readl_relaxed(SH2_OWN_ROW1_BASE_REG);
2731 ownership_regs[SH2_OWN_ROW2] = readl_relaxed(SH2_OWN_ROW2_BASE_REG);
2732 ownership_regs[SH2_OWN_APPS3] = readl_relaxed(SH2_OWN_APPS3_BASE_REG);
2733}
2734
2735static void __init print_ownership(void)
2736{
2737 pr_info("Clock ownership\n");
2738 pr_info(" GLBL : %08x\n", ownership_regs[SH2_OWN_GLBL]);
2739 pr_info(" APPS : %08x %08x %08x\n", ownership_regs[SH2_OWN_APPS1],
2740 ownership_regs[SH2_OWN_APPS2], ownership_regs[SH2_OWN_APPS3]);
2741 pr_info(" ROW : %08x %08x\n", ownership_regs[SH2_OWN_ROW1],
2742 ownership_regs[SH2_OWN_ROW2]);
2743}
2744
2745#define O(x) (&ownership_regs[(SH2_OWN_##x)])
2746#define OWN(r, b, name, clk, dev) \
2747 { \
2748 .lk = CLK_LOOKUP(name, clk.c, dev), \
2749 .remote = &p_##clk.c, \
2750 .reg = O(r), \
2751 .bit = BIT(b), \
2752 }
2753
2754static struct clk_local_ownership {
2755 struct clk_lookup lk;
2756 const u32 *reg;
2757 const u32 bit;
2758 struct clk *remote;
2759} ownership_map[] __initdata = {
2760 /* Sources */
2761 { CLK_LOOKUP("pll1_clk", pll1_clk.c, "acpu") },
2762 { CLK_LOOKUP("pll2_clk", pll2_clk.c, "acpu") },
2763 { CLK_LOOKUP("pll3_clk", pll3_clk.c, "acpu") },
2764 { CLK_LOOKUP("measure", measure_clk, "debug") },
2765
2766 /* PCOM */
2767 { CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL) },
2768 { CLK_LOOKUP("codec_ssbi_clk", codec_ssbi_clk.c, NULL) },
2769 { CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL) },
2770 { CLK_LOOKUP("ebi1_fixed_clk", ebi1_fixed_clk.c, NULL) },
2771 { CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL) },
Matt Wagantallc00f95d2012-01-05 14:22:45 -08002772 { CLK_LOOKUP("core_clk", gp_clk.c, "") },
Matt Wagantalle2522372011-08-17 14:52:21 -07002773 { CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2") },
Manu Gautam5143b252012-01-05 19:25:23 -08002774 { CLK_LOOKUP("phy_clk", usb_phy_clk.c, "msm_otg") },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002775
2776 /* Voters */
2777 { CLK_LOOKUP("ebi1_dtv_clk", ebi_dtv_clk.c, NULL) },
Matt Wagantall9dc01632011-08-17 18:55:04 -07002778 { CLK_LOOKUP("bus_clk", ebi_grp_2d_clk.c, "kgsl-2d0.0") },
2779 { CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0") },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002780 { CLK_LOOKUP("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL) },
2781 { CLK_LOOKUP("ebi1_mddi_clk", ebi_mddi_clk.c, NULL) },
2782 { CLK_LOOKUP("ebi1_tv_clk", ebi_tv_clk.c, NULL) },
Matt Wagantall3f7660b2011-08-17 21:25:13 -07002783 { CLK_LOOKUP("mem_clk", ebi_vcd_clk.c, "msm_vidc.0") },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002784 { CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL) },
Matt Wagantalle1a86062011-08-18 17:46:10 -07002785 { CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov") },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002786
2787 /*
2788 * This is a many-to-one mapping because we don't know how the remote
2789 * clock code has decided to handle the dependencies between clocks for
2790 * a particular hardware block. We determine the ownership for all the
2791 * clocks going into a block by checking the ownership bit of one
2792 * register (usually the ns register).
2793 */
Matt Wagantall9dc01632011-08-17 18:55:04 -07002794 OWN(APPS1, 6, "core_clk", grp_2d_clk, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002795 OWN(APPS1, 6, "core_clk", grp_2d_clk, "footswitch-pcom.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07002796 OWN(APPS1, 6, "iface_clk", grp_2d_p_clk, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002797 OWN(APPS1, 6, "iface_clk", grp_2d_p_clk, "footswitch-pcom.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002798 OWN(APPS1, 31, "hdmi_clk", hdmi_clk, NULL),
2799 OWN(APPS1, 0, "jpeg_clk", jpeg_clk, NULL),
2800 OWN(APPS1, 0, "jpeg_pclk", jpeg_p_clk, NULL),
2801 OWN(APPS1, 23, "lpa_codec_clk", lpa_codec_clk, NULL),
2802 OWN(APPS1, 23, "lpa_core_clk", lpa_core_clk, NULL),
2803 OWN(APPS1, 23, "lpa_pclk", lpa_p_clk, NULL),
2804 OWN(APPS1, 28, "mi2s_m_clk", mi2s_m_clk, NULL),
2805 OWN(APPS1, 28, "mi2s_s_clk", mi2s_s_clk, NULL),
2806 OWN(APPS1, 12, "mi2s_codec_rx_m_clk", mi2s_codec_rx_m_clk, NULL),
2807 OWN(APPS1, 12, "mi2s_codec_rx_s_clk", mi2s_codec_rx_s_clk, NULL),
2808 OWN(APPS1, 14, "mi2s_codec_tx_m_clk", mi2s_codec_tx_m_clk, NULL),
2809 OWN(APPS1, 14, "mi2s_codec_tx_s_clk", mi2s_codec_tx_s_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002810 OWN(APPS1, 26, "sdac_clk", sdac_clk, NULL),
2811 OWN(APPS1, 26, "sdac_m_clk", sdac_m_clk, NULL),
2812 OWN(APPS1, 8, "vfe_clk", vfe_clk, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07002813 OWN(APPS1, 8, "core_clk", vfe_clk, "footswitch-pcom.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002814 OWN(APPS1, 8, "vfe_camif_clk", vfe_camif_clk, NULL),
2815 OWN(APPS1, 8, "vfe_mdc_clk", vfe_mdc_clk, NULL),
2816 OWN(APPS1, 8, "vfe_pclk", vfe_p_clk, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07002817 OWN(APPS1, 8, "iface_clk", vfe_p_clk, "footswitch-pcom.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002818
Matt Wagantall9dc01632011-08-17 18:55:04 -07002819 OWN(APPS2, 0, "core_clk", grp_3d_clk, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002820 OWN(APPS2, 0, "core_clk", grp_3d_clk, "footswitch-pcom.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07002821 OWN(APPS2, 0, "iface_clk", grp_3d_p_clk, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002822 OWN(APPS2, 0, "iface_clk", grp_3d_p_clk, "footswitch-pcom.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07002823 { CLK_LOOKUP("src_clk", grp_3d_src_clk.c, "kgsl-3d0.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002824 O(APPS2), BIT(0), &p_grp_3d_clk.c },
Matt Wagantall49722712011-08-17 18:50:53 -07002825 { CLK_LOOKUP("src_clk", grp_3d_src_clk.c, "footswitch-pcom.2"),
2826 O(APPS2), BIT(0), &p_grp_3d_clk.c },
Matt Wagantall9dc01632011-08-17 18:55:04 -07002827 OWN(APPS2, 0, "mem_clk", imem_clk, "kgsl-3d0.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002828 OWN(APPS2, 4, "mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk, NULL),
2829 OWN(APPS2, 4, "mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk, NULL),
2830 OWN(APPS2, 4, "mdp_pclk", mdp_p_clk, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07002831 OWN(APPS2, 4, "iface_clk", mdp_p_clk, "footswitch-pcom.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002832 OWN(APPS2, 28, "mdp_vsync_clk", mdp_vsync_clk, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07002833 OWN(APPS2, 5, "ref_clk", tsif_ref_clk, "msm_tsif.0"),
2834 OWN(APPS2, 5, "iface_clk", tsif_p_clk, "msm_tsif.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002835 { CLK_LOOKUP("tv_src_clk", tv_clk.c, NULL),
2836 O(APPS2), BIT(2), &p_tv_enc_clk.c },
2837 OWN(APPS2, 2, "tv_dac_clk", tv_dac_clk, NULL),
2838 OWN(APPS2, 2, "tv_enc_clk", tv_enc_clk, NULL),
2839
2840 OWN(ROW1, 7, "emdh_clk", emdh_clk, "msm_mddi.1"),
2841 OWN(ROW1, 7, "emdh_pclk", emdh_p_clk, "msm_mddi.1"),
Matt Wagantallac294852011-08-17 15:44:58 -07002842 OWN(ROW1, 11, "core_clk", i2c_clk, "msm_i2c.0"),
2843 OWN(ROW1, 12, "core_clk", i2c_2_clk, "msm_i2c.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002844 OWN(ROW1, 17, "mdc_clk", mdc_clk, NULL),
2845 OWN(ROW1, 19, "mddi_clk", pmdh_clk, NULL),
2846 OWN(ROW1, 19, "mddi_pclk", pmdh_p_clk, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07002847 OWN(ROW1, 23, "core_clk", sdc1_clk, "msm_sdcc.1"),
2848 OWN(ROW1, 23, "iface_clk", sdc1_p_clk, "msm_sdcc.1"),
2849 OWN(ROW1, 25, "core_clk", sdc2_clk, "msm_sdcc.2"),
2850 OWN(ROW1, 25, "iface_clk", sdc2_p_clk, "msm_sdcc.2"),
2851 OWN(ROW1, 27, "core_clk", sdc3_clk, "msm_sdcc.3"),
2852 OWN(ROW1, 27, "iface_clk", sdc3_p_clk, "msm_sdcc.3"),
2853 OWN(ROW1, 29, "core_clk", sdc4_clk, "msm_sdcc.4"),
2854 OWN(ROW1, 29, "iface_clk", sdc4_p_clk, "msm_sdcc.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07002855 OWN(ROW1, 0, "core_clk", uart2_clk, "msm_serial.1"),
Manu Gautam5143b252012-01-05 19:25:23 -08002856 OWN(ROW1, 2, "alt_core_clk", usb_hs2_clk, "msm_hsusb_host.0"),
2857 OWN(ROW1, 2, "core_clk", usb_hs2_core_clk, "msm_hsusb_host.0"),
2858 OWN(ROW1, 2, "iface_clk", usb_hs2_p_clk, "msm_hsusb_host.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08002859 OWN(ROW1, 4, "alt_core_clk", usb_hs3_clk, ""),
2860 OWN(ROW1, 4, "core_clk", usb_hs3_core_clk, ""),
2861 OWN(ROW1, 4, "iface_clk", usb_hs3_p_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002862
Matt Wagantallac294852011-08-17 15:44:58 -07002863 OWN(ROW2, 3, "core_clk", qup_i2c_clk, "qup_i2c.4"),
2864 OWN(ROW2, 1, "core_clk", spi_clk, "spi_qsd.0"),
2865 OWN(ROW2, 1, "iface_clk", spi_p_clk, "spi_qsd.0"),
Matt Wagantalle2522372011-08-17 14:52:21 -07002866 OWN(ROW2, 9, "core_clk", uart1_clk, "msm_serial.0"),
2867 OWN(ROW2, 6, "core_clk", uart1dm_clk, "msm_serial_hs.0"),
2868 OWN(ROW2, 8, "core_clk", uart2dm_clk, "msm_serial_hs.1"),
Manu Gautam5143b252012-01-05 19:25:23 -08002869 OWN(ROW2, 11, "alt_core_clk", usb_hs_clk, "msm_otg"),
2870 OWN(ROW2, 11, "core_clk", usb_hs_core_clk, "msm_otg"),
2871 OWN(ROW2, 11, "iface_clk", usb_hs_p_clk, "msm_otg"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002872
2873 OWN(APPS3, 6, "cam_m_clk", cam_m_clk, NULL),
2874 OWN(APPS3, 6, "camif_pad_pclk", camif_pad_p_clk, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07002875 OWN(APPS3, 6, "iface_clk", camif_pad_p_clk, "qup_i2c.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002876 OWN(APPS3, 11, "csi_clk", csi0_clk, NULL),
2877 OWN(APPS3, 11, "csi_vfe_clk", csi0_vfe_clk, NULL),
2878 OWN(APPS3, 11, "csi_pclk", csi0_p_clk, NULL),
2879 OWN(APPS3, 0, "mdp_clk", mdp_clk, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07002880 OWN(APPS3, 0, "core_clk", mdp_clk, "footswitch-pcom.4"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07002881 OWN(APPS3, 2, "core_clk", mfc_clk, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002882 OWN(APPS3, 2, "core_clk", mfc_clk, "footswitch-pcom.5"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07002883 OWN(APPS3, 2, "core_div2_clk", mfc_div2_clk, "msm_vidc.0"),
2884 OWN(APPS3, 2, "iface_clk", mfc_p_clk, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002885 OWN(APPS3, 2, "iface_clk", mfc_p_clk, "footswitch-pcom.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002886 OWN(APPS3, 4, "vpe_clk", vpe_clk, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07002887 OWN(APPS3, 4, "core_clk", vpe_clk, "footswitch-pcom.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002888
Matt Wagantalle1a86062011-08-18 17:46:10 -07002889 OWN(GLBL, 8, "core_clk", adm_clk, "msm_dmov"),
2890 { CLK_LOOKUP("iface_clk", adm_p_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002891 O(GLBL), BIT(13), &dummy_clk },
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07002892 OWN(GLBL, 8, "core_clk", ce_clk, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07002893 OWN(GLBL, 8, "core_clk", ce_clk, "crypto.0"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07002894 OWN(GLBL, 13, "core_clk", axi_rotator_clk, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002895 OWN(GLBL, 13, "core_clk", axi_rotator_clk, "footswitch-pcom.6"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07002896 OWN(GLBL, 13, "mem_clk", rotator_imem_clk, "msm_rotator.0"),
2897 OWN(GLBL, 13, "iface_clk", rotator_p_clk, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07002898 OWN(GLBL, 13, "iface_clk", rotator_p_clk, "footswitch-pcom.6"),
Matt Wagantalle2522372011-08-17 14:52:21 -07002899 { CLK_LOOKUP("iface_clk", uart1dm_p_clk.c, "msm_serial_hs.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002900 O(GLBL), BIT(8), &dummy_clk },
Matt Wagantalle2522372011-08-17 14:52:21 -07002901 { CLK_LOOKUP("iface_clk", uart2dm_p_clk.c, "msm_serial_hs.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002902 O(GLBL), BIT(8), &dummy_clk },
2903};
2904
2905static struct clk_lookup msm_clocks_7x30[ARRAY_SIZE(ownership_map)];
2906
2907static void __init set_clock_ownership(void)
2908{
2909 unsigned i;
2910 struct clk_lookup *lk;
2911
2912 for (i = 0; i < ARRAY_SIZE(ownership_map); i++) {
2913 const u32 *reg = ownership_map[i].reg;
2914 u32 bit = ownership_map[i].bit;
2915 struct clk *remote = ownership_map[i].remote;
2916
2917 lk = &ownership_map[i].lk;
2918 memcpy(&msm_clocks_7x30[i], lk, sizeof(*lk));
2919
2920 if (reg && !(*reg & bit))
2921 msm_clocks_7x30[i].clk = remote;
2922 }
2923}
2924
2925/*
2926 * Miscellaneous clock register initializations
2927 */
2928static const struct reg_init {
2929 const void __iomem *reg;
2930 uint32_t mask;
2931 uint32_t val;
2932} ri_list[] __initconst = {
2933 /* Enable UMDX_P clock. Known to causes issues, so never turn off. */
2934 {GLBL_CLK_ENA_2_SC_REG, BIT(2), BIT(2)},
2935
2936 /* Disable all the child clocks of USB_HS_SRC. */
2937 { USBH_NS_REG, BIT(13) | BIT(9), 0 },
2938 { USBH2_NS_REG, BIT(9) | BIT(4), 0 },
2939 { USBH3_NS_REG, BIT(9) | BIT(4), 0 },
2940
2941 {EMDH_NS_REG, BM(18, 17) , BVAL(18, 17, 0x3)}, /* RX div = div-4. */
2942 {PMDH_NS_REG, BM(18, 17), BVAL(18, 17, 0x3)}, /* RX div = div-4. */
2943 /* MI2S_CODEC_RX_S src = MI2S_CODEC_RX_M. */
2944 {MI2S_RX_NS_REG, BIT(14), 0x0},
2945 /* MI2S_CODEC_TX_S src = MI2S_CODEC_TX_M. */
2946 {MI2S_TX_NS_REG, BIT(14), 0x0},
2947 {MI2S_NS_REG, BIT(14), 0x0}, /* MI2S_S src = MI2S_M. */
2948 /* Allow DSP to decide the LPA CORE src. */
2949 {LPA_CORE_CLK_MA0_REG, BIT(0), BIT(0)},
2950 {LPA_CORE_CLK_MA2_REG, BIT(0), BIT(0)},
2951 {MI2S_CODEC_RX_DIV_REG, 0xF, 0xD}, /* MI2S_CODEC_RX_S div = div-8. */
2952 {MI2S_CODEC_TX_DIV_REG, 0xF, 0xD}, /* MI2S_CODEC_TX_S div = div-8. */
2953 {MI2S_DIV_REG, 0xF, 0x7}, /* MI2S_S div = div-8. */
2954 {MDC_NS_REG, 0x3, 0x3}, /* MDC src = external MDH src. */
2955 {SDAC_NS_REG, BM(15, 14), 0x0}, /* SDAC div = div-1. */
2956 /* Disable sources TCXO/5 & TCXO/6. UART1 src = TCXO*/
2957 {UART_NS_REG, BM(26, 25) | BM(2, 0), 0x0},
2958 /* HDMI div = div-1, non-inverted. tv_enc_src = tv_clk_src */
2959 {HDMI_NS_REG, 0x7, 0x0},
2960 {TV_NS_REG, BM(15, 14), 0x0}, /* tv_clk_src_div2 = div-1 */
2961
2962 /* USBH core clocks src = USB_HS_SRC. */
2963 {USBH_NS_REG, BIT(15), BIT(15)},
2964 {USBH2_NS_REG, BIT(6), BIT(6)},
2965 {USBH3_NS_REG, BIT(6), BIT(6)},
2966};
2967
2968/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07002969static void __init msm7x30_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002970{
2971 int i;
2972 uint32_t val;
2973
2974 cache_ownership();
2975 print_ownership();
2976 set_clock_ownership();
2977
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002978 /* When we have no local clock control, the rest of the code in this
2979 * function is a NOP since writes to shadow regions that we don't own
2980 * are ignored. */
2981
2982 clk_set_rate(&usb_hs_src_clk.c, clk_tbl_usb[1].freq_hz);
2983
2984 for (i = 0; i < ARRAY_SIZE(ri_list); i++) {
2985 val = readl_relaxed(ri_list[i].reg);
2986 val &= ~ri_list[i].mask;
2987 val |= ri_list[i].val;
2988 writel_relaxed(val, ri_list[i].reg);
2989 }
2990
2991 clk_set_rate(&i2c_clk.c, 19200000);
2992 clk_set_rate(&i2c_2_clk.c, 19200000);
2993 clk_set_rate(&qup_i2c_clk.c, 19200000);
2994 clk_set_rate(&uart1_clk.c, 19200000);
2995 clk_set_rate(&uart2_clk.c, 19200000);
2996 clk_set_rate(&mi2s_m_clk.c, 12288000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002997 clk_set_rate(&mdp_vsync_clk.c, 24576000);
2998 clk_set_rate(&glbl_root_clk.c, 1);
2999 clk_set_rate(&mdc_clk.c, 1);
3000 /* Sync the LPA_CODEC clock to MI2S_CODEC_RX */
3001 clk_set_rate(&lpa_codec_clk.c, 1);
3002 /* Sync the GRP2D clock to AXI */
3003 clk_set_rate(&grp_2d_clk.c, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003004}
3005
Stephen Boydbb600ae2011-08-02 20:11:40 -07003006struct clock_init_data msm7x30_clock_init_data __initdata = {
3007 .table = msm_clocks_7x30,
3008 .size = ARRAY_SIZE(msm_clocks_7x30),
3009 .init = msm7x30_clock_init,
3010};
3011
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003012/*
3013 * Clock operation handler registration
3014 */
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003015static struct clk_ops clk_ops_rcg_7x30 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -07003016 .enable = rcg_clk_enable,
3017 .disable = rcg_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -07003018 .auto_off = rcg_clk_disable,
Matt Wagantall0625ea02011-07-13 18:51:56 -07003019 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -07003020 .list_rate = rcg_clk_list_rate,
3021 .is_enabled = rcg_clk_is_enabled,
3022 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003023 .reset = msm7x30_clk_reset,
3024 .set_flags = soc_clk_set_flags,
3025 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -07003026 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003027};
3028
3029static struct clk_ops clk_ops_branch = {
3030 .enable = branch_clk_enable,
3031 .disable = branch_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -07003032 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003033 .is_enabled = branch_clk_is_enabled,
3034 .reset = soc_branch_clk_reset,
3035 .set_flags = soc_clk_set_flags,
3036 .is_local = local_clk_is_local,
3037 .get_parent = branch_clk_get_parent,
3038 .set_parent = branch_clk_set_parent,
3039};