blob: 2acb53318175b4e9323d3c6733f26b5f5b4c8b06 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
46#define DMA_BAM_HCLK_CTL REG(0x25C0)
47#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
48#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
49#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
50#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
51#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
52#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
53#define CLK_TEST_REG REG(0x2FA0)
54#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
55#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
56#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
57#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
58#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
59#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define PDM_CLK_NS_REG REG(0x2CC0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061#define BB_PLL_ENA_SC0_REG REG(0x34C0)
62#define BB_PLL0_STATUS_REG REG(0x30D8)
63#define BB_PLL5_STATUS_REG REG(0x30F8)
64#define BB_PLL6_STATUS_REG REG(0x3118)
65#define BB_PLL7_STATUS_REG REG(0x3138)
66#define BB_PLL8_L_VAL_REG REG(0x3144)
67#define BB_PLL8_M_VAL_REG REG(0x3148)
68#define BB_PLL8_MODE_REG REG(0x3140)
69#define BB_PLL8_N_VAL_REG REG(0x314C)
70#define BB_PLL8_STATUS_REG REG(0x3158)
71#define BB_PLL8_CONFIG_REG REG(0x3154)
72#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070073#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
74#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
75#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
77#define PMEM_ACLK_CTL_REG REG(0x25A0)
78#define RINGOSC_NS_REG REG(0x2DC0)
79#define RINGOSC_STATUS_REG REG(0x2DCC)
80#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
81#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
82#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
83#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
84#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
85#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
86#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
87#define TSIF_HCLK_CTL_REG REG(0x2700)
88#define TSIF_REF_CLK_MD_REG REG(0x270C)
89#define TSIF_REF_CLK_NS_REG REG(0x2710)
90#define TSSC_CLK_CTL_REG REG(0x2CA0)
91#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
92#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
93#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
94#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
95#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
96#define USB_HS1_HCLK_CTL_REG REG(0x2900)
97#define USB_HS1_RESET_REG REG(0x2910)
98#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
99#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700100#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
101#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
102#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
103#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
104#define USB_HSIC_RESET_REG REG(0x2934)
105#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
106#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
107#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700108#define USB_PHY0_RESET_REG REG(0x2E20)
109
110/* Multimedia clock registers. */
111#define AHB_EN_REG REG_MM(0x0008)
112#define AHB_EN2_REG REG_MM(0x0038)
113#define AHB_NS_REG REG_MM(0x0004)
114#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700115#define CAMCLK0_NS_REG REG_MM(0x0148)
116#define CAMCLK0_CC_REG REG_MM(0x0140)
117#define CAMCLK0_MD_REG REG_MM(0x0144)
118#define CAMCLK1_NS_REG REG_MM(0x015C)
119#define CAMCLK1_CC_REG REG_MM(0x0154)
120#define CAMCLK1_MD_REG REG_MM(0x0158)
121#define CAMCLK2_NS_REG REG_MM(0x0228)
122#define CAMCLK2_CC_REG REG_MM(0x0220)
123#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700124#define CSI0_NS_REG REG_MM(0x0048)
125#define CSI0_CC_REG REG_MM(0x0040)
126#define CSI0_MD_REG REG_MM(0x0044)
127#define CSI1_NS_REG REG_MM(0x0010)
128#define CSI1_CC_REG REG_MM(0x0024)
129#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700130#define CSI2_NS_REG REG_MM(0x0234)
131#define CSI2_CC_REG REG_MM(0x022C)
132#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700133#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
134#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
135#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
136#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
137#define DSI1_BYTE_CC_REG REG_MM(0x0090)
138#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
139#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
140#define DSI1_ESC_NS_REG REG_MM(0x011C)
141#define DSI1_ESC_CC_REG REG_MM(0x00CC)
142#define DSI2_ESC_NS_REG REG_MM(0x0150)
143#define DSI2_ESC_CC_REG REG_MM(0x013C)
144#define DSI_PIXEL_CC_REG REG_MM(0x0130)
145#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
146#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
147#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
148#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
149#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
150#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
151#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
152#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
153#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
154#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
155#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
156#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
157#define GFX2D0_CC_REG REG_MM(0x0060)
158#define GFX2D0_MD0_REG REG_MM(0x0064)
159#define GFX2D0_MD1_REG REG_MM(0x0068)
160#define GFX2D0_NS_REG REG_MM(0x0070)
161#define GFX2D1_CC_REG REG_MM(0x0074)
162#define GFX2D1_MD0_REG REG_MM(0x0078)
163#define GFX2D1_MD1_REG REG_MM(0x006C)
164#define GFX2D1_NS_REG REG_MM(0x007C)
165#define GFX3D_CC_REG REG_MM(0x0080)
166#define GFX3D_MD0_REG REG_MM(0x0084)
167#define GFX3D_MD1_REG REG_MM(0x0088)
168#define GFX3D_NS_REG REG_MM(0x008C)
169#define IJPEG_CC_REG REG_MM(0x0098)
170#define IJPEG_MD_REG REG_MM(0x009C)
171#define IJPEG_NS_REG REG_MM(0x00A0)
172#define JPEGD_CC_REG REG_MM(0x00A4)
173#define JPEGD_NS_REG REG_MM(0x00AC)
174#define MAXI_EN_REG REG_MM(0x0018)
175#define MAXI_EN2_REG REG_MM(0x0020)
176#define MAXI_EN3_REG REG_MM(0x002C)
177#define MAXI_EN4_REG REG_MM(0x0114)
178#define MDP_CC_REG REG_MM(0x00C0)
179#define MDP_LUT_CC_REG REG_MM(0x016C)
180#define MDP_MD0_REG REG_MM(0x00C4)
181#define MDP_MD1_REG REG_MM(0x00C8)
182#define MDP_NS_REG REG_MM(0x00D0)
183#define MISC_CC_REG REG_MM(0x0058)
184#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700185#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700186#define MM_PLL1_MODE_REG REG_MM(0x031C)
187#define ROT_CC_REG REG_MM(0x00E0)
188#define ROT_NS_REG REG_MM(0x00E8)
189#define SAXI_EN_REG REG_MM(0x0030)
190#define SW_RESET_AHB_REG REG_MM(0x020C)
191#define SW_RESET_AHB2_REG REG_MM(0x0200)
192#define SW_RESET_ALL_REG REG_MM(0x0204)
193#define SW_RESET_AXI_REG REG_MM(0x0208)
194#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700195#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700196#define TV_CC_REG REG_MM(0x00EC)
197#define TV_CC2_REG REG_MM(0x0124)
198#define TV_MD_REG REG_MM(0x00F0)
199#define TV_NS_REG REG_MM(0x00F4)
200#define VCODEC_CC_REG REG_MM(0x00F8)
201#define VCODEC_MD0_REG REG_MM(0x00FC)
202#define VCODEC_MD1_REG REG_MM(0x0128)
203#define VCODEC_NS_REG REG_MM(0x0100)
204#define VFE_CC_REG REG_MM(0x0104)
205#define VFE_MD_REG REG_MM(0x0108)
206#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700207#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700208#define VPE_CC_REG REG_MM(0x0110)
209#define VPE_NS_REG REG_MM(0x0118)
210
211/* Low-power Audio clock registers. */
212#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
213#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
214#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
215#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
216#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
217#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
218#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
219#define LCC_MI2S_MD_REG REG_LPA(0x004C)
220#define LCC_MI2S_NS_REG REG_LPA(0x0048)
221#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
222#define LCC_PCM_MD_REG REG_LPA(0x0058)
223#define LCC_PCM_NS_REG REG_LPA(0x0054)
224#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
225#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700226#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
227#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
228#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
229#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
230#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
231#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
232#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
233#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
234#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
235#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
236
Matt Wagantall8b38f942011-08-02 18:23:18 -0700237#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
238
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700239/* MUX source input identifiers. */
240#define pxo_to_bb_mux 0
241#define cxo_to_bb_mux pxo_to_bb_mux
242#define pll0_to_bb_mux 2
243#define pll8_to_bb_mux 3
244#define pll6_to_bb_mux 4
245#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700246#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700247#define pxo_to_mm_mux 0
248#define pll1_to_mm_mux 1
249#define pll2_to_mm_mux 1
250#define pll8_to_mm_mux 2
251#define pll0_to_mm_mux 3
252#define gnd_to_mm_mux 4
Stephen Boyd94625ef2011-07-12 17:06:01 -0700253#define pll3_to_mm_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700254#define hdmi_pll_to_mm_mux 3
255#define cxo_to_xo_mux 0
256#define pxo_to_xo_mux 1
257#define gnd_to_xo_mux 3
258#define pxo_to_lpa_mux 0
259#define cxo_to_lpa_mux 1
260#define pll4_to_lpa_mux 2
261#define gnd_to_lpa_mux 6
262
263/* Test Vector Macros */
264#define TEST_TYPE_PER_LS 1
265#define TEST_TYPE_PER_HS 2
266#define TEST_TYPE_MM_LS 3
267#define TEST_TYPE_MM_HS 4
268#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700269#define TEST_TYPE_CPUL2 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270#define TEST_TYPE_SHIFT 24
271#define TEST_CLK_SEL_MASK BM(23, 0)
272#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
273#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
274#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
275#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
276#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
277#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700278#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700279
280#define MN_MODE_DUAL_EDGE 0x2
281
282/* MD Registers */
283#define MD4(m_lsb, m, n_lsb, n) \
284 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
285#define MD8(m_lsb, m, n_lsb, n) \
286 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
287#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
288
289/* NS Registers */
290#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
291 (BVAL(n_msb, n_lsb, ~(n-m)) \
292 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
293 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
294
295#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
296 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
297 | BVAL(s_msb, s_lsb, s))
298
299#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
300 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
301
302#define NS_DIV(d_msb , d_lsb, d) \
303 BVAL(d_msb, d_lsb, (d-1))
304
305#define NS_SRC_SEL(s_msb, s_lsb, s) \
306 BVAL(s_msb, s_lsb, s)
307
308#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
309 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
310 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
311 | BVAL((s0_lsb+2), s0_lsb, s) \
312 | BVAL((s1_lsb+2), s1_lsb, s))
313
314#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
315 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
316 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
317 | BVAL((s0_lsb+2), s0_lsb, s) \
318 | BVAL((s1_lsb+2), s1_lsb, s))
319
320#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
321 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
322 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
323 | BVAL(s0_msb, s0_lsb, s) \
324 | BVAL(s1_msb, s1_lsb, s))
325
326/* CC Registers */
327#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
328#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
329 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
330 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
331 * !!(n))
332
333struct pll_rate {
334 const uint32_t l_val;
335 const uint32_t m_val;
336 const uint32_t n_val;
337 const uint32_t vco;
338 const uint32_t post_div;
339 const uint32_t i_bits;
340};
341#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
342
343/*
344 * Clock Descriptions
345 */
346
347static struct msm_xo_voter *xo_pxo, *xo_cxo;
348
349static int pxo_clk_enable(struct clk *clk)
350{
351 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
352}
353
354static void pxo_clk_disable(struct clk *clk)
355{
356 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
357}
358
359static struct clk_ops clk_ops_pxo = {
360 .enable = pxo_clk_enable,
361 .disable = pxo_clk_disable,
362 .get_rate = fixed_clk_get_rate,
363 .is_local = local_clk_is_local,
364};
365
366static struct fixed_clk pxo_clk = {
367 .rate = 27000000,
368 .c = {
369 .dbg_name = "pxo_clk",
370 .ops = &clk_ops_pxo,
371 CLK_INIT(pxo_clk.c),
372 },
373};
374
375static int cxo_clk_enable(struct clk *clk)
376{
377 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
378}
379
380static void cxo_clk_disable(struct clk *clk)
381{
382 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
383}
384
385static struct clk_ops clk_ops_cxo = {
386 .enable = cxo_clk_enable,
387 .disable = cxo_clk_disable,
388 .get_rate = fixed_clk_get_rate,
389 .is_local = local_clk_is_local,
390};
391
392static struct fixed_clk cxo_clk = {
393 .rate = 19200000,
394 .c = {
395 .dbg_name = "cxo_clk",
396 .ops = &clk_ops_cxo,
397 CLK_INIT(cxo_clk.c),
398 },
399};
400
401static struct pll_clk pll2_clk = {
402 .rate = 800000000,
403 .mode_reg = MM_PLL1_MODE_REG,
404 .parent = &pxo_clk.c,
405 .c = {
406 .dbg_name = "pll2_clk",
407 .ops = &clk_ops_pll,
408 CLK_INIT(pll2_clk.c),
409 },
410};
411
Stephen Boyd94625ef2011-07-12 17:06:01 -0700412static struct pll_clk pll3_clk = {
413 .rate = 1200000000,
414 .mode_reg = BB_MMCC_PLL2_MODE_REG,
415 .parent = &pxo_clk.c,
416 .c = {
417 .dbg_name = "pll3_clk",
418 .ops = &clk_ops_pll,
419 CLK_INIT(pll3_clk.c),
420 },
421};
422
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700423static struct pll_vote_clk pll4_clk = {
424 .rate = 393216000,
425 .en_reg = BB_PLL_ENA_SC0_REG,
426 .en_mask = BIT(4),
427 .status_reg = LCC_PLL0_STATUS_REG,
428 .parent = &pxo_clk.c,
429 .c = {
430 .dbg_name = "pll4_clk",
431 .ops = &clk_ops_pll_vote,
432 CLK_INIT(pll4_clk.c),
433 },
434};
435
436static struct pll_vote_clk pll8_clk = {
437 .rate = 384000000,
438 .en_reg = BB_PLL_ENA_SC0_REG,
439 .en_mask = BIT(8),
440 .status_reg = BB_PLL8_STATUS_REG,
441 .parent = &pxo_clk.c,
442 .c = {
443 .dbg_name = "pll8_clk",
444 .ops = &clk_ops_pll_vote,
445 CLK_INIT(pll8_clk.c),
446 },
447};
448
Stephen Boyd94625ef2011-07-12 17:06:01 -0700449static struct pll_vote_clk pll14_clk = {
450 .rate = 480000000,
451 .en_reg = BB_PLL_ENA_SC0_REG,
452 .en_mask = BIT(14),
453 .status_reg = BB_PLL14_STATUS_REG,
454 .parent = &pxo_clk.c,
455 .c = {
456 .dbg_name = "pll14_clk",
457 .ops = &clk_ops_pll_vote,
458 CLK_INIT(pll14_clk.c),
459 },
460};
461
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700462/*
463 * SoC-specific functions required by clock-local driver
464 */
465
466/* Update the sys_vdd voltage given a level. */
467static int msm8960_update_sys_vdd(enum sys_vdd_level level)
468{
469 static const int vdd_uv[] = {
470 [NONE...LOW] = 945000,
471 [NOMINAL] = 1050000,
472 [HIGH] = 1150000,
473 };
474
475 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
476 vdd_uv[level], vdd_uv[HIGH], 1);
477}
478
479static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
480{
481 return branch_reset(&to_rcg_clk(clk)->b, action);
482}
483
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700484static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700485 .enable = rcg_clk_enable,
486 .disable = rcg_clk_disable,
487 .auto_off = rcg_clk_auto_off,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700488 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700489 .set_rate = rcg_clk_set_rate,
490 .set_min_rate = rcg_clk_set_min_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700491 .get_rate = rcg_clk_get_rate,
492 .list_rate = rcg_clk_list_rate,
493 .is_enabled = rcg_clk_is_enabled,
494 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700495 .reset = soc_clk_reset,
496 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700497 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700498};
499
500static struct clk_ops clk_ops_branch = {
501 .enable = branch_clk_enable,
502 .disable = branch_clk_disable,
503 .auto_off = branch_clk_auto_off,
504 .is_enabled = branch_clk_is_enabled,
505 .reset = branch_clk_reset,
506 .is_local = local_clk_is_local,
507 .get_parent = branch_clk_get_parent,
508 .set_parent = branch_clk_set_parent,
509};
510
511static struct clk_ops clk_ops_reset = {
512 .reset = branch_clk_reset,
513 .is_local = local_clk_is_local,
514};
515
516/* AXI Interfaces */
517static struct branch_clk gmem_axi_clk = {
518 .b = {
519 .ctl_reg = MAXI_EN_REG,
520 .en_mask = BIT(24),
521 .halt_reg = DBG_BUS_VEC_E_REG,
522 .halt_bit = 6,
523 },
524 .c = {
525 .dbg_name = "gmem_axi_clk",
526 .ops = &clk_ops_branch,
527 CLK_INIT(gmem_axi_clk.c),
528 },
529};
530
531static struct branch_clk ijpeg_axi_clk = {
532 .b = {
533 .ctl_reg = MAXI_EN_REG,
534 .en_mask = BIT(21),
535 .reset_reg = SW_RESET_AXI_REG,
536 .reset_mask = BIT(14),
537 .halt_reg = DBG_BUS_VEC_E_REG,
538 .halt_bit = 4,
539 },
540 .c = {
541 .dbg_name = "ijpeg_axi_clk",
542 .ops = &clk_ops_branch,
543 CLK_INIT(ijpeg_axi_clk.c),
544 },
545};
546
547static struct branch_clk imem_axi_clk = {
548 .b = {
549 .ctl_reg = MAXI_EN_REG,
550 .en_mask = BIT(22),
551 .reset_reg = SW_RESET_CORE_REG,
552 .reset_mask = BIT(10),
553 .halt_reg = DBG_BUS_VEC_E_REG,
554 .halt_bit = 7,
555 },
556 .c = {
557 .dbg_name = "imem_axi_clk",
558 .ops = &clk_ops_branch,
559 CLK_INIT(imem_axi_clk.c),
560 },
561};
562
563static struct branch_clk jpegd_axi_clk = {
564 .b = {
565 .ctl_reg = MAXI_EN_REG,
566 .en_mask = BIT(25),
567 .halt_reg = DBG_BUS_VEC_E_REG,
568 .halt_bit = 5,
569 },
570 .c = {
571 .dbg_name = "jpegd_axi_clk",
572 .ops = &clk_ops_branch,
573 CLK_INIT(jpegd_axi_clk.c),
574 },
575};
576
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700577static struct branch_clk vcodec_axi_b_clk = {
578 .b = {
579 .ctl_reg = MAXI_EN4_REG,
580 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700581 .halt_reg = DBG_BUS_VEC_I_REG,
582 .halt_bit = 25,
583 },
584 .c = {
585 .dbg_name = "vcodec_axi_b_clk",
586 .ops = &clk_ops_branch,
587 CLK_INIT(vcodec_axi_b_clk.c),
588 },
589};
590
Matt Wagantall91f42702011-07-14 12:01:15 -0700591static struct branch_clk vcodec_axi_a_clk = {
592 .b = {
593 .ctl_reg = MAXI_EN4_REG,
594 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700595 .halt_reg = DBG_BUS_VEC_I_REG,
596 .halt_bit = 26,
597 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700598 .c = {
599 .dbg_name = "vcodec_axi_a_clk",
600 .ops = &clk_ops_branch,
601 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700602 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700603 },
604};
605
606static struct branch_clk vcodec_axi_clk = {
607 .b = {
608 .ctl_reg = MAXI_EN_REG,
609 .en_mask = BIT(19),
610 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700611 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700612 .halt_reg = DBG_BUS_VEC_E_REG,
613 .halt_bit = 3,
614 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700615 .c = {
616 .dbg_name = "vcodec_axi_clk",
617 .ops = &clk_ops_branch,
618 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700619 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700620 },
621};
622
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700623static struct branch_clk vfe_axi_clk = {
624 .b = {
625 .ctl_reg = MAXI_EN_REG,
626 .en_mask = BIT(18),
627 .reset_reg = SW_RESET_AXI_REG,
628 .reset_mask = BIT(9),
629 .halt_reg = DBG_BUS_VEC_E_REG,
630 .halt_bit = 0,
631 },
632 .c = {
633 .dbg_name = "vfe_axi_clk",
634 .ops = &clk_ops_branch,
635 CLK_INIT(vfe_axi_clk.c),
636 },
637};
638
639static struct branch_clk mdp_axi_clk = {
640 .b = {
641 .ctl_reg = MAXI_EN_REG,
642 .en_mask = BIT(23),
643 .reset_reg = SW_RESET_AXI_REG,
644 .reset_mask = BIT(13),
645 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700646 .halt_bit = 8,
647 },
648 .c = {
649 .dbg_name = "mdp_axi_clk",
650 .ops = &clk_ops_branch,
651 CLK_INIT(mdp_axi_clk.c),
652 },
653};
654
655static struct branch_clk rot_axi_clk = {
656 .b = {
657 .ctl_reg = MAXI_EN2_REG,
658 .en_mask = BIT(24),
659 .reset_reg = SW_RESET_AXI_REG,
660 .reset_mask = BIT(6),
661 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700662 .halt_bit = 2,
663 },
664 .c = {
665 .dbg_name = "rot_axi_clk",
666 .ops = &clk_ops_branch,
667 CLK_INIT(rot_axi_clk.c),
668 },
669};
670
671static struct branch_clk vpe_axi_clk = {
672 .b = {
673 .ctl_reg = MAXI_EN2_REG,
674 .en_mask = BIT(26),
675 .reset_reg = SW_RESET_AXI_REG,
676 .reset_mask = BIT(15),
677 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700678 .halt_bit = 1,
679 },
680 .c = {
681 .dbg_name = "vpe_axi_clk",
682 .ops = &clk_ops_branch,
683 CLK_INIT(vpe_axi_clk.c),
684 },
685};
686
687/* AHB Interfaces */
688static struct branch_clk amp_p_clk = {
689 .b = {
690 .ctl_reg = AHB_EN_REG,
691 .en_mask = BIT(24),
692 .halt_reg = DBG_BUS_VEC_F_REG,
693 .halt_bit = 18,
694 },
695 .c = {
696 .dbg_name = "amp_p_clk",
697 .ops = &clk_ops_branch,
698 CLK_INIT(amp_p_clk.c),
699 },
700};
701
Matt Wagantallc23eee92011-08-16 23:06:52 -0700702static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700703 .b = {
704 .ctl_reg = AHB_EN_REG,
705 .en_mask = BIT(7),
706 .reset_reg = SW_RESET_AHB_REG,
707 .reset_mask = BIT(17),
708 .halt_reg = DBG_BUS_VEC_F_REG,
709 .halt_bit = 16,
710 },
711 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700712 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700713 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700714 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700715 },
716};
717
718static struct branch_clk dsi1_m_p_clk = {
719 .b = {
720 .ctl_reg = AHB_EN_REG,
721 .en_mask = BIT(9),
722 .reset_reg = SW_RESET_AHB_REG,
723 .reset_mask = BIT(6),
724 .halt_reg = DBG_BUS_VEC_F_REG,
725 .halt_bit = 19,
726 },
727 .c = {
728 .dbg_name = "dsi1_m_p_clk",
729 .ops = &clk_ops_branch,
730 CLK_INIT(dsi1_m_p_clk.c),
731 },
732};
733
734static struct branch_clk dsi1_s_p_clk = {
735 .b = {
736 .ctl_reg = AHB_EN_REG,
737 .en_mask = BIT(18),
738 .reset_reg = SW_RESET_AHB_REG,
739 .reset_mask = BIT(5),
740 .halt_reg = DBG_BUS_VEC_F_REG,
741 .halt_bit = 21,
742 },
743 .c = {
744 .dbg_name = "dsi1_s_p_clk",
745 .ops = &clk_ops_branch,
746 CLK_INIT(dsi1_s_p_clk.c),
747 },
748};
749
750static struct branch_clk dsi2_m_p_clk = {
751 .b = {
752 .ctl_reg = AHB_EN_REG,
753 .en_mask = BIT(17),
754 .reset_reg = SW_RESET_AHB2_REG,
755 .reset_mask = BIT(1),
756 .halt_reg = DBG_BUS_VEC_E_REG,
757 .halt_bit = 18,
758 },
759 .c = {
760 .dbg_name = "dsi2_m_p_clk",
761 .ops = &clk_ops_branch,
762 CLK_INIT(dsi2_m_p_clk.c),
763 },
764};
765
766static struct branch_clk dsi2_s_p_clk = {
767 .b = {
768 .ctl_reg = AHB_EN_REG,
769 .en_mask = BIT(22),
770 .reset_reg = SW_RESET_AHB2_REG,
771 .reset_mask = BIT(0),
772 .halt_reg = DBG_BUS_VEC_F_REG,
773 .halt_bit = 20,
774 },
775 .c = {
776 .dbg_name = "dsi2_s_p_clk",
777 .ops = &clk_ops_branch,
778 CLK_INIT(dsi2_s_p_clk.c),
779 },
780};
781
782static struct branch_clk gfx2d0_p_clk = {
783 .b = {
784 .ctl_reg = AHB_EN_REG,
785 .en_mask = BIT(19),
786 .reset_reg = SW_RESET_AHB_REG,
787 .reset_mask = BIT(12),
788 .halt_reg = DBG_BUS_VEC_F_REG,
789 .halt_bit = 2,
790 },
791 .c = {
792 .dbg_name = "gfx2d0_p_clk",
793 .ops = &clk_ops_branch,
794 CLK_INIT(gfx2d0_p_clk.c),
795 },
796};
797
798static struct branch_clk gfx2d1_p_clk = {
799 .b = {
800 .ctl_reg = AHB_EN_REG,
801 .en_mask = BIT(2),
802 .reset_reg = SW_RESET_AHB_REG,
803 .reset_mask = BIT(11),
804 .halt_reg = DBG_BUS_VEC_F_REG,
805 .halt_bit = 3,
806 },
807 .c = {
808 .dbg_name = "gfx2d1_p_clk",
809 .ops = &clk_ops_branch,
810 CLK_INIT(gfx2d1_p_clk.c),
811 },
812};
813
814static struct branch_clk gfx3d_p_clk = {
815 .b = {
816 .ctl_reg = AHB_EN_REG,
817 .en_mask = BIT(3),
818 .reset_reg = SW_RESET_AHB_REG,
819 .reset_mask = BIT(10),
820 .halt_reg = DBG_BUS_VEC_F_REG,
821 .halt_bit = 4,
822 },
823 .c = {
824 .dbg_name = "gfx3d_p_clk",
825 .ops = &clk_ops_branch,
826 CLK_INIT(gfx3d_p_clk.c),
827 },
828};
829
830static struct branch_clk hdmi_m_p_clk = {
831 .b = {
832 .ctl_reg = AHB_EN_REG,
833 .en_mask = BIT(14),
834 .reset_reg = SW_RESET_AHB_REG,
835 .reset_mask = BIT(9),
836 .halt_reg = DBG_BUS_VEC_F_REG,
837 .halt_bit = 5,
838 },
839 .c = {
840 .dbg_name = "hdmi_m_p_clk",
841 .ops = &clk_ops_branch,
842 CLK_INIT(hdmi_m_p_clk.c),
843 },
844};
845
846static struct branch_clk hdmi_s_p_clk = {
847 .b = {
848 .ctl_reg = AHB_EN_REG,
849 .en_mask = BIT(4),
850 .reset_reg = SW_RESET_AHB_REG,
851 .reset_mask = BIT(9),
852 .halt_reg = DBG_BUS_VEC_F_REG,
853 .halt_bit = 6,
854 },
855 .c = {
856 .dbg_name = "hdmi_s_p_clk",
857 .ops = &clk_ops_branch,
858 CLK_INIT(hdmi_s_p_clk.c),
859 },
860};
861
862static struct branch_clk ijpeg_p_clk = {
863 .b = {
864 .ctl_reg = AHB_EN_REG,
865 .en_mask = BIT(5),
866 .reset_reg = SW_RESET_AHB_REG,
867 .reset_mask = BIT(7),
868 .halt_reg = DBG_BUS_VEC_F_REG,
869 .halt_bit = 9,
870 },
871 .c = {
872 .dbg_name = "ijpeg_p_clk",
873 .ops = &clk_ops_branch,
874 CLK_INIT(ijpeg_p_clk.c),
875 },
876};
877
878static struct branch_clk imem_p_clk = {
879 .b = {
880 .ctl_reg = AHB_EN_REG,
881 .en_mask = BIT(6),
882 .reset_reg = SW_RESET_AHB_REG,
883 .reset_mask = BIT(8),
884 .halt_reg = DBG_BUS_VEC_F_REG,
885 .halt_bit = 10,
886 },
887 .c = {
888 .dbg_name = "imem_p_clk",
889 .ops = &clk_ops_branch,
890 CLK_INIT(imem_p_clk.c),
891 },
892};
893
894static struct branch_clk jpegd_p_clk = {
895 .b = {
896 .ctl_reg = AHB_EN_REG,
897 .en_mask = BIT(21),
898 .reset_reg = SW_RESET_AHB_REG,
899 .reset_mask = BIT(4),
900 .halt_reg = DBG_BUS_VEC_F_REG,
901 .halt_bit = 7,
902 },
903 .c = {
904 .dbg_name = "jpegd_p_clk",
905 .ops = &clk_ops_branch,
906 CLK_INIT(jpegd_p_clk.c),
907 },
908};
909
910static struct branch_clk mdp_p_clk = {
911 .b = {
912 .ctl_reg = AHB_EN_REG,
913 .en_mask = BIT(10),
914 .reset_reg = SW_RESET_AHB_REG,
915 .reset_mask = BIT(3),
916 .halt_reg = DBG_BUS_VEC_F_REG,
917 .halt_bit = 11,
918 },
919 .c = {
920 .dbg_name = "mdp_p_clk",
921 .ops = &clk_ops_branch,
922 CLK_INIT(mdp_p_clk.c),
923 },
924};
925
926static struct branch_clk rot_p_clk = {
927 .b = {
928 .ctl_reg = AHB_EN_REG,
929 .en_mask = BIT(12),
930 .reset_reg = SW_RESET_AHB_REG,
931 .reset_mask = BIT(2),
932 .halt_reg = DBG_BUS_VEC_F_REG,
933 .halt_bit = 13,
934 },
935 .c = {
936 .dbg_name = "rot_p_clk",
937 .ops = &clk_ops_branch,
938 CLK_INIT(rot_p_clk.c),
939 },
940};
941
942static struct branch_clk smmu_p_clk = {
943 .b = {
944 .ctl_reg = AHB_EN_REG,
945 .en_mask = BIT(15),
946 .halt_reg = DBG_BUS_VEC_F_REG,
947 .halt_bit = 22,
948 },
949 .c = {
950 .dbg_name = "smmu_p_clk",
951 .ops = &clk_ops_branch,
952 CLK_INIT(smmu_p_clk.c),
953 },
954};
955
956static struct branch_clk tv_enc_p_clk = {
957 .b = {
958 .ctl_reg = AHB_EN_REG,
959 .en_mask = BIT(25),
960 .reset_reg = SW_RESET_AHB_REG,
961 .reset_mask = BIT(15),
962 .halt_reg = DBG_BUS_VEC_F_REG,
963 .halt_bit = 23,
964 },
965 .c = {
966 .dbg_name = "tv_enc_p_clk",
967 .ops = &clk_ops_branch,
968 CLK_INIT(tv_enc_p_clk.c),
969 },
970};
971
972static struct branch_clk vcodec_p_clk = {
973 .b = {
974 .ctl_reg = AHB_EN_REG,
975 .en_mask = BIT(11),
976 .reset_reg = SW_RESET_AHB_REG,
977 .reset_mask = BIT(1),
978 .halt_reg = DBG_BUS_VEC_F_REG,
979 .halt_bit = 12,
980 },
981 .c = {
982 .dbg_name = "vcodec_p_clk",
983 .ops = &clk_ops_branch,
984 CLK_INIT(vcodec_p_clk.c),
985 },
986};
987
988static struct branch_clk vfe_p_clk = {
989 .b = {
990 .ctl_reg = AHB_EN_REG,
991 .en_mask = BIT(13),
992 .reset_reg = SW_RESET_AHB_REG,
993 .reset_mask = BIT(0),
994 .halt_reg = DBG_BUS_VEC_F_REG,
995 .halt_bit = 14,
996 },
997 .c = {
998 .dbg_name = "vfe_p_clk",
999 .ops = &clk_ops_branch,
1000 CLK_INIT(vfe_p_clk.c),
1001 },
1002};
1003
1004static struct branch_clk vpe_p_clk = {
1005 .b = {
1006 .ctl_reg = AHB_EN_REG,
1007 .en_mask = BIT(16),
1008 .reset_reg = SW_RESET_AHB_REG,
1009 .reset_mask = BIT(14),
1010 .halt_reg = DBG_BUS_VEC_F_REG,
1011 .halt_bit = 15,
1012 },
1013 .c = {
1014 .dbg_name = "vpe_p_clk",
1015 .ops = &clk_ops_branch,
1016 CLK_INIT(vpe_p_clk.c),
1017 },
1018};
1019
1020/*
1021 * Peripheral Clocks
1022 */
1023#define CLK_GSBI_UART(i, n, h_r, h_b) \
1024 struct rcg_clk i##_clk = { \
1025 .b = { \
1026 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1027 .en_mask = BIT(9), \
1028 .reset_reg = GSBIn_RESET_REG(n), \
1029 .reset_mask = BIT(0), \
1030 .halt_reg = h_r, \
1031 .halt_bit = h_b, \
1032 }, \
1033 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1034 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1035 .root_en_mask = BIT(11), \
1036 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1037 .set_rate = set_rate_mnd, \
1038 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001039 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001040 .c = { \
1041 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001042 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001043 CLK_INIT(i##_clk.c), \
1044 }, \
1045 }
1046#define F_GSBI_UART(f, s, d, m, n, v) \
1047 { \
1048 .freq_hz = f, \
1049 .src_clk = &s##_clk.c, \
1050 .md_val = MD16(m, n), \
1051 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1052 .mnd_en_mask = BIT(8) * !!(n), \
1053 .sys_vdd = v, \
1054 }
1055static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
1056 F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
1057 F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
1058 F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
1059 F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
1060 F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
1061 F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
1062 F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
1063 F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
1064 F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
1065 F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
1066 F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
1067 F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
1068 F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
1069 F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
1070 F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
1071 F_END
1072};
1073
1074static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1075static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1076static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1077static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1078static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1079static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1080static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1081static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1082static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1083static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1084static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1085static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1086
1087#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1088 struct rcg_clk i##_clk = { \
1089 .b = { \
1090 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1091 .en_mask = BIT(9), \
1092 .reset_reg = GSBIn_RESET_REG(n), \
1093 .reset_mask = BIT(0), \
1094 .halt_reg = h_r, \
1095 .halt_bit = h_b, \
1096 }, \
1097 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1098 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1099 .root_en_mask = BIT(11), \
1100 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1101 .set_rate = set_rate_mnd, \
1102 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001103 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001104 .c = { \
1105 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001106 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001107 CLK_INIT(i##_clk.c), \
1108 }, \
1109 }
1110#define F_GSBI_QUP(f, s, d, m, n, v) \
1111 { \
1112 .freq_hz = f, \
1113 .src_clk = &s##_clk.c, \
1114 .md_val = MD8(16, m, 0, n), \
1115 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1116 .mnd_en_mask = BIT(8) * !!(n), \
1117 .sys_vdd = v, \
1118 }
1119static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
1120 F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
1121 F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
1122 F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
1123 F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
1124 F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
1125 F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
1126 F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
1127 F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
1128 F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
1129 F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
1130 F_END
1131};
1132
1133static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1134static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1135static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1136static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1137static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1138static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1139static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1140static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1141static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1142static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1143static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1144static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1145
1146#define F_PDM(f, s, d, v) \
1147 { \
1148 .freq_hz = f, \
1149 .src_clk = &s##_clk.c, \
1150 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1151 .sys_vdd = v, \
1152 }
1153static struct clk_freq_tbl clk_tbl_pdm[] = {
1154 F_PDM( 0, gnd, 1, NONE),
1155 F_PDM(27000000, pxo, 1, LOW),
1156 F_END
1157};
1158
1159static struct rcg_clk pdm_clk = {
1160 .b = {
1161 .ctl_reg = PDM_CLK_NS_REG,
1162 .en_mask = BIT(9),
1163 .reset_reg = PDM_CLK_NS_REG,
1164 .reset_mask = BIT(12),
1165 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1166 .halt_bit = 3,
1167 },
1168 .ns_reg = PDM_CLK_NS_REG,
1169 .root_en_mask = BIT(11),
1170 .ns_mask = BM(1, 0),
1171 .set_rate = set_rate_nop,
1172 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001173 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001174 .c = {
1175 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001176 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001177 CLK_INIT(pdm_clk.c),
1178 },
1179};
1180
1181static struct branch_clk pmem_clk = {
1182 .b = {
1183 .ctl_reg = PMEM_ACLK_CTL_REG,
1184 .en_mask = BIT(4),
1185 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1186 .halt_bit = 20,
1187 },
1188 .c = {
1189 .dbg_name = "pmem_clk",
1190 .ops = &clk_ops_branch,
1191 CLK_INIT(pmem_clk.c),
1192 },
1193};
1194
1195#define F_PRNG(f, s, v) \
1196 { \
1197 .freq_hz = f, \
1198 .src_clk = &s##_clk.c, \
1199 .sys_vdd = v, \
1200 }
1201static struct clk_freq_tbl clk_tbl_prng[] = {
1202 F_PRNG(64000000, pll8, NOMINAL),
1203 F_END
1204};
1205
1206static struct rcg_clk prng_clk = {
1207 .b = {
1208 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1209 .en_mask = BIT(10),
1210 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1211 .halt_check = HALT_VOTED,
1212 .halt_bit = 10,
1213 },
1214 .set_rate = set_rate_nop,
1215 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001216 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001217 .c = {
1218 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001219 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001220 CLK_INIT(prng_clk.c),
1221 },
1222};
1223
Stephen Boyda78a7402011-08-02 11:23:39 -07001224#define CLK_SDC(name, n, h_b, f_table) \
1225 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001226 .b = { \
1227 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1228 .en_mask = BIT(9), \
1229 .reset_reg = SDCn_RESET_REG(n), \
1230 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001231 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001232 .halt_bit = h_b, \
1233 }, \
1234 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1235 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1236 .root_en_mask = BIT(11), \
1237 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1238 .set_rate = set_rate_mnd, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001239 .freq_tbl = f_table, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001240 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001241 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001242 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001243 .ops = &clk_ops_rcg_8960, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001244 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001245 }, \
1246 }
1247#define F_SDC(f, s, d, m, n, v) \
1248 { \
1249 .freq_hz = f, \
1250 .src_clk = &s##_clk.c, \
1251 .md_val = MD8(16, m, 0, n), \
1252 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1253 .mnd_en_mask = BIT(8) * !!(n), \
1254 .sys_vdd = v, \
1255 }
Stephen Boyda78a7402011-08-02 11:23:39 -07001256static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
1257 F_SDC( 0, gnd, 1, 0, 0, NONE),
1258 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1259 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1260 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1261 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1262 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1263 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1264 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1265 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
1266 F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
1267 F_END
1268};
1269
1270static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
1271static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
1272
1273static struct clk_freq_tbl clk_tbl_sdc3[] = {
1274 F_SDC( 0, gnd, 1, 0, 0, NONE),
1275 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1276 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1277 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1278 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1279 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1280 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1281 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1282 F_SDC( 64000000, pll8, 3, 1, 2, LOW),
1283 F_SDC( 96000000, pll8, 4, 0, 0, LOW),
1284 F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
1285 F_END
1286};
1287
1288static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
1289
1290static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001291 F_SDC( 0, gnd, 1, 0, 0, NONE),
1292 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1293 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1294 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1295 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1296 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1297 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1298 F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
1299 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001300 F_END
1301};
1302
Stephen Boyda78a7402011-08-02 11:23:39 -07001303static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
1304static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001305
1306#define F_TSIF_REF(f, s, d, m, n, v) \
1307 { \
1308 .freq_hz = f, \
1309 .src_clk = &s##_clk.c, \
1310 .md_val = MD16(m, n), \
1311 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1312 .mnd_en_mask = BIT(8) * !!(n), \
1313 .sys_vdd = v, \
1314 }
1315static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
1316 F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
1317 F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
1318 F_END
1319};
1320
1321static struct rcg_clk tsif_ref_clk = {
1322 .b = {
1323 .ctl_reg = TSIF_REF_CLK_NS_REG,
1324 .en_mask = BIT(9),
1325 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1326 .halt_bit = 5,
1327 },
1328 .ns_reg = TSIF_REF_CLK_NS_REG,
1329 .md_reg = TSIF_REF_CLK_MD_REG,
1330 .root_en_mask = BIT(11),
1331 .ns_mask = (BM(31, 16) | BM(6, 0)),
1332 .set_rate = set_rate_mnd,
1333 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001334 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001335 .c = {
1336 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001337 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001338 CLK_INIT(tsif_ref_clk.c),
1339 },
1340};
1341
1342#define F_TSSC(f, s, v) \
1343 { \
1344 .freq_hz = f, \
1345 .src_clk = &s##_clk.c, \
1346 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1347 .sys_vdd = v, \
1348 }
1349static struct clk_freq_tbl clk_tbl_tssc[] = {
1350 F_TSSC( 0, gnd, NONE),
1351 F_TSSC(27000000, pxo, LOW),
1352 F_END
1353};
1354
1355static struct rcg_clk tssc_clk = {
1356 .b = {
1357 .ctl_reg = TSSC_CLK_CTL_REG,
1358 .en_mask = BIT(4),
1359 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1360 .halt_bit = 4,
1361 },
1362 .ns_reg = TSSC_CLK_CTL_REG,
1363 .ns_mask = BM(1, 0),
1364 .set_rate = set_rate_nop,
1365 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001366 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001367 .c = {
1368 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001369 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001370 CLK_INIT(tssc_clk.c),
1371 },
1372};
1373
1374#define F_USB(f, s, d, m, n, v) \
1375 { \
1376 .freq_hz = f, \
1377 .src_clk = &s##_clk.c, \
1378 .md_val = MD8(16, m, 0, n), \
1379 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1380 .mnd_en_mask = BIT(8) * !!(n), \
1381 .sys_vdd = v, \
1382 }
1383static struct clk_freq_tbl clk_tbl_usb[] = {
1384 F_USB( 0, gnd, 1, 0, 0, NONE),
1385 F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
1386 F_END
1387};
1388
1389static struct rcg_clk usb_hs1_xcvr_clk = {
1390 .b = {
1391 .ctl_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1392 .en_mask = BIT(9),
1393 .reset_reg = USB_HS1_RESET_REG,
1394 .reset_mask = BIT(0),
1395 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1396 .halt_bit = 0,
1397 },
1398 .ns_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1399 .md_reg = USB_HS1_XCVR_FS_CLK_MD_REG,
1400 .root_en_mask = BIT(11),
1401 .ns_mask = (BM(23, 16) | BM(6, 0)),
1402 .set_rate = set_rate_mnd,
1403 .freq_tbl = clk_tbl_usb,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001404 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001405 .c = {
1406 .dbg_name = "usb_hs1_xcvr_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001407 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001408 CLK_INIT(usb_hs1_xcvr_clk.c),
1409 },
1410};
1411
Stephen Boyd94625ef2011-07-12 17:06:01 -07001412static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
1413 F_USB( 0, gnd, 1, 0, 0, NONE),
1414 F_USB(60000000, pll8, 1, 5, 32, LOW),
1415 F_END
1416};
1417
1418static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1419 .b = {
1420 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1421 .en_mask = BIT(9),
1422 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1423 .halt_bit = 26,
1424 },
1425 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1426 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1427 .root_en_mask = BIT(11),
1428 .ns_mask = (BM(23, 16) | BM(6, 0)),
1429 .set_rate = set_rate_mnd,
1430 .freq_tbl = clk_tbl_usb_hsic,
1431 .current_freq = &rcg_dummy_freq,
1432 .c = {
1433 .dbg_name = "usb_hsic_xcvr_fs_clk",
1434 .ops = &clk_ops_rcg_8960,
1435 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1436 },
1437};
1438
1439static struct branch_clk usb_hsic_system_clk = {
1440 .b = {
1441 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1442 .en_mask = BIT(4),
1443 .reset_reg = USB_HSIC_RESET_REG,
1444 .reset_mask = BIT(0),
1445 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1446 .halt_bit = 24,
1447 },
1448 .parent = &usb_hsic_xcvr_fs_clk.c,
1449 .c = {
1450 .dbg_name = "usb_hsic_system_clk",
1451 .ops = &clk_ops_branch,
1452 CLK_INIT(usb_hsic_system_clk.c),
1453 },
1454};
1455
1456#define F_USB_HSIC(f, s, v) \
1457 { \
1458 .freq_hz = f, \
1459 .src_clk = &s##_clk.c, \
1460 .sys_vdd = v, \
1461 }
1462static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
1463 F_USB_HSIC(480000000, pll14, LOW),
1464 F_END
1465};
1466
1467static struct rcg_clk usb_hsic_hsic_src_clk = {
1468 .b = {
1469 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1470 .halt_check = NOCHECK,
1471 },
1472 .root_en_mask = BIT(0),
1473 .set_rate = set_rate_nop,
1474 .freq_tbl = clk_tbl_usb2_hsic,
1475 .current_freq = &rcg_dummy_freq,
1476 .c = {
1477 .dbg_name = "usb_hsic_hsic_src_clk",
1478 .ops = &clk_ops_rcg_8960,
1479 CLK_INIT(usb_hsic_hsic_src_clk.c),
1480 },
1481};
1482
1483static struct branch_clk usb_hsic_hsic_clk = {
1484 .b = {
1485 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1486 .en_mask = BIT(0),
1487 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1488 .halt_bit = 19,
1489 },
1490 .parent = &usb_hsic_hsic_src_clk.c,
1491 .c = {
1492 .dbg_name = "usb_hsic_hsic_clk",
1493 .ops = &clk_ops_branch,
1494 CLK_INIT(usb_hsic_hsic_clk.c),
1495 },
1496};
1497
1498#define F_USB_HSIO_CAL(f, s, v) \
1499 { \
1500 .freq_hz = f, \
1501 .src_clk = &s##_clk.c, \
1502 .sys_vdd = v, \
1503 }
1504static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
1505 F_USB_HSIO_CAL(9000000, pxo, LOW),
1506 F_END
1507};
1508
1509static struct rcg_clk usb_hsic_hsio_cal_clk = {
1510 .b = {
1511 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1512 .en_mask = BIT(0),
1513 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1514 .halt_bit = 23,
1515 },
1516 .set_rate = set_rate_nop,
1517 .freq_tbl = clk_tbl_usb_hsio_cal,
1518 .current_freq = &rcg_dummy_freq,
1519 .c = {
1520 .dbg_name = "usb_hsic_hsio_cal_clk",
1521 .ops = &clk_ops_branch,
1522 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1523 },
1524};
1525
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001526static struct branch_clk usb_phy0_clk = {
1527 .b = {
1528 .reset_reg = USB_PHY0_RESET_REG,
1529 .reset_mask = BIT(0),
1530 },
1531 .c = {
1532 .dbg_name = "usb_phy0_clk",
1533 .ops = &clk_ops_reset,
1534 CLK_INIT(usb_phy0_clk.c),
1535 },
1536};
1537
1538#define CLK_USB_FS(i, n) \
1539 struct rcg_clk i##_clk = { \
1540 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1541 .b = { \
1542 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1543 .halt_check = NOCHECK, \
1544 }, \
1545 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1546 .root_en_mask = BIT(11), \
1547 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1548 .set_rate = set_rate_mnd, \
1549 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001550 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001551 .c = { \
1552 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001553 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001554 CLK_INIT(i##_clk.c), \
1555 }, \
1556 }
1557
1558static CLK_USB_FS(usb_fs1_src, 1);
1559static struct branch_clk usb_fs1_xcvr_clk = {
1560 .b = {
1561 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1562 .en_mask = BIT(9),
1563 .reset_reg = USB_FSn_RESET_REG(1),
1564 .reset_mask = BIT(1),
1565 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1566 .halt_bit = 15,
1567 },
1568 .parent = &usb_fs1_src_clk.c,
1569 .c = {
1570 .dbg_name = "usb_fs1_xcvr_clk",
1571 .ops = &clk_ops_branch,
1572 CLK_INIT(usb_fs1_xcvr_clk.c),
1573 },
1574};
1575
1576static struct branch_clk usb_fs1_sys_clk = {
1577 .b = {
1578 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1579 .en_mask = BIT(4),
1580 .reset_reg = USB_FSn_RESET_REG(1),
1581 .reset_mask = BIT(0),
1582 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1583 .halt_bit = 16,
1584 },
1585 .parent = &usb_fs1_src_clk.c,
1586 .c = {
1587 .dbg_name = "usb_fs1_sys_clk",
1588 .ops = &clk_ops_branch,
1589 CLK_INIT(usb_fs1_sys_clk.c),
1590 },
1591};
1592
1593static CLK_USB_FS(usb_fs2_src, 2);
1594static struct branch_clk usb_fs2_xcvr_clk = {
1595 .b = {
1596 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1597 .en_mask = BIT(9),
1598 .reset_reg = USB_FSn_RESET_REG(2),
1599 .reset_mask = BIT(1),
1600 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1601 .halt_bit = 12,
1602 },
1603 .parent = &usb_fs2_src_clk.c,
1604 .c = {
1605 .dbg_name = "usb_fs2_xcvr_clk",
1606 .ops = &clk_ops_branch,
1607 CLK_INIT(usb_fs2_xcvr_clk.c),
1608 },
1609};
1610
1611static struct branch_clk usb_fs2_sys_clk = {
1612 .b = {
1613 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1614 .en_mask = BIT(4),
1615 .reset_reg = USB_FSn_RESET_REG(2),
1616 .reset_mask = BIT(0),
1617 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1618 .halt_bit = 13,
1619 },
1620 .parent = &usb_fs2_src_clk.c,
1621 .c = {
1622 .dbg_name = "usb_fs2_sys_clk",
1623 .ops = &clk_ops_branch,
1624 CLK_INIT(usb_fs2_sys_clk.c),
1625 },
1626};
1627
1628/* Fast Peripheral Bus Clocks */
1629static struct branch_clk ce1_core_clk = {
1630 .b = {
1631 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1632 .en_mask = BIT(4),
1633 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1634 .halt_bit = 27,
1635 },
1636 .c = {
1637 .dbg_name = "ce1_core_clk",
1638 .ops = &clk_ops_branch,
1639 CLK_INIT(ce1_core_clk.c),
1640 },
1641};
1642static struct branch_clk ce1_p_clk = {
1643 .b = {
1644 .ctl_reg = CE1_HCLK_CTL_REG,
1645 .en_mask = BIT(4),
1646 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1647 .halt_bit = 1,
1648 },
1649 .c = {
1650 .dbg_name = "ce1_p_clk",
1651 .ops = &clk_ops_branch,
1652 CLK_INIT(ce1_p_clk.c),
1653 },
1654};
1655
1656static struct branch_clk dma_bam_p_clk = {
1657 .b = {
1658 .ctl_reg = DMA_BAM_HCLK_CTL,
1659 .en_mask = BIT(4),
1660 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1661 .halt_bit = 12,
1662 },
1663 .c = {
1664 .dbg_name = "dma_bam_p_clk",
1665 .ops = &clk_ops_branch,
1666 CLK_INIT(dma_bam_p_clk.c),
1667 },
1668};
1669
1670static struct branch_clk gsbi1_p_clk = {
1671 .b = {
1672 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1673 .en_mask = BIT(4),
1674 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1675 .halt_bit = 11,
1676 },
1677 .c = {
1678 .dbg_name = "gsbi1_p_clk",
1679 .ops = &clk_ops_branch,
1680 CLK_INIT(gsbi1_p_clk.c),
1681 },
1682};
1683
1684static struct branch_clk gsbi2_p_clk = {
1685 .b = {
1686 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
1687 .en_mask = BIT(4),
1688 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1689 .halt_bit = 7,
1690 },
1691 .c = {
1692 .dbg_name = "gsbi2_p_clk",
1693 .ops = &clk_ops_branch,
1694 CLK_INIT(gsbi2_p_clk.c),
1695 },
1696};
1697
1698static struct branch_clk gsbi3_p_clk = {
1699 .b = {
1700 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
1701 .en_mask = BIT(4),
1702 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1703 .halt_bit = 3,
1704 },
1705 .c = {
1706 .dbg_name = "gsbi3_p_clk",
1707 .ops = &clk_ops_branch,
1708 CLK_INIT(gsbi3_p_clk.c),
1709 },
1710};
1711
1712static struct branch_clk gsbi4_p_clk = {
1713 .b = {
1714 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
1715 .en_mask = BIT(4),
1716 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1717 .halt_bit = 27,
1718 },
1719 .c = {
1720 .dbg_name = "gsbi4_p_clk",
1721 .ops = &clk_ops_branch,
1722 CLK_INIT(gsbi4_p_clk.c),
1723 },
1724};
1725
1726static struct branch_clk gsbi5_p_clk = {
1727 .b = {
1728 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
1729 .en_mask = BIT(4),
1730 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1731 .halt_bit = 23,
1732 },
1733 .c = {
1734 .dbg_name = "gsbi5_p_clk",
1735 .ops = &clk_ops_branch,
1736 CLK_INIT(gsbi5_p_clk.c),
1737 },
1738};
1739
1740static struct branch_clk gsbi6_p_clk = {
1741 .b = {
1742 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
1743 .en_mask = BIT(4),
1744 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1745 .halt_bit = 19,
1746 },
1747 .c = {
1748 .dbg_name = "gsbi6_p_clk",
1749 .ops = &clk_ops_branch,
1750 CLK_INIT(gsbi6_p_clk.c),
1751 },
1752};
1753
1754static struct branch_clk gsbi7_p_clk = {
1755 .b = {
1756 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
1757 .en_mask = BIT(4),
1758 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1759 .halt_bit = 15,
1760 },
1761 .c = {
1762 .dbg_name = "gsbi7_p_clk",
1763 .ops = &clk_ops_branch,
1764 CLK_INIT(gsbi7_p_clk.c),
1765 },
1766};
1767
1768static struct branch_clk gsbi8_p_clk = {
1769 .b = {
1770 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
1771 .en_mask = BIT(4),
1772 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1773 .halt_bit = 11,
1774 },
1775 .c = {
1776 .dbg_name = "gsbi8_p_clk",
1777 .ops = &clk_ops_branch,
1778 CLK_INIT(gsbi8_p_clk.c),
1779 },
1780};
1781
1782static struct branch_clk gsbi9_p_clk = {
1783 .b = {
1784 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
1785 .en_mask = BIT(4),
1786 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1787 .halt_bit = 7,
1788 },
1789 .c = {
1790 .dbg_name = "gsbi9_p_clk",
1791 .ops = &clk_ops_branch,
1792 CLK_INIT(gsbi9_p_clk.c),
1793 },
1794};
1795
1796static struct branch_clk gsbi10_p_clk = {
1797 .b = {
1798 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
1799 .en_mask = BIT(4),
1800 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1801 .halt_bit = 3,
1802 },
1803 .c = {
1804 .dbg_name = "gsbi10_p_clk",
1805 .ops = &clk_ops_branch,
1806 CLK_INIT(gsbi10_p_clk.c),
1807 },
1808};
1809
1810static struct branch_clk gsbi11_p_clk = {
1811 .b = {
1812 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
1813 .en_mask = BIT(4),
1814 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1815 .halt_bit = 18,
1816 },
1817 .c = {
1818 .dbg_name = "gsbi11_p_clk",
1819 .ops = &clk_ops_branch,
1820 CLK_INIT(gsbi11_p_clk.c),
1821 },
1822};
1823
1824static struct branch_clk gsbi12_p_clk = {
1825 .b = {
1826 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
1827 .en_mask = BIT(4),
1828 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1829 .halt_bit = 14,
1830 },
1831 .c = {
1832 .dbg_name = "gsbi12_p_clk",
1833 .ops = &clk_ops_branch,
1834 CLK_INIT(gsbi12_p_clk.c),
1835 },
1836};
1837
1838static struct branch_clk tsif_p_clk = {
1839 .b = {
1840 .ctl_reg = TSIF_HCLK_CTL_REG,
1841 .en_mask = BIT(4),
1842 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1843 .halt_bit = 7,
1844 },
1845 .c = {
1846 .dbg_name = "tsif_p_clk",
1847 .ops = &clk_ops_branch,
1848 CLK_INIT(tsif_p_clk.c),
1849 },
1850};
1851
1852static struct branch_clk usb_fs1_p_clk = {
1853 .b = {
1854 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
1855 .en_mask = BIT(4),
1856 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1857 .halt_bit = 17,
1858 },
1859 .c = {
1860 .dbg_name = "usb_fs1_p_clk",
1861 .ops = &clk_ops_branch,
1862 CLK_INIT(usb_fs1_p_clk.c),
1863 },
1864};
1865
1866static struct branch_clk usb_fs2_p_clk = {
1867 .b = {
1868 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
1869 .en_mask = BIT(4),
1870 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1871 .halt_bit = 14,
1872 },
1873 .c = {
1874 .dbg_name = "usb_fs2_p_clk",
1875 .ops = &clk_ops_branch,
1876 CLK_INIT(usb_fs2_p_clk.c),
1877 },
1878};
1879
1880static struct branch_clk usb_hs1_p_clk = {
1881 .b = {
1882 .ctl_reg = USB_HS1_HCLK_CTL_REG,
1883 .en_mask = BIT(4),
1884 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1885 .halt_bit = 1,
1886 },
1887 .c = {
1888 .dbg_name = "usb_hs1_p_clk",
1889 .ops = &clk_ops_branch,
1890 CLK_INIT(usb_hs1_p_clk.c),
1891 },
1892};
1893
Stephen Boyd94625ef2011-07-12 17:06:01 -07001894static struct branch_clk usb_hsic_p_clk = {
1895 .b = {
1896 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
1897 .en_mask = BIT(4),
1898 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1899 .halt_bit = 28,
1900 },
1901 .c = {
1902 .dbg_name = "usb_hsic_p_clk",
1903 .ops = &clk_ops_branch,
1904 CLK_INIT(usb_hsic_p_clk.c),
1905 },
1906};
1907
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001908static struct branch_clk sdc1_p_clk = {
1909 .b = {
1910 .ctl_reg = SDCn_HCLK_CTL_REG(1),
1911 .en_mask = BIT(4),
1912 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1913 .halt_bit = 11,
1914 },
1915 .c = {
1916 .dbg_name = "sdc1_p_clk",
1917 .ops = &clk_ops_branch,
1918 CLK_INIT(sdc1_p_clk.c),
1919 },
1920};
1921
1922static struct branch_clk sdc2_p_clk = {
1923 .b = {
1924 .ctl_reg = SDCn_HCLK_CTL_REG(2),
1925 .en_mask = BIT(4),
1926 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1927 .halt_bit = 10,
1928 },
1929 .c = {
1930 .dbg_name = "sdc2_p_clk",
1931 .ops = &clk_ops_branch,
1932 CLK_INIT(sdc2_p_clk.c),
1933 },
1934};
1935
1936static struct branch_clk sdc3_p_clk = {
1937 .b = {
1938 .ctl_reg = SDCn_HCLK_CTL_REG(3),
1939 .en_mask = BIT(4),
1940 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1941 .halt_bit = 9,
1942 },
1943 .c = {
1944 .dbg_name = "sdc3_p_clk",
1945 .ops = &clk_ops_branch,
1946 CLK_INIT(sdc3_p_clk.c),
1947 },
1948};
1949
1950static struct branch_clk sdc4_p_clk = {
1951 .b = {
1952 .ctl_reg = SDCn_HCLK_CTL_REG(4),
1953 .en_mask = BIT(4),
1954 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1955 .halt_bit = 8,
1956 },
1957 .c = {
1958 .dbg_name = "sdc4_p_clk",
1959 .ops = &clk_ops_branch,
1960 CLK_INIT(sdc4_p_clk.c),
1961 },
1962};
1963
1964static struct branch_clk sdc5_p_clk = {
1965 .b = {
1966 .ctl_reg = SDCn_HCLK_CTL_REG(5),
1967 .en_mask = BIT(4),
1968 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1969 .halt_bit = 7,
1970 },
1971 .c = {
1972 .dbg_name = "sdc5_p_clk",
1973 .ops = &clk_ops_branch,
1974 CLK_INIT(sdc5_p_clk.c),
1975 },
1976};
1977
1978/* HW-Voteable Clocks */
1979static struct branch_clk adm0_clk = {
1980 .b = {
1981 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1982 .en_mask = BIT(2),
1983 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1984 .halt_check = HALT_VOTED,
1985 .halt_bit = 14,
1986 },
1987 .c = {
1988 .dbg_name = "adm0_clk",
1989 .ops = &clk_ops_branch,
1990 CLK_INIT(adm0_clk.c),
1991 },
1992};
1993
1994static struct branch_clk adm0_p_clk = {
1995 .b = {
1996 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1997 .en_mask = BIT(3),
1998 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1999 .halt_check = HALT_VOTED,
2000 .halt_bit = 13,
2001 },
2002 .c = {
2003 .dbg_name = "adm0_p_clk",
2004 .ops = &clk_ops_branch,
2005 CLK_INIT(adm0_p_clk.c),
2006 },
2007};
2008
2009static struct branch_clk pmic_arb0_p_clk = {
2010 .b = {
2011 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2012 .en_mask = BIT(8),
2013 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2014 .halt_check = HALT_VOTED,
2015 .halt_bit = 22,
2016 },
2017 .c = {
2018 .dbg_name = "pmic_arb0_p_clk",
2019 .ops = &clk_ops_branch,
2020 CLK_INIT(pmic_arb0_p_clk.c),
2021 },
2022};
2023
2024static struct branch_clk pmic_arb1_p_clk = {
2025 .b = {
2026 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2027 .en_mask = BIT(9),
2028 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2029 .halt_check = HALT_VOTED,
2030 .halt_bit = 21,
2031 },
2032 .c = {
2033 .dbg_name = "pmic_arb1_p_clk",
2034 .ops = &clk_ops_branch,
2035 CLK_INIT(pmic_arb1_p_clk.c),
2036 },
2037};
2038
2039static struct branch_clk pmic_ssbi2_clk = {
2040 .b = {
2041 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2042 .en_mask = BIT(7),
2043 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2044 .halt_check = HALT_VOTED,
2045 .halt_bit = 23,
2046 },
2047 .c = {
2048 .dbg_name = "pmic_ssbi2_clk",
2049 .ops = &clk_ops_branch,
2050 CLK_INIT(pmic_ssbi2_clk.c),
2051 },
2052};
2053
2054static struct branch_clk rpm_msg_ram_p_clk = {
2055 .b = {
2056 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2057 .en_mask = BIT(6),
2058 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2059 .halt_check = HALT_VOTED,
2060 .halt_bit = 12,
2061 },
2062 .c = {
2063 .dbg_name = "rpm_msg_ram_p_clk",
2064 .ops = &clk_ops_branch,
2065 CLK_INIT(rpm_msg_ram_p_clk.c),
2066 },
2067};
2068
2069/*
2070 * Multimedia Clocks
2071 */
2072
2073static struct branch_clk amp_clk = {
2074 .b = {
2075 .reset_reg = SW_RESET_CORE_REG,
2076 .reset_mask = BIT(20),
2077 },
2078 .c = {
2079 .dbg_name = "amp_clk",
2080 .ops = &clk_ops_reset,
2081 CLK_INIT(amp_clk.c),
2082 },
2083};
2084
Stephen Boyd94625ef2011-07-12 17:06:01 -07002085#define CLK_CAM(name, n, hb) \
2086 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002087 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002088 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002089 .en_mask = BIT(0), \
2090 .halt_reg = DBG_BUS_VEC_I_REG, \
2091 .halt_bit = hb, \
2092 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002093 .ns_reg = CAMCLK##n##_NS_REG, \
2094 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002095 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002096 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002097 .ctl_mask = BM(7, 6), \
2098 .set_rate = set_rate_mnd_8, \
2099 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002100 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002101 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002102 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002103 .ops = &clk_ops_rcg_8960, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002104 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002105 }, \
2106 }
2107#define F_CAM(f, s, d, m, n, v) \
2108 { \
2109 .freq_hz = f, \
2110 .src_clk = &s##_clk.c, \
2111 .md_val = MD8(8, m, 0, n), \
2112 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2113 .ctl_val = CC(6, n), \
2114 .mnd_en_mask = BIT(5) * !!(n), \
2115 .sys_vdd = v, \
2116 }
2117static struct clk_freq_tbl clk_tbl_cam[] = {
2118 F_CAM( 0, gnd, 1, 0, 0, NONE),
2119 F_CAM( 6000000, pll8, 4, 1, 16, LOW),
2120 F_CAM( 8000000, pll8, 4, 1, 12, LOW),
2121 F_CAM( 12000000, pll8, 4, 1, 8, LOW),
2122 F_CAM( 16000000, pll8, 4, 1, 6, LOW),
2123 F_CAM( 19200000, pll8, 4, 1, 5, LOW),
2124 F_CAM( 24000000, pll8, 4, 1, 4, LOW),
2125 F_CAM( 32000000, pll8, 4, 1, 3, LOW),
2126 F_CAM( 48000000, pll8, 4, 1, 2, LOW),
2127 F_CAM( 64000000, pll8, 3, 1, 2, LOW),
2128 F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
2129 F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
2130 F_END
2131};
2132
Stephen Boyd94625ef2011-07-12 17:06:01 -07002133static CLK_CAM(cam0_clk, 0, 15);
2134static CLK_CAM(cam1_clk, 1, 16);
2135static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002136
2137#define F_CSI(f, s, d, m, n, v) \
2138 { \
2139 .freq_hz = f, \
2140 .src_clk = &s##_clk.c, \
2141 .md_val = MD8(8, m, 0, n), \
2142 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2143 .ctl_val = CC(6, n), \
2144 .mnd_en_mask = BIT(5) * !!(n), \
2145 .sys_vdd = v, \
2146 }
2147static struct clk_freq_tbl clk_tbl_csi[] = {
2148 F_CSI( 0, gnd, 1, 0, 0, NONE),
2149 F_CSI( 85330000, pll8, 1, 2, 9, LOW),
2150 F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
2151 F_END
2152};
2153
2154static struct rcg_clk csi0_src_clk = {
2155 .ns_reg = CSI0_NS_REG,
2156 .b = {
2157 .ctl_reg = CSI0_CC_REG,
2158 .halt_check = NOCHECK,
2159 },
2160 .md_reg = CSI0_MD_REG,
2161 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002162 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002163 .ctl_mask = BM(7, 6),
2164 .set_rate = set_rate_mnd,
2165 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002166 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002167 .c = {
2168 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002169 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002170 CLK_INIT(csi0_src_clk.c),
2171 },
2172};
2173
2174static struct branch_clk csi0_clk = {
2175 .b = {
2176 .ctl_reg = CSI0_CC_REG,
2177 .en_mask = BIT(0),
2178 .reset_reg = SW_RESET_CORE_REG,
2179 .reset_mask = BIT(8),
2180 .halt_reg = DBG_BUS_VEC_B_REG,
2181 .halt_bit = 13,
2182 },
2183 .parent = &csi0_src_clk.c,
2184 .c = {
2185 .dbg_name = "csi0_clk",
2186 .ops = &clk_ops_branch,
2187 CLK_INIT(csi0_clk.c),
2188 },
2189};
2190
2191static struct branch_clk csi0_phy_clk = {
2192 .b = {
2193 .ctl_reg = CSI0_CC_REG,
2194 .en_mask = BIT(8),
2195 .reset_reg = SW_RESET_CORE_REG,
2196 .reset_mask = BIT(29),
2197 .halt_reg = DBG_BUS_VEC_I_REG,
2198 .halt_bit = 9,
2199 },
2200 .parent = &csi0_src_clk.c,
2201 .c = {
2202 .dbg_name = "csi0_phy_clk",
2203 .ops = &clk_ops_branch,
2204 CLK_INIT(csi0_phy_clk.c),
2205 },
2206};
2207
2208static struct rcg_clk csi1_src_clk = {
2209 .ns_reg = CSI1_NS_REG,
2210 .b = {
2211 .ctl_reg = CSI1_CC_REG,
2212 .halt_check = NOCHECK,
2213 },
2214 .md_reg = CSI1_MD_REG,
2215 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002216 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002217 .ctl_mask = BM(7, 6),
2218 .set_rate = set_rate_mnd,
2219 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002220 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002221 .c = {
2222 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002223 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002224 CLK_INIT(csi1_src_clk.c),
2225 },
2226};
2227
2228static struct branch_clk csi1_clk = {
2229 .b = {
2230 .ctl_reg = CSI1_CC_REG,
2231 .en_mask = BIT(0),
2232 .reset_reg = SW_RESET_CORE_REG,
2233 .reset_mask = BIT(18),
2234 .halt_reg = DBG_BUS_VEC_B_REG,
2235 .halt_bit = 14,
2236 },
2237 .parent = &csi1_src_clk.c,
2238 .c = {
2239 .dbg_name = "csi1_clk",
2240 .ops = &clk_ops_branch,
2241 CLK_INIT(csi1_clk.c),
2242 },
2243};
2244
2245static struct branch_clk csi1_phy_clk = {
2246 .b = {
2247 .ctl_reg = CSI1_CC_REG,
2248 .en_mask = BIT(8),
2249 .reset_reg = SW_RESET_CORE_REG,
2250 .reset_mask = BIT(28),
2251 .halt_reg = DBG_BUS_VEC_I_REG,
2252 .halt_bit = 10,
2253 },
2254 .parent = &csi1_src_clk.c,
2255 .c = {
2256 .dbg_name = "csi1_phy_clk",
2257 .ops = &clk_ops_branch,
2258 CLK_INIT(csi1_phy_clk.c),
2259 },
2260};
2261
Stephen Boyd94625ef2011-07-12 17:06:01 -07002262static struct rcg_clk csi2_src_clk = {
2263 .ns_reg = CSI2_NS_REG,
2264 .b = {
2265 .ctl_reg = CSI2_CC_REG,
2266 .halt_check = NOCHECK,
2267 },
2268 .md_reg = CSI2_MD_REG,
2269 .root_en_mask = BIT(2),
2270 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2271 .ctl_mask = BM(7, 6),
2272 .set_rate = set_rate_mnd,
2273 .freq_tbl = clk_tbl_csi,
2274 .current_freq = &rcg_dummy_freq,
2275 .c = {
2276 .dbg_name = "csi2_src_clk",
2277 .ops = &clk_ops_rcg_8960,
2278 CLK_INIT(csi2_src_clk.c),
2279 },
2280};
2281
2282static struct branch_clk csi2_clk = {
2283 .b = {
2284 .ctl_reg = CSI2_CC_REG,
2285 .en_mask = BIT(0),
2286 .reset_reg = SW_RESET_CORE2_REG,
2287 .reset_mask = BIT(2),
2288 .halt_reg = DBG_BUS_VEC_B_REG,
2289 .halt_bit = 29,
2290 },
2291 .parent = &csi2_src_clk.c,
2292 .c = {
2293 .dbg_name = "csi2_clk",
2294 .ops = &clk_ops_branch,
2295 CLK_INIT(csi2_clk.c),
2296 },
2297};
2298
2299static struct branch_clk csi2_phy_clk = {
2300 .b = {
2301 .ctl_reg = CSI2_CC_REG,
2302 .en_mask = BIT(8),
2303 .reset_reg = SW_RESET_CORE_REG,
2304 .reset_mask = BIT(31),
2305 .halt_reg = DBG_BUS_VEC_I_REG,
2306 .halt_bit = 29,
2307 },
2308 .parent = &csi2_src_clk.c,
2309 .c = {
2310 .dbg_name = "csi2_phy_clk",
2311 .ops = &clk_ops_branch,
2312 CLK_INIT(csi2_phy_clk.c),
2313 },
2314};
2315
2316/*
2317 * The csi pix and csi rdi clocks have two bits in two registers to control a
2318 * three input mux. So we have the generic rcg_clk_enable() path handle the
2319 * first bit, and this function handle the second bit.
2320 */
2321static void set_rate_pix_rdi(struct rcg_clk *clk, struct clk_freq_tbl *nf)
2322{
2323 u32 reg = readl_relaxed(MISC_CC3_REG);
2324 u32 bit = (u32)nf->extra_freq_data;
2325 if (nf->freq_hz == 2)
2326 reg |= bit;
2327 else
2328 reg &= ~bit;
2329 writel_relaxed(reg, MISC_CC3_REG);
2330}
2331
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002332#define F_CSI_PIX(s) \
2333 { \
2334 .src_clk = &csi##s##_clk.c, \
2335 .freq_hz = s, \
2336 .ns_val = BVAL(25, 25, s), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002337 .extra_freq_data = (void *)BIT(13), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002338 }
2339static struct clk_freq_tbl clk_tbl_csi_pix[] = {
2340 F_CSI_PIX(0), /* CSI0 source */
2341 F_CSI_PIX(1), /* CSI1 source */
Stephen Boyd94625ef2011-07-12 17:06:01 -07002342 F_CSI_PIX(2), /* CSI2 source */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002343 F_END
2344};
2345
2346static struct rcg_clk csi_pix_clk = {
2347 .b = {
2348 .ctl_reg = MISC_CC_REG,
2349 .en_mask = BIT(26),
2350 .halt_check = DELAY,
2351 .reset_reg = SW_RESET_CORE_REG,
2352 .reset_mask = BIT(26),
2353 },
2354 .ns_reg = MISC_CC_REG,
2355 .ns_mask = BIT(25),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002356 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002357 .freq_tbl = clk_tbl_csi_pix,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002358 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002359 .c = {
2360 .dbg_name = "csi_pix_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002361 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002362 CLK_INIT(csi_pix_clk.c),
2363 },
2364};
2365
Stephen Boyd94625ef2011-07-12 17:06:01 -07002366#define F_CSI_PIX1(s) \
2367 { \
2368 .src_clk = &csi##s##_clk.c, \
2369 .freq_hz = s, \
2370 .ns_val = BVAL(9, 8, s), \
2371 }
2372static struct clk_freq_tbl clk_tbl_csi_pix1[] = {
2373 F_CSI_PIX1(0), /* CSI0 source */
2374 F_CSI_PIX1(1), /* CSI1 source */
2375 F_CSI_PIX1(2), /* CSI2 source */
2376 F_END
2377};
2378
2379static struct rcg_clk csi_pix1_clk = {
2380 .b = {
2381 .ctl_reg = MISC_CC3_REG,
2382 .en_mask = BIT(10),
2383 .halt_check = DELAY,
2384 .reset_reg = SW_RESET_CORE_REG,
2385 .reset_mask = BIT(30),
2386 },
2387 .ns_reg = MISC_CC3_REG,
2388 .ns_mask = BM(9, 8),
2389 .set_rate = set_rate_nop,
2390 .freq_tbl = clk_tbl_csi_pix1,
2391 .current_freq = &rcg_dummy_freq,
2392 .c = {
2393 .dbg_name = "csi_pix1_clk",
2394 .ops = &clk_ops_rcg_8960,
2395 CLK_INIT(csi_pix1_clk.c),
2396 },
2397};
2398
2399#define F_CSI_RDI(s) \
2400 { \
2401 .src_clk = &csi##s##_clk.c, \
2402 .freq_hz = s, \
2403 .ns_val = BVAL(12, 12, s), \
2404 .extra_freq_data = (void *)BIT(12), \
2405 }
2406static struct clk_freq_tbl clk_tbl_csi_rdi[] = {
2407 F_CSI_RDI(0), /* CSI0 source */
2408 F_CSI_RDI(1), /* CSI1 source */
2409 F_CSI_RDI(2), /* CSI2 source */
2410 F_END
2411};
2412
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002413static struct rcg_clk csi_rdi_clk = {
2414 .b = {
2415 .ctl_reg = MISC_CC_REG,
2416 .en_mask = BIT(13),
2417 .halt_check = DELAY,
2418 .reset_reg = SW_RESET_CORE_REG,
2419 .reset_mask = BIT(27),
2420 },
2421 .ns_reg = MISC_CC_REG,
2422 .ns_mask = BIT(12),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002423 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002424 .freq_tbl = clk_tbl_csi_rdi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002425 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002426 .c = {
2427 .dbg_name = "csi_rdi_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002428 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002429 CLK_INIT(csi_rdi_clk.c),
2430 },
2431};
2432
Stephen Boyd94625ef2011-07-12 17:06:01 -07002433#define F_CSI_RDI1(s) \
2434 { \
2435 .src_clk = &csi##s##_clk.c, \
2436 .freq_hz = s, \
2437 .ns_val = BVAL(1, 0, s), \
2438 }
2439static struct clk_freq_tbl clk_tbl_csi_rdi1[] = {
2440 F_CSI_RDI1(0), /* CSI0 source */
2441 F_CSI_RDI1(1), /* CSI1 source */
2442 F_CSI_RDI1(2), /* CSI2 source */
2443 F_END
2444};
2445
2446static struct rcg_clk csi_rdi1_clk = {
2447 .b = {
2448 .ctl_reg = MISC_CC3_REG,
2449 .en_mask = BIT(2),
2450 .halt_check = DELAY,
2451 .reset_reg = SW_RESET_CORE2_REG,
2452 .reset_mask = BIT(1),
2453 },
2454 .ns_reg = MISC_CC3_REG,
2455 .ns_mask = BM(1, 0),
2456 .set_rate = set_rate_nop,
2457 .freq_tbl = clk_tbl_csi_rdi1,
2458 .current_freq = &rcg_dummy_freq,
2459 .c = {
2460 .dbg_name = "csi_rdi1_clk",
2461 .ops = &clk_ops_rcg_8960,
2462 CLK_INIT(csi_rdi1_clk.c),
2463 },
2464};
2465
2466#define F_CSI_RDI2(s) \
2467 { \
2468 .src_clk = &csi##s##_clk.c, \
2469 .freq_hz = s, \
2470 .ns_val = BVAL(5, 4, s), \
2471 }
2472static struct clk_freq_tbl clk_tbl_csi_rdi2[] = {
2473 F_CSI_RDI2(0), /* CSI0 source */
2474 F_CSI_RDI2(1), /* CSI1 source */
2475 F_CSI_RDI2(2), /* CSI2 source */
2476 F_END
2477};
2478
2479static struct rcg_clk csi_rdi2_clk = {
2480 .b = {
2481 .ctl_reg = MISC_CC3_REG,
2482 .en_mask = BIT(6),
2483 .halt_check = DELAY,
2484 .reset_reg = SW_RESET_CORE2_REG,
2485 .reset_mask = BIT(0),
2486 },
2487 .ns_reg = MISC_CC3_REG,
2488 .ns_mask = BM(5, 4),
2489 .set_rate = set_rate_nop,
2490 .freq_tbl = clk_tbl_csi_rdi2,
2491 .current_freq = &rcg_dummy_freq,
2492 .c = {
2493 .dbg_name = "csi_rdi2_clk",
2494 .ops = &clk_ops_rcg_8960,
2495 CLK_INIT(csi_rdi2_clk.c),
2496 },
2497};
2498
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002499#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
2500 { \
2501 .freq_hz = f, \
2502 .src_clk = &s##_clk.c, \
2503 .md_val = MD8(8, m, 0, n), \
2504 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2505 .ctl_val = CC(6, n), \
2506 .mnd_en_mask = BIT(5) * !!(n), \
2507 .sys_vdd = v, \
2508 }
2509static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
2510 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
2511 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
2512 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
2513 F_END
2514};
2515
2516static struct rcg_clk csiphy_timer_src_clk = {
2517 .ns_reg = CSIPHYTIMER_NS_REG,
2518 .b = {
2519 .ctl_reg = CSIPHYTIMER_CC_REG,
2520 .halt_check = NOCHECK,
2521 },
2522 .md_reg = CSIPHYTIMER_MD_REG,
2523 .root_en_mask = BIT(2),
2524 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
2525 .ctl_mask = BM(7, 6),
2526 .set_rate = set_rate_mnd_8,
2527 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002528 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002529 .c = {
2530 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002531 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002532 CLK_INIT(csiphy_timer_src_clk.c),
2533 },
2534};
2535
2536static struct branch_clk csi0phy_timer_clk = {
2537 .b = {
2538 .ctl_reg = CSIPHYTIMER_CC_REG,
2539 .en_mask = BIT(0),
2540 .halt_reg = DBG_BUS_VEC_I_REG,
2541 .halt_bit = 17,
2542 },
2543 .parent = &csiphy_timer_src_clk.c,
2544 .c = {
2545 .dbg_name = "csi0phy_timer_clk",
2546 .ops = &clk_ops_branch,
2547 CLK_INIT(csi0phy_timer_clk.c),
2548 },
2549};
2550
2551static struct branch_clk csi1phy_timer_clk = {
2552 .b = {
2553 .ctl_reg = CSIPHYTIMER_CC_REG,
2554 .en_mask = BIT(9),
2555 .halt_reg = DBG_BUS_VEC_I_REG,
2556 .halt_bit = 18,
2557 },
2558 .parent = &csiphy_timer_src_clk.c,
2559 .c = {
2560 .dbg_name = "csi1phy_timer_clk",
2561 .ops = &clk_ops_branch,
2562 CLK_INIT(csi1phy_timer_clk.c),
2563 },
2564};
2565
Stephen Boyd94625ef2011-07-12 17:06:01 -07002566static struct branch_clk csi2phy_timer_clk = {
2567 .b = {
2568 .ctl_reg = CSIPHYTIMER_CC_REG,
2569 .en_mask = BIT(11),
2570 .halt_reg = DBG_BUS_VEC_I_REG,
2571 .halt_bit = 30,
2572 },
2573 .parent = &csiphy_timer_src_clk.c,
2574 .c = {
2575 .dbg_name = "csi2phy_timer_clk",
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(csi2phy_timer_clk.c),
2578 },
2579};
2580
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002581#define F_DSI(d) \
2582 { \
2583 .freq_hz = d, \
2584 .ns_val = BVAL(15, 12, (d-1)), \
2585 }
2586/*
2587 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
2588 * without this clock driver knowing. So, overload the clk_set_rate() to set
2589 * the divider (1 to 16) of the clock with respect to the PLL rate.
2590 */
2591static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
2592 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
2593 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
2594 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
2595 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
2596 F_END
2597};
2598
2599static struct rcg_clk dsi1_byte_clk = {
2600 .b = {
2601 .ctl_reg = DSI1_BYTE_CC_REG,
2602 .en_mask = BIT(0),
2603 .reset_reg = SW_RESET_CORE_REG,
2604 .reset_mask = BIT(7),
2605 .halt_reg = DBG_BUS_VEC_B_REG,
2606 .halt_bit = 21,
2607 },
2608 .ns_reg = DSI1_BYTE_NS_REG,
2609 .root_en_mask = BIT(2),
2610 .ns_mask = BM(15, 12),
2611 .set_rate = set_rate_nop,
2612 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002613 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002614 .c = {
2615 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002616 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002617 CLK_INIT(dsi1_byte_clk.c),
2618 },
2619};
2620
2621static struct rcg_clk dsi2_byte_clk = {
2622 .b = {
2623 .ctl_reg = DSI2_BYTE_CC_REG,
2624 .en_mask = BIT(0),
2625 .reset_reg = SW_RESET_CORE_REG,
2626 .reset_mask = BIT(25),
2627 .halt_reg = DBG_BUS_VEC_B_REG,
2628 .halt_bit = 20,
2629 },
2630 .ns_reg = DSI2_BYTE_NS_REG,
2631 .root_en_mask = BIT(2),
2632 .ns_mask = BM(15, 12),
2633 .set_rate = set_rate_nop,
2634 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002635 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002636 .c = {
2637 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002638 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002639 CLK_INIT(dsi2_byte_clk.c),
2640 },
2641};
2642
2643static struct rcg_clk dsi1_esc_clk = {
2644 .b = {
2645 .ctl_reg = DSI1_ESC_CC_REG,
2646 .en_mask = BIT(0),
2647 .reset_reg = SW_RESET_CORE_REG,
2648 .halt_reg = DBG_BUS_VEC_I_REG,
2649 .halt_bit = 1,
2650 },
2651 .ns_reg = DSI1_ESC_NS_REG,
2652 .root_en_mask = BIT(2),
2653 .ns_mask = BM(15, 12),
2654 .set_rate = set_rate_nop,
2655 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002656 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002657 .c = {
2658 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002659 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002660 CLK_INIT(dsi1_esc_clk.c),
2661 },
2662};
2663
2664static struct rcg_clk dsi2_esc_clk = {
2665 .b = {
2666 .ctl_reg = DSI2_ESC_CC_REG,
2667 .en_mask = BIT(0),
2668 .halt_reg = DBG_BUS_VEC_I_REG,
2669 .halt_bit = 3,
2670 },
2671 .ns_reg = DSI2_ESC_NS_REG,
2672 .root_en_mask = BIT(2),
2673 .ns_mask = BM(15, 12),
2674 .set_rate = set_rate_nop,
2675 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002676 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002677 .c = {
2678 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002679 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002680 CLK_INIT(dsi2_esc_clk.c),
2681 },
2682};
2683
2684#define F_GFX2D(f, s, m, n, v) \
2685 { \
2686 .freq_hz = f, \
2687 .src_clk = &s##_clk.c, \
2688 .md_val = MD4(4, m, 0, n), \
2689 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
2690 .ctl_val = CC_BANKED(9, 6, n), \
2691 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
2692 .sys_vdd = v, \
2693 }
2694static struct clk_freq_tbl clk_tbl_gfx2d[] = {
2695 F_GFX2D( 0, gnd, 0, 0, NONE),
2696 F_GFX2D( 27000000, pxo, 0, 0, LOW),
2697 F_GFX2D( 48000000, pll8, 1, 8, LOW),
2698 F_GFX2D( 54857000, pll8, 1, 7, LOW),
2699 F_GFX2D( 64000000, pll8, 1, 6, LOW),
2700 F_GFX2D( 76800000, pll8, 1, 5, LOW),
2701 F_GFX2D( 96000000, pll8, 1, 4, LOW),
2702 F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
2703 F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
2704 F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
2705 F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
2706 F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
2707 F_GFX2D(228571000, pll2, 2, 7, HIGH),
2708 F_END
2709};
2710
2711static struct bank_masks bmnd_info_gfx2d0 = {
2712 .bank_sel_mask = BIT(11),
2713 .bank0_mask = {
2714 .md_reg = GFX2D0_MD0_REG,
2715 .ns_mask = BM(23, 20) | BM(5, 3),
2716 .rst_mask = BIT(25),
2717 .mnd_en_mask = BIT(8),
2718 .mode_mask = BM(10, 9),
2719 },
2720 .bank1_mask = {
2721 .md_reg = GFX2D0_MD1_REG,
2722 .ns_mask = BM(19, 16) | BM(2, 0),
2723 .rst_mask = BIT(24),
2724 .mnd_en_mask = BIT(5),
2725 .mode_mask = BM(7, 6),
2726 },
2727};
2728
2729static struct rcg_clk gfx2d0_clk = {
2730 .b = {
2731 .ctl_reg = GFX2D0_CC_REG,
2732 .en_mask = BIT(0),
2733 .reset_reg = SW_RESET_CORE_REG,
2734 .reset_mask = BIT(14),
2735 .halt_reg = DBG_BUS_VEC_A_REG,
2736 .halt_bit = 9,
2737 },
2738 .ns_reg = GFX2D0_NS_REG,
2739 .root_en_mask = BIT(2),
2740 .set_rate = set_rate_mnd_banked,
2741 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07002742 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002743 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002744 .c = {
2745 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002746 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002747 CLK_INIT(gfx2d0_clk.c),
2748 },
2749};
2750
2751static struct bank_masks bmnd_info_gfx2d1 = {
2752 .bank_sel_mask = BIT(11),
2753 .bank0_mask = {
2754 .md_reg = GFX2D1_MD0_REG,
2755 .ns_mask = BM(23, 20) | BM(5, 3),
2756 .rst_mask = BIT(25),
2757 .mnd_en_mask = BIT(8),
2758 .mode_mask = BM(10, 9),
2759 },
2760 .bank1_mask = {
2761 .md_reg = GFX2D1_MD1_REG,
2762 .ns_mask = BM(19, 16) | BM(2, 0),
2763 .rst_mask = BIT(24),
2764 .mnd_en_mask = BIT(5),
2765 .mode_mask = BM(7, 6),
2766 },
2767};
2768
2769static struct rcg_clk gfx2d1_clk = {
2770 .b = {
2771 .ctl_reg = GFX2D1_CC_REG,
2772 .en_mask = BIT(0),
2773 .reset_reg = SW_RESET_CORE_REG,
2774 .reset_mask = BIT(13),
2775 .halt_reg = DBG_BUS_VEC_A_REG,
2776 .halt_bit = 14,
2777 },
2778 .ns_reg = GFX2D1_NS_REG,
2779 .root_en_mask = BIT(2),
2780 .set_rate = set_rate_mnd_banked,
2781 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07002782 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002783 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002784 .c = {
2785 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002786 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002787 CLK_INIT(gfx2d1_clk.c),
2788 },
2789};
2790
2791#define F_GFX3D(f, s, m, n, v) \
2792 { \
2793 .freq_hz = f, \
2794 .src_clk = &s##_clk.c, \
2795 .md_val = MD4(4, m, 0, n), \
2796 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
2797 .ctl_val = CC_BANKED(9, 6, n), \
2798 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
2799 .sys_vdd = v, \
2800 }
2801static struct clk_freq_tbl clk_tbl_gfx3d[] = {
2802 F_GFX3D( 0, gnd, 0, 0, NONE),
2803 F_GFX3D( 27000000, pxo, 0, 0, LOW),
2804 F_GFX3D( 48000000, pll8, 1, 8, LOW),
2805 F_GFX3D( 54857000, pll8, 1, 7, LOW),
2806 F_GFX3D( 64000000, pll8, 1, 6, LOW),
2807 F_GFX3D( 76800000, pll8, 1, 5, LOW),
2808 F_GFX3D( 96000000, pll8, 1, 4, LOW),
Stephen Boydd7797422011-08-10 16:01:45 -07002809 F_GFX3D(128000000, pll8, 1, 3, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002810 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
2811 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
2812 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
2813 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
2814 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
2815 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
2816 F_GFX3D(320000000, pll2, 2, 5, HIGH),
2817 F_END
2818};
2819
Stephen Boyd94625ef2011-07-12 17:06:01 -07002820static struct clk_freq_tbl clk_tbl_gfx3d_v2[] = {
2821 F_GFX3D( 0, gnd, 0, 0, NONE),
2822 F_GFX3D( 27000000, pxo, 0, 0, LOW),
2823 F_GFX3D( 48000000, pll8, 1, 8, LOW),
2824 F_GFX3D( 54857000, pll8, 1, 7, LOW),
2825 F_GFX3D( 64000000, pll8, 1, 6, LOW),
2826 F_GFX3D( 76800000, pll8, 1, 5, LOW),
2827 F_GFX3D( 96000000, pll8, 1, 4, LOW),
2828 F_GFX3D(128000000, pll8, 1, 3, LOW),
2829 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
2830 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
2831 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
2832 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
2833 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
2834 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
2835 F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
2836 F_GFX3D(320000000, pll2, 2, 5, HIGH),
2837 F_GFX3D(400000000, pll2, 1, 2, HIGH),
2838 F_END
2839};
2840
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002841static struct bank_masks bmnd_info_gfx3d = {
2842 .bank_sel_mask = BIT(11),
2843 .bank0_mask = {
2844 .md_reg = GFX3D_MD0_REG,
2845 .ns_mask = BM(21, 18) | BM(5, 3),
2846 .rst_mask = BIT(23),
2847 .mnd_en_mask = BIT(8),
2848 .mode_mask = BM(10, 9),
2849 },
2850 .bank1_mask = {
2851 .md_reg = GFX3D_MD1_REG,
2852 .ns_mask = BM(17, 14) | BM(2, 0),
2853 .rst_mask = BIT(22),
2854 .mnd_en_mask = BIT(5),
2855 .mode_mask = BM(7, 6),
2856 },
2857};
2858
2859static struct rcg_clk gfx3d_clk = {
2860 .b = {
2861 .ctl_reg = GFX3D_CC_REG,
2862 .en_mask = BIT(0),
2863 .reset_reg = SW_RESET_CORE_REG,
2864 .reset_mask = BIT(12),
2865 .halt_reg = DBG_BUS_VEC_A_REG,
2866 .halt_bit = 4,
2867 },
2868 .ns_reg = GFX3D_NS_REG,
2869 .root_en_mask = BIT(2),
2870 .set_rate = set_rate_mnd_banked,
2871 .freq_tbl = clk_tbl_gfx3d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07002872 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002873 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002874 .c = {
2875 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002876 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002877 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002878 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002879 },
2880};
2881
2882#define F_IJPEG(f, s, d, m, n, v) \
2883 { \
2884 .freq_hz = f, \
2885 .src_clk = &s##_clk.c, \
2886 .md_val = MD8(8, m, 0, n), \
2887 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
2888 .ctl_val = CC(6, n), \
2889 .mnd_en_mask = BIT(5) * !!(n), \
2890 .sys_vdd = v, \
2891 }
2892static struct clk_freq_tbl clk_tbl_ijpeg[] = {
2893 F_IJPEG( 0, gnd, 1, 0, 0, NONE),
2894 F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
2895 F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
2896 F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
2897 F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
2898 F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
2899 F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
2900 F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
2901 F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
2902 F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002903 F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002904 F_END
2905};
2906
2907static struct rcg_clk ijpeg_clk = {
2908 .b = {
2909 .ctl_reg = IJPEG_CC_REG,
2910 .en_mask = BIT(0),
2911 .reset_reg = SW_RESET_CORE_REG,
2912 .reset_mask = BIT(9),
2913 .halt_reg = DBG_BUS_VEC_A_REG,
2914 .halt_bit = 24,
2915 },
2916 .ns_reg = IJPEG_NS_REG,
2917 .md_reg = IJPEG_MD_REG,
2918 .root_en_mask = BIT(2),
2919 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
2920 .ctl_mask = BM(7, 6),
2921 .set_rate = set_rate_mnd,
2922 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002923 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002924 .c = {
2925 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002926 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002927 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002928 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002929 },
2930};
2931
2932#define F_JPEGD(f, s, d, v) \
2933 { \
2934 .freq_hz = f, \
2935 .src_clk = &s##_clk.c, \
2936 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
2937 .sys_vdd = v, \
2938 }
2939static struct clk_freq_tbl clk_tbl_jpegd[] = {
2940 F_JPEGD( 0, gnd, 1, NONE),
2941 F_JPEGD( 64000000, pll8, 6, LOW),
2942 F_JPEGD( 76800000, pll8, 5, LOW),
2943 F_JPEGD( 96000000, pll8, 4, LOW),
2944 F_JPEGD(160000000, pll2, 5, NOMINAL),
2945 F_JPEGD(200000000, pll2, 4, NOMINAL),
2946 F_END
2947};
2948
2949static struct rcg_clk jpegd_clk = {
2950 .b = {
2951 .ctl_reg = JPEGD_CC_REG,
2952 .en_mask = BIT(0),
2953 .reset_reg = SW_RESET_CORE_REG,
2954 .reset_mask = BIT(19),
2955 .halt_reg = DBG_BUS_VEC_A_REG,
2956 .halt_bit = 19,
2957 },
2958 .ns_reg = JPEGD_NS_REG,
2959 .root_en_mask = BIT(2),
2960 .ns_mask = (BM(15, 12) | BM(2, 0)),
2961 .set_rate = set_rate_nop,
2962 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002963 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002964 .c = {
2965 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002966 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002967 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07002968 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002969 },
2970};
2971
2972#define F_MDP(f, s, m, n, v) \
2973 { \
2974 .freq_hz = f, \
2975 .src_clk = &s##_clk.c, \
2976 .md_val = MD8(8, m, 0, n), \
2977 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
2978 .ctl_val = CC_BANKED(9, 6, n), \
2979 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
2980 .sys_vdd = v, \
2981 }
2982static struct clk_freq_tbl clk_tbl_mdp[] = {
2983 F_MDP( 0, gnd, 0, 0, NONE),
2984 F_MDP( 9600000, pll8, 1, 40, LOW),
2985 F_MDP( 13710000, pll8, 1, 28, LOW),
2986 F_MDP( 27000000, pxo, 0, 0, LOW),
2987 F_MDP( 29540000, pll8, 1, 13, LOW),
2988 F_MDP( 34910000, pll8, 1, 11, LOW),
2989 F_MDP( 38400000, pll8, 1, 10, LOW),
2990 F_MDP( 59080000, pll8, 2, 13, LOW),
2991 F_MDP( 76800000, pll8, 1, 5, LOW),
2992 F_MDP( 85330000, pll8, 2, 9, LOW),
2993 F_MDP( 96000000, pll8, 1, 4, NOMINAL),
2994 F_MDP(128000000, pll8, 1, 3, NOMINAL),
2995 F_MDP(160000000, pll2, 1, 5, NOMINAL),
2996 F_MDP(177780000, pll2, 2, 9, NOMINAL),
2997 F_MDP(200000000, pll2, 1, 4, NOMINAL),
2998 F_END
2999};
3000
3001static struct bank_masks bmnd_info_mdp = {
3002 .bank_sel_mask = BIT(11),
3003 .bank0_mask = {
3004 .md_reg = MDP_MD0_REG,
3005 .ns_mask = BM(29, 22) | BM(5, 3),
3006 .rst_mask = BIT(31),
3007 .mnd_en_mask = BIT(8),
3008 .mode_mask = BM(10, 9),
3009 },
3010 .bank1_mask = {
3011 .md_reg = MDP_MD1_REG,
3012 .ns_mask = BM(21, 14) | BM(2, 0),
3013 .rst_mask = BIT(30),
3014 .mnd_en_mask = BIT(5),
3015 .mode_mask = BM(7, 6),
3016 },
3017};
3018
3019static struct rcg_clk mdp_clk = {
3020 .b = {
3021 .ctl_reg = MDP_CC_REG,
3022 .en_mask = BIT(0),
3023 .reset_reg = SW_RESET_CORE_REG,
3024 .reset_mask = BIT(21),
3025 .halt_reg = DBG_BUS_VEC_C_REG,
3026 .halt_bit = 10,
3027 },
3028 .ns_reg = MDP_NS_REG,
3029 .root_en_mask = BIT(2),
3030 .set_rate = set_rate_mnd_banked,
3031 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003032 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003033 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003034 .c = {
3035 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003036 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003037 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003038 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003039 },
3040};
3041
3042static struct branch_clk lut_mdp_clk = {
3043 .b = {
3044 .ctl_reg = MDP_LUT_CC_REG,
3045 .en_mask = BIT(0),
3046 .halt_reg = DBG_BUS_VEC_I_REG,
3047 .halt_bit = 13,
3048 },
3049 .parent = &mdp_clk.c,
3050 .c = {
3051 .dbg_name = "lut_mdp_clk",
3052 .ops = &clk_ops_branch,
3053 CLK_INIT(lut_mdp_clk.c),
3054 },
3055};
3056
3057#define F_MDP_VSYNC(f, s, v) \
3058 { \
3059 .freq_hz = f, \
3060 .src_clk = &s##_clk.c, \
3061 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
3062 .sys_vdd = v, \
3063 }
3064static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
3065 F_MDP_VSYNC(27000000, pxo, LOW),
3066 F_END
3067};
3068
3069static struct rcg_clk mdp_vsync_clk = {
3070 .b = {
3071 .ctl_reg = MISC_CC_REG,
3072 .en_mask = BIT(6),
3073 .reset_reg = SW_RESET_CORE_REG,
3074 .reset_mask = BIT(3),
3075 .halt_reg = DBG_BUS_VEC_B_REG,
3076 .halt_bit = 22,
3077 },
3078 .ns_reg = MISC_CC2_REG,
3079 .ns_mask = BIT(13),
3080 .set_rate = set_rate_nop,
3081 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003082 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003083 .c = {
3084 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003085 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003086 CLK_INIT(mdp_vsync_clk.c),
3087 },
3088};
3089
3090#define F_ROT(f, s, d, v) \
3091 { \
3092 .freq_hz = f, \
3093 .src_clk = &s##_clk.c, \
3094 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3095 21, 19, 18, 16, s##_to_mm_mux), \
3096 .sys_vdd = v, \
3097 }
3098static struct clk_freq_tbl clk_tbl_rot[] = {
3099 F_ROT( 0, gnd, 1, NONE),
3100 F_ROT( 27000000, pxo, 1, LOW),
3101 F_ROT( 29540000, pll8, 13, LOW),
3102 F_ROT( 32000000, pll8, 12, LOW),
3103 F_ROT( 38400000, pll8, 10, LOW),
3104 F_ROT( 48000000, pll8, 8, LOW),
3105 F_ROT( 54860000, pll8, 7, LOW),
3106 F_ROT( 64000000, pll8, 6, LOW),
3107 F_ROT( 76800000, pll8, 5, LOW),
3108 F_ROT( 96000000, pll8, 4, NOMINAL),
3109 F_ROT(100000000, pll2, 8, NOMINAL),
3110 F_ROT(114290000, pll2, 7, NOMINAL),
3111 F_ROT(133330000, pll2, 6, NOMINAL),
3112 F_ROT(160000000, pll2, 5, NOMINAL),
3113 F_END
3114};
3115
3116static struct bank_masks bdiv_info_rot = {
3117 .bank_sel_mask = BIT(30),
3118 .bank0_mask = {
3119 .ns_mask = BM(25, 22) | BM(18, 16),
3120 },
3121 .bank1_mask = {
3122 .ns_mask = BM(29, 26) | BM(21, 19),
3123 },
3124};
3125
3126static struct rcg_clk rot_clk = {
3127 .b = {
3128 .ctl_reg = ROT_CC_REG,
3129 .en_mask = BIT(0),
3130 .reset_reg = SW_RESET_CORE_REG,
3131 .reset_mask = BIT(2),
3132 .halt_reg = DBG_BUS_VEC_C_REG,
3133 .halt_bit = 15,
3134 },
3135 .ns_reg = ROT_NS_REG,
3136 .root_en_mask = BIT(2),
3137 .set_rate = set_rate_div_banked,
3138 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003139 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003140 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003141 .c = {
3142 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003143 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003144 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003145 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003146 },
3147};
3148
3149static int hdmi_pll_clk_enable(struct clk *clk)
3150{
3151 int ret;
3152 unsigned long flags;
3153 spin_lock_irqsave(&local_clock_reg_lock, flags);
3154 ret = hdmi_pll_enable();
3155 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3156 return ret;
3157}
3158
3159static void hdmi_pll_clk_disable(struct clk *clk)
3160{
3161 unsigned long flags;
3162 spin_lock_irqsave(&local_clock_reg_lock, flags);
3163 hdmi_pll_disable();
3164 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3165}
3166
3167static unsigned hdmi_pll_clk_get_rate(struct clk *clk)
3168{
3169 return hdmi_pll_get_rate();
3170}
3171
3172static struct clk_ops clk_ops_hdmi_pll = {
3173 .enable = hdmi_pll_clk_enable,
3174 .disable = hdmi_pll_clk_disable,
3175 .get_rate = hdmi_pll_clk_get_rate,
3176 .is_local = local_clk_is_local,
3177};
3178
3179static struct clk hdmi_pll_clk = {
3180 .dbg_name = "hdmi_pll_clk",
3181 .ops = &clk_ops_hdmi_pll,
3182 CLK_INIT(hdmi_pll_clk),
3183};
3184
3185#define F_TV_GND(f, s, p_r, d, m, n, v) \
3186 { \
3187 .freq_hz = f, \
3188 .src_clk = &s##_clk.c, \
3189 .md_val = MD8(8, m, 0, n), \
3190 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3191 .ctl_val = CC(6, n), \
3192 .mnd_en_mask = BIT(5) * !!(n), \
3193 .sys_vdd = v, \
3194 }
3195#define F_TV(f, s, p_r, d, m, n, v) \
3196 { \
3197 .freq_hz = f, \
3198 .src_clk = &s##_clk, \
3199 .md_val = MD8(8, m, 0, n), \
3200 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3201 .ctl_val = CC(6, n), \
3202 .mnd_en_mask = BIT(5) * !!(n), \
3203 .sys_vdd = v, \
3204 .extra_freq_data = (void *)p_r, \
3205 }
3206/* Switching TV freqs requires PLL reconfiguration. */
3207static struct clk_freq_tbl clk_tbl_tv[] = {
3208 F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
3209 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
3210 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
3211 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
3212 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
3213 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
3214 F_END
3215};
3216
3217/*
3218 * Unlike other clocks, the TV rate is adjusted through PLL
3219 * re-programming. It is also routed through an MND divider.
3220 */
3221void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3222{
3223 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3224 if (pll_rate)
3225 hdmi_pll_set_rate(pll_rate);
3226 set_rate_mnd(clk, nf);
3227}
3228
3229static struct rcg_clk tv_src_clk = {
3230 .ns_reg = TV_NS_REG,
3231 .b = {
3232 .ctl_reg = TV_CC_REG,
3233 .halt_check = NOCHECK,
3234 },
3235 .md_reg = TV_MD_REG,
3236 .root_en_mask = BIT(2),
3237 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3238 .ctl_mask = BM(7, 6),
3239 .set_rate = set_rate_tv,
3240 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003241 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003242 .c = {
3243 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003244 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003245 CLK_INIT(tv_src_clk.c),
3246 },
3247};
3248
3249static struct branch_clk tv_enc_clk = {
3250 .b = {
3251 .ctl_reg = TV_CC_REG,
3252 .en_mask = BIT(8),
3253 .reset_reg = SW_RESET_CORE_REG,
3254 .reset_mask = BIT(0),
3255 .halt_reg = DBG_BUS_VEC_D_REG,
3256 .halt_bit = 9,
3257 },
3258 .parent = &tv_src_clk.c,
3259 .c = {
3260 .dbg_name = "tv_enc_clk",
3261 .ops = &clk_ops_branch,
3262 CLK_INIT(tv_enc_clk.c),
3263 },
3264};
3265
3266static struct branch_clk tv_dac_clk = {
3267 .b = {
3268 .ctl_reg = TV_CC_REG,
3269 .en_mask = BIT(10),
3270 .halt_reg = DBG_BUS_VEC_D_REG,
3271 .halt_bit = 10,
3272 },
3273 .parent = &tv_src_clk.c,
3274 .c = {
3275 .dbg_name = "tv_dac_clk",
3276 .ops = &clk_ops_branch,
3277 CLK_INIT(tv_dac_clk.c),
3278 },
3279};
3280
3281static struct branch_clk mdp_tv_clk = {
3282 .b = {
3283 .ctl_reg = TV_CC_REG,
3284 .en_mask = BIT(0),
3285 .reset_reg = SW_RESET_CORE_REG,
3286 .reset_mask = BIT(4),
3287 .halt_reg = DBG_BUS_VEC_D_REG,
3288 .halt_bit = 12,
3289 },
3290 .parent = &tv_src_clk.c,
3291 .c = {
3292 .dbg_name = "mdp_tv_clk",
3293 .ops = &clk_ops_branch,
3294 CLK_INIT(mdp_tv_clk.c),
3295 },
3296};
3297
3298static struct branch_clk hdmi_tv_clk = {
3299 .b = {
3300 .ctl_reg = TV_CC_REG,
3301 .en_mask = BIT(12),
3302 .reset_reg = SW_RESET_CORE_REG,
3303 .reset_mask = BIT(1),
3304 .halt_reg = DBG_BUS_VEC_D_REG,
3305 .halt_bit = 11,
3306 },
3307 .parent = &tv_src_clk.c,
3308 .c = {
3309 .dbg_name = "hdmi_tv_clk",
3310 .ops = &clk_ops_branch,
3311 CLK_INIT(hdmi_tv_clk.c),
3312 },
3313};
3314
3315static struct branch_clk hdmi_app_clk = {
3316 .b = {
3317 .ctl_reg = MISC_CC2_REG,
3318 .en_mask = BIT(11),
3319 .reset_reg = SW_RESET_CORE_REG,
3320 .reset_mask = BIT(11),
3321 .halt_reg = DBG_BUS_VEC_B_REG,
3322 .halt_bit = 25,
3323 },
3324 .c = {
3325 .dbg_name = "hdmi_app_clk",
3326 .ops = &clk_ops_branch,
3327 CLK_INIT(hdmi_app_clk.c),
3328 },
3329};
3330
3331static struct bank_masks bmnd_info_vcodec = {
3332 .bank_sel_mask = BIT(13),
3333 .bank0_mask = {
3334 .md_reg = VCODEC_MD0_REG,
3335 .ns_mask = BM(18, 11) | BM(2, 0),
3336 .rst_mask = BIT(31),
3337 .mnd_en_mask = BIT(5),
3338 .mode_mask = BM(7, 6),
3339 },
3340 .bank1_mask = {
3341 .md_reg = VCODEC_MD1_REG,
3342 .ns_mask = BM(26, 19) | BM(29, 27),
3343 .rst_mask = BIT(30),
3344 .mnd_en_mask = BIT(10),
3345 .mode_mask = BM(12, 11),
3346 },
3347};
3348#define F_VCODEC(f, s, m, n, v) \
3349 { \
3350 .freq_hz = f, \
3351 .src_clk = &s##_clk.c, \
3352 .md_val = MD8(8, m, 0, n), \
3353 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
3354 .ctl_val = CC_BANKED(6, 11, n), \
3355 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
3356 .sys_vdd = v, \
3357 }
3358static struct clk_freq_tbl clk_tbl_vcodec[] = {
3359 F_VCODEC( 0, gnd, 0, 0, NONE),
3360 F_VCODEC( 27000000, pxo, 0, 0, LOW),
3361 F_VCODEC( 32000000, pll8, 1, 12, LOW),
3362 F_VCODEC( 48000000, pll8, 1, 8, LOW),
3363 F_VCODEC( 54860000, pll8, 1, 7, LOW),
3364 F_VCODEC( 96000000, pll8, 1, 4, LOW),
3365 F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
3366 F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
3367 F_VCODEC(228570000, pll2, 2, 7, HIGH),
3368 F_END
3369};
3370
3371static struct rcg_clk vcodec_clk = {
3372 .b = {
3373 .ctl_reg = VCODEC_CC_REG,
3374 .en_mask = BIT(0),
3375 .reset_reg = SW_RESET_CORE_REG,
3376 .reset_mask = BIT(6),
3377 .halt_reg = DBG_BUS_VEC_C_REG,
3378 .halt_bit = 29,
3379 },
3380 .ns_reg = VCODEC_NS_REG,
3381 .root_en_mask = BIT(2),
3382 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003383 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003384 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003385 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003386 .c = {
3387 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003388 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003389 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003390 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003391 },
3392};
3393
3394#define F_VPE(f, s, d, v) \
3395 { \
3396 .freq_hz = f, \
3397 .src_clk = &s##_clk.c, \
3398 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3399 .sys_vdd = v, \
3400 }
3401static struct clk_freq_tbl clk_tbl_vpe[] = {
3402 F_VPE( 0, gnd, 1, NONE),
3403 F_VPE( 27000000, pxo, 1, LOW),
3404 F_VPE( 34909000, pll8, 11, LOW),
3405 F_VPE( 38400000, pll8, 10, LOW),
3406 F_VPE( 64000000, pll8, 6, LOW),
3407 F_VPE( 76800000, pll8, 5, LOW),
3408 F_VPE( 96000000, pll8, 4, NOMINAL),
3409 F_VPE(100000000, pll2, 8, NOMINAL),
3410 F_VPE(160000000, pll2, 5, NOMINAL),
3411 F_END
3412};
3413
3414static struct rcg_clk vpe_clk = {
3415 .b = {
3416 .ctl_reg = VPE_CC_REG,
3417 .en_mask = BIT(0),
3418 .reset_reg = SW_RESET_CORE_REG,
3419 .reset_mask = BIT(17),
3420 .halt_reg = DBG_BUS_VEC_A_REG,
3421 .halt_bit = 28,
3422 },
3423 .ns_reg = VPE_NS_REG,
3424 .root_en_mask = BIT(2),
3425 .ns_mask = (BM(15, 12) | BM(2, 0)),
3426 .set_rate = set_rate_nop,
3427 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003428 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003429 .c = {
3430 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003431 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003432 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003433 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003434 },
3435};
3436
3437#define F_VFE(f, s, d, m, n, v) \
3438 { \
3439 .freq_hz = f, \
3440 .src_clk = &s##_clk.c, \
3441 .md_val = MD8(8, m, 0, n), \
3442 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
3443 .ctl_val = CC(6, n), \
3444 .mnd_en_mask = BIT(5) * !!(n), \
3445 .sys_vdd = v, \
3446 }
3447static struct clk_freq_tbl clk_tbl_vfe[] = {
3448 F_VFE( 0, gnd, 1, 0, 0, NONE),
3449 F_VFE( 13960000, pll8, 1, 2, 55, LOW),
3450 F_VFE( 27000000, pxo, 1, 0, 0, LOW),
3451 F_VFE( 36570000, pll8, 1, 2, 21, LOW),
3452 F_VFE( 38400000, pll8, 2, 1, 5, LOW),
3453 F_VFE( 45180000, pll8, 1, 2, 17, LOW),
3454 F_VFE( 48000000, pll8, 2, 1, 4, LOW),
3455 F_VFE( 54860000, pll8, 1, 1, 7, LOW),
3456 F_VFE( 64000000, pll8, 2, 1, 3, LOW),
3457 F_VFE( 76800000, pll8, 1, 1, 5, LOW),
3458 F_VFE( 96000000, pll8, 2, 1, 2, LOW),
3459 F_VFE(109710000, pll8, 1, 2, 7, LOW),
3460 F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
3461 F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
3462 F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
3463 F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
3464 F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003465 F_VFE(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003466 F_END
3467};
3468
3469
3470static struct rcg_clk vfe_clk = {
3471 .b = {
3472 .ctl_reg = VFE_CC_REG,
3473 .reset_reg = SW_RESET_CORE_REG,
3474 .reset_mask = BIT(15),
3475 .halt_reg = DBG_BUS_VEC_B_REG,
3476 .halt_bit = 6,
3477 .en_mask = BIT(0),
3478 },
3479 .ns_reg = VFE_NS_REG,
3480 .md_reg = VFE_MD_REG,
3481 .root_en_mask = BIT(2),
3482 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
3483 .ctl_mask = BM(7, 6),
3484 .set_rate = set_rate_mnd,
3485 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003486 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003487 .c = {
3488 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003489 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003490 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003491 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003492 },
3493};
3494
Matt Wagantallc23eee92011-08-16 23:06:52 -07003495static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003496 .b = {
3497 .ctl_reg = VFE_CC_REG,
3498 .en_mask = BIT(12),
3499 .reset_reg = SW_RESET_CORE_REG,
3500 .reset_mask = BIT(24),
3501 .halt_reg = DBG_BUS_VEC_B_REG,
3502 .halt_bit = 8,
3503 },
3504 .parent = &vfe_clk.c,
3505 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07003506 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003507 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07003508 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003509 },
3510};
3511
3512/*
3513 * Low Power Audio Clocks
3514 */
3515#define F_AIF_OSR(f, s, d, m, n, v) \
3516 { \
3517 .freq_hz = f, \
3518 .src_clk = &s##_clk.c, \
3519 .md_val = MD8(8, m, 0, n), \
3520 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
3521 .mnd_en_mask = BIT(8) * !!(n), \
3522 .sys_vdd = v, \
3523 }
3524static struct clk_freq_tbl clk_tbl_aif_osr[] = {
3525 F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
3526 F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
3527 F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
3528 F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
3529 F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
3530 F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
3531 F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
3532 F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
3533 F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
3534 F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
3535 F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
3536 F_END
3537};
3538
3539#define CLK_AIF_OSR(i, ns, md, h_r) \
3540 struct rcg_clk i##_clk = { \
3541 .b = { \
3542 .ctl_reg = ns, \
3543 .en_mask = BIT(17), \
3544 .reset_reg = ns, \
3545 .reset_mask = BIT(19), \
3546 .halt_reg = h_r, \
3547 .halt_check = ENABLE, \
3548 .halt_bit = 1, \
3549 }, \
3550 .ns_reg = ns, \
3551 .md_reg = md, \
3552 .root_en_mask = BIT(9), \
3553 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3554 .set_rate = set_rate_mnd, \
3555 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003556 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003557 .c = { \
3558 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003559 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003560 CLK_INIT(i##_clk.c), \
3561 }, \
3562 }
3563#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
3564 struct rcg_clk i##_clk = { \
3565 .b = { \
3566 .ctl_reg = ns, \
3567 .en_mask = BIT(21), \
3568 .reset_reg = ns, \
3569 .reset_mask = BIT(23), \
3570 .halt_reg = h_r, \
3571 .halt_check = ENABLE, \
3572 .halt_bit = 1, \
3573 }, \
3574 .ns_reg = ns, \
3575 .md_reg = md, \
3576 .root_en_mask = BIT(9), \
3577 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3578 .set_rate = set_rate_mnd, \
3579 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003580 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003581 .c = { \
3582 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003583 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003584 CLK_INIT(i##_clk.c), \
3585 }, \
3586 }
3587
3588#define F_AIF_BIT(d, s) \
3589 { \
3590 .freq_hz = d, \
3591 .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
3592 }
3593static struct clk_freq_tbl clk_tbl_aif_bit[] = {
3594 F_AIF_BIT(0, 1), /* Use external clock. */
3595 F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
3596 F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
3597 F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
3598 F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
3599 F_END
3600};
3601
3602#define CLK_AIF_BIT(i, ns, h_r) \
3603 struct rcg_clk i##_clk = { \
3604 .b = { \
3605 .ctl_reg = ns, \
3606 .en_mask = BIT(15), \
3607 .halt_reg = h_r, \
3608 .halt_check = DELAY, \
3609 }, \
3610 .ns_reg = ns, \
3611 .ns_mask = BM(14, 10), \
3612 .set_rate = set_rate_nop, \
3613 .freq_tbl = clk_tbl_aif_bit, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003614 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003615 .c = { \
3616 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003617 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003618 CLK_INIT(i##_clk.c), \
3619 }, \
3620 }
3621
3622#define F_AIF_BIT_D(d, s) \
3623 { \
3624 .freq_hz = d, \
3625 .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
3626 }
3627static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
3628 F_AIF_BIT_D(0, 1), /* Use external clock. */
3629 F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
3630 F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
3631 F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
3632 F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
3633 F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
3634 F_AIF_BIT_D(16, 0),
3635 F_END
3636};
3637
3638#define CLK_AIF_BIT_DIV(i, ns, h_r) \
3639 struct rcg_clk i##_clk = { \
3640 .b = { \
3641 .ctl_reg = ns, \
3642 .en_mask = BIT(19), \
3643 .halt_reg = h_r, \
3644 .halt_check = ENABLE, \
3645 }, \
3646 .ns_reg = ns, \
3647 .ns_mask = BM(18, 10), \
3648 .set_rate = set_rate_nop, \
3649 .freq_tbl = clk_tbl_aif_bit_div, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003650 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003651 .c = { \
3652 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003653 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003654 CLK_INIT(i##_clk.c), \
3655 }, \
3656 }
3657
3658static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
3659 LCC_MI2S_STATUS_REG);
3660static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
3661
3662static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
3663 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
3664static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
3665 LCC_CODEC_I2S_MIC_STATUS_REG);
3666
3667static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
3668 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
3669static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
3670 LCC_SPARE_I2S_MIC_STATUS_REG);
3671
3672static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
3673 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
3674static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
3675 LCC_CODEC_I2S_SPKR_STATUS_REG);
3676
3677static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
3678 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
3679static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
3680 LCC_SPARE_I2S_SPKR_STATUS_REG);
3681
3682#define F_PCM(f, s, d, m, n, v) \
3683 { \
3684 .freq_hz = f, \
3685 .src_clk = &s##_clk.c, \
3686 .md_val = MD16(m, n), \
3687 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
3688 .mnd_en_mask = BIT(8) * !!(n), \
3689 .sys_vdd = v, \
3690 }
3691static struct clk_freq_tbl clk_tbl_pcm[] = {
3692 F_PCM( 0, gnd, 1, 0, 0, NONE),
3693 F_PCM( 512000, pll4, 4, 1, 192, LOW),
3694 F_PCM( 768000, pll4, 4, 1, 128, LOW),
3695 F_PCM( 1024000, pll4, 4, 1, 96, LOW),
3696 F_PCM( 1536000, pll4, 4, 1, 64, LOW),
3697 F_PCM( 2048000, pll4, 4, 1, 48, LOW),
3698 F_PCM( 3072000, pll4, 4, 1, 32, LOW),
3699 F_PCM( 4096000, pll4, 4, 1, 24, LOW),
3700 F_PCM( 6144000, pll4, 4, 1, 16, LOW),
3701 F_PCM( 8192000, pll4, 4, 1, 12, LOW),
3702 F_PCM(12288000, pll4, 4, 1, 8, LOW),
3703 F_PCM(24576000, pll4, 4, 1, 4, LOW),
3704 F_END
3705};
3706
3707static struct rcg_clk pcm_clk = {
3708 .b = {
3709 .ctl_reg = LCC_PCM_NS_REG,
3710 .en_mask = BIT(11),
3711 .reset_reg = LCC_PCM_NS_REG,
3712 .reset_mask = BIT(13),
3713 .halt_reg = LCC_PCM_STATUS_REG,
3714 .halt_check = ENABLE,
3715 .halt_bit = 0,
3716 },
3717 .ns_reg = LCC_PCM_NS_REG,
3718 .md_reg = LCC_PCM_MD_REG,
3719 .root_en_mask = BIT(9),
3720 .ns_mask = (BM(31, 16) | BM(6, 0)),
3721 .set_rate = set_rate_mnd,
3722 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003723 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003724 .c = {
3725 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003726 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003727 CLK_INIT(pcm_clk.c),
3728 },
3729};
3730
3731static struct rcg_clk audio_slimbus_clk = {
3732 .b = {
3733 .ctl_reg = LCC_SLIMBUS_NS_REG,
3734 .en_mask = BIT(10),
3735 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
3736 .reset_mask = BIT(5),
3737 .halt_reg = LCC_SLIMBUS_STATUS_REG,
3738 .halt_check = ENABLE,
3739 .halt_bit = 0,
3740 },
3741 .ns_reg = LCC_SLIMBUS_NS_REG,
3742 .md_reg = LCC_SLIMBUS_MD_REG,
3743 .root_en_mask = BIT(9),
3744 .ns_mask = (BM(31, 24) | BM(6, 0)),
3745 .set_rate = set_rate_mnd,
3746 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003747 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003748 .c = {
3749 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003750 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003751 CLK_INIT(audio_slimbus_clk.c),
3752 },
3753};
3754
3755static struct branch_clk sps_slimbus_clk = {
3756 .b = {
3757 .ctl_reg = LCC_SLIMBUS_NS_REG,
3758 .en_mask = BIT(12),
3759 .halt_reg = LCC_SLIMBUS_STATUS_REG,
3760 .halt_check = ENABLE,
3761 .halt_bit = 1,
3762 },
3763 .parent = &audio_slimbus_clk.c,
3764 .c = {
3765 .dbg_name = "sps_slimbus_clk",
3766 .ops = &clk_ops_branch,
3767 CLK_INIT(sps_slimbus_clk.c),
3768 },
3769};
3770
3771static struct branch_clk slimbus_xo_src_clk = {
3772 .b = {
3773 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
3774 .en_mask = BIT(2),
3775 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003776 .halt_bit = 28,
3777 },
3778 .parent = &sps_slimbus_clk.c,
3779 .c = {
3780 .dbg_name = "slimbus_xo_src_clk",
3781 .ops = &clk_ops_branch,
3782 CLK_INIT(slimbus_xo_src_clk.c),
3783 },
3784};
3785
Matt Wagantall735f01a2011-08-12 12:40:28 -07003786DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
3787DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
3788DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
3789DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
3790DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
3791DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
3792DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
3793DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003794
3795static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
3796static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
3797static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
3798static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
3799static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
3800static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
3801static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
3802static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
3803
3804static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
3805/*
3806 * TODO: replace dummy_clk below with ebi1_clk.c once the
3807 * bus driver starts voting on ebi1 rates.
3808 */
3809static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
3810
3811#ifdef CONFIG_DEBUG_FS
3812struct measure_sel {
3813 u32 test_vector;
3814 struct clk *clk;
3815};
3816
Matt Wagantall8b38f942011-08-02 18:23:18 -07003817static DEFINE_CLK_MEASURE(l2_m_clk);
3818static DEFINE_CLK_MEASURE(krait0_m_clk);
3819static DEFINE_CLK_MEASURE(krait1_m_clk);
3820
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003821static struct measure_sel measure_mux[] = {
3822 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
3823 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
3824 { TEST_PER_LS(0x13), &sdc1_clk.c },
3825 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
3826 { TEST_PER_LS(0x15), &sdc2_clk.c },
3827 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
3828 { TEST_PER_LS(0x17), &sdc3_clk.c },
3829 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
3830 { TEST_PER_LS(0x19), &sdc4_clk.c },
3831 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
3832 { TEST_PER_LS(0x1B), &sdc5_clk.c },
3833 { TEST_PER_LS(0x25), &dfab_clk.c },
3834 { TEST_PER_LS(0x25), &dfab_a_clk.c },
3835 { TEST_PER_LS(0x26), &pmem_clk.c },
3836 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
3837 { TEST_PER_LS(0x33), &cfpb_clk.c },
3838 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
3839 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
3840 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
3841 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
3842 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
3843 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
3844 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
3845 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
3846 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
3847 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
3848 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
3849 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
3850 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
3851 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
3852 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
3853 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
3854 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
3855 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
3856 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
3857 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
3858 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
3859 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
3860 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
3861 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
3862 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
3863 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
3864 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
3865 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
3866 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
3867 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
3868 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
3869 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
3870 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
3871 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
3872 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
3873 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
3874 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
3875 { TEST_PER_LS(0x78), &sfpb_clk.c },
3876 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
3877 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
3878 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
3879 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
3880 { TEST_PER_LS(0x7D), &prng_clk.c },
3881 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
3882 { TEST_PER_LS(0x80), &adm0_p_clk.c },
3883 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
3884 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07003885 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
3886 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
3887 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003888 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
3889 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
3890 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
3891 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
3892 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
3893 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
3894 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
3895 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
3896 { TEST_PER_LS(0x92), &ce1_p_clk.c },
3897 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07003898 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003899 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
3900
3901 { TEST_PER_HS(0x07), &afab_clk.c },
3902 { TEST_PER_HS(0x07), &afab_a_clk.c },
3903 { TEST_PER_HS(0x18), &sfab_clk.c },
3904 { TEST_PER_HS(0x18), &sfab_a_clk.c },
3905 { TEST_PER_HS(0x2A), &adm0_clk.c },
3906 { TEST_PER_HS(0x34), &ebi1_clk.c },
3907 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07003908 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003909
3910 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
3911 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
3912 { TEST_MM_LS(0x02), &cam1_clk.c },
3913 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07003914 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003915 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
3916 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
3917 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
3918 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
3919 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
3920 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
3921 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
3922 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
3923 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
3924 { TEST_MM_LS(0x12), &imem_p_clk.c },
3925 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
3926 { TEST_MM_LS(0x14), &mdp_p_clk.c },
3927 { TEST_MM_LS(0x16), &rot_p_clk.c },
3928 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
3929 { TEST_MM_LS(0x18), &smmu_p_clk.c },
3930 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
3931 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
3932 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
3933 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
3934 { TEST_MM_LS(0x1D), &cam0_clk.c },
3935 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
3936 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
3937 { TEST_MM_LS(0x21), &tv_dac_clk.c },
3938 { TEST_MM_LS(0x22), &tv_enc_clk.c },
3939 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
3940 { TEST_MM_LS(0x25), &mmfpb_clk.c },
3941 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
3942 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07003943 { TEST_MM_LS(0x27), &cam2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003944
3945 { TEST_MM_HS(0x00), &csi0_clk.c },
3946 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07003947 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003948 { TEST_MM_HS(0x05), &ijpeg_clk.c },
3949 { TEST_MM_HS(0x06), &vfe_clk.c },
3950 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
3951 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
3952 { TEST_MM_HS(0x09), &gfx3d_clk.c },
3953 { TEST_MM_HS(0x0A), &jpegd_clk.c },
3954 { TEST_MM_HS(0x0B), &vcodec_clk.c },
3955 { TEST_MM_HS(0x0F), &mmfab_clk.c },
3956 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
3957 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
3958 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
3959 { TEST_MM_HS(0x13), &imem_axi_clk.c },
3960 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
3961 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
3962 { TEST_MM_HS(0x16), &rot_axi_clk.c },
3963 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
3964 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
3965 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
3966 { TEST_MM_HS(0x1A), &mdp_clk.c },
3967 { TEST_MM_HS(0x1B), &rot_clk.c },
3968 { TEST_MM_HS(0x1C), &vpe_clk.c },
3969 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
3970 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
3971 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
3972 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
3973 { TEST_MM_HS(0x26), &csi_pix_clk.c },
3974 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
3975 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
3976 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
3977 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
3978 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
3979 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07003980 { TEST_MM_HS(0x2D), &csi2_clk.c },
3981 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
3982 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
3983 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
3984 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
3985 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003986
3987 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
3988 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
3989 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
3990 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
3991 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
3992 { TEST_LPA(0x14), &pcm_clk.c },
3993 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07003994
3995 { TEST_CPUL2(0x1), &l2_m_clk },
3996 { TEST_CPUL2(0x2), &krait0_m_clk },
3997 { TEST_CPUL2(0x3), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003998};
3999
4000static struct measure_sel *find_measure_sel(struct clk *clk)
4001{
4002 int i;
4003
4004 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4005 if (measure_mux[i].clk == clk)
4006 return &measure_mux[i];
4007 return NULL;
4008}
4009
Matt Wagantall8b38f942011-08-02 18:23:18 -07004010static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004011{
4012 int ret = 0;
4013 u32 clk_sel;
4014 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004015 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004016 unsigned long flags;
4017
4018 if (!parent)
4019 return -EINVAL;
4020
4021 p = find_measure_sel(parent);
4022 if (!p)
4023 return -EINVAL;
4024
4025 spin_lock_irqsave(&local_clock_reg_lock, flags);
4026
Matt Wagantall8b38f942011-08-02 18:23:18 -07004027 /*
4028 * Program the test vector, measurement period (sample_ticks)
4029 * and scaling multiplier.
4030 */
4031 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004032 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004033 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004034 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4035 case TEST_TYPE_PER_LS:
4036 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4037 break;
4038 case TEST_TYPE_PER_HS:
4039 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4040 break;
4041 case TEST_TYPE_MM_LS:
4042 writel_relaxed(0x4030D97, CLK_TEST_REG);
4043 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4044 break;
4045 case TEST_TYPE_MM_HS:
4046 writel_relaxed(0x402B800, CLK_TEST_REG);
4047 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4048 break;
4049 case TEST_TYPE_LPA:
4050 writel_relaxed(0x4030D98, CLK_TEST_REG);
4051 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4052 LCC_CLK_LS_DEBUG_CFG_REG);
4053 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004054 case TEST_TYPE_CPUL2:
4055 writel_relaxed(0x4030400, CLK_TEST_REG);
4056 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4057 clk->sample_ticks = 0x4000;
4058 clk->multiplier = 2;
4059 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004060 default:
4061 ret = -EPERM;
4062 }
4063 /* Make sure test vector is set before starting measurements. */
4064 mb();
4065
4066 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4067
4068 return ret;
4069}
4070
4071/* Sample clock for 'ticks' reference clock ticks. */
4072static u32 run_measurement(unsigned ticks)
4073{
4074 /* Stop counters and set the XO4 counter start value. */
4075 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4076 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4077
4078 /* Wait for timer to become ready. */
4079 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4080 cpu_relax();
4081
4082 /* Run measurement and wait for completion. */
4083 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4084 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4085 cpu_relax();
4086
4087 /* Stop counters. */
4088 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4089
4090 /* Return measured ticks. */
4091 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4092}
4093
4094
4095/* Perform a hardware rate measurement for a given clock.
4096 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004097static unsigned measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004098{
4099 unsigned long flags;
4100 u32 pdm_reg_backup, ringosc_reg_backup;
4101 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004102 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004103 unsigned ret;
4104
4105 spin_lock_irqsave(&local_clock_reg_lock, flags);
4106
4107 /* Enable CXO/4 and RINGOSC branch and root. */
4108 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4109 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4110 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4111 writel_relaxed(0xA00, RINGOSC_NS_REG);
4112
4113 /*
4114 * The ring oscillator counter will not reset if the measured clock
4115 * is not running. To detect this, run a short measurement before
4116 * the full measurement. If the raw results of the two are the same
4117 * then the clock must be off.
4118 */
4119
4120 /* Run a short measurement. (~1 ms) */
4121 raw_count_short = run_measurement(0x1000);
4122 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004123 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004124
4125 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4126 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4127
4128 /* Return 0 if the clock is off. */
4129 if (raw_count_full == raw_count_short)
4130 ret = 0;
4131 else {
4132 /* Compute rate in Hz. */
4133 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004134 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4135 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004136 }
4137
4138 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004139 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004140 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4141
4142 return ret;
4143}
4144#else /* !CONFIG_DEBUG_FS */
4145static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4146{
4147 return -EINVAL;
4148}
4149
4150static unsigned measure_clk_get_rate(struct clk *clk)
4151{
4152 return 0;
4153}
4154#endif /* CONFIG_DEBUG_FS */
4155
4156static struct clk_ops measure_clk_ops = {
4157 .set_parent = measure_clk_set_parent,
4158 .get_rate = measure_clk_get_rate,
4159 .is_local = local_clk_is_local,
4160};
4161
Matt Wagantall8b38f942011-08-02 18:23:18 -07004162static struct measure_clk measure_clk = {
4163 .c = {
4164 .dbg_name = "measure_clk",
4165 .ops = &measure_clk_ops,
4166 CLK_INIT(measure_clk.c),
4167 },
4168 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004169};
4170
Stephen Boyd94625ef2011-07-12 17:06:01 -07004171static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004172 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
4173 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4174 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4175 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004176 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004177
4178 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
4179 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
4180 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
4181 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
4182 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
4183 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
4184 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
4185 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
4186 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
4187 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
4188 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
4189 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
4190 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
4191 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
4192 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
4193 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
4194
Matt Wagantalle2522372011-08-17 14:52:21 -07004195 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
4196 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
4197 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
4198 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
4199 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
4200 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
4201 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
4202 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
4203 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
4204 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
4205 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
4206 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004207 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004208 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004209 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
4210 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004211 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
4212 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
4213 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
4214 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
4215 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004216 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004217 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004218 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004219 CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
4220 CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
4221 CLK_LOOKUP("prng_clk", prng_clk.c, NULL),
4222 CLK_LOOKUP("sdc_clk", sdc1_clk.c, "msm_sdcc.1"),
4223 CLK_LOOKUP("sdc_clk", sdc2_clk.c, "msm_sdcc.2"),
4224 CLK_LOOKUP("sdc_clk", sdc3_clk.c, "msm_sdcc.3"),
4225 CLK_LOOKUP("sdc_clk", sdc4_clk.c, "msm_sdcc.4"),
4226 CLK_LOOKUP("sdc_clk", sdc5_clk.c, "msm_sdcc.5"),
4227 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
4228 CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
4229 CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
4230 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
4231 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
4232 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
4233 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
4234 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
4235 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
4236 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
4237 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
4238 CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
4239 CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
4240 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004241 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004242 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004243 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
4244 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07004245 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
4246 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004247 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
4248 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
4249 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004250 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004251 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004252 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004253 CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
4254 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
4255 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
4256 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
4257 CLK_LOOKUP("sdc_pclk", sdc1_p_clk.c, "msm_sdcc.1"),
4258 CLK_LOOKUP("sdc_pclk", sdc2_p_clk.c, "msm_sdcc.2"),
4259 CLK_LOOKUP("sdc_pclk", sdc3_p_clk.c, "msm_sdcc.3"),
4260 CLK_LOOKUP("sdc_pclk", sdc4_p_clk.c, "msm_sdcc.4"),
4261 CLK_LOOKUP("sdc_pclk", sdc5_p_clk.c, "msm_sdcc.5"),
4262 CLK_LOOKUP("adm_clk", adm0_clk.c, NULL),
4263 CLK_LOOKUP("adm_pclk", adm0_p_clk.c, NULL),
4264 CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
4265 CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
4266 CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
4267 CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
4268 CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
4269 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4270 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
4271 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
4272 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004273 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004274 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
4275 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
4276 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004277 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004278 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_camera_ov2720.0"),
4279 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
4280 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
4281 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004282 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004283 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov2720.0"),
4284 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
4285 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
4286 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004287 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004288 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_camera_ov2720.0"),
4289 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
4290 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
4291 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
4292 CLK_LOOKUP("csi0phy_timer_clk", csi0phy_timer_clk.c, NULL),
4293 CLK_LOOKUP("csi1phy_timer_clk", csi1phy_timer_clk.c, NULL),
4294 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4295 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4296 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4297 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
4298 CLK_LOOKUP("gfx2d0_clk", gfx2d0_clk.c, NULL),
4299 CLK_LOOKUP("gfx2d1_clk", gfx2d1_clk.c, NULL),
4300 CLK_LOOKUP("gfx3d_clk", gfx3d_clk.c, NULL),
4301 CLK_LOOKUP("ijpeg_axi_clk", ijpeg_axi_clk.c, NULL),
4302 CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
4303 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
4304 CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
4305 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
4306 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
4307 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
4308 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
4309 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
4310 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
4311 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
4312 CLK_LOOKUP("vcodec_clk", vcodec_clk.c, NULL),
4313 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
4314 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
4315 CLK_LOOKUP("hdmi_app_clk", hdmi_app_clk.c, NULL),
4316 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
4317 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004318 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004319 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
4320 CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
4321 CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
4322 CLK_LOOKUP("vcodec_axi_clk", vcodec_axi_clk.c, NULL),
4323 CLK_LOOKUP("vcodec_axi_a_clk", vcodec_axi_a_clk.c, NULL),
4324 CLK_LOOKUP("vcodec_axi_b_clk", vcodec_axi_b_clk.c, NULL),
4325 CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
4326 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004327 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004328 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
4329 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
4330 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
4331 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
4332 CLK_LOOKUP("gfx2d0_pclk", gfx2d0_p_clk.c, NULL),
4333 CLK_LOOKUP("gfx2d1_pclk", gfx2d1_p_clk.c, NULL),
4334 CLK_LOOKUP("gfx3d_pclk", gfx3d_p_clk.c, NULL),
4335 CLK_LOOKUP("hdmi_m_pclk", hdmi_m_p_clk.c, NULL),
4336 CLK_LOOKUP("hdmi_s_pclk", hdmi_s_p_clk.c, NULL),
4337 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
4338 CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
4339 CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
4340 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
4341 CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
4342 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
4343 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
4344 CLK_LOOKUP("vcodec_pclk", vcodec_p_clk.c, NULL),
4345 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
4346 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
4347 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
4348 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
4349 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
4350 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
4351 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
4352 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
4353 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
4354 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
4355 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
4356 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
4357 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
4358 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
4359 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
4360 CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
4361 CLK_LOOKUP("iommu_clk", vpe_axi_clk.c, "msm_iommu.1"),
4362 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
4363 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
4364 CLK_LOOKUP("iommu_clk", rot_axi_clk.c, "msm_iommu.4"),
4365 CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
4366 CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
4367 CLK_LOOKUP("iommu_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
4368 CLK_LOOKUP("iommu_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
4369 CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
4370 CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
4371 CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
4372 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
4373 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
4374 CLK_LOOKUP("dfab_sdc_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
4375 CLK_LOOKUP("dfab_sdc_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
4376 CLK_LOOKUP("dfab_sdc_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
4377 CLK_LOOKUP("dfab_sdc_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
4378 CLK_LOOKUP("dfab_sdc_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07004379 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004380
4381 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
4382 CLK_LOOKUP("ebi1_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004383
4384 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
4385 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
4386 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004387};
4388
Stephen Boyd94625ef2011-07-12 17:06:01 -07004389static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
4390 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
4391 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
4392 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
4393 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, NULL),
4394 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, NULL),
4395 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, NULL),
4396 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
4397 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
4398 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
4399 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
4400 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
4401 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
4402 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
4403};
4404
4405/* Add v2 clocks dynamically at runtime */
4406static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
4407 ARRAY_SIZE(msm_clocks_8960_v2)];
4408
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004409/*
4410 * Miscellaneous clock register initializations
4411 */
4412
4413/* Read, modify, then write-back a register. */
4414static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
4415{
4416 uint32_t regval = readl_relaxed(reg);
4417 regval &= ~mask;
4418 regval |= val;
4419 writel_relaxed(regval, reg);
4420}
4421
4422static void __init reg_init(void)
4423{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004424 /* Deassert MM SW_RESET_ALL signal. */
4425 writel_relaxed(0, SW_RESET_ALL_REG);
4426
4427 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
4428 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
4429 * prevent its memory from being collapsed when the clock is halted.
4430 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004431 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
4432 writel_relaxed(0x000007F9, AHB_EN2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004433
4434 /* Deassert all locally-owned MM AHB resets. */
4435 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
4436
4437 /* Initialize MM AXI registers: Enable HW gating for all clocks that
4438 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
4439 * delays to safe values. */
4440 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004441 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
4442 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
4443 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
4444 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
4445 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004446
4447 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
4448 * memories retain state even when not clocked. Also, set sleep and
4449 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004450 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
4451 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
4452 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
4453 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
4454 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
4455 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
4456 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
4457 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
4458 rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
4459 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
4460 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
4461 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
4462 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
4463 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
4464 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
4465 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
4466 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
4467 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004468 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07004469 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004470
4471 /* De-assert MM AXI resets to all hardware blocks. */
4472 writel_relaxed(0, SW_RESET_AXI_REG);
4473
4474 /* Deassert all MM core resets. */
4475 writel_relaxed(0, SW_RESET_CORE_REG);
4476
4477 /* Reset 3D core once more, with its clock enabled. This can
4478 * eventually be done as part of the GDFS footswitch driver. */
4479 clk_set_rate(&gfx3d_clk.c, 27000000);
4480 clk_enable(&gfx3d_clk.c);
4481 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
4482 mb();
4483 udelay(5);
4484 writel_relaxed(0, SW_RESET_CORE_REG);
4485 /* Make sure reset is de-asserted before clock is disabled. */
4486 mb();
4487 clk_disable(&gfx3d_clk.c);
4488
4489 /* Enable TSSC and PDM PXO sources. */
4490 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
4491 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
4492
4493 /* Source SLIMBus xo src from slimbus reference clock */
4494 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
4495
4496 /* Source the dsi_byte_clks from the DSI PHY PLLs */
4497 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
4498 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
4499}
4500
4501static int wr_pll_clk_enable(struct clk *clk)
4502{
4503 u32 mode;
4504 unsigned long flags;
4505 struct pll_clk *pll = to_pll_clk(clk);
4506
4507 spin_lock_irqsave(&local_clock_reg_lock, flags);
4508 mode = readl_relaxed(pll->mode_reg);
4509 /* De-assert active-low PLL reset. */
4510 mode |= BIT(2);
4511 writel_relaxed(mode, pll->mode_reg);
4512
4513 /*
4514 * H/W requires a 5us delay between disabling the bypass and
4515 * de-asserting the reset. Delay 10us just to be safe.
4516 */
4517 mb();
4518 udelay(10);
4519
4520 /* Disable PLL bypass mode. */
4521 mode |= BIT(1);
4522 writel_relaxed(mode, pll->mode_reg);
4523
4524 /* Wait until PLL is locked. */
4525 mb();
4526 udelay(60);
4527
4528 /* Enable PLL output. */
4529 mode |= BIT(0);
4530 writel_relaxed(mode, pll->mode_reg);
4531
4532 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4533 return 0;
4534}
4535
Stephen Boyd94625ef2011-07-12 17:06:01 -07004536struct clock_init_data msm8960_clock_init_data __initdata;
4537
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004538/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07004539static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004540{
Stephen Boyd94625ef2011-07-12 17:06:01 -07004541 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004542 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
4543 if (IS_ERR(xo_pxo)) {
4544 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
4545 BUG();
4546 }
4547 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
4548 if (IS_ERR(xo_cxo)) {
4549 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
4550 BUG();
4551 }
4552
Stephen Boyd94625ef2011-07-12 17:06:01 -07004553 memcpy(msm_clocks_8960, msm_clocks_8960_v1, sizeof(msm_clocks_8960_v1));
4554 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
4555 struct clk_freq_tbl **ptr =
4556 (struct clk_freq_tbl **)&gfx3d_clk.freq_tbl;
4557 *ptr = clk_tbl_gfx3d_v2;
4558 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
4559 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
4560 num_lookups = ARRAY_SIZE(msm_clocks_8960);
4561 }
4562 msm8960_clock_init_data.size = num_lookups;
4563
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004564 soc_update_sys_vdd = msm8960_update_sys_vdd;
4565 local_vote_sys_vdd(HIGH);
4566
4567 clk_ops_pll.enable = wr_pll_clk_enable;
4568
4569 /* Initialize clock registers. */
4570 reg_init();
4571
4572 /* Initialize rates for clocks that only support one. */
4573 clk_set_rate(&pdm_clk.c, 27000000);
4574 clk_set_rate(&prng_clk.c, 64000000);
4575 clk_set_rate(&mdp_vsync_clk.c, 27000000);
4576 clk_set_rate(&tsif_ref_clk.c, 105000);
4577 clk_set_rate(&tssc_clk.c, 27000000);
4578 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
4579 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
4580 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004581 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
4582 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
4583 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004584
4585 /*
4586 * The halt status bits for PDM and TSSC may be incorrect at boot.
4587 * Toggle these clocks on and off to refresh them.
4588 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07004589 rcg_clk_enable(&pdm_clk.c);
4590 rcg_clk_disable(&pdm_clk.c);
4591 rcg_clk_enable(&tssc_clk.c);
4592 rcg_clk_disable(&tssc_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004593
4594 if (machine_is_msm8960_sim()) {
4595 clk_set_rate(&sdc1_clk.c, 48000000);
4596 clk_enable(&sdc1_clk.c);
4597 clk_enable(&sdc1_p_clk.c);
4598 clk_set_rate(&sdc3_clk.c, 48000000);
4599 clk_enable(&sdc3_clk.c);
4600 clk_enable(&sdc3_p_clk.c);
4601 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004602}
4603
Stephen Boydbb600ae2011-08-02 20:11:40 -07004604static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004605{
4606 return local_unvote_sys_vdd(HIGH);
4607}
Stephen Boydbb600ae2011-08-02 20:11:40 -07004608
4609struct clock_init_data msm8960_clock_init_data __initdata = {
4610 .table = msm_clocks_8960,
4611 .size = ARRAY_SIZE(msm_clocks_8960),
4612 .init = msm8960_clock_init,
4613 .late_init = msm8960_clock_late_init,
4614};