Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/console.h> |
| 29 | #include <drm/drmP.h> |
| 30 | #include <drm/drm_crtc_helper.h> |
| 31 | #include <drm/radeon_drm.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 32 | #include <linux/vgaarb.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 33 | #include <linux/vga_switcheroo.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | #include "radeon_reg.h" |
| 35 | #include "radeon.h" |
| 36 | #include "radeon_asic.h" |
| 37 | #include "atom.h" |
| 38 | |
| 39 | /* |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 40 | * Clear GPU surface registers. |
| 41 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 42 | void radeon_surface_init(struct radeon_device *rdev) |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 43 | { |
| 44 | /* FIXME: check this out */ |
| 45 | if (rdev->family < CHIP_R600) { |
| 46 | int i; |
| 47 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 48 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 49 | if (rdev->surface_regs[i].bo) |
| 50 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
| 51 | else |
| 52 | radeon_clear_surface_reg(rdev, i); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 53 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 54 | /* enable surfaces */ |
| 55 | WREG32(RADEON_SURFACE_CNTL, 0); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 56 | } |
| 57 | } |
| 58 | |
| 59 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 60 | * GPU scratch registers helpers function. |
| 61 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 62 | void radeon_scratch_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | { |
| 64 | int i; |
| 65 | |
| 66 | /* FIXME: check this out */ |
| 67 | if (rdev->family < CHIP_R300) { |
| 68 | rdev->scratch.num_reg = 5; |
| 69 | } else { |
| 70 | rdev->scratch.num_reg = 7; |
| 71 | } |
| 72 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 73 | rdev->scratch.free[i] = true; |
| 74 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
| 79 | { |
| 80 | int i; |
| 81 | |
| 82 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 83 | if (rdev->scratch.free[i]) { |
| 84 | rdev->scratch.free[i] = false; |
| 85 | *reg = rdev->scratch.reg[i]; |
| 86 | return 0; |
| 87 | } |
| 88 | } |
| 89 | return -EINVAL; |
| 90 | } |
| 91 | |
| 92 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
| 93 | { |
| 94 | int i; |
| 95 | |
| 96 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 97 | if (rdev->scratch.reg[i] == reg) { |
| 98 | rdev->scratch.free[i] = true; |
| 99 | return; |
| 100 | } |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * MC common functions |
| 106 | */ |
| 107 | int radeon_mc_setup(struct radeon_device *rdev) |
| 108 | { |
| 109 | uint32_t tmp; |
| 110 | |
| 111 | /* Some chips have an "issue" with the memory controller, the |
| 112 | * location must be aligned to the size. We just align it down, |
| 113 | * too bad if we walk over the top of system memory, we don't |
| 114 | * use DMA without a remapped anyway. |
| 115 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
| 116 | */ |
| 117 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
| 118 | */ |
| 119 | /* |
| 120 | * Note: from R6xx the address space is 40bits but here we only |
| 121 | * use 32bits (still have to see a card which would exhaust 4G |
| 122 | * address space). |
| 123 | */ |
| 124 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
| 125 | /* vram location was already setup try to put gtt after |
| 126 | * if it fits */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 127 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 128 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
| 129 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
| 130 | rdev->mc.gtt_location = tmp; |
| 131 | } else { |
| 132 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
| 133 | printk(KERN_ERR "[drm] GTT too big to fit " |
| 134 | "before or after vram location.\n"); |
| 135 | return -EINVAL; |
| 136 | } |
| 137 | rdev->mc.gtt_location = 0; |
| 138 | } |
| 139 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
| 140 | /* gtt location was already setup try to put vram before |
| 141 | * if it fits */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 142 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 143 | rdev->mc.vram_location = 0; |
| 144 | } else { |
| 145 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 146 | tmp += (rdev->mc.mc_vram_size - 1); |
| 147 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
| 148 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 149 | rdev->mc.vram_location = tmp; |
| 150 | } else { |
| 151 | printk(KERN_ERR "[drm] vram too big to fit " |
| 152 | "before or after GTT location.\n"); |
| 153 | return -EINVAL; |
| 154 | } |
| 155 | } |
| 156 | } else { |
| 157 | rdev->mc.vram_location = 0; |
Dave Airlie | 1733292 | 2009-08-07 11:03:26 +1000 | [diff] [blame] | 158 | tmp = rdev->mc.mc_vram_size; |
| 159 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
| 160 | rdev->mc.gtt_location = tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | } |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 162 | rdev->mc.vram_start = rdev->mc.vram_location; |
| 163 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| 164 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
| 165 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 166 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 167 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 168 | (unsigned)rdev->mc.vram_location, |
| 169 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
| 170 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 171 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 172 | (unsigned)rdev->mc.gtt_location, |
| 173 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | |
| 178 | /* |
| 179 | * GPU helpers function. |
| 180 | */ |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 181 | bool radeon_card_posted(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 182 | { |
| 183 | uint32_t reg; |
| 184 | |
| 185 | /* first check CRTCs */ |
| 186 | if (ASIC_IS_AVIVO(rdev)) { |
| 187 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
| 188 | RREG32(AVIVO_D2CRTC_CONTROL); |
| 189 | if (reg & AVIVO_CRTC_EN) { |
| 190 | return true; |
| 191 | } |
| 192 | } else { |
| 193 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
| 194 | RREG32(RADEON_CRTC2_GEN_CNTL); |
| 195 | if (reg & RADEON_CRTC_EN) { |
| 196 | return true; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | /* then check MEM_SIZE, in case the crtcs are off */ |
| 201 | if (rdev->family >= CHIP_R600) |
| 202 | reg = RREG32(R600_CONFIG_MEMSIZE); |
| 203 | else |
| 204 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
| 205 | |
| 206 | if (reg) |
| 207 | return true; |
| 208 | |
| 209 | return false; |
| 210 | |
| 211 | } |
| 212 | |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 213 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
| 214 | { |
| 215 | if (radeon_card_posted(rdev)) |
| 216 | return true; |
| 217 | |
| 218 | if (rdev->bios) { |
| 219 | DRM_INFO("GPU not posted. posting now...\n"); |
| 220 | if (rdev->is_atom_bios) |
| 221 | atom_asic_init(rdev->mode_info.atom_context); |
| 222 | else |
| 223 | radeon_combios_asic_init(rdev->ddev); |
| 224 | return true; |
| 225 | } else { |
| 226 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 227 | return false; |
| 228 | } |
| 229 | } |
| 230 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 231 | int radeon_dummy_page_init(struct radeon_device *rdev) |
| 232 | { |
| 233 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
| 234 | if (rdev->dummy_page.page == NULL) |
| 235 | return -ENOMEM; |
| 236 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
| 237 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 238 | if (!rdev->dummy_page.addr) { |
| 239 | __free_page(rdev->dummy_page.page); |
| 240 | rdev->dummy_page.page = NULL; |
| 241 | return -ENOMEM; |
| 242 | } |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
| 247 | { |
| 248 | if (rdev->dummy_page.page == NULL) |
| 249 | return; |
| 250 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, |
| 251 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 252 | __free_page(rdev->dummy_page.page); |
| 253 | rdev->dummy_page.page = NULL; |
| 254 | } |
| 255 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | |
| 257 | /* |
| 258 | * Registers accessors functions. |
| 259 | */ |
| 260 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
| 261 | { |
| 262 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
| 263 | BUG_ON(1); |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 268 | { |
| 269 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
| 270 | reg, v); |
| 271 | BUG_ON(1); |
| 272 | } |
| 273 | |
| 274 | void radeon_register_accessor_init(struct radeon_device *rdev) |
| 275 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | rdev->mc_rreg = &radeon_invalid_rreg; |
| 277 | rdev->mc_wreg = &radeon_invalid_wreg; |
| 278 | rdev->pll_rreg = &radeon_invalid_rreg; |
| 279 | rdev->pll_wreg = &radeon_invalid_wreg; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 280 | rdev->pciep_rreg = &radeon_invalid_rreg; |
| 281 | rdev->pciep_wreg = &radeon_invalid_wreg; |
| 282 | |
| 283 | /* Don't change order as we are overridding accessor. */ |
| 284 | if (rdev->family < CHIP_RV515) { |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 285 | rdev->pcie_reg_mask = 0xff; |
| 286 | } else { |
| 287 | rdev->pcie_reg_mask = 0x7ff; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | } |
| 289 | /* FIXME: not sure here */ |
| 290 | if (rdev->family <= CHIP_R580) { |
| 291 | rdev->pll_rreg = &r100_pll_rreg; |
| 292 | rdev->pll_wreg = &r100_pll_wreg; |
| 293 | } |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 294 | if (rdev->family >= CHIP_R420) { |
| 295 | rdev->mc_rreg = &r420_mc_rreg; |
| 296 | rdev->mc_wreg = &r420_mc_wreg; |
| 297 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 298 | if (rdev->family >= CHIP_RV515) { |
| 299 | rdev->mc_rreg = &rv515_mc_rreg; |
| 300 | rdev->mc_wreg = &rv515_mc_wreg; |
| 301 | } |
| 302 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| 303 | rdev->mc_rreg = &rs400_mc_rreg; |
| 304 | rdev->mc_wreg = &rs400_mc_wreg; |
| 305 | } |
| 306 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| 307 | rdev->mc_rreg = &rs690_mc_rreg; |
| 308 | rdev->mc_wreg = &rs690_mc_wreg; |
| 309 | } |
| 310 | if (rdev->family == CHIP_RS600) { |
| 311 | rdev->mc_rreg = &rs600_mc_rreg; |
| 312 | rdev->mc_wreg = &rs600_mc_wreg; |
| 313 | } |
| 314 | if (rdev->family >= CHIP_R600) { |
| 315 | rdev->pciep_rreg = &r600_pciep_rreg; |
| 316 | rdev->pciep_wreg = &r600_pciep_wreg; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | |
| 321 | /* |
| 322 | * ASIC |
| 323 | */ |
| 324 | int radeon_asic_init(struct radeon_device *rdev) |
| 325 | { |
| 326 | radeon_register_accessor_init(rdev); |
| 327 | switch (rdev->family) { |
| 328 | case CHIP_R100: |
| 329 | case CHIP_RV100: |
| 330 | case CHIP_RS100: |
| 331 | case CHIP_RV200: |
| 332 | case CHIP_RS200: |
| 333 | case CHIP_R200: |
| 334 | case CHIP_RV250: |
| 335 | case CHIP_RS300: |
| 336 | case CHIP_RV280: |
| 337 | rdev->asic = &r100_asic; |
| 338 | break; |
| 339 | case CHIP_R300: |
| 340 | case CHIP_R350: |
| 341 | case CHIP_RV350: |
| 342 | case CHIP_RV380: |
| 343 | rdev->asic = &r300_asic; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 344 | if (rdev->flags & RADEON_IS_PCIE) { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 345 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 346 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| 347 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 348 | break; |
| 349 | case CHIP_R420: |
| 350 | case CHIP_R423: |
| 351 | case CHIP_RV410: |
| 352 | rdev->asic = &r420_asic; |
| 353 | break; |
| 354 | case CHIP_RS400: |
| 355 | case CHIP_RS480: |
| 356 | rdev->asic = &rs400_asic; |
| 357 | break; |
| 358 | case CHIP_RS600: |
| 359 | rdev->asic = &rs600_asic; |
| 360 | break; |
| 361 | case CHIP_RS690: |
| 362 | case CHIP_RS740: |
| 363 | rdev->asic = &rs690_asic; |
| 364 | break; |
| 365 | case CHIP_RV515: |
| 366 | rdev->asic = &rv515_asic; |
| 367 | break; |
| 368 | case CHIP_R520: |
| 369 | case CHIP_RV530: |
| 370 | case CHIP_RV560: |
| 371 | case CHIP_RV570: |
| 372 | case CHIP_R580: |
| 373 | rdev->asic = &r520_asic; |
| 374 | break; |
| 375 | case CHIP_R600: |
| 376 | case CHIP_RV610: |
| 377 | case CHIP_RV630: |
| 378 | case CHIP_RV620: |
| 379 | case CHIP_RV635: |
| 380 | case CHIP_RV670: |
| 381 | case CHIP_RS780: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 382 | case CHIP_RS880: |
| 383 | rdev->asic = &r600_asic; |
| 384 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 385 | case CHIP_RV770: |
| 386 | case CHIP_RV730: |
| 387 | case CHIP_RV710: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 388 | case CHIP_RV740: |
| 389 | rdev->asic = &rv770_asic; |
| 390 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | default: |
| 392 | /* FIXME: not supported yet */ |
| 393 | return -EINVAL; |
| 394 | } |
Rafał Miłecki | 5ea597f | 2009-12-17 13:50:09 +0100 | [diff] [blame] | 395 | |
| 396 | if (rdev->flags & RADEON_IS_IGP) { |
| 397 | rdev->asic->get_memory_clock = NULL; |
| 398 | rdev->asic->set_memory_clock = NULL; |
| 399 | } |
| 400 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | |
| 405 | /* |
| 406 | * Wrapper around modesetting bits. |
| 407 | */ |
| 408 | int radeon_clocks_init(struct radeon_device *rdev) |
| 409 | { |
| 410 | int r; |
| 411 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 412 | r = radeon_static_clocks_init(rdev->ddev); |
| 413 | if (r) { |
| 414 | return r; |
| 415 | } |
| 416 | DRM_INFO("Clocks initialized !\n"); |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | void radeon_clocks_fini(struct radeon_device *rdev) |
| 421 | { |
| 422 | } |
| 423 | |
| 424 | /* ATOM accessor methods */ |
| 425 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
| 426 | { |
| 427 | struct radeon_device *rdev = info->dev->dev_private; |
| 428 | uint32_t r; |
| 429 | |
| 430 | r = rdev->pll_rreg(rdev, reg); |
| 431 | return r; |
| 432 | } |
| 433 | |
| 434 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 435 | { |
| 436 | struct radeon_device *rdev = info->dev->dev_private; |
| 437 | |
| 438 | rdev->pll_wreg(rdev, reg, val); |
| 439 | } |
| 440 | |
| 441 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
| 442 | { |
| 443 | struct radeon_device *rdev = info->dev->dev_private; |
| 444 | uint32_t r; |
| 445 | |
| 446 | r = rdev->mc_rreg(rdev, reg); |
| 447 | return r; |
| 448 | } |
| 449 | |
| 450 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 451 | { |
| 452 | struct radeon_device *rdev = info->dev->dev_private; |
| 453 | |
| 454 | rdev->mc_wreg(rdev, reg, val); |
| 455 | } |
| 456 | |
| 457 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 458 | { |
| 459 | struct radeon_device *rdev = info->dev->dev_private; |
| 460 | |
| 461 | WREG32(reg*4, val); |
| 462 | } |
| 463 | |
| 464 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
| 465 | { |
| 466 | struct radeon_device *rdev = info->dev->dev_private; |
| 467 | uint32_t r; |
| 468 | |
| 469 | r = RREG32(reg*4); |
| 470 | return r; |
| 471 | } |
| 472 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 473 | int radeon_atombios_init(struct radeon_device *rdev) |
| 474 | { |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 475 | struct card_info *atom_card_info = |
| 476 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
| 477 | |
| 478 | if (!atom_card_info) |
| 479 | return -ENOMEM; |
| 480 | |
| 481 | rdev->mode_info.atom_card_info = atom_card_info; |
| 482 | atom_card_info->dev = rdev->ddev; |
| 483 | atom_card_info->reg_read = cail_reg_read; |
| 484 | atom_card_info->reg_write = cail_reg_write; |
| 485 | atom_card_info->mc_read = cail_mc_read; |
| 486 | atom_card_info->mc_write = cail_mc_write; |
| 487 | atom_card_info->pll_read = cail_pll_read; |
| 488 | atom_card_info->pll_write = cail_pll_write; |
| 489 | |
| 490 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
Rafał Miłecki | c31ad97 | 2009-12-17 00:00:46 +0100 | [diff] [blame] | 491 | mutex_init(&rdev->mode_info.atom_context->mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 492 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
Dave Airlie | d904ef9 | 2009-11-17 06:29:46 +1000 | [diff] [blame] | 493 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | void radeon_atombios_fini(struct radeon_device *rdev) |
| 498 | { |
Jerome Glisse | 4a04a84 | 2009-12-09 17:39:16 +0100 | [diff] [blame] | 499 | if (rdev->mode_info.atom_context) { |
| 500 | kfree(rdev->mode_info.atom_context->scratch); |
| 501 | kfree(rdev->mode_info.atom_context); |
| 502 | } |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 503 | kfree(rdev->mode_info.atom_card_info); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | int radeon_combios_init(struct radeon_device *rdev) |
| 507 | { |
| 508 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | void radeon_combios_fini(struct radeon_device *rdev) |
| 513 | { |
| 514 | } |
| 515 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 516 | /* if we get transitioned to only one device, tak VGA back */ |
| 517 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
| 518 | { |
| 519 | struct radeon_device *rdev = cookie; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 520 | radeon_vga_set_state(rdev, state); |
| 521 | if (state) |
| 522 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 523 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 524 | else |
| 525 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 526 | } |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 527 | |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 528 | void radeon_agp_disable(struct radeon_device *rdev) |
| 529 | { |
| 530 | rdev->flags &= ~RADEON_IS_AGP; |
| 531 | if (rdev->family >= CHIP_R600) { |
| 532 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 533 | rdev->flags |= RADEON_IS_PCIE; |
| 534 | } else if (rdev->family >= CHIP_RV515 || |
| 535 | rdev->family == CHIP_RV380 || |
| 536 | rdev->family == CHIP_RV410 || |
| 537 | rdev->family == CHIP_R423) { |
| 538 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 539 | rdev->flags |= RADEON_IS_PCIE; |
| 540 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 541 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| 542 | } else { |
| 543 | DRM_INFO("Forcing AGP to PCI mode\n"); |
| 544 | rdev->flags |= RADEON_IS_PCI; |
| 545 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
| 546 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
| 547 | } |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 548 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 549 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 550 | |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 551 | void radeon_check_arguments(struct radeon_device *rdev) |
| 552 | { |
| 553 | /* vramlimit must be a power of two */ |
| 554 | switch (radeon_vram_limit) { |
| 555 | case 0: |
| 556 | case 4: |
| 557 | case 8: |
| 558 | case 16: |
| 559 | case 32: |
| 560 | case 64: |
| 561 | case 128: |
| 562 | case 256: |
| 563 | case 512: |
| 564 | case 1024: |
| 565 | case 2048: |
| 566 | case 4096: |
| 567 | break; |
| 568 | default: |
| 569 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
| 570 | radeon_vram_limit); |
| 571 | radeon_vram_limit = 0; |
| 572 | break; |
| 573 | } |
| 574 | radeon_vram_limit = radeon_vram_limit << 20; |
| 575 | /* gtt size must be power of two and greater or equal to 32M */ |
| 576 | switch (radeon_gart_size) { |
| 577 | case 4: |
| 578 | case 8: |
| 579 | case 16: |
| 580 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
| 581 | radeon_gart_size); |
| 582 | radeon_gart_size = 512; |
| 583 | break; |
| 584 | case 32: |
| 585 | case 64: |
| 586 | case 128: |
| 587 | case 256: |
| 588 | case 512: |
| 589 | case 1024: |
| 590 | case 2048: |
| 591 | case 4096: |
| 592 | break; |
| 593 | default: |
| 594 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
| 595 | radeon_gart_size); |
| 596 | radeon_gart_size = 512; |
| 597 | break; |
| 598 | } |
| 599 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 600 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
| 601 | switch (radeon_agpmode) { |
| 602 | case -1: |
| 603 | case 0: |
| 604 | case 1: |
| 605 | case 2: |
| 606 | case 4: |
| 607 | case 8: |
| 608 | break; |
| 609 | default: |
| 610 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
| 611 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
| 612 | radeon_agpmode = 0; |
| 613 | break; |
| 614 | } |
| 615 | } |
| 616 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 617 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 618 | { |
| 619 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 620 | struct radeon_device *rdev = dev->dev_private; |
| 621 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 622 | if (state == VGA_SWITCHEROO_ON) { |
| 623 | printk(KERN_INFO "radeon: switched on\n"); |
| 624 | /* don't suspend or resume card normally */ |
| 625 | rdev->powered_down = false; |
| 626 | radeon_resume_kms(dev); |
| 627 | } else { |
| 628 | printk(KERN_INFO "radeon: switched off\n"); |
| 629 | radeon_suspend_kms(dev, pmm); |
| 630 | /* don't suspend or resume card normally */ |
| 631 | rdev->powered_down = true; |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) |
| 636 | { |
| 637 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 638 | bool can_switch; |
| 639 | |
| 640 | spin_lock(&dev->count_lock); |
| 641 | can_switch = (dev->open_count == 0); |
| 642 | spin_unlock(&dev->count_lock); |
| 643 | return can_switch; |
| 644 | } |
| 645 | |
| 646 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 647 | int radeon_device_init(struct radeon_device *rdev, |
| 648 | struct drm_device *ddev, |
| 649 | struct pci_dev *pdev, |
| 650 | uint32_t flags) |
| 651 | { |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 652 | int r; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 653 | int dma_bits; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 654 | |
| 655 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
| 656 | rdev->shutdown = false; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 657 | rdev->dev = &pdev->dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 658 | rdev->ddev = ddev; |
| 659 | rdev->pdev = pdev; |
| 660 | rdev->flags = flags; |
| 661 | rdev->family = flags & RADEON_FAMILY_MASK; |
| 662 | rdev->is_atom_bios = false; |
| 663 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
| 664 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 665 | rdev->gpu_lockup = false; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 666 | rdev->accel_working = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 667 | /* mutex initialization are all done here so we |
| 668 | * can recall function without having locking issues */ |
| 669 | mutex_init(&rdev->cs_mutex); |
| 670 | mutex_init(&rdev->ib_pool.mutex); |
| 671 | mutex_init(&rdev->cp.mutex); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 672 | if (rdev->family >= CHIP_R600) |
| 673 | spin_lock_init(&rdev->ih.lock); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 674 | mutex_init(&rdev->gem.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 675 | rwlock_init(&rdev->fence_drv.lock); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 676 | INIT_LIST_HEAD(&rdev->gem.objects); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 677 | |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 678 | /* setup workqueue */ |
| 679 | rdev->wq = create_workqueue("radeon"); |
| 680 | if (rdev->wq == NULL) |
| 681 | return -ENOMEM; |
| 682 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 683 | /* Set asic functions */ |
| 684 | r = radeon_asic_init(rdev); |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 685 | if (r) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 686 | return r; |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 687 | radeon_check_arguments(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 688 | |
Jerome Glisse | 30256a3 | 2009-11-30 17:47:59 +0100 | [diff] [blame] | 689 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 690 | radeon_agp_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 691 | } |
| 692 | |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 693 | /* set DMA mask + need_dma32 flags. |
| 694 | * PCIE - can handle 40-bits. |
| 695 | * IGP - can handle 40-bits (in theory) |
| 696 | * AGP - generally dma32 is safest |
| 697 | * PCI - only dma32 |
| 698 | */ |
| 699 | rdev->need_dma32 = false; |
| 700 | if (rdev->flags & RADEON_IS_AGP) |
| 701 | rdev->need_dma32 = true; |
| 702 | if (rdev->flags & RADEON_IS_PCI) |
| 703 | rdev->need_dma32 = true; |
| 704 | |
| 705 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| 706 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 707 | if (r) { |
| 708 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
| 709 | } |
| 710 | |
| 711 | /* Registers mapping */ |
| 712 | /* TODO: block userspace mapping of io register */ |
| 713 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); |
| 714 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); |
| 715 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
| 716 | if (rdev->rmmio == NULL) { |
| 717 | return -ENOMEM; |
| 718 | } |
| 719 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| 720 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| 721 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 722 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
Dave Airlie | 93239ea | 2009-10-28 11:09:58 +1000 | [diff] [blame] | 723 | /* this will fail for cards that aren't VGA class devices, just |
| 724 | * ignore it */ |
| 725 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 726 | vga_switcheroo_register_client(rdev->pdev, |
| 727 | radeon_switcheroo_set_state, |
| 728 | radeon_switcheroo_can_switch); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 729 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 730 | r = radeon_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 731 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 732 | return r; |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 733 | |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 734 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
| 735 | /* Acceleration not working on AGP card try again |
| 736 | * with fallback to PCI or PCIE GART |
| 737 | */ |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 738 | radeon_gpu_reset(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 739 | radeon_fini(rdev); |
| 740 | radeon_agp_disable(rdev); |
| 741 | r = radeon_init(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 742 | if (r) |
| 743 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 744 | } |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 745 | if (radeon_testing) { |
| 746 | radeon_test_moves(rdev); |
| 747 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 748 | if (radeon_benchmarking) { |
| 749 | radeon_benchmark(rdev); |
| 750 | } |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 751 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 752 | } |
| 753 | |
| 754 | void radeon_device_fini(struct radeon_device *rdev) |
| 755 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 756 | DRM_INFO("radeon: finishing device.\n"); |
| 757 | rdev->shutdown = true; |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 758 | radeon_fini(rdev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 759 | destroy_workqueue(rdev->wq); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 760 | vga_switcheroo_unregister_client(rdev->pdev); |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 761 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 762 | iounmap(rdev->rmmio); |
| 763 | rdev->rmmio = NULL; |
| 764 | } |
| 765 | |
| 766 | |
| 767 | /* |
| 768 | * Suspend & resume. |
| 769 | */ |
| 770 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) |
| 771 | { |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 772 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | struct drm_crtc *crtc; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 774 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 775 | |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 776 | if (dev == NULL || dev->dev_private == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 777 | return -ENODEV; |
| 778 | } |
| 779 | if (state.event == PM_EVENT_PRETHAW) { |
| 780 | return 0; |
| 781 | } |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 782 | rdev = dev->dev_private; |
| 783 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 784 | if (rdev->powered_down) |
| 785 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 786 | /* unpin the front buffers */ |
| 787 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 788 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 789 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 790 | |
| 791 | if (rfb == NULL || rfb->obj == NULL) { |
| 792 | continue; |
| 793 | } |
| 794 | robj = rfb->obj->driver_private; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 795 | if (robj != rdev->fbdev_rbo) { |
| 796 | r = radeon_bo_reserve(robj, false); |
| 797 | if (unlikely(r == 0)) { |
| 798 | radeon_bo_unpin(robj); |
| 799 | radeon_bo_unreserve(robj); |
| 800 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 801 | } |
| 802 | } |
| 803 | /* evict vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 804 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 805 | /* wait for gpu to finish processing current batch */ |
| 806 | radeon_fence_wait_last(rdev); |
| 807 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 808 | radeon_save_bios_scratch_regs(rdev); |
| 809 | |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 810 | radeon_suspend(rdev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 811 | radeon_hpd_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 812 | /* evict remaining vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 813 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 814 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 815 | pci_save_state(dev->pdev); |
| 816 | if (state.event == PM_EVENT_SUSPEND) { |
| 817 | /* Shut down the device */ |
| 818 | pci_disable_device(dev->pdev); |
| 819 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 820 | } |
| 821 | acquire_console_sem(); |
| 822 | fb_set_suspend(rdev->fbdev_info, 1); |
| 823 | release_console_sem(); |
| 824 | return 0; |
| 825 | } |
| 826 | |
| 827 | int radeon_resume_kms(struct drm_device *dev) |
| 828 | { |
| 829 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 830 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame^] | 831 | if (rdev->powered_down) |
| 832 | return 0; |
| 833 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 834 | acquire_console_sem(); |
| 835 | pci_set_power_state(dev->pdev, PCI_D0); |
| 836 | pci_restore_state(dev->pdev); |
| 837 | if (pci_enable_device(dev->pdev)) { |
| 838 | release_console_sem(); |
| 839 | return -1; |
| 840 | } |
| 841 | pci_set_master(dev->pdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 842 | /* resume AGP if in use */ |
| 843 | radeon_agp_resume(rdev); |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 844 | radeon_resume(rdev); |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 845 | radeon_restore_bios_scratch_regs(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 846 | fb_set_suspend(rdev->fbdev_info, 0); |
| 847 | release_console_sem(); |
| 848 | |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 849 | /* reset hpd state */ |
| 850 | radeon_hpd_init(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 851 | /* blat the mode back in */ |
| 852 | drm_helper_resume_force_mode(dev); |
| 853 | return 0; |
| 854 | } |
| 855 | |
| 856 | |
| 857 | /* |
| 858 | * Debugfs |
| 859 | */ |
| 860 | struct radeon_debugfs { |
| 861 | struct drm_info_list *files; |
| 862 | unsigned num_files; |
| 863 | }; |
| 864 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; |
| 865 | static unsigned _radeon_debugfs_count = 0; |
| 866 | |
| 867 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 868 | struct drm_info_list *files, |
| 869 | unsigned nfiles) |
| 870 | { |
| 871 | unsigned i; |
| 872 | |
| 873 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 874 | if (_radeon_debugfs[i].files == files) { |
| 875 | /* Already registered */ |
| 876 | return 0; |
| 877 | } |
| 878 | } |
| 879 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { |
| 880 | DRM_ERROR("Reached maximum number of debugfs files.\n"); |
| 881 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); |
| 882 | return -EINVAL; |
| 883 | } |
| 884 | _radeon_debugfs[_radeon_debugfs_count].files = files; |
| 885 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; |
| 886 | _radeon_debugfs_count++; |
| 887 | #if defined(CONFIG_DEBUG_FS) |
| 888 | drm_debugfs_create_files(files, nfiles, |
| 889 | rdev->ddev->control->debugfs_root, |
| 890 | rdev->ddev->control); |
| 891 | drm_debugfs_create_files(files, nfiles, |
| 892 | rdev->ddev->primary->debugfs_root, |
| 893 | rdev->ddev->primary); |
| 894 | #endif |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | #if defined(CONFIG_DEBUG_FS) |
| 899 | int radeon_debugfs_init(struct drm_minor *minor) |
| 900 | { |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | void radeon_debugfs_cleanup(struct drm_minor *minor) |
| 905 | { |
| 906 | unsigned i; |
| 907 | |
| 908 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 909 | drm_debugfs_remove_files(_radeon_debugfs[i].files, |
| 910 | _radeon_debugfs[i].num_files, minor); |
| 911 | } |
| 912 | } |
| 913 | #endif |