Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/common/gic.c |
| 3 | * |
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Interrupt architecture for the GIC: |
| 11 | * |
| 12 | * o There is one Interrupt Distributor, which receives interrupts |
| 13 | * from system devices and sends them to the Interrupt Controllers. |
| 14 | * |
| 15 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 16 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 17 | * associated CPU. The base address of the CPU interface is usually |
| 18 | * aliased so that the same address points to different chips depending |
| 19 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 20 | * |
| 21 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 22 | * As such, the enable set/clear, pending set/clear and active bit |
| 23 | * registers are banked per-cpu for these sources. |
| 24 | */ |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 29 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 30 | #include <linux/io.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 31 | #include <linux/syscore_ops.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 32 | |
| 33 | #include <asm/irq.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 34 | #include <asm/mach/irq.h> |
| 35 | #include <asm/hardware/gic.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 36 | #include <asm/system.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 37 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 38 | static DEFINE_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 39 | |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 40 | /* Address of GIC 0 CPU interface */ |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 41 | void __iomem *gic_cpu_base_addr __read_mostly; |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 42 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 43 | struct gic_chip_data { |
| 44 | unsigned int irq_offset; |
| 45 | void __iomem *dist_base; |
| 46 | void __iomem *cpu_base; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 47 | unsigned int max_irq; |
| 48 | #ifdef CONFIG_PM |
| 49 | unsigned int wakeup_irqs[32]; |
| 50 | unsigned int enabled_irqs[32]; |
| 51 | #endif |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 52 | }; |
| 53 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 54 | /* |
| 55 | * Supported arch specific GIC irq extension. |
| 56 | * Default make them NULL. |
| 57 | */ |
| 58 | struct irq_chip gic_arch_extn = { |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 59 | .irq_eoi = NULL, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 60 | .irq_mask = NULL, |
| 61 | .irq_unmask = NULL, |
| 62 | .irq_retrigger = NULL, |
| 63 | .irq_set_type = NULL, |
| 64 | .irq_set_wake = NULL, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 65 | .irq_disable = NULL, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 66 | }; |
| 67 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 68 | #ifndef MAX_GIC_NR |
| 69 | #define MAX_GIC_NR 1 |
| 70 | #endif |
| 71 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 72 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 73 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 74 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 75 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 76 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 77 | return gic_data->dist_base; |
| 78 | } |
| 79 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 80 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 81 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 82 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 83 | return gic_data->cpu_base; |
| 84 | } |
| 85 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 86 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 87 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 88 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
| 89 | return d->irq - gic_data->irq_offset; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 90 | } |
| 91 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 92 | /* |
| 93 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 94 | */ |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 95 | static void gic_mask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 96 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 97 | u32 mask = 1 << (d->irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 98 | |
| 99 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 100 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 101 | if (gic_arch_extn.irq_mask) |
| 102 | gic_arch_extn.irq_mask(d); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 103 | spin_unlock(&irq_controller_lock); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 104 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 105 | } |
| 106 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 107 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 108 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 109 | u32 mask = 1 << (d->irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 110 | |
| 111 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 112 | if (gic_arch_extn.irq_unmask) |
| 113 | gic_arch_extn.irq_unmask(d); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 114 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 115 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 116 | } |
| 117 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 118 | static void gic_disable_irq(struct irq_data *d) |
| 119 | { |
| 120 | if (gic_arch_extn.irq_disable) |
| 121 | gic_arch_extn.irq_disable(d); |
| 122 | } |
| 123 | |
| 124 | #ifdef CONFIG_PM |
| 125 | static int gic_suspend_one(struct gic_chip_data *gic) |
| 126 | { |
| 127 | unsigned int i; |
| 128 | void __iomem *base = gic->dist_base; |
| 129 | |
| 130 | for (i = 0; i * 32 < gic->max_irq; i++) { |
| 131 | gic->enabled_irqs[i] |
| 132 | = readl_relaxed(base + GIC_DIST_ENABLE_SET + i * 4); |
| 133 | /* disable all of them */ |
| 134 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4); |
| 135 | /* enable the wakeup set */ |
| 136 | writel_relaxed(gic->wakeup_irqs[i], |
| 137 | base + GIC_DIST_ENABLE_SET + i * 4); |
| 138 | } |
| 139 | mb(); |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | static int gic_suspend(void) |
| 144 | { |
| 145 | int i; |
| 146 | for (i = 0; i < MAX_GIC_NR; i++) |
| 147 | gic_suspend_one(&gic_data[i]); |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | extern int msm_show_resume_irq_mask; |
| 152 | |
| 153 | static void gic_show_resume_irq(struct gic_chip_data *gic) |
| 154 | { |
| 155 | unsigned int i; |
| 156 | u32 enabled; |
| 157 | unsigned long pending[32]; |
| 158 | void __iomem *base = gic->dist_base; |
| 159 | |
| 160 | if (!msm_show_resume_irq_mask) |
| 161 | return; |
| 162 | |
| 163 | spin_lock(&irq_controller_lock); |
| 164 | for (i = 0; i * 32 < gic->max_irq; i++) { |
| 165 | enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4); |
| 166 | pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4); |
| 167 | pending[i] &= enabled; |
| 168 | } |
| 169 | spin_unlock(&irq_controller_lock); |
| 170 | |
| 171 | for (i = find_first_bit(pending, gic->max_irq); |
| 172 | i < gic->max_irq; |
| 173 | i = find_next_bit(pending, gic->max_irq, i+1)) { |
| 174 | pr_warning("%s: %d triggered", __func__, |
| 175 | i + gic->irq_offset); |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | static void gic_resume_one(struct gic_chip_data *gic) |
| 180 | { |
| 181 | unsigned int i; |
| 182 | void __iomem *base = gic->dist_base; |
| 183 | |
| 184 | gic_show_resume_irq(gic); |
| 185 | for (i = 0; i * 32 < gic->max_irq; i++) { |
| 186 | /* disable all of them */ |
| 187 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4); |
| 188 | /* enable the enabled set */ |
| 189 | writel_relaxed(gic->enabled_irqs[i], |
| 190 | base + GIC_DIST_ENABLE_SET + i * 4); |
| 191 | } |
| 192 | mb(); |
| 193 | } |
| 194 | |
| 195 | static void gic_resume(void) |
| 196 | { |
| 197 | int i; |
| 198 | for (i = 0; i < MAX_GIC_NR; i++) |
| 199 | gic_resume_one(&gic_data[i]); |
| 200 | } |
| 201 | |
| 202 | static struct syscore_ops gic_syscore_ops = { |
| 203 | .suspend = gic_suspend, |
| 204 | .resume = gic_resume, |
| 205 | }; |
| 206 | |
| 207 | static int __init gic_init_sys(void) |
| 208 | { |
| 209 | register_syscore_ops(&gic_syscore_ops); |
| 210 | return 0; |
| 211 | } |
| 212 | arch_initcall(gic_init_sys); |
| 213 | |
| 214 | #endif |
| 215 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 216 | static void gic_eoi_irq(struct irq_data *d) |
| 217 | { |
| 218 | if (gic_arch_extn.irq_eoi) { |
| 219 | spin_lock(&irq_controller_lock); |
| 220 | gic_arch_extn.irq_eoi(d); |
| 221 | spin_unlock(&irq_controller_lock); |
| 222 | } |
| 223 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 224 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 225 | } |
| 226 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 227 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 228 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 229 | void __iomem *base = gic_dist_base(d); |
| 230 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 231 | u32 enablemask = 1 << (gicirq % 32); |
| 232 | u32 enableoff = (gicirq / 32) * 4; |
| 233 | u32 confmask = 0x2 << ((gicirq % 16) * 2); |
| 234 | u32 confoff = (gicirq / 16) * 4; |
| 235 | bool enabled = false; |
| 236 | u32 val; |
| 237 | |
| 238 | /* Interrupt configuration for SGIs can't be changed */ |
| 239 | if (gicirq < 16) |
| 240 | return -EINVAL; |
| 241 | |
| 242 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
| 243 | return -EINVAL; |
| 244 | |
| 245 | spin_lock(&irq_controller_lock); |
| 246 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 247 | if (gic_arch_extn.irq_set_type) |
| 248 | gic_arch_extn.irq_set_type(d, type); |
| 249 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 250 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 251 | if (type == IRQ_TYPE_LEVEL_HIGH) |
| 252 | val &= ~confmask; |
| 253 | else if (type == IRQ_TYPE_EDGE_RISING) |
| 254 | val |= confmask; |
| 255 | |
| 256 | /* |
| 257 | * As recommended by the spec, disable the interrupt before changing |
| 258 | * the configuration |
| 259 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 260 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
| 261 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 262 | enabled = true; |
| 263 | } |
| 264 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 265 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 266 | |
| 267 | if (enabled) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 268 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 269 | |
| 270 | spin_unlock(&irq_controller_lock); |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 275 | static int gic_retrigger(struct irq_data *d) |
| 276 | { |
| 277 | if (gic_arch_extn.irq_retrigger) |
| 278 | return gic_arch_extn.irq_retrigger(d); |
| 279 | |
| 280 | return -ENXIO; |
| 281 | } |
| 282 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 283 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 284 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 285 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 286 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 287 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
| 288 | unsigned int shift = (d->irq % 4) * 8; |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 289 | unsigned int cpu = cpumask_first(mask_val); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 290 | u32 val, mask, bit; |
| 291 | |
| 292 | if (cpu >= 8) |
| 293 | return -EINVAL; |
| 294 | |
| 295 | mask = 0xff << shift; |
| 296 | bit = 1 << (cpu + shift); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 297 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 298 | spin_lock(&irq_controller_lock); |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 299 | d->node = cpu; |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 300 | val = readl_relaxed(reg) & ~mask; |
| 301 | writel_relaxed(val | bit, reg); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 302 | spin_unlock(&irq_controller_lock); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 303 | |
| 304 | return 0; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 305 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 306 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 307 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 308 | #ifdef CONFIG_PM |
| 309 | static int gic_set_wake(struct irq_data *d, unsigned int on) |
| 310 | { |
| 311 | int ret = -ENXIO; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 312 | unsigned int reg_offset, bit_offset; |
| 313 | unsigned int gicirq = gic_irq(d); |
| 314 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
| 315 | |
| 316 | /* per-cpu interrupts cannot be wakeup interrupts */ |
| 317 | WARN_ON(gicirq < 32); |
| 318 | |
| 319 | reg_offset = gicirq / 32; |
| 320 | bit_offset = gicirq % 32; |
| 321 | |
| 322 | if (on) |
| 323 | gic_data->wakeup_irqs[reg_offset] |= 1 << bit_offset; |
| 324 | else |
| 325 | gic_data->wakeup_irqs[reg_offset] &= ~(1 << bit_offset); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 326 | |
| 327 | if (gic_arch_extn.irq_set_wake) |
| 328 | ret = gic_arch_extn.irq_set_wake(d, on); |
| 329 | |
| 330 | return ret; |
| 331 | } |
| 332 | |
| 333 | #else |
Rohit Vaswani | 550aa1a | 2011-10-06 21:15:37 -0700 | [diff] [blame] | 334 | static int gic_set_wake(struct irq_data *d, unsigned int on) |
| 335 | { |
| 336 | return 0; |
| 337 | } |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 338 | #endif |
| 339 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 340 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 341 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 342 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
| 343 | struct irq_chip *chip = irq_get_chip(irq); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 344 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 345 | unsigned long status; |
| 346 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 347 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 348 | |
| 349 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 350 | status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 351 | spin_unlock(&irq_controller_lock); |
| 352 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 353 | gic_irq = (status & 0x3ff); |
| 354 | if (gic_irq == 1023) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 355 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 356 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 357 | cascade_irq = gic_irq + chip_data->irq_offset; |
| 358 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
| 359 | do_bad_IRQ(cascade_irq, desc); |
| 360 | else |
| 361 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 362 | |
| 363 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 364 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 365 | } |
| 366 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 367 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 368 | .name = "GIC", |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 369 | .irq_mask = gic_mask_irq, |
| 370 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 371 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 372 | .irq_set_type = gic_set_type, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 373 | .irq_retrigger = gic_retrigger, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 374 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 375 | .irq_set_affinity = gic_set_affinity, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 376 | #endif |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 377 | .irq_disable = gic_disable_irq, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 378 | .irq_set_wake = gic_set_wake, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 379 | }; |
| 380 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 381 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 382 | { |
| 383 | if (gic_nr >= MAX_GIC_NR) |
| 384 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 385 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 386 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 387 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 388 | } |
| 389 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 390 | static void __init gic_dist_init(struct gic_chip_data *gic, |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 391 | unsigned int irq_start) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 392 | { |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 393 | unsigned int gic_irqs, irq_limit, i; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 394 | void __iomem *base = gic->dist_base; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 395 | u32 cpumask = 1 << smp_processor_id(); |
| 396 | |
| 397 | cpumask |= cpumask << 8; |
| 398 | cpumask |= cpumask << 16; |
| 399 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 400 | writel_relaxed(0, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 401 | |
| 402 | /* |
| 403 | * Find out how many interrupts are supported. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 404 | * The GIC only supports up to 1020 interrupt sources. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 405 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 406 | gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 407 | gic_irqs = (gic_irqs + 1) * 32; |
| 408 | if (gic_irqs > 1020) |
| 409 | gic_irqs = 1020; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 410 | |
| 411 | /* |
| 412 | * Set all global interrupts to be level triggered, active low. |
| 413 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 414 | for (i = 32; i < gic_irqs; i += 16) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 415 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 416 | |
| 417 | /* |
| 418 | * Set all global interrupts to this CPU only. |
| 419 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 420 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 421 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 422 | |
| 423 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 424 | * Set priority on all global interrupts. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 425 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 426 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 427 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 428 | |
| 429 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 430 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 431 | * as these enables are banked registers. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 432 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 433 | for (i = 32; i < gic_irqs; i += 32) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 434 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 435 | |
| 436 | /* |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 437 | * Limit number of interrupts registered to the platform maximum |
| 438 | */ |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 439 | irq_limit = gic->irq_offset + gic_irqs; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 440 | if (WARN_ON(irq_limit > NR_IRQS)) |
| 441 | irq_limit = NR_IRQS; |
| 442 | |
| 443 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 444 | * Setup the Linux IRQ subsystem. |
| 445 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 446 | for (i = irq_start; i < irq_limit; i++) { |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 447 | irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); |
Thomas Gleixner | 9323f261 | 2011-03-24 13:29:39 +0100 | [diff] [blame] | 448 | irq_set_chip_data(i, gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 449 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 450 | } |
| 451 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 452 | gic->max_irq = gic_irqs; |
| 453 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 454 | writel_relaxed(1, base + GIC_DIST_CTRL); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 455 | mb(); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 456 | } |
| 457 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 458 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 459 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 460 | void __iomem *dist_base = gic->dist_base; |
| 461 | void __iomem *base = gic->cpu_base; |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 462 | int i; |
| 463 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 464 | /* |
| 465 | * Deal with the banked PPI and SGI interrupts - disable all |
| 466 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| 467 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 468 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
| 469 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 470 | |
| 471 | /* |
| 472 | * Set priority on PPI and SGI interrupts |
| 473 | */ |
| 474 | for (i = 0; i < 32; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 475 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 476 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 477 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
| 478 | writel_relaxed(1, base + GIC_CPU_CTRL); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 479 | mb(); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 480 | } |
| 481 | |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 482 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, |
| 483 | void __iomem *dist_base, void __iomem *cpu_base) |
| 484 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 485 | struct gic_chip_data *gic; |
| 486 | |
| 487 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 488 | |
| 489 | gic = &gic_data[gic_nr]; |
| 490 | gic->dist_base = dist_base; |
| 491 | gic->cpu_base = cpu_base; |
| 492 | gic->irq_offset = (irq_start - 1) & ~31; |
| 493 | |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 494 | if (gic_nr == 0) |
| 495 | gic_cpu_base_addr = cpu_base; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 496 | |
| 497 | gic_dist_init(gic, irq_start); |
| 498 | gic_cpu_init(gic); |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 499 | } |
| 500 | |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 501 | void __cpuinit gic_secondary_init(unsigned int gic_nr) |
| 502 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 503 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 504 | |
| 505 | gic_cpu_init(&gic_data[gic_nr]); |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 506 | } |
| 507 | |
Russell King | ac61d14 | 2010-12-06 10:38:14 +0000 | [diff] [blame] | 508 | void __cpuinit gic_enable_ppi(unsigned int irq) |
| 509 | { |
| 510 | unsigned long flags; |
| 511 | |
| 512 | local_irq_save(flags); |
Thomas Gleixner | fdea77b | 2011-03-24 12:48:54 +0100 | [diff] [blame] | 513 | irq_set_status_flags(irq, IRQ_NOPROBE); |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 514 | gic_unmask_irq(irq_get_irq_data(irq)); |
Russell King | ac61d14 | 2010-12-06 10:38:14 +0000 | [diff] [blame] | 515 | local_irq_restore(flags); |
| 516 | } |
| 517 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 518 | #ifdef CONFIG_SMP |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 519 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 520 | { |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 521 | unsigned long map = *cpus_addr(*mask); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 522 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 523 | /* |
| 524 | * Ensure that stores to Normal memory are visible to the |
| 525 | * other CPUs before issuing the IPI. |
| 526 | */ |
| 527 | dsb(); |
| 528 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 529 | /* this always happens on GIC0 */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 530 | writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 531 | mb(); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 532 | } |
| 533 | #endif |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 534 | |
| 535 | /* before calling this function the interrupts should be disabled |
| 536 | * and the irq must be disabled at gic to avoid spurious interrupts */ |
| 537 | bool gic_is_spi_pending(unsigned int irq) |
| 538 | { |
| 539 | struct irq_data *d = irq_get_irq_data(irq); |
| 540 | struct gic_chip_data *gic_data = &gic_data[0]; |
| 541 | u32 mask, val; |
| 542 | |
| 543 | WARN_ON(!irqs_disabled()); |
| 544 | spin_lock(&irq_controller_lock); |
| 545 | mask = 1 << (gic_irq(d) % 32); |
| 546 | val = readl(gic_dist_base(d) + |
| 547 | GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
| 548 | /* warn if the interrupt is enabled */ |
| 549 | WARN_ON(val & mask); |
| 550 | val = readl(gic_dist_base(d) + |
| 551 | GIC_DIST_PENDING_SET + (gic_irq(d) / 32) * 4); |
| 552 | spin_unlock(&irq_controller_lock); |
| 553 | return (bool) (val & mask); |
| 554 | } |
| 555 | |
| 556 | /* before calling this function the interrupts should be disabled |
| 557 | * and the irq must be disabled at gic to avoid spurious interrupts */ |
| 558 | void gic_clear_spi_pending(unsigned int irq) |
| 559 | { |
| 560 | struct gic_chip_data *gic_data = &gic_data[0]; |
| 561 | struct irq_data *d = irq_get_irq_data(irq); |
| 562 | |
| 563 | u32 mask, val; |
| 564 | WARN_ON(!irqs_disabled()); |
| 565 | spin_lock(&irq_controller_lock); |
| 566 | mask = 1 << (gic_irq(d) % 32); |
| 567 | val = readl(gic_dist_base(d) + |
| 568 | GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
| 569 | /* warn if the interrupt is enabled */ |
| 570 | WARN_ON(val & mask); |
| 571 | writel(mask, gic_dist_base(d) + |
| 572 | GIC_DIST_PENDING_CLEAR + (gic_irq(d) / 32) * 4); |
| 573 | spin_unlock(&irq_controller_lock); |
| 574 | } |