blob: 786f4fa9318671907993f96bdf5a9d1f21fad4c1 [file] [log] [blame]
Russell Kingf27ecac2005-08-18 21:31:00 +01001/*
2 * linux/arch/arm/common/gic.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Interrupt architecture for the GIC:
11 *
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
14 *
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010017 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
Russell Kingf27ecac2005-08-18 21:31:00 +010020 *
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
24 */
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/smp.h>
Catalin Marinasdcb86e82005-08-31 21:45:14 +010029#include <linux/cpumask.h>
Russell Kingfced80c2008-09-06 12:10:45 +010030#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031#include <linux/syscore_ops.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010032
33#include <asm/irq.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010034#include <asm/mach/irq.h>
35#include <asm/hardware/gic.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#include <asm/system.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010037
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010038static DEFINE_SPINLOCK(irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +010039
Russell Kingff2e27a2010-12-04 16:13:29 +000040/* Address of GIC 0 CPU interface */
Russell Kingbef8f9e2010-12-04 16:50:58 +000041void __iomem *gic_cpu_base_addr __read_mostly;
Russell Kingff2e27a2010-12-04 16:13:29 +000042
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010043struct gic_chip_data {
44 unsigned int irq_offset;
45 void __iomem *dist_base;
46 void __iomem *cpu_base;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047 unsigned int max_irq;
48#ifdef CONFIG_PM
49 unsigned int wakeup_irqs[32];
50 unsigned int enabled_irqs[32];
51#endif
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010052};
53
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +010054/*
55 * Supported arch specific GIC irq extension.
56 * Default make them NULL.
57 */
58struct irq_chip gic_arch_extn = {
Will Deacon1a017532011-02-09 12:01:12 +000059 .irq_eoi = NULL,
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +010060 .irq_mask = NULL,
61 .irq_unmask = NULL,
62 .irq_retrigger = NULL,
63 .irq_set_type = NULL,
64 .irq_set_wake = NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070065 .irq_disable = NULL,
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +010066};
67
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010068#ifndef MAX_GIC_NR
69#define MAX_GIC_NR 1
70#endif
71
Russell Kingbef8f9e2010-12-04 16:50:58 +000072static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010073
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010074static inline void __iomem *gic_dist_base(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010075{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010076 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010077 return gic_data->dist_base;
78}
79
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010080static inline void __iomem *gic_cpu_base(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010081{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010082 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010083 return gic_data->cpu_base;
84}
85
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010086static inline unsigned int gic_irq(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010087{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010088 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
89 return d->irq - gic_data->irq_offset;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010090}
91
Russell Kingf27ecac2005-08-18 21:31:00 +010092/*
93 * Routines to acknowledge, disable and enable interrupts
Russell Kingf27ecac2005-08-18 21:31:00 +010094 */
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010095static void gic_mask_irq(struct irq_data *d)
Russell Kingf27ecac2005-08-18 21:31:00 +010096{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +010097 u32 mask = 1 << (d->irq % 32);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010098
99 spin_lock(&irq_controller_lock);
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530100 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100101 if (gic_arch_extn.irq_mask)
102 gic_arch_extn.irq_mask(d);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100103 spin_unlock(&irq_controller_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104
Russell Kingf27ecac2005-08-18 21:31:00 +0100105}
106
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100107static void gic_unmask_irq(struct irq_data *d)
Russell Kingf27ecac2005-08-18 21:31:00 +0100108{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100109 u32 mask = 1 << (d->irq % 32);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100110
111 spin_lock(&irq_controller_lock);
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100112 if (gic_arch_extn.irq_unmask)
113 gic_arch_extn.irq_unmask(d);
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530114 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100115 spin_unlock(&irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +0100116}
117
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700118static void gic_disable_irq(struct irq_data *d)
119{
120 if (gic_arch_extn.irq_disable)
121 gic_arch_extn.irq_disable(d);
122}
123
124#ifdef CONFIG_PM
125static int gic_suspend_one(struct gic_chip_data *gic)
126{
127 unsigned int i;
128 void __iomem *base = gic->dist_base;
129
130 for (i = 0; i * 32 < gic->max_irq; i++) {
131 gic->enabled_irqs[i]
132 = readl_relaxed(base + GIC_DIST_ENABLE_SET + i * 4);
133 /* disable all of them */
134 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4);
135 /* enable the wakeup set */
136 writel_relaxed(gic->wakeup_irqs[i],
137 base + GIC_DIST_ENABLE_SET + i * 4);
138 }
139 mb();
140 return 0;
141}
142
143static int gic_suspend(void)
144{
145 int i;
146 for (i = 0; i < MAX_GIC_NR; i++)
147 gic_suspend_one(&gic_data[i]);
148 return 0;
149}
150
151extern int msm_show_resume_irq_mask;
152
153static void gic_show_resume_irq(struct gic_chip_data *gic)
154{
155 unsigned int i;
156 u32 enabled;
157 unsigned long pending[32];
158 void __iomem *base = gic->dist_base;
159
160 if (!msm_show_resume_irq_mask)
161 return;
162
163 spin_lock(&irq_controller_lock);
164 for (i = 0; i * 32 < gic->max_irq; i++) {
165 enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4);
166 pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4);
167 pending[i] &= enabled;
168 }
169 spin_unlock(&irq_controller_lock);
170
171 for (i = find_first_bit(pending, gic->max_irq);
172 i < gic->max_irq;
173 i = find_next_bit(pending, gic->max_irq, i+1)) {
174 pr_warning("%s: %d triggered", __func__,
175 i + gic->irq_offset);
176 }
177}
178
179static void gic_resume_one(struct gic_chip_data *gic)
180{
181 unsigned int i;
182 void __iomem *base = gic->dist_base;
183
184 gic_show_resume_irq(gic);
185 for (i = 0; i * 32 < gic->max_irq; i++) {
186 /* disable all of them */
187 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4);
188 /* enable the enabled set */
189 writel_relaxed(gic->enabled_irqs[i],
190 base + GIC_DIST_ENABLE_SET + i * 4);
191 }
192 mb();
193}
194
195static void gic_resume(void)
196{
197 int i;
198 for (i = 0; i < MAX_GIC_NR; i++)
199 gic_resume_one(&gic_data[i]);
200}
201
202static struct syscore_ops gic_syscore_ops = {
203 .suspend = gic_suspend,
204 .resume = gic_resume,
205};
206
207static int __init gic_init_sys(void)
208{
209 register_syscore_ops(&gic_syscore_ops);
210 return 0;
211}
212arch_initcall(gic_init_sys);
213
214#endif
215
Will Deacon1a017532011-02-09 12:01:12 +0000216static void gic_eoi_irq(struct irq_data *d)
217{
218 if (gic_arch_extn.irq_eoi) {
219 spin_lock(&irq_controller_lock);
220 gic_arch_extn.irq_eoi(d);
221 spin_unlock(&irq_controller_lock);
222 }
223
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530224 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
Will Deacon1a017532011-02-09 12:01:12 +0000225}
226
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100227static int gic_set_type(struct irq_data *d, unsigned int type)
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100228{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100229 void __iomem *base = gic_dist_base(d);
230 unsigned int gicirq = gic_irq(d);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100231 u32 enablemask = 1 << (gicirq % 32);
232 u32 enableoff = (gicirq / 32) * 4;
233 u32 confmask = 0x2 << ((gicirq % 16) * 2);
234 u32 confoff = (gicirq / 16) * 4;
235 bool enabled = false;
236 u32 val;
237
238 /* Interrupt configuration for SGIs can't be changed */
239 if (gicirq < 16)
240 return -EINVAL;
241
242 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
243 return -EINVAL;
244
245 spin_lock(&irq_controller_lock);
246
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100247 if (gic_arch_extn.irq_set_type)
248 gic_arch_extn.irq_set_type(d, type);
249
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530250 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100251 if (type == IRQ_TYPE_LEVEL_HIGH)
252 val &= ~confmask;
253 else if (type == IRQ_TYPE_EDGE_RISING)
254 val |= confmask;
255
256 /*
257 * As recommended by the spec, disable the interrupt before changing
258 * the configuration
259 */
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530260 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
261 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100262 enabled = true;
263 }
264
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530265 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100266
267 if (enabled)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530268 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100269
270 spin_unlock(&irq_controller_lock);
271
272 return 0;
273}
274
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100275static int gic_retrigger(struct irq_data *d)
276{
277 if (gic_arch_extn.irq_retrigger)
278 return gic_arch_extn.irq_retrigger(d);
279
280 return -ENXIO;
281}
282
Catalin Marinasa06f5462005-09-30 16:07:05 +0100283#ifdef CONFIG_SMP
Russell Kingc1917892011-01-23 12:12:01 +0000284static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
285 bool force)
Russell Kingf27ecac2005-08-18 21:31:00 +0100286{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100287 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
288 unsigned int shift = (d->irq % 4) * 8;
Rusty Russell0de26522008-12-13 21:20:26 +1030289 unsigned int cpu = cpumask_first(mask_val);
Russell Kingc1917892011-01-23 12:12:01 +0000290 u32 val, mask, bit;
291
292 if (cpu >= 8)
293 return -EINVAL;
294
295 mask = 0xff << shift;
296 bit = 1 << (cpu + shift);
Russell Kingf27ecac2005-08-18 21:31:00 +0100297
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100298 spin_lock(&irq_controller_lock);
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100299 d->node = cpu;
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530300 val = readl_relaxed(reg) & ~mask;
301 writel_relaxed(val | bit, reg);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100302 spin_unlock(&irq_controller_lock);
Yinghai Lud5dedd42009-04-27 17:59:21 -0700303
304 return 0;
Russell Kingf27ecac2005-08-18 21:31:00 +0100305}
Catalin Marinasa06f5462005-09-30 16:07:05 +0100306#endif
Russell Kingf27ecac2005-08-18 21:31:00 +0100307
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100308#ifdef CONFIG_PM
309static int gic_set_wake(struct irq_data *d, unsigned int on)
310{
311 int ret = -ENXIO;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700312 unsigned int reg_offset, bit_offset;
313 unsigned int gicirq = gic_irq(d);
314 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
315
316 /* per-cpu interrupts cannot be wakeup interrupts */
317 WARN_ON(gicirq < 32);
318
319 reg_offset = gicirq / 32;
320 bit_offset = gicirq % 32;
321
322 if (on)
323 gic_data->wakeup_irqs[reg_offset] |= 1 << bit_offset;
324 else
325 gic_data->wakeup_irqs[reg_offset] &= ~(1 << bit_offset);
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100326
327 if (gic_arch_extn.irq_set_wake)
328 ret = gic_arch_extn.irq_set_wake(d, on);
329
330 return ret;
331}
332
333#else
Rohit Vaswani550aa1a2011-10-06 21:15:37 -0700334static int gic_set_wake(struct irq_data *d, unsigned int on)
335{
336 return 0;
337}
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100338#endif
339
Russell King0f347bb2007-05-17 10:11:34 +0100340static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100341{
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100342 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
343 struct irq_chip *chip = irq_get_chip(irq);
Russell King0f347bb2007-05-17 10:11:34 +0100344 unsigned int cascade_irq, gic_irq;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100345 unsigned long status;
346
Will Deacon1a017532011-02-09 12:01:12 +0000347 chained_irq_enter(chip, desc);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100348
349 spin_lock(&irq_controller_lock);
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530350 status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100351 spin_unlock(&irq_controller_lock);
352
Russell King0f347bb2007-05-17 10:11:34 +0100353 gic_irq = (status & 0x3ff);
354 if (gic_irq == 1023)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100355 goto out;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100356
Russell King0f347bb2007-05-17 10:11:34 +0100357 cascade_irq = gic_irq + chip_data->irq_offset;
358 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
359 do_bad_IRQ(cascade_irq, desc);
360 else
361 generic_handle_irq(cascade_irq);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100362
363 out:
Will Deacon1a017532011-02-09 12:01:12 +0000364 chained_irq_exit(chip, desc);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100365}
366
David Brownell38c677c2006-08-01 22:26:25 +0100367static struct irq_chip gic_chip = {
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100368 .name = "GIC",
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100369 .irq_mask = gic_mask_irq,
370 .irq_unmask = gic_unmask_irq,
Will Deacon1a017532011-02-09 12:01:12 +0000371 .irq_eoi = gic_eoi_irq,
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100372 .irq_set_type = gic_set_type,
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100373 .irq_retrigger = gic_retrigger,
Russell Kingf27ecac2005-08-18 21:31:00 +0100374#ifdef CONFIG_SMP
Russell Kingc1917892011-01-23 12:12:01 +0000375 .irq_set_affinity = gic_set_affinity,
Russell Kingf27ecac2005-08-18 21:31:00 +0100376#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700377 .irq_disable = gic_disable_irq,
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100378 .irq_set_wake = gic_set_wake,
Russell Kingf27ecac2005-08-18 21:31:00 +0100379};
380
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100381void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
382{
383 if (gic_nr >= MAX_GIC_NR)
384 BUG();
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100385 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100386 BUG();
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100387 irq_set_chained_handler(irq, gic_handle_cascade_irq);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100388}
389
Russell Kingbef8f9e2010-12-04 16:50:58 +0000390static void __init gic_dist_init(struct gic_chip_data *gic,
Russell Kingb580b892010-12-04 15:55:14 +0000391 unsigned int irq_start)
Russell Kingf27ecac2005-08-18 21:31:00 +0100392{
Pawel Molle6afec92010-11-26 13:45:43 +0100393 unsigned int gic_irqs, irq_limit, i;
Russell Kingbef8f9e2010-12-04 16:50:58 +0000394 void __iomem *base = gic->dist_base;
Russell Kingf27ecac2005-08-18 21:31:00 +0100395 u32 cpumask = 1 << smp_processor_id();
396
397 cpumask |= cpumask << 8;
398 cpumask |= cpumask << 16;
399
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530400 writel_relaxed(0, base + GIC_DIST_CTRL);
Russell Kingf27ecac2005-08-18 21:31:00 +0100401
402 /*
403 * Find out how many interrupts are supported.
Russell Kingf27ecac2005-08-18 21:31:00 +0100404 * The GIC only supports up to 1020 interrupt sources.
Russell Kingf27ecac2005-08-18 21:31:00 +0100405 */
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530406 gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
Pawel Molle6afec92010-11-26 13:45:43 +0100407 gic_irqs = (gic_irqs + 1) * 32;
408 if (gic_irqs > 1020)
409 gic_irqs = 1020;
Russell Kingf27ecac2005-08-18 21:31:00 +0100410
411 /*
412 * Set all global interrupts to be level triggered, active low.
413 */
Pawel Molle6afec92010-11-26 13:45:43 +0100414 for (i = 32; i < gic_irqs; i += 16)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530415 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
Russell Kingf27ecac2005-08-18 21:31:00 +0100416
417 /*
418 * Set all global interrupts to this CPU only.
419 */
Pawel Molle6afec92010-11-26 13:45:43 +0100420 for (i = 32; i < gic_irqs; i += 4)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530421 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
Russell Kingf27ecac2005-08-18 21:31:00 +0100422
423 /*
Russell King9395f6e2010-11-11 23:10:30 +0000424 * Set priority on all global interrupts.
Russell Kingf27ecac2005-08-18 21:31:00 +0100425 */
Pawel Molle6afec92010-11-26 13:45:43 +0100426 for (i = 32; i < gic_irqs; i += 4)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530427 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
Russell Kingf27ecac2005-08-18 21:31:00 +0100428
429 /*
Russell King9395f6e2010-11-11 23:10:30 +0000430 * Disable all interrupts. Leave the PPI and SGIs alone
431 * as these enables are banked registers.
Russell Kingf27ecac2005-08-18 21:31:00 +0100432 */
Pawel Molle6afec92010-11-26 13:45:43 +0100433 for (i = 32; i < gic_irqs; i += 32)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530434 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
Russell Kingf27ecac2005-08-18 21:31:00 +0100435
436 /*
Pawel Molle6afec92010-11-26 13:45:43 +0100437 * Limit number of interrupts registered to the platform maximum
438 */
Russell Kingbef8f9e2010-12-04 16:50:58 +0000439 irq_limit = gic->irq_offset + gic_irqs;
Pawel Molle6afec92010-11-26 13:45:43 +0100440 if (WARN_ON(irq_limit > NR_IRQS))
441 irq_limit = NR_IRQS;
442
443 /*
Russell Kingf27ecac2005-08-18 21:31:00 +0100444 * Setup the Linux IRQ subsystem.
445 */
Pawel Molle6afec92010-11-26 13:45:43 +0100446 for (i = irq_start; i < irq_limit; i++) {
Will Deacon1a017532011-02-09 12:01:12 +0000447 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
Thomas Gleixner9323f2612011-03-24 13:29:39 +0100448 irq_set_chip_data(i, gic);
Russell Kingf27ecac2005-08-18 21:31:00 +0100449 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
450 }
451
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700452 gic->max_irq = gic_irqs;
453
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530454 writel_relaxed(1, base + GIC_DIST_CTRL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700455 mb();
Russell Kingf27ecac2005-08-18 21:31:00 +0100456}
457
Russell Kingbef8f9e2010-12-04 16:50:58 +0000458static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
Russell Kingf27ecac2005-08-18 21:31:00 +0100459{
Russell Kingbef8f9e2010-12-04 16:50:58 +0000460 void __iomem *dist_base = gic->dist_base;
461 void __iomem *base = gic->cpu_base;
Russell King9395f6e2010-11-11 23:10:30 +0000462 int i;
463
Russell King9395f6e2010-11-11 23:10:30 +0000464 /*
465 * Deal with the banked PPI and SGI interrupts - disable all
466 * PPI interrupts, ensure all SGI interrupts are enabled.
467 */
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530468 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
469 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
Russell King9395f6e2010-11-11 23:10:30 +0000470
471 /*
472 * Set priority on PPI and SGI interrupts
473 */
474 for (i = 0; i < 32; i += 4)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530475 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
Russell King9395f6e2010-11-11 23:10:30 +0000476
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530477 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
478 writel_relaxed(1, base + GIC_CPU_CTRL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700479 mb();
Russell Kingf27ecac2005-08-18 21:31:00 +0100480}
481
Russell Kingb580b892010-12-04 15:55:14 +0000482void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
483 void __iomem *dist_base, void __iomem *cpu_base)
484{
Russell Kingbef8f9e2010-12-04 16:50:58 +0000485 struct gic_chip_data *gic;
486
487 BUG_ON(gic_nr >= MAX_GIC_NR);
488
489 gic = &gic_data[gic_nr];
490 gic->dist_base = dist_base;
491 gic->cpu_base = cpu_base;
492 gic->irq_offset = (irq_start - 1) & ~31;
493
Russell Kingff2e27a2010-12-04 16:13:29 +0000494 if (gic_nr == 0)
495 gic_cpu_base_addr = cpu_base;
Russell Kingbef8f9e2010-12-04 16:50:58 +0000496
497 gic_dist_init(gic, irq_start);
498 gic_cpu_init(gic);
Russell Kingb580b892010-12-04 15:55:14 +0000499}
500
Russell King38489532010-12-04 16:01:03 +0000501void __cpuinit gic_secondary_init(unsigned int gic_nr)
502{
Russell Kingbef8f9e2010-12-04 16:50:58 +0000503 BUG_ON(gic_nr >= MAX_GIC_NR);
504
505 gic_cpu_init(&gic_data[gic_nr]);
Russell King38489532010-12-04 16:01:03 +0000506}
507
Russell Kingac61d142010-12-06 10:38:14 +0000508void __cpuinit gic_enable_ppi(unsigned int irq)
509{
510 unsigned long flags;
511
512 local_irq_save(flags);
Thomas Gleixnerfdea77b2011-03-24 12:48:54 +0100513 irq_set_status_flags(irq, IRQ_NOPROBE);
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100514 gic_unmask_irq(irq_get_irq_data(irq));
Russell Kingac61d142010-12-06 10:38:14 +0000515 local_irq_restore(flags);
516}
517
Russell Kingf27ecac2005-08-18 21:31:00 +0100518#ifdef CONFIG_SMP
Russell King82668102009-05-17 16:20:18 +0100519void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
Russell Kingf27ecac2005-08-18 21:31:00 +0100520{
Russell King82668102009-05-17 16:20:18 +0100521 unsigned long map = *cpus_addr(*mask);
Russell Kingf27ecac2005-08-18 21:31:00 +0100522
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530523 /*
524 * Ensure that stores to Normal memory are visible to the
525 * other CPUs before issuing the IPI.
526 */
527 dsb();
528
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100529 /* this always happens on GIC0 */
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530530 writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700531 mb();
Russell Kingf27ecac2005-08-18 21:31:00 +0100532}
533#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700534
535/* before calling this function the interrupts should be disabled
536 * and the irq must be disabled at gic to avoid spurious interrupts */
537bool gic_is_spi_pending(unsigned int irq)
538{
539 struct irq_data *d = irq_get_irq_data(irq);
540 struct gic_chip_data *gic_data = &gic_data[0];
541 u32 mask, val;
542
543 WARN_ON(!irqs_disabled());
544 spin_lock(&irq_controller_lock);
545 mask = 1 << (gic_irq(d) % 32);
546 val = readl(gic_dist_base(d) +
547 GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
548 /* warn if the interrupt is enabled */
549 WARN_ON(val & mask);
550 val = readl(gic_dist_base(d) +
551 GIC_DIST_PENDING_SET + (gic_irq(d) / 32) * 4);
552 spin_unlock(&irq_controller_lock);
553 return (bool) (val & mask);
554}
555
556/* before calling this function the interrupts should be disabled
557 * and the irq must be disabled at gic to avoid spurious interrupts */
558void gic_clear_spi_pending(unsigned int irq)
559{
560 struct gic_chip_data *gic_data = &gic_data[0];
561 struct irq_data *d = irq_get_irq_data(irq);
562
563 u32 mask, val;
564 WARN_ON(!irqs_disabled());
565 spin_lock(&irq_controller_lock);
566 mask = 1 << (gic_irq(d) % 32);
567 val = readl(gic_dist_base(d) +
568 GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
569 /* warn if the interrupt is enabled */
570 WARN_ON(val & mask);
571 writel(mask, gic_dist_base(d) +
572 GIC_DIST_PENDING_CLEAR + (gic_irq(d) / 32) * 4);
573 spin_unlock(&irq_controller_lock);
574}