Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm / 7a5cc772c39e93d748bccfd2022696ea95098bca / . / arch / arm / mach-msm / clock-8226.c
blob: 14775412d436f8b4ba30942aa4e884dc94c6f3b8 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]27#include <mach/clock-generic.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]28
29#include "clock-local2.h"
30#include "clock-pll.h"
31#include "clock-rpm.h"
32#include "clock-voter.h"
33#include "clock-mdss-8974.h"
34#include "clock.h"
35
36enum {
37 GCC_BASE,
38 MMSS_BASE,
39 LPASS_BASE,
40 APCS_BASE,
41 APCS_PLL_BASE,
42 N_BASES,
43};
44
45static void __iomem *virt_bases[N_BASES];
46
47#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
48#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
49#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
50#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
51
52/* Mux source select values */
53#define xo_source_val 0
54#define gpll0_source_val 1
55#define gpll1_source_val 2
56
57#define xo_mm_source_val 0
58#define mmpll0_pll_mm_source_val 1
59#define mmpll1_pll_mm_source_val 2
60#define mmpll2_pll_mm_source_val 3
61#define gpll0_mm_source_val 5
62#define dsipll_750_mm_source_val 1
63#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]64#define dsipll0_byte_mm_source_val 1
65#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]66
67#define gpll1_hsic_source_val 4
68
69#define xo_lpass_source_val 0
70#define lpaaudio_pll_lpass_source_val 1
71#define gpll0_lpass_source_val 5
72
73/* Prevent a divider of -1 */
74#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
75
76#define F_GCC(f, s, div, m, n) \
77 { \
78 .freq_hz = (f), \
79 .src_clk = &s.c, \
80 .m_val = (m), \
81 .n_val = ~((n)-(m)) * !!(n), \
82 .d_val = ~(n),\
83 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
84 | BVAL(10, 8, s##_source_val), \
85 }
86
87#define F_MMSS(f, s, div, m, n) \
88 { \
89 .freq_hz = (f), \
90 .src_clk = &s.c, \
91 .m_val = (m), \
92 .n_val = ~((n)-(m)) * !!(n), \
93 .d_val = ~(n),\
94 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
95 | BVAL(10, 8, s##_mm_source_val), \
96 }
97
98#define F_MDSS(f, s, div, m, n) \
99 { \
100 .freq_hz = (f), \
101 .m_val = (m), \
102 .n_val = ~((n)-(m)) * !!(n), \
103 .d_val = ~(n),\
104 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
105 | BVAL(10, 8, s##_mm_source_val), \
106 }
107
108#define F_HSIC(f, s, div, m, n) \
109 { \
110 .freq_hz = (f), \
111 .src_clk = &s.c, \
112 .m_val = (m), \
113 .n_val = ~((n)-(m)) * !!(n), \
114 .d_val = ~(n),\
115 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
116 | BVAL(10, 8, s##_hsic_source_val), \
117 }
118
119#define F_LPASS(f, s, div, m, n) \
120 { \
121 .freq_hz = (f), \
122 .src_clk = &s.c, \
123 .m_val = (m), \
124 .n_val = ~((n)-(m)) * !!(n), \
125 .d_val = ~(n),\
126 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
127 | BVAL(10, 8, s##_lpass_source_val), \
128 }
129
130#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
131 { \
132 .freq_hz = (f), \
133 .l_val = (l), \
134 .m_val = (m), \
135 .n_val = (n), \
136 .pre_div_val = BVAL(12, 12, (pre_div)), \
137 .post_div_val = BVAL(9, 8, (post_div)), \
138 .vco_val = BVAL(29, 28, (vco)), \
139 }
140
141#define VDD_DIG_FMAX_MAP1(l1, f1) \
142 .vdd_class = &vdd_dig, \
143 .fmax = (unsigned long[VDD_DIG_NUM]) { \
144 [VDD_DIG_##l1] = (f1), \
145 }, \
146 .num_fmax = VDD_DIG_NUM
147
148#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
149 .vdd_class = &vdd_dig, \
150 .fmax = (unsigned long[VDD_DIG_NUM]) { \
151 [VDD_DIG_##l1] = (f1), \
152 [VDD_DIG_##l2] = (f2), \
153 }, \
154 .num_fmax = VDD_DIG_NUM
155
156#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
157 .vdd_class = &vdd_dig, \
158 .fmax = (unsigned long[VDD_DIG_NUM]) { \
159 [VDD_DIG_##l1] = (f1), \
160 [VDD_DIG_##l2] = (f2), \
161 [VDD_DIG_##l3] = (f3), \
162 }, \
163 .num_fmax = VDD_DIG_NUM
164
165enum vdd_dig_levels {
166 VDD_DIG_NONE,
167 VDD_DIG_LOW,
168 VDD_DIG_NOMINAL,
169 VDD_DIG_HIGH,
170 VDD_DIG_NUM
171};
172
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]173static int vdd_corner[] = {
174 RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
175 RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_LOW */
176 RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
177 RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_HIGH */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]178};
179
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]180static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]181
182#define RPM_MISC_CLK_TYPE 0x306b6c63
183#define RPM_BUS_CLK_TYPE 0x316b6c63
184#define RPM_MEM_CLK_TYPE 0x326b6c63
185
186#define RPM_SMD_KEY_ENABLE 0x62616E45
187
188#define CXO_ID 0x0
189#define QDSS_ID 0x1
190
191#define PNOC_ID 0x0
192#define SNOC_ID 0x1
193#define CNOC_ID 0x2
194#define MMSSNOC_AHB_ID 0x3
195
196#define BIMC_ID 0x0
197#define OXILI_ID 0x1
198#define OCMEM_ID 0x2
199
200#define D0_ID 1
201#define D1_ID 2
202#define A0_ID 4
203#define A1_ID 5
204#define A2_ID 6
205#define DIFF_CLK_ID 7
206#define DIV_CLK1_ID 11
207#define DIV_CLK2_ID 12
208
209DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
210DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
211DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
212DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
213 MMSSNOC_AHB_ID, NULL);
214
215DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
216DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
217 NULL);
218DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
219 NULL);
220
221DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
222 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
223DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
224
225DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
226DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
227DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
228DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
229DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
230DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
232DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
233
234DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
235DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
239
240struct measure_mux_entry {
241 struct clk *c;
242 int base;
243 u32 debug_mux;
244};
245
246static struct branch_clk oxilicx_axi_clk;
247
248#define MSS_DEBUG_CLOCK_CTL 0x0078
249#define LPASS_DEBUG_CLK_CTL 0x29000
250#define GLB_CLK_DIAG 0x01C
251#define GLB_TEST_BUS_SEL 0x020
252
253#define MMPLL0_PLL_MODE (0x0000)
254#define MMPLL0_PLL_L_VAL (0x0004)
255#define MMPLL0_PLL_M_VAL (0x0008)
256#define MMPLL0_PLL_N_VAL (0x000C)
257#define MMPLL0_PLL_USER_CTL (0x0010)
258#define MMPLL0_PLL_STATUS (0x001C)
259#define MMPLL1_PLL_MODE (0x0040)
260#define MMPLL1_PLL_L_VAL (0x0044)
261#define MMPLL1_PLL_M_VAL (0x0048)
262#define MMPLL1_PLL_N_VAL (0x004C)
263#define MMPLL1_PLL_USER_CTL (0x0050)
264#define MMPLL1_PLL_STATUS (0x005C)
265#define MMSS_PLL_VOTE_APCS (0x0100)
266#define VCODEC0_CMD_RCGR (0x1000)
267#define VENUS0_VCODEC0_CBCR (0x1028)
268#define VENUS0_AHB_CBCR (0x1030)
269#define VENUS0_AXI_CBCR (0x1034)
270#define PCLK0_CMD_RCGR (0x2000)
271#define MDP_CMD_RCGR (0x2040)
272#define VSYNC_CMD_RCGR (0x2080)
273#define BYTE0_CMD_RCGR (0x2120)
274#define ESC0_CMD_RCGR (0x2160)
275#define MDSS_AHB_CBCR (0x2308)
276#define MDSS_AXI_CBCR (0x2310)
277#define MDSS_PCLK0_CBCR (0x2314)
278#define MDSS_MDP_CBCR (0x231C)
279#define MDSS_MDP_LUT_CBCR (0x2320)
280#define MDSS_VSYNC_CBCR (0x2328)
281#define MDSS_BYTE0_CBCR (0x233C)
282#define MDSS_ESC0_CBCR (0x2344)
283#define CSI0PHYTIMER_CMD_RCGR (0x3000)
284#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
285#define CSI1PHYTIMER_CMD_RCGR (0x3030)
286#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
287#define CSI0_CMD_RCGR (0x3090)
288#define CAMSS_CSI0_CBCR (0x30B4)
289#define CAMSS_CSI0_AHB_CBCR (0x30BC)
290#define CAMSS_CSI0PHY_CBCR (0x30C4)
291#define CAMSS_CSI0RDI_CBCR (0x30D4)
292#define CAMSS_CSI0PIX_CBCR (0x30E4)
293#define CSI1_CMD_RCGR (0x3100)
294#define CAMSS_CSI1_CBCR (0x3124)
295#define CAMSS_CSI1_AHB_CBCR (0x3128)
296#define CAMSS_CSI1PHY_CBCR (0x3134)
297#define CAMSS_CSI1RDI_CBCR (0x3144)
298#define CAMSS_CSI1PIX_CBCR (0x3154)
299#define CAMSS_ISPIF_AHB_CBCR (0x3224)
300#define CCI_CMD_RCGR (0x3300)
301#define CAMSS_CCI_CCI_CBCR (0x3344)
302#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
303#define MCLK0_CMD_RCGR (0x3360)
304#define CAMSS_MCLK0_CBCR (0x3384)
305#define MCLK1_CMD_RCGR (0x3390)
306#define CAMSS_MCLK1_CBCR (0x33B4)
307#define MMSS_GP0_CMD_RCGR (0x3420)
308#define CAMSS_GP0_CBCR (0x3444)
309#define MMSS_GP1_CMD_RCGR (0x3450)
310#define CAMSS_GP1_CBCR (0x3474)
311#define CAMSS_TOP_AHB_CBCR (0x3484)
312#define CAMSS_MICRO_AHB_CBCR (0x3494)
313#define JPEG0_CMD_RCGR (0x3500)
314#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
315#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
316#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
317#define VFE0_CMD_RCGR (0x3600)
318#define CPP_CMD_RCGR (0x3640)
319#define CAMSS_VFE_VFE0_CBCR (0x36A8)
320#define CAMSS_VFE_CPP_CBCR (0x36B0)
321#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
322#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
323#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
324#define CAMSS_CSI_VFE0_CBCR (0x3704)
325#define OXILI_GFX3D_CBCR (0x4028)
326#define OXILICX_AXI_CBCR (0x4038)
327#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]328#define MMPLL2_PLL_MODE (0x4100)
329#define MMPLL2_PLL_STATUS (0x411C)
330#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
331#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
332#define MMSS_MISC_AHB_CBCR (0x502C)
333#define AXI_CMD_RCGR (0x5040)
334#define MMSS_S0_AXI_CBCR (0x5064)
335#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
336#define MMSS_DEBUG_CLK_CTL (0x0900)
337#define GPLL0_MODE (0x0000)
338#define GPLL0_L_VAL (0x0004)
339#define GPLL0_M_VAL (0x0008)
340#define GPLL0_N_VAL (0x000C)
341#define GPLL0_USER_CTL (0x0010)
342#define GPLL0_STATUS (0x001C)
343#define GPLL1_MODE (0x0040)
344#define GPLL1_L_VAL (0x0044)
345#define GPLL1_M_VAL (0x0048)
346#define GPLL1_N_VAL (0x004C)
347#define GPLL1_USER_CTL (0x0050)
348#define GPLL1_STATUS (0x005C)
349#define PERIPH_NOC_AHB_CBCR (0x0184)
350#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
351#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
352#define MSS_CFG_AHB_CBCR (0x0280)
353#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
354#define USB_HS_HSIC_BCR (0x0400)
355#define USB_HSIC_AHB_CBCR (0x0408)
356#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
357#define USB_HSIC_SYSTEM_CBCR (0x040C)
358#define USB_HSIC_CMD_RCGR (0x0440)
359#define USB_HSIC_CBCR (0x0410)
360#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
361#define USB_HSIC_IO_CAL_CBCR (0x0414)
362#define USB_HS_BCR (0x0480)
363#define USB_HS_SYSTEM_CBCR (0x0484)
364#define USB_HS_AHB_CBCR (0x0488)
365#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
366#define USB2A_PHY_SLEEP_CBCR (0x04AC)
367#define SDCC1_APPS_CMD_RCGR (0x04D0)
368#define SDCC1_APPS_CBCR (0x04C4)
369#define SDCC1_AHB_CBCR (0x04C8)
370#define SDCC2_APPS_CMD_RCGR (0x0510)
371#define SDCC2_APPS_CBCR (0x0504)
372#define SDCC2_AHB_CBCR (0x0508)
373#define SDCC3_APPS_CMD_RCGR (0x0550)
374#define SDCC3_APPS_CBCR (0x0544)
375#define SDCC3_AHB_CBCR (0x0548)
376#define BLSP1_AHB_CBCR (0x05C4)
377#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
378#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
379#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
380#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
381#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
382#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
383#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
384#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
385#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
386#define BLSP1_UART1_APPS_CBCR (0x0684)
387#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
388#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
389#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
390#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
391#define BLSP1_UART2_APPS_CBCR (0x0704)
392#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
393#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
394#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
395#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
396#define BLSP1_UART3_APPS_CBCR (0x0784)
397#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
398#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
399#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
400#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
401#define BLSP1_UART4_APPS_CBCR (0x0804)
402#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
403#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
404#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
405#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
406#define BLSP1_UART5_APPS_CBCR (0x0884)
407#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
408#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
409#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
410#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
411#define BLSP1_UART6_APPS_CBCR (0x0904)
412#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
413#define PDM_AHB_CBCR (0x0CC4)
414#define PDM_XO4_CBCR (0x0CC8)
415#define PDM2_CBCR (0x0CCC)
416#define PDM2_CMD_RCGR (0x0CD0)
417#define PRNG_AHB_CBCR (0x0D04)
418#define BAM_DMA_AHB_CBCR (0x0D44)
419#define BOOT_ROM_AHB_CBCR (0x0E04)
420#define CE1_CMD_RCGR (0x1050)
421#define CE1_CBCR (0x1044)
422#define CE1_AXI_CBCR (0x1048)
423#define CE1_AHB_CBCR (0x104C)
424#define GCC_XO_DIV4_CBCR (0x10C8)
425#define LPASS_Q6_AXI_CBCR (0x11C0)
426#define APCS_GPLL_ENA_VOTE (0x1480)
427#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
428#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
429#define GCC_DEBUG_CLK_CTL (0x1880)
430#define CLOCK_FRQ_MEASURE_CTL (0x1884)
431#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
432#define PLLTEST_PAD_CFG (0x188C)
433#define GP1_CBCR (0x1900)
434#define GP1_CMD_RCGR (0x1904)
435#define GP2_CBCR (0x1940)
436#define GP2_CMD_RCGR (0x1944)
437#define GP3_CBCR (0x1980)
438#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]439#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]440#define Q6SS_AHB_LFABIF_CBCR (0x22000)
441#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]442#define Q6SS_XO_CBCR (0x26000)
443
444static unsigned int soft_vote_gpll0;
445
446static struct pll_vote_clk gpll0 = {
447 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
448 .en_mask = BIT(0),
449 .status_reg = (void __iomem *)GPLL0_STATUS,
450 .status_mask = BIT(17),
451 .soft_vote = &soft_vote_gpll0,
452 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
453 .base = &virt_bases[GCC_BASE],
454 .c = {
455 .rate = 600000000,
456 .parent = &xo.c,
457 .dbg_name = "gpll0",
458 .ops = &clk_ops_pll_acpu_vote,
459 CLK_INIT(gpll0.c),
460 },
461};
462
463/*Don't vote for xo if using this clock to allow xo shutdown*/
464static struct pll_vote_clk gpll0_ao = {
465 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
466 .en_mask = BIT(0),
467 .status_reg = (void __iomem *)GPLL0_STATUS,
468 .status_mask = BIT(17),
469 .soft_vote = &soft_vote_gpll0,
470 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
471 .base = &virt_bases[GCC_BASE],
472 .c = {
473 .rate = 600000000,
474 .dbg_name = "gpll0_ao",
475 .ops = &clk_ops_pll_acpu_vote,
476 CLK_INIT(gpll0_ao.c),
477 },
478};
479
480static struct pll_vote_clk gpll1 = {
481 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
482 .en_mask = BIT(1),
483 .status_reg = (void __iomem *)GPLL1_STATUS,
484 .status_mask = BIT(17),
485 .base = &virt_bases[GCC_BASE],
486 .c = {
487 .rate = 480000000,
488 .parent = &xo.c,
489 .dbg_name = "gpll1",
490 .ops = &clk_ops_pll_vote,
491 CLK_INIT(gpll1.c),
492 },
493};
494
495static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]496 F_GCC( 19200000, xo, 1, 0, 0),
497 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]498 F_END
499};
500
501static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
502 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
503 .set_rate = set_rate_hid,
504 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
505 .current_freq = &rcg_dummy_freq,
506 .base = &virt_bases[GCC_BASE],
507 .c = {
508 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
509 .ops = &clk_ops_rcg,
510 VDD_DIG_FMAX_MAP1(LOW, 50000000),
511 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
512 },
513};
514
515static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
516 F_GCC( 960000, xo, 10, 1, 2),
517 F_GCC( 4800000, xo, 4, 0, 0),
518 F_GCC( 9600000, xo, 2, 0, 0),
519 F_GCC( 15000000, gpll0, 10, 1, 4),
520 F_GCC( 19200000, xo, 1, 0, 0),
521 F_GCC( 25000000, gpll0, 12, 1, 2),
522 F_GCC( 50000000, gpll0, 12, 0, 0),
523 F_END
524};
525
526static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
527 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
528 .set_rate = set_rate_mnd,
529 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
530 .current_freq = &rcg_dummy_freq,
531 .base = &virt_bases[GCC_BASE],
532 .c = {
533 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
534 .ops = &clk_ops_rcg_mnd,
535 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
536 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
537 },
538};
539
540static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
541 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
542 .set_rate = set_rate_hid,
543 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
544 .current_freq = &rcg_dummy_freq,
545 .base = &virt_bases[GCC_BASE],
546 .c = {
547 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
548 .ops = &clk_ops_rcg,
549 VDD_DIG_FMAX_MAP1(LOW, 50000000),
550 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
551 },
552};
553
554static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
555 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
556 .set_rate = set_rate_mnd,
557 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
558 .current_freq = &rcg_dummy_freq,
559 .base = &virt_bases[GCC_BASE],
560 .c = {
561 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
562 .ops = &clk_ops_rcg_mnd,
563 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
564 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
565 },
566};
567
568static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
569 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
570 .set_rate = set_rate_hid,
571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
572 .current_freq = &rcg_dummy_freq,
573 .base = &virt_bases[GCC_BASE],
574 .c = {
575 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
576 .ops = &clk_ops_rcg,
577 VDD_DIG_FMAX_MAP1(LOW, 50000000),
578 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
579 },
580};
581
582static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
583 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
584 .set_rate = set_rate_mnd,
585 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
586 .current_freq = &rcg_dummy_freq,
587 .base = &virt_bases[GCC_BASE],
588 .c = {
589 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
590 .ops = &clk_ops_rcg_mnd,
591 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
592 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
593 },
594};
595
596static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
597 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
598 .set_rate = set_rate_hid,
599 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
600 .current_freq = &rcg_dummy_freq,
601 .base = &virt_bases[GCC_BASE],
602 .c = {
603 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
604 .ops = &clk_ops_rcg,
605 VDD_DIG_FMAX_MAP1(LOW, 50000000),
606 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
607 },
608};
609
610static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
611 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
612 .set_rate = set_rate_mnd,
613 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
614 .current_freq = &rcg_dummy_freq,
615 .base = &virt_bases[GCC_BASE],
616 .c = {
617 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
618 .ops = &clk_ops_rcg_mnd,
619 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
620 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
621 },
622};
623
624static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
625 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
626 .set_rate = set_rate_hid,
627 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
628 .current_freq = &rcg_dummy_freq,
629 .base = &virt_bases[GCC_BASE],
630 .c = {
631 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
632 .ops = &clk_ops_rcg,
633 VDD_DIG_FMAX_MAP1(LOW, 50000000),
634 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
635 },
636};
637
638static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
639 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
640 .set_rate = set_rate_mnd,
641 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
642 .current_freq = &rcg_dummy_freq,
643 .base = &virt_bases[GCC_BASE],
644 .c = {
645 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
646 .ops = &clk_ops_rcg_mnd,
647 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
648 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
649 },
650};
651
652static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
653 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
654 .set_rate = set_rate_hid,
655 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
656 .current_freq = &rcg_dummy_freq,
657 .base = &virt_bases[GCC_BASE],
658 .c = {
659 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
660 .ops = &clk_ops_rcg,
661 VDD_DIG_FMAX_MAP1(LOW, 50000000),
662 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
663 },
664};
665
666static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
667 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
668 .set_rate = set_rate_mnd,
669 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
670 .current_freq = &rcg_dummy_freq,
671 .base = &virt_bases[GCC_BASE],
672 .c = {
673 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
674 .ops = &clk_ops_rcg_mnd,
675 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
676 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
677 },
678};
679
680static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
681 F_GCC( 3686400, gpll0, 1, 96, 15625),
682 F_GCC( 7372800, gpll0, 1, 192, 15625),
683 F_GCC( 14745600, gpll0, 1, 384, 15625),
684 F_GCC( 16000000, gpll0, 5, 2, 15),
685 F_GCC( 19200000, xo, 1, 0, 0),
686 F_GCC( 24000000, gpll0, 5, 1, 5),
687 F_GCC( 32000000, gpll0, 1, 4, 75),
688 F_GCC( 40000000, gpll0, 15, 0, 0),
689 F_GCC( 46400000, gpll0, 1, 29, 375),
690 F_GCC( 48000000, gpll0, 12.5, 0, 0),
691 F_GCC( 51200000, gpll0, 1, 32, 375),
692 F_GCC( 56000000, gpll0, 1, 7, 75),
693 F_GCC( 58982400, gpll0, 1, 1536, 15625),
694 F_GCC( 60000000, gpll0, 10, 0, 0),
695 F_END
696};
697
698static struct rcg_clk blsp1_uart1_apps_clk_src = {
699 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
700 .set_rate = set_rate_mnd,
701 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
702 .current_freq = &rcg_dummy_freq,
703 .base = &virt_bases[GCC_BASE],
704 .c = {
705 .dbg_name = "blsp1_uart1_apps_clk_src",
706 .ops = &clk_ops_rcg_mnd,
707 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
708 CLK_INIT(blsp1_uart1_apps_clk_src.c),
709 },
710};
711
712static struct rcg_clk blsp1_uart2_apps_clk_src = {
713 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
714 .set_rate = set_rate_mnd,
715 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
716 .current_freq = &rcg_dummy_freq,
717 .base = &virt_bases[GCC_BASE],
718 .c = {
719 .dbg_name = "blsp1_uart2_apps_clk_src",
720 .ops = &clk_ops_rcg_mnd,
721 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
722 CLK_INIT(blsp1_uart2_apps_clk_src.c),
723 },
724};
725
726static struct rcg_clk blsp1_uart3_apps_clk_src = {
727 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
728 .set_rate = set_rate_mnd,
729 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
730 .current_freq = &rcg_dummy_freq,
731 .base = &virt_bases[GCC_BASE],
732 .c = {
733 .dbg_name = "blsp1_uart3_apps_clk_src",
734 .ops = &clk_ops_rcg_mnd,
735 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
736 CLK_INIT(blsp1_uart3_apps_clk_src.c),
737 },
738};
739
740static struct rcg_clk blsp1_uart4_apps_clk_src = {
741 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
742 .set_rate = set_rate_mnd,
743 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
744 .current_freq = &rcg_dummy_freq,
745 .base = &virt_bases[GCC_BASE],
746 .c = {
747 .dbg_name = "blsp1_uart4_apps_clk_src",
748 .ops = &clk_ops_rcg_mnd,
749 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
750 CLK_INIT(blsp1_uart4_apps_clk_src.c),
751 },
752};
753
754static struct rcg_clk blsp1_uart5_apps_clk_src = {
755 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
756 .set_rate = set_rate_mnd,
757 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
758 .current_freq = &rcg_dummy_freq,
759 .base = &virt_bases[GCC_BASE],
760 .c = {
761 .dbg_name = "blsp1_uart5_apps_clk_src",
762 .ops = &clk_ops_rcg_mnd,
763 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
764 CLK_INIT(blsp1_uart5_apps_clk_src.c),
765 },
766};
767
768static struct rcg_clk blsp1_uart6_apps_clk_src = {
769 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
770 .set_rate = set_rate_mnd,
771 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
772 .current_freq = &rcg_dummy_freq,
773 .base = &virt_bases[GCC_BASE],
774 .c = {
775 .dbg_name = "blsp1_uart6_apps_clk_src",
776 .ops = &clk_ops_rcg_mnd,
777 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
778 CLK_INIT(blsp1_uart6_apps_clk_src.c),
779 },
780};
781
782static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
783 F_GCC( 50000000, gpll0, 12, 0, 0),
784 F_GCC( 100000000, gpll0, 6, 0, 0),
785 F_END
786};
787
788static struct rcg_clk ce1_clk_src = {
789 .cmd_rcgr_reg = CE1_CMD_RCGR,
790 .set_rate = set_rate_hid,
791 .freq_tbl = ftbl_gcc_ce1_clk,
792 .current_freq = &rcg_dummy_freq,
793 .base = &virt_bases[GCC_BASE],
794 .c = {
795 .dbg_name = "ce1_clk_src",
796 .ops = &clk_ops_rcg,
797 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
798 CLK_INIT(ce1_clk_src.c),
799 },
800};
801
802static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
803 F_GCC( 19200000, xo, 1, 0, 0),
804 F_END
805};
806
807static struct rcg_clk gp1_clk_src = {
808 .cmd_rcgr_reg = GP1_CMD_RCGR,
809 .set_rate = set_rate_mnd,
810 .freq_tbl = ftbl_gcc_gp1_3_clk,
811 .current_freq = &rcg_dummy_freq,
812 .base = &virt_bases[GCC_BASE],
813 .c = {
814 .dbg_name = "gp1_clk_src",
815 .ops = &clk_ops_rcg_mnd,
816 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
817 CLK_INIT(gp1_clk_src.c),
818 },
819};
820
821static struct rcg_clk gp2_clk_src = {
822 .cmd_rcgr_reg = GP2_CMD_RCGR,
823 .set_rate = set_rate_mnd,
824 .freq_tbl = ftbl_gcc_gp1_3_clk,
825 .current_freq = &rcg_dummy_freq,
826 .base = &virt_bases[GCC_BASE],
827 .c = {
828 .dbg_name = "gp2_clk_src",
829 .ops = &clk_ops_rcg_mnd,
830 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
831 CLK_INIT(gp2_clk_src.c),
832 },
833};
834
835static struct rcg_clk gp3_clk_src = {
836 .cmd_rcgr_reg = GP3_CMD_RCGR,
837 .set_rate = set_rate_mnd,
838 .freq_tbl = ftbl_gcc_gp1_3_clk,
839 .current_freq = &rcg_dummy_freq,
840 .base = &virt_bases[GCC_BASE],
841 .c = {
842 .dbg_name = "gp3_clk_src",
843 .ops = &clk_ops_rcg_mnd,
844 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
845 CLK_INIT(gp3_clk_src.c),
846 },
847};
848
849static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
850 F_GCC( 60000000, gpll0, 10, 0, 0),
851 F_END
852};
853
854static struct rcg_clk pdm2_clk_src = {
855 .cmd_rcgr_reg = PDM2_CMD_RCGR,
856 .set_rate = set_rate_hid,
857 .freq_tbl = ftbl_gcc_pdm2_clk,
858 .current_freq = &rcg_dummy_freq,
859 .base = &virt_bases[GCC_BASE],
860 .c = {
861 .dbg_name = "pdm2_clk_src",
862 .ops = &clk_ops_rcg,
863 VDD_DIG_FMAX_MAP1(LOW, 60000000),
864 CLK_INIT(pdm2_clk_src.c),
865 },
866};
867
868static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
869 F_GCC( 144000, xo, 16, 3, 25),
870 F_GCC( 400000, xo, 12, 1, 4),
871 F_GCC( 20000000, gpll0, 15, 1, 2),
872 F_GCC( 25000000, gpll0, 12, 1, 2),
873 F_GCC( 50000000, gpll0, 12, 0, 0),
874 F_GCC( 100000000, gpll0, 6, 0, 0),
875 F_GCC( 200000000, gpll0, 3, 0, 0),
876 F_END
877};
878
879static struct rcg_clk sdcc1_apps_clk_src = {
880 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
881 .set_rate = set_rate_mnd,
882 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
883 .current_freq = &rcg_dummy_freq,
884 .base = &virt_bases[GCC_BASE],
885 .c = {
886 .dbg_name = "sdcc1_apps_clk_src",
887 .ops = &clk_ops_rcg_mnd,
888 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
889 CLK_INIT(sdcc1_apps_clk_src.c),
890 },
891};
892
893static struct rcg_clk sdcc2_apps_clk_src = {
894 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
895 .set_rate = set_rate_mnd,
896 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
897 .current_freq = &rcg_dummy_freq,
898 .base = &virt_bases[GCC_BASE],
899 .c = {
900 .dbg_name = "sdcc2_apps_clk_src",
901 .ops = &clk_ops_rcg_mnd,
902 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
903 CLK_INIT(sdcc2_apps_clk_src.c),
904 },
905};
906
907static struct rcg_clk sdcc3_apps_clk_src = {
908 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
909 .set_rate = set_rate_mnd,
910 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
911 .current_freq = &rcg_dummy_freq,
912 .base = &virt_bases[GCC_BASE],
913 .c = {
914 .dbg_name = "sdcc3_apps_clk_src",
915 .ops = &clk_ops_rcg_mnd,
916 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
917 CLK_INIT(sdcc3_apps_clk_src.c),
918 },
919};
920
921static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
922 F_GCC( 75000000, gpll0, 8, 0, 0),
923 F_END
924};
925
926static struct rcg_clk usb_hs_system_clk_src = {
927 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
928 .set_rate = set_rate_hid,
929 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
930 .current_freq = &rcg_dummy_freq,
931 .base = &virt_bases[GCC_BASE],
932 .c = {
933 .dbg_name = "usb_hs_system_clk_src",
934 .ops = &clk_ops_rcg,
935 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
936 CLK_INIT(usb_hs_system_clk_src.c),
937 },
938};
939
940static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
941 F_HSIC( 480000000, gpll1, 0, 0, 0),
942 F_END
943};
944
945static struct rcg_clk usb_hsic_clk_src = {
946 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
947 .set_rate = set_rate_hid,
948 .freq_tbl = ftbl_gcc_usb_hsic_clk,
949 .current_freq = &rcg_dummy_freq,
950 .base = &virt_bases[GCC_BASE],
951 .c = {
952 .dbg_name = "usb_hsic_clk_src",
953 .ops = &clk_ops_rcg,
954 VDD_DIG_FMAX_MAP1(LOW, 480000000),
955 CLK_INIT(usb_hsic_clk_src.c),
956 },
957};
958
959static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
960 F_GCC( 9600000, xo, 2, 0, 0),
961 F_END
962};
963
964static struct rcg_clk usb_hsic_io_cal_clk_src = {
965 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
966 .set_rate = set_rate_hid,
967 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
968 .current_freq = &rcg_dummy_freq,
969 .base = &virt_bases[GCC_BASE],
970 .c = {
971 .dbg_name = "usb_hsic_io_cal_clk_src",
972 .ops = &clk_ops_rcg,
973 VDD_DIG_FMAX_MAP1(LOW, 9600000),
974 CLK_INIT(usb_hsic_io_cal_clk_src.c),
975 },
976};
977
978static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
979 F_GCC( 75000000, gpll0, 8, 0, 0),
980 F_END
981};
982
983static struct rcg_clk usb_hsic_system_clk_src = {
984 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
985 .set_rate = set_rate_hid,
986 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
987 .current_freq = &rcg_dummy_freq,
988 .base = &virt_bases[GCC_BASE],
989 .c = {
990 .dbg_name = "usb_hsic_system_clk_src",
991 .ops = &clk_ops_rcg,
992 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
993 CLK_INIT(usb_hsic_system_clk_src.c),
994 },
995};
996
997static struct local_vote_clk gcc_bam_dma_ahb_clk = {
998 .cbcr_reg = BAM_DMA_AHB_CBCR,
999 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1000 .en_mask = BIT(12),
1001 .base = &virt_bases[GCC_BASE],
1002 .c = {
1003 .dbg_name = "gcc_bam_dma_ahb_clk",
1004 .ops = &clk_ops_vote,
1005 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1006 },
1007};
1008
1009static struct local_vote_clk gcc_blsp1_ahb_clk = {
1010 .cbcr_reg = BLSP1_AHB_CBCR,
1011 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1012 .en_mask = BIT(17),
1013 .base = &virt_bases[GCC_BASE],
1014 .c = {
1015 .dbg_name = "gcc_blsp1_ahb_clk",
1016 .ops = &clk_ops_vote,
1017 CLK_INIT(gcc_blsp1_ahb_clk.c),
1018 },
1019};
1020
1021static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1022 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1023 .has_sibling = 0,
1024 .base = &virt_bases[GCC_BASE],
1025 .c = {
1026 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1027 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1028 .ops = &clk_ops_branch,
1029 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1030 },
1031};
1032
1033static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1034 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1035 .has_sibling = 0,
1036 .base = &virt_bases[GCC_BASE],
1037 .c = {
1038 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1039 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1040 .ops = &clk_ops_branch,
1041 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1042 },
1043};
1044
1045static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1046 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1047 .has_sibling = 0,
1048 .base = &virt_bases[GCC_BASE],
1049 .c = {
1050 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1051 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1052 .ops = &clk_ops_branch,
1053 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1054 },
1055};
1056
1057static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1058 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1059 .has_sibling = 0,
1060 .base = &virt_bases[GCC_BASE],
1061 .c = {
1062 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1063 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1064 .ops = &clk_ops_branch,
1065 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1066 },
1067};
1068
1069static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1070 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1071 .has_sibling = 0,
1072 .base = &virt_bases[GCC_BASE],
1073 .c = {
1074 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1075 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1076 .ops = &clk_ops_branch,
1077 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1078 },
1079};
1080
1081static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1082 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1083 .has_sibling = 0,
1084 .base = &virt_bases[GCC_BASE],
1085 .c = {
1086 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1087 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1088 .ops = &clk_ops_branch,
1089 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1090 },
1091};
1092
1093static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1094 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1095 .has_sibling = 0,
1096 .base = &virt_bases[GCC_BASE],
1097 .c = {
1098 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1099 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1100 .ops = &clk_ops_branch,
1101 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1102 },
1103};
1104
1105static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1106 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1107 .has_sibling = 0,
1108 .base = &virt_bases[GCC_BASE],
1109 .c = {
1110 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1111 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1112 .ops = &clk_ops_branch,
1113 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1114 },
1115};
1116
1117static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1118 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1119 .has_sibling = 0,
1120 .base = &virt_bases[GCC_BASE],
1121 .c = {
1122 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1123 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1124 .ops = &clk_ops_branch,
1125 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1126 },
1127};
1128
1129static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1130 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1131 .has_sibling = 0,
1132 .base = &virt_bases[GCC_BASE],
1133 .c = {
1134 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1135 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1136 .ops = &clk_ops_branch,
1137 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1138 },
1139};
1140
1141static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1142 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1143 .has_sibling = 0,
1144 .base = &virt_bases[GCC_BASE],
1145 .c = {
1146 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1147 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1148 .ops = &clk_ops_branch,
1149 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1150 },
1151};
1152
1153static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1154 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1155 .has_sibling = 0,
1156 .base = &virt_bases[GCC_BASE],
1157 .c = {
1158 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1159 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1160 .ops = &clk_ops_branch,
1161 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1162 },
1163};
1164
1165static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1166 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1167 .has_sibling = 0,
1168 .base = &virt_bases[GCC_BASE],
1169 .c = {
1170 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1171 .parent = &blsp1_uart1_apps_clk_src.c,
1172 .ops = &clk_ops_branch,
1173 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1174 },
1175};
1176
1177static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1178 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1179 .has_sibling = 0,
1180 .base = &virt_bases[GCC_BASE],
1181 .c = {
1182 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1183 .parent = &blsp1_uart2_apps_clk_src.c,
1184 .ops = &clk_ops_branch,
1185 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1186 },
1187};
1188
1189static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1190 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1191 .has_sibling = 0,
1192 .base = &virt_bases[GCC_BASE],
1193 .c = {
1194 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1195 .parent = &blsp1_uart3_apps_clk_src.c,
1196 .ops = &clk_ops_branch,
1197 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1198 },
1199};
1200
1201static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1202 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1203 .has_sibling = 0,
1204 .base = &virt_bases[GCC_BASE],
1205 .c = {
1206 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1207 .parent = &blsp1_uart4_apps_clk_src.c,
1208 .ops = &clk_ops_branch,
1209 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1210 },
1211};
1212
1213static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1214 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1215 .has_sibling = 0,
1216 .base = &virt_bases[GCC_BASE],
1217 .c = {
1218 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1219 .parent = &blsp1_uart5_apps_clk_src.c,
1220 .ops = &clk_ops_branch,
1221 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1222 },
1223};
1224
1225static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1226 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1227 .has_sibling = 0,
1228 .base = &virt_bases[GCC_BASE],
1229 .c = {
1230 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1231 .parent = &blsp1_uart6_apps_clk_src.c,
1232 .ops = &clk_ops_branch,
1233 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1234 },
1235};
1236
1237static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1238 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1239 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1240 .en_mask = BIT(10),
1241 .base = &virt_bases[GCC_BASE],
1242 .c = {
1243 .dbg_name = "gcc_boot_rom_ahb_clk",
1244 .ops = &clk_ops_vote,
1245 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1246 },
1247};
1248
1249static struct local_vote_clk gcc_ce1_ahb_clk = {
1250 .cbcr_reg = CE1_AHB_CBCR,
1251 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1252 .en_mask = BIT(3),
1253 .base = &virt_bases[GCC_BASE],
1254 .c = {
1255 .dbg_name = "gcc_ce1_ahb_clk",
1256 .ops = &clk_ops_vote,
1257 CLK_INIT(gcc_ce1_ahb_clk.c),
1258 },
1259};
1260
1261static struct local_vote_clk gcc_ce1_axi_clk = {
1262 .cbcr_reg = CE1_AXI_CBCR,
1263 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1264 .en_mask = BIT(4),
1265 .base = &virt_bases[GCC_BASE],
1266 .c = {
1267 .dbg_name = "gcc_ce1_axi_clk",
1268 .ops = &clk_ops_vote,
1269 CLK_INIT(gcc_ce1_axi_clk.c),
1270 },
1271};
1272
1273static struct local_vote_clk gcc_ce1_clk = {
1274 .cbcr_reg = CE1_CBCR,
1275 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1276 .en_mask = BIT(5),
1277 .base = &virt_bases[GCC_BASE],
1278 .c = {
1279 .dbg_name = "gcc_ce1_clk",
1280 .ops = &clk_ops_vote,
1281 CLK_INIT(gcc_ce1_clk.c),
1282 },
1283};
1284
1285static struct branch_clk gcc_gp1_clk = {
1286 .cbcr_reg = GP1_CBCR,
1287 .has_sibling = 0,
1288 .base = &virt_bases[GCC_BASE],
1289 .c = {
1290 .dbg_name = "gcc_gp1_clk",
1291 .parent = &gp1_clk_src.c,
1292 .ops = &clk_ops_branch,
1293 CLK_INIT(gcc_gp1_clk.c),
1294 },
1295};
1296
1297static struct branch_clk gcc_gp2_clk = {
1298 .cbcr_reg = GP2_CBCR,
1299 .has_sibling = 0,
1300 .base = &virt_bases[GCC_BASE],
1301 .c = {
1302 .dbg_name = "gcc_gp2_clk",
1303 .parent = &gp2_clk_src.c,
1304 .ops = &clk_ops_branch,
1305 CLK_INIT(gcc_gp2_clk.c),
1306 },
1307};
1308
1309static struct branch_clk gcc_gp3_clk = {
1310 .cbcr_reg = GP3_CBCR,
1311 .has_sibling = 0,
1312 .base = &virt_bases[GCC_BASE],
1313 .c = {
1314 .dbg_name = "gcc_gp3_clk",
1315 .parent = &gp3_clk_src.c,
1316 .ops = &clk_ops_branch,
1317 CLK_INIT(gcc_gp3_clk.c),
1318 },
1319};
1320
1321static struct branch_clk gcc_lpass_q6_axi_clk = {
1322 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1323 .has_sibling = 1,
1324 .base = &virt_bases[GCC_BASE],
1325 .c = {
1326 .dbg_name = "gcc_lpass_q6_axi_clk",
1327 .ops = &clk_ops_branch,
1328 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1329 },
1330};
1331
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1332static struct branch_clk gcc_mss_cfg_ahb_clk = {
1333 .cbcr_reg = MSS_CFG_AHB_CBCR,
1334 .has_sibling = 1,
1335 .base = &virt_bases[GCC_BASE],
1336 .c = {
1337 .dbg_name = "gcc_mss_cfg_ahb_clk",
1338 .ops = &clk_ops_branch,
1339 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1340 },
1341};
1342
1343static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1344 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1345 .has_sibling = 1,
1346 .base = &virt_bases[GCC_BASE],
1347 .c = {
1348 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1349 .ops = &clk_ops_branch,
1350 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1351 },
1352};
1353
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1354static struct branch_clk gcc_pdm2_clk = {
1355 .cbcr_reg = PDM2_CBCR,
1356 .has_sibling = 0,
1357 .base = &virt_bases[GCC_BASE],
1358 .c = {
1359 .dbg_name = "gcc_pdm2_clk",
1360 .parent = &pdm2_clk_src.c,
1361 .ops = &clk_ops_branch,
1362 CLK_INIT(gcc_pdm2_clk.c),
1363 },
1364};
1365
1366static struct branch_clk gcc_pdm_ahb_clk = {
1367 .cbcr_reg = PDM_AHB_CBCR,
1368 .has_sibling = 1,
1369 .base = &virt_bases[GCC_BASE],
1370 .c = {
1371 .dbg_name = "gcc_pdm_ahb_clk",
1372 .ops = &clk_ops_branch,
1373 CLK_INIT(gcc_pdm_ahb_clk.c),
1374 },
1375};
1376
1377static struct branch_clk gcc_pdm_xo4_clk = {
1378 .cbcr_reg = PDM_XO4_CBCR,
1379 .has_sibling = 1,
1380 .base = &virt_bases[GCC_BASE],
1381 .c = {
1382 .dbg_name = "gcc_pdm_xo4_clk",
1383 .parent = &xo.c,
1384 .ops = &clk_ops_branch,
1385 CLK_INIT(gcc_pdm_xo4_clk.c),
1386 },
1387};
1388
1389static struct branch_clk gcc_periph_noc_ahb_clk = {
1390 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1391 .has_sibling = 1,
1392 .base = &virt_bases[GCC_BASE],
1393 .c = {
1394 .dbg_name = "gcc_periph_noc_ahb_clk",
1395 .ops = &clk_ops_branch,
1396 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1397 },
1398};
1399
1400static struct local_vote_clk gcc_prng_ahb_clk = {
1401 .cbcr_reg = PRNG_AHB_CBCR,
1402 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1403 .en_mask = BIT(13),
1404 .base = &virt_bases[GCC_BASE],
1405 .c = {
1406 .dbg_name = "gcc_prng_ahb_clk",
1407 .ops = &clk_ops_vote,
1408 CLK_INIT(gcc_prng_ahb_clk.c),
1409 },
1410};
1411
1412static struct branch_clk gcc_sdcc1_ahb_clk = {
1413 .cbcr_reg = SDCC1_AHB_CBCR,
1414 .has_sibling = 1,
1415 .base = &virt_bases[GCC_BASE],
1416 .c = {
1417 .dbg_name = "gcc_sdcc1_ahb_clk",
1418 .ops = &clk_ops_branch,
1419 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1420 },
1421};
1422
1423static struct branch_clk gcc_sdcc1_apps_clk = {
1424 .cbcr_reg = SDCC1_APPS_CBCR,
1425 .has_sibling = 0,
1426 .base = &virt_bases[GCC_BASE],
1427 .c = {
1428 .dbg_name = "gcc_sdcc1_apps_clk",
1429 .parent = &sdcc1_apps_clk_src.c,
1430 .ops = &clk_ops_branch,
1431 CLK_INIT(gcc_sdcc1_apps_clk.c),
1432 },
1433};
1434
1435static struct branch_clk gcc_sdcc2_ahb_clk = {
1436 .cbcr_reg = SDCC2_AHB_CBCR,
1437 .has_sibling = 1,
1438 .base = &virt_bases[GCC_BASE],
1439 .c = {
1440 .dbg_name = "gcc_sdcc2_ahb_clk",
1441 .ops = &clk_ops_branch,
1442 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1443 },
1444};
1445
1446static struct branch_clk gcc_sdcc2_apps_clk = {
1447 .cbcr_reg = SDCC2_APPS_CBCR,
1448 .has_sibling = 0,
1449 .base = &virt_bases[GCC_BASE],
1450 .c = {
1451 .dbg_name = "gcc_sdcc2_apps_clk",
1452 .parent = &sdcc2_apps_clk_src.c,
1453 .ops = &clk_ops_branch,
1454 CLK_INIT(gcc_sdcc2_apps_clk.c),
1455 },
1456};
1457
1458static struct branch_clk gcc_sdcc3_ahb_clk = {
1459 .cbcr_reg = SDCC3_AHB_CBCR,
1460 .has_sibling = 1,
1461 .base = &virt_bases[GCC_BASE],
1462 .c = {
1463 .dbg_name = "gcc_sdcc3_ahb_clk",
1464 .ops = &clk_ops_branch,
1465 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1466 },
1467};
1468
1469static struct branch_clk gcc_sdcc3_apps_clk = {
1470 .cbcr_reg = SDCC3_APPS_CBCR,
1471 .has_sibling = 0,
1472 .base = &virt_bases[GCC_BASE],
1473 .c = {
1474 .dbg_name = "gcc_sdcc3_apps_clk",
1475 .parent = &sdcc3_apps_clk_src.c,
1476 .ops = &clk_ops_branch,
1477 CLK_INIT(gcc_sdcc3_apps_clk.c),
1478 },
1479};
1480
1481static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1482 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1483 .has_sibling = 1,
1484 .base = &virt_bases[GCC_BASE],
1485 .c = {
1486 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1487 .ops = &clk_ops_branch,
1488 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1489 },
1490};
1491
1492static struct branch_clk gcc_usb_hs_ahb_clk = {
1493 .cbcr_reg = USB_HS_AHB_CBCR,
1494 .has_sibling = 1,
1495 .base = &virt_bases[GCC_BASE],
1496 .c = {
1497 .dbg_name = "gcc_usb_hs_ahb_clk",
1498 .ops = &clk_ops_branch,
1499 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1500 },
1501};
1502
1503static struct branch_clk gcc_usb_hs_system_clk = {
1504 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1505 .has_sibling = 0,
1506 .bcr_reg = USB_HS_BCR,
1507 .base = &virt_bases[GCC_BASE],
1508 .c = {
1509 .dbg_name = "gcc_usb_hs_system_clk",
1510 .parent = &usb_hs_system_clk_src.c,
1511 .ops = &clk_ops_branch,
1512 CLK_INIT(gcc_usb_hs_system_clk.c),
1513 },
1514};
1515
1516static struct branch_clk gcc_usb_hsic_ahb_clk = {
1517 .cbcr_reg = USB_HSIC_AHB_CBCR,
1518 .has_sibling = 1,
1519 .base = &virt_bases[GCC_BASE],
1520 .c = {
1521 .dbg_name = "gcc_usb_hsic_ahb_clk",
1522 .ops = &clk_ops_branch,
1523 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1524 },
1525};
1526
1527static struct branch_clk gcc_usb_hsic_clk = {
1528 .cbcr_reg = USB_HSIC_CBCR,
1529 .has_sibling = 0,
1530 .bcr_reg = USB_HS_HSIC_BCR,
1531 .base = &virt_bases[GCC_BASE],
1532 .c = {
1533 .dbg_name = "gcc_usb_hsic_clk",
1534 .parent = &usb_hsic_clk_src.c,
1535 .ops = &clk_ops_branch,
1536 CLK_INIT(gcc_usb_hsic_clk.c),
1537 },
1538};
1539
1540static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1541 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1542 .has_sibling = 0,
1543 .base = &virt_bases[GCC_BASE],
1544 .c = {
1545 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1546 .parent = &usb_hsic_io_cal_clk_src.c,
1547 .ops = &clk_ops_branch,
1548 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1549 },
1550};
1551
1552static struct branch_clk gcc_usb_hsic_system_clk = {
1553 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1554 .has_sibling = 0,
1555 .bcr_reg = USB_HS_HSIC_BCR,
1556 .base = &virt_bases[GCC_BASE],
1557 .c = {
1558 .dbg_name = "gcc_usb_hsic_system_clk",
1559 .parent = &usb_hsic_system_clk_src.c,
1560 .ops = &clk_ops_branch,
1561 CLK_INIT(gcc_usb_hsic_system_clk.c),
1562 },
1563};
1564
1565static struct measure_mux_entry measure_mux_GCC[] = {
1566 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1567 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1568 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1569 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1570 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1571 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1572 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1573 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1574 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1575 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1576 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1577 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1578 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1579 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1580 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1581 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1582 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1583 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1584 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1585 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1586 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1587 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1588 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1589 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1590 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1591 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1592 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1593 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1594 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1595 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1596 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1597 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1598 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1599 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1600 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1601 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1602 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1603 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1604 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1605 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1606 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1607 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1608 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1609 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1610 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1611 {&dummy_clk, N_BASES, 0x0000},
1612};
1613
1614static struct pll_vote_clk mmpll0_pll = {
1615 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1616 .en_mask = BIT(0),
1617 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1618 .status_mask = BIT(17),
1619 .base = &virt_bases[MMSS_BASE],
1620 .c = {
1621 .rate = 800000000,
1622 .parent = &xo.c,
1623 .dbg_name = "mmpll0_pll",
1624 .ops = &clk_ops_pll_vote,
1625 CLK_INIT(mmpll0_pll.c),
1626 },
1627};
1628
1629static struct pll_vote_clk mmpll1_pll = {
1630 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1631 .en_mask = BIT(1),
1632 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1633 .status_mask = BIT(17),
1634 .base = &virt_bases[MMSS_BASE],
1635 .c = {
1636 .rate = 1000000000,
1637 .parent = &xo.c,
1638 .dbg_name = "mmpll1_pll",
1639 .ops = &clk_ops_pll_vote,
1640 CLK_INIT(mmpll1_pll.c),
1641 },
1642};
1643
1644static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1645 F_MMSS( 19200000, xo, 1, 0, 0),
1646 F_MMSS( 37500000, gpll0, 16, 0, 0),
1647 F_MMSS( 50000000, gpll0, 12, 0, 0),
1648 F_MMSS( 75000000, gpll0, 8, 0, 0),
1649 F_MMSS( 100000000, gpll0, 6, 0, 0),
1650 F_MMSS( 150000000, gpll0, 4, 0, 0),
1651 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1652 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1653 F_END
1654};
1655
1656static struct rcg_clk axi_clk_src = {
1657 .cmd_rcgr_reg = AXI_CMD_RCGR,
1658 .set_rate = set_rate_hid,
1659 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1660 .current_freq = &rcg_dummy_freq,
1661 .base = &virt_bases[MMSS_BASE],
1662 .c = {
1663 .dbg_name = "axi_clk_src",
1664 .ops = &clk_ops_rcg,
1665 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1666 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1667 CLK_INIT(axi_clk_src.c),
1668 },
1669};
1670
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1671static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1672 F_MMSS( 100000000, gpll0, 6, 0, 0),
1673 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1674 F_END
1675};
1676
1677static struct rcg_clk csi0_clk_src = {
1678 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1679 .set_rate = set_rate_hid,
1680 .freq_tbl = ftbl_camss_csi0_1_clk,
1681 .current_freq = &rcg_dummy_freq,
1682 .base = &virt_bases[MMSS_BASE],
1683 .c = {
1684 .dbg_name = "csi0_clk_src",
1685 .ops = &clk_ops_rcg,
1686 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1687 CLK_INIT(csi0_clk_src.c),
1688 },
1689};
1690
1691static struct rcg_clk csi1_clk_src = {
1692 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1693 .set_rate = set_rate_hid,
1694 .freq_tbl = ftbl_camss_csi0_1_clk,
1695 .current_freq = &rcg_dummy_freq,
1696 .base = &virt_bases[MMSS_BASE],
1697 .c = {
1698 .dbg_name = "csi1_clk_src",
1699 .ops = &clk_ops_rcg,
1700 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1701 CLK_INIT(csi1_clk_src.c),
1702 },
1703};
1704
1705static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1706 F_MMSS( 37500000, gpll0, 16, 0, 0),
1707 F_MMSS( 50000000, gpll0, 12, 0, 0),
1708 F_MMSS( 60000000, gpll0, 10, 0, 0),
1709 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1710 F_MMSS( 100000000, gpll0, 6, 0, 0),
1711 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1712 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1713 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1714 F_MMSS( 200000000, gpll0, 3, 0, 0),
1715 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1716 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1717 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1718 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1719 F_END
1720};
1721
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1722static unsigned long camss_vfe_vfe0_fmax_v2[VDD_DIG_NUM] = {
1723 150000000, 320000000, 400000000,
1724};
1725
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1726static struct rcg_clk vfe0_clk_src = {
1727 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1728 .set_rate = set_rate_hid,
1729 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1730 .current_freq = &rcg_dummy_freq,
1731 .base = &virt_bases[MMSS_BASE],
1732 .c = {
1733 .dbg_name = "vfe0_clk_src",
1734 .ops = &clk_ops_rcg,
1735 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1736 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1737 CLK_INIT(vfe0_clk_src.c),
1738 },
1739};
1740
1741static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1742 F_MMSS( 37500000, gpll0, 16, 0, 0),
1743 F_MMSS( 60000000, gpll0, 10, 0, 0),
1744 F_MMSS( 75000000, gpll0, 8, 0, 0),
1745 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1746 F_MMSS( 100000000, gpll0, 6, 0, 0),
1747 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1748 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1749 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1750 F_END
1751};
1752
1753static struct rcg_clk mdp_clk_src = {
1754 .cmd_rcgr_reg = MDP_CMD_RCGR,
1755 .set_rate = set_rate_hid,
1756 .freq_tbl = ftbl_mdss_mdp_clk,
1757 .current_freq = &rcg_dummy_freq,
1758 .base = &virt_bases[MMSS_BASE],
1759 .c = {
1760 .dbg_name = "mdp_clk_src",
1761 .ops = &clk_ops_rcg,
1762 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1763 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1764 CLK_INIT(mdp_clk_src.c),
1765 },
1766};
1767
1768static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1769 F_MMSS( 75000000, gpll0, 8, 0, 0),
1770 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1771 F_MMSS( 200000000, gpll0, 3, 0, 0),
1772 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1773 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1774 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1775 F_END
1776};
1777
1778static struct rcg_clk jpeg0_clk_src = {
1779 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1780 .set_rate = set_rate_hid,
1781 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1782 .current_freq = &rcg_dummy_freq,
1783 .base = &virt_bases[MMSS_BASE],
1784 .c = {
1785 .dbg_name = "jpeg0_clk_src",
1786 .ops = &clk_ops_rcg,
1787 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1788 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1789 CLK_INIT(jpeg0_clk_src.c),
1790 },
1791};
1792
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1793struct clk_ops clk_ops_pixel_clock;
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1794
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1795static long round_rate_pixel(struct clk *clk, unsigned long rate)
1796{
1797 int frac_num[] = {3, 2, 4, 1};
1798 int frac_den[] = {8, 9, 9, 1};
1799 int delta = 100000;
1800 int i;
1801
1802 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1803 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1804 unsigned long src_rate;
1805
1806 src_rate = clk_round_rate(clk->parent, request);
1807 if ((src_rate < (request - delta)) ||
1808 (src_rate > (request + delta)))
1809 continue;
1810
1811 return (src_rate * frac_num[i]) / frac_den[i];
1812 }
1813
1814 return -EINVAL;
1815}
1816
1817
1818static int set_rate_pixel(struct clk *clk, unsigned long rate)
1819{
1820 struct rcg_clk *rcg = to_rcg_clk(clk);
1821 struct clk_freq_tbl *pixel_freq = rcg->current_freq;
1822 int frac_num[] = {3, 2, 4, 1};
1823 int frac_den[] = {8, 9, 9, 1};
1824 int delta = 100000;
1825 int i, rc;
1826
1827 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1828 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1829 unsigned long src_rate;
1830
1831 src_rate = clk_round_rate(clk->parent, request);
1832 if ((src_rate < (request - delta)) ||
1833 (src_rate > (request + delta)))
1834 continue;
1835
1836 rc = clk_set_rate(clk->parent, src_rate);
1837 if (rc)
1838 return rc;
1839
1840 pixel_freq->div_src_val &= ~BM(4, 0);
1841 if (frac_den[i] == frac_num[i]) {
1842 pixel_freq->m_val = 0;
1843 pixel_freq->n_val = 0;
1844 } else {
1845 pixel_freq->m_val = frac_num[i];
1846 pixel_freq->n_val = ~(frac_den[i] - frac_num[i]);
1847 pixel_freq->d_val = ~frac_den[i];
1848 }
1849 set_rate_mnd(rcg, pixel_freq);
1850 return 0;
1851 }
1852 return -EINVAL;
1853}
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1854
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1855static struct clk_freq_tbl pixel_freq_tbl[] = {
1856 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1857 .src_clk = &pixel_clk_src_8226.c,
1858 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val)
1859 | BVAL(4, 0, 0),
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1860 },
1861 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1862};
1863
1864static struct rcg_clk pclk0_clk_src = {
1865 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1866 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1867 .base = &virt_bases[MMSS_BASE],
1868 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1869 .parent = &pixel_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1870 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1871 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1872 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1873 CLK_INIT(pclk0_clk_src.c),
1874 },
1875};
1876
1877static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1878 F_MMSS( 66700000, gpll0, 9, 0, 0),
1879 F_MMSS( 100000000, gpll0, 6, 0, 0),
1880 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1881 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1882 F_END
1883};
1884
1885static struct rcg_clk vcodec0_clk_src = {
1886 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1887 .set_rate = set_rate_mnd,
1888 .freq_tbl = ftbl_venus0_vcodec0_clk,
1889 .current_freq = &rcg_dummy_freq,
1890 .base = &virt_bases[MMSS_BASE],
1891 .c = {
1892 .dbg_name = "vcodec0_clk_src",
1893 .ops = &clk_ops_rcg_mnd,
1894 VDD_DIG_FMAX_MAP3(LOW, 66670000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1895 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1896 CLK_INIT(vcodec0_clk_src.c),
1897 },
1898};
1899
1900static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1901 F_MMSS( 19200000, xo, 1, 0, 0),
1902 F_END
1903};
1904
1905static struct rcg_clk cci_clk_src = {
1906 .cmd_rcgr_reg = CCI_CMD_RCGR,
1907 .set_rate = set_rate_mnd,
1908 .freq_tbl = ftbl_camss_cci_cci_clk,
1909 .current_freq = &rcg_dummy_freq,
1910 .base = &virt_bases[MMSS_BASE],
1911 .c = {
1912 .dbg_name = "cci_clk_src",
1913 .ops = &clk_ops_rcg_mnd,
1914 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1915 CLK_INIT(cci_clk_src.c),
1916 },
1917};
1918
1919static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1920 F_MMSS( 10000, xo, 16, 1, 120),
1921 F_MMSS( 24000, xo, 16, 1, 50),
1922 F_MMSS( 6000000, gpll0, 10, 1, 10),
1923 F_MMSS( 12000000, gpll0, 10, 1, 5),
1924 F_MMSS( 13000000, gpll0, 4, 13, 150),
1925 F_MMSS( 24000000, gpll0, 5, 1, 5),
1926 F_END
1927};
1928
1929static struct rcg_clk mmss_gp0_clk_src = {
1930 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1931 .set_rate = set_rate_mnd,
1932 .freq_tbl = ftbl_camss_gp0_1_clk,
1933 .current_freq = &rcg_dummy_freq,
1934 .base = &virt_bases[MMSS_BASE],
1935 .c = {
1936 .dbg_name = "mmss_gp0_clk_src",
1937 .ops = &clk_ops_rcg_mnd,
1938 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1939 CLK_INIT(mmss_gp0_clk_src.c),
1940 },
1941};
1942
1943static struct rcg_clk mmss_gp1_clk_src = {
1944 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1945 .set_rate = set_rate_mnd,
1946 .freq_tbl = ftbl_camss_gp0_1_clk,
1947 .current_freq = &rcg_dummy_freq,
1948 .base = &virt_bases[MMSS_BASE],
1949 .c = {
1950 .dbg_name = "mmss_gp1_clk_src",
1951 .ops = &clk_ops_rcg_mnd,
1952 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1953 CLK_INIT(mmss_gp1_clk_src.c),
1954 },
1955};
1956
1957static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1958 F_MMSS( 19200000, xo, 1, 0, 0),
1959 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1960 F_MMSS( 66670000, gpll0, 9, 0, 0),
1961 F_END
1962};
1963
1964static struct rcg_clk mclk0_clk_src = {
1965 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1966 .set_rate = set_rate_mnd,
1967 .freq_tbl = ftbl_camss_mclk0_1_clk,
1968 .current_freq = &rcg_dummy_freq,
1969 .base = &virt_bases[MMSS_BASE],
1970 .c = {
1971 .dbg_name = "mclk0_clk_src",
1972 .ops = &clk_ops_rcg_mnd,
1973 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1974 CLK_INIT(mclk0_clk_src.c),
1975 },
1976};
1977
1978static struct rcg_clk mclk1_clk_src = {
1979 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1980 .set_rate = set_rate_mnd,
1981 .freq_tbl = ftbl_camss_mclk0_1_clk,
1982 .current_freq = &rcg_dummy_freq,
1983 .base = &virt_bases[MMSS_BASE],
1984 .c = {
1985 .dbg_name = "mclk1_clk_src",
1986 .ops = &clk_ops_rcg_mnd,
1987 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1988 CLK_INIT(mclk1_clk_src.c),
1989 },
1990};
1991
1992static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1993 F_MMSS( 100000000, gpll0, 6, 0, 0),
1994 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1995 F_END
1996};
1997
1998static struct rcg_clk csi0phytimer_clk_src = {
1999 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
2000 .set_rate = set_rate_hid,
2001 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2002 .current_freq = &rcg_dummy_freq,
2003 .base = &virt_bases[MMSS_BASE],
2004 .c = {
2005 .dbg_name = "csi0phytimer_clk_src",
2006 .ops = &clk_ops_rcg,
2007 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2008 CLK_INIT(csi0phytimer_clk_src.c),
2009 },
2010};
2011
2012static struct rcg_clk csi1phytimer_clk_src = {
2013 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
2014 .set_rate = set_rate_hid,
2015 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2016 .current_freq = &rcg_dummy_freq,
2017 .base = &virt_bases[MMSS_BASE],
2018 .c = {
2019 .dbg_name = "csi1phytimer_clk_src",
2020 .ops = &clk_ops_rcg,
2021 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2022 CLK_INIT(csi1phytimer_clk_src.c),
2023 },
2024};
2025
2026static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
2027 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2028 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2029 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
2030 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2031 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2032 F_END
2033};
2034
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2035static unsigned long camss_vfe_cpp_fmax_v2[VDD_DIG_NUM] = {
2036 150000000, 320000000, 400000000,
2037};
2038
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2039static struct rcg_clk cpp_clk_src = {
2040 .cmd_rcgr_reg = CPP_CMD_RCGR,
2041 .set_rate = set_rate_hid,
2042 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2043 .current_freq = &rcg_dummy_freq,
2044 .base = &virt_bases[MMSS_BASE],
2045 .c = {
2046 .dbg_name = "cpp_clk_src",
2047 .ops = &clk_ops_rcg,
2048 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2049 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2050 CLK_INIT(cpp_clk_src.c),
2051 },
2052};
2053
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2054static struct clk_freq_tbl byte_freq_tbl[] = {
2055 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2056 .src_clk = &byte_clk_src_8226.c,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2057 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
2058 },
2059 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2060};
2061
2062static struct rcg_clk byte0_clk_src = {
2063 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2064 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2065 .base = &virt_bases[MMSS_BASE],
2066 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2067 .parent = &byte_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2068 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2069 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2070 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2071 CLK_INIT(byte0_clk_src.c),
2072 },
2073};
2074
2075static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2076 F_MDSS( 19200000, xo, 1, 0, 0),
2077 F_END
2078};
2079
2080static struct rcg_clk esc0_clk_src = {
2081 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2082 .set_rate = set_rate_hid,
2083 .freq_tbl = ftbl_mdss_esc0_clk,
2084 .current_freq = &rcg_dummy_freq,
2085 .base = &virt_bases[MMSS_BASE],
2086 .c = {
2087 .dbg_name = "esc0_clk_src",
2088 .ops = &clk_ops_rcg,
2089 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2090 CLK_INIT(esc0_clk_src.c),
2091 },
2092};
2093
2094static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2095 F_MDSS( 19200000, xo, 1, 0, 0),
2096 F_END
2097};
2098
2099static struct rcg_clk vsync_clk_src = {
2100 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2101 .set_rate = set_rate_hid,
2102 .freq_tbl = ftbl_mdss_vsync_clk,
2103 .current_freq = &rcg_dummy_freq,
2104 .base = &virt_bases[MMSS_BASE],
2105 .c = {
2106 .dbg_name = "vsync_clk_src",
2107 .ops = &clk_ops_rcg,
2108 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2109 CLK_INIT(vsync_clk_src.c),
2110 },
2111};
2112
2113static struct branch_clk camss_cci_cci_ahb_clk = {
2114 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2115 .has_sibling = 1,
2116 .base = &virt_bases[MMSS_BASE],
2117 .c = {
2118 .dbg_name = "camss_cci_cci_ahb_clk",
2119 .ops = &clk_ops_branch,
2120 CLK_INIT(camss_cci_cci_ahb_clk.c),
2121 },
2122};
2123
2124static struct branch_clk camss_cci_cci_clk = {
2125 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2126 .has_sibling = 0,
2127 .base = &virt_bases[MMSS_BASE],
2128 .c = {
2129 .dbg_name = "camss_cci_cci_clk",
2130 .parent = &cci_clk_src.c,
2131 .ops = &clk_ops_branch,
2132 CLK_INIT(camss_cci_cci_clk.c),
2133 },
2134};
2135
2136static struct branch_clk camss_csi0_ahb_clk = {
2137 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2138 .has_sibling = 1,
2139 .base = &virt_bases[MMSS_BASE],
2140 .c = {
2141 .dbg_name = "camss_csi0_ahb_clk",
2142 .ops = &clk_ops_branch,
2143 CLK_INIT(camss_csi0_ahb_clk.c),
2144 },
2145};
2146
2147static struct branch_clk camss_csi0_clk = {
2148 .cbcr_reg = CAMSS_CSI0_CBCR,
2149 .has_sibling = 1,
2150 .base = &virt_bases[MMSS_BASE],
2151 .c = {
2152 .dbg_name = "camss_csi0_clk",
2153 .parent = &csi0_clk_src.c,
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(camss_csi0_clk.c),
2156 },
2157};
2158
2159static struct branch_clk camss_csi0phy_clk = {
2160 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2161 .has_sibling = 1,
2162 .base = &virt_bases[MMSS_BASE],
2163 .c = {
2164 .dbg_name = "camss_csi0phy_clk",
2165 .parent = &csi0_clk_src.c,
2166 .ops = &clk_ops_branch,
2167 CLK_INIT(camss_csi0phy_clk.c),
2168 },
2169};
2170
2171static struct branch_clk camss_csi0pix_clk = {
2172 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2173 .has_sibling = 1,
2174 .base = &virt_bases[MMSS_BASE],
2175 .c = {
2176 .dbg_name = "camss_csi0pix_clk",
2177 .parent = &csi0_clk_src.c,
2178 .ops = &clk_ops_branch,
2179 CLK_INIT(camss_csi0pix_clk.c),
2180 },
2181};
2182
2183static struct branch_clk camss_csi0rdi_clk = {
2184 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2185 .has_sibling = 1,
2186 .base = &virt_bases[MMSS_BASE],
2187 .c = {
2188 .dbg_name = "camss_csi0rdi_clk",
2189 .parent = &csi0_clk_src.c,
2190 .ops = &clk_ops_branch,
2191 CLK_INIT(camss_csi0rdi_clk.c),
2192 },
2193};
2194
2195static struct branch_clk camss_csi1_ahb_clk = {
2196 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2197 .has_sibling = 1,
2198 .base = &virt_bases[MMSS_BASE],
2199 .c = {
2200 .dbg_name = "camss_csi1_ahb_clk",
2201 .ops = &clk_ops_branch,
2202 CLK_INIT(camss_csi1_ahb_clk.c),
2203 },
2204};
2205
2206static struct branch_clk camss_csi1_clk = {
2207 .cbcr_reg = CAMSS_CSI1_CBCR,
2208 .has_sibling = 1,
2209 .base = &virt_bases[MMSS_BASE],
2210 .c = {
2211 .dbg_name = "camss_csi1_clk",
2212 .parent = &csi1_clk_src.c,
2213 .ops = &clk_ops_branch,
2214 CLK_INIT(camss_csi1_clk.c),
2215 },
2216};
2217
2218static struct branch_clk camss_csi1phy_clk = {
2219 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2220 .has_sibling = 1,
2221 .base = &virt_bases[MMSS_BASE],
2222 .c = {
2223 .dbg_name = "camss_csi1phy_clk",
2224 .parent = &csi1_clk_src.c,
2225 .ops = &clk_ops_branch,
2226 CLK_INIT(camss_csi1phy_clk.c),
2227 },
2228};
2229
2230static struct branch_clk camss_csi1pix_clk = {
2231 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2232 .has_sibling = 1,
2233 .base = &virt_bases[MMSS_BASE],
2234 .c = {
2235 .dbg_name = "camss_csi1pix_clk",
2236 .parent = &csi1_clk_src.c,
2237 .ops = &clk_ops_branch,
2238 CLK_INIT(camss_csi1pix_clk.c),
2239 },
2240};
2241
2242static struct branch_clk camss_csi1rdi_clk = {
2243 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2244 .has_sibling = 1,
2245 .base = &virt_bases[MMSS_BASE],
2246 .c = {
2247 .dbg_name = "camss_csi1rdi_clk",
2248 .parent = &csi1_clk_src.c,
2249 .ops = &clk_ops_branch,
2250 CLK_INIT(camss_csi1rdi_clk.c),
2251 },
2252};
2253
2254static struct branch_clk camss_csi_vfe0_clk = {
2255 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2256 .has_sibling = 1,
2257 .base = &virt_bases[MMSS_BASE],
2258 .c = {
2259 .dbg_name = "camss_csi_vfe0_clk",
2260 .parent = &vfe0_clk_src.c,
2261 .ops = &clk_ops_branch,
2262 CLK_INIT(camss_csi_vfe0_clk.c),
2263 },
2264};
2265
2266static struct branch_clk camss_gp0_clk = {
2267 .cbcr_reg = CAMSS_GP0_CBCR,
2268 .has_sibling = 0,
2269 .base = &virt_bases[MMSS_BASE],
2270 .c = {
2271 .dbg_name = "camss_gp0_clk",
2272 .parent = &mmss_gp0_clk_src.c,
2273 .ops = &clk_ops_branch,
2274 CLK_INIT(camss_gp0_clk.c),
2275 },
2276};
2277
2278static struct branch_clk camss_gp1_clk = {
2279 .cbcr_reg = CAMSS_GP1_CBCR,
2280 .has_sibling = 0,
2281 .base = &virt_bases[MMSS_BASE],
2282 .c = {
2283 .dbg_name = "camss_gp1_clk",
2284 .parent = &mmss_gp1_clk_src.c,
2285 .ops = &clk_ops_branch,
2286 CLK_INIT(camss_gp1_clk.c),
2287 },
2288};
2289
2290static struct branch_clk camss_ispif_ahb_clk = {
2291 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2292 .has_sibling = 1,
2293 .base = &virt_bases[MMSS_BASE],
2294 .c = {
2295 .dbg_name = "camss_ispif_ahb_clk",
2296 .ops = &clk_ops_branch,
2297 CLK_INIT(camss_ispif_ahb_clk.c),
2298 },
2299};
2300
2301static struct branch_clk camss_jpeg_jpeg0_clk = {
2302 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
2303 .has_sibling = 0,
2304 .base = &virt_bases[MMSS_BASE],
2305 .c = {
2306 .dbg_name = "camss_jpeg_jpeg0_clk",
2307 .parent = &jpeg0_clk_src.c,
2308 .ops = &clk_ops_branch,
2309 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2310 },
2311};
2312
2313static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2314 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2315 .has_sibling = 1,
2316 .base = &virt_bases[MMSS_BASE],
2317 .c = {
2318 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2319 .ops = &clk_ops_branch,
2320 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2321 },
2322};
2323
2324static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2325 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2326 .has_sibling = 1,
2327 .base = &virt_bases[MMSS_BASE],
2328 .c = {
2329 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2330 .parent = &axi_clk_src.c,
2331 .ops = &clk_ops_branch,
2332 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2333 },
2334};
2335
2336static struct branch_clk camss_mclk0_clk = {
2337 .cbcr_reg = CAMSS_MCLK0_CBCR,
2338 .has_sibling = 0,
2339 .base = &virt_bases[MMSS_BASE],
2340 .c = {
2341 .dbg_name = "camss_mclk0_clk",
2342 .parent = &mclk0_clk_src.c,
2343 .ops = &clk_ops_branch,
2344 CLK_INIT(camss_mclk0_clk.c),
2345 },
2346};
2347
2348static struct branch_clk camss_mclk1_clk = {
2349 .cbcr_reg = CAMSS_MCLK1_CBCR,
2350 .has_sibling = 0,
2351 .base = &virt_bases[MMSS_BASE],
2352 .c = {
2353 .dbg_name = "camss_mclk1_clk",
2354 .parent = &mclk1_clk_src.c,
2355 .ops = &clk_ops_branch,
2356 CLK_INIT(camss_mclk1_clk.c),
2357 },
2358};
2359
2360static struct branch_clk camss_micro_ahb_clk = {
2361 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2362 .has_sibling = 1,
2363 .base = &virt_bases[MMSS_BASE],
2364 .c = {
2365 .dbg_name = "camss_micro_ahb_clk",
2366 .ops = &clk_ops_branch,
2367 CLK_INIT(camss_micro_ahb_clk.c),
2368 },
2369};
2370
2371static struct branch_clk camss_phy0_csi0phytimer_clk = {
2372 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2373 .has_sibling = 0,
2374 .base = &virt_bases[MMSS_BASE],
2375 .c = {
2376 .dbg_name = "camss_phy0_csi0phytimer_clk",
2377 .parent = &csi0phytimer_clk_src.c,
2378 .ops = &clk_ops_branch,
2379 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2380 },
2381};
2382
2383static struct branch_clk camss_phy1_csi1phytimer_clk = {
2384 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2385 .has_sibling = 0,
2386 .base = &virt_bases[MMSS_BASE],
2387 .c = {
2388 .dbg_name = "camss_phy1_csi1phytimer_clk",
2389 .parent = &csi1phytimer_clk_src.c,
2390 .ops = &clk_ops_branch,
2391 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2392 },
2393};
2394
2395static struct branch_clk camss_top_ahb_clk = {
2396 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2397 .has_sibling = 1,
2398 .base = &virt_bases[MMSS_BASE],
2399 .c = {
2400 .dbg_name = "camss_top_ahb_clk",
2401 .ops = &clk_ops_branch,
2402 CLK_INIT(camss_top_ahb_clk.c),
2403 },
2404};
2405
2406static struct branch_clk camss_vfe_cpp_ahb_clk = {
2407 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2408 .has_sibling = 1,
2409 .base = &virt_bases[MMSS_BASE],
2410 .c = {
2411 .dbg_name = "camss_vfe_cpp_ahb_clk",
2412 .ops = &clk_ops_branch,
2413 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2414 },
2415};
2416
2417static struct branch_clk camss_vfe_cpp_clk = {
2418 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2419 .has_sibling = 0,
2420 .base = &virt_bases[MMSS_BASE],
2421 .c = {
2422 .dbg_name = "camss_vfe_cpp_clk",
2423 .parent = &cpp_clk_src.c,
2424 .ops = &clk_ops_branch,
2425 CLK_INIT(camss_vfe_cpp_clk.c),
2426 },
2427};
2428
2429static struct branch_clk camss_vfe_vfe0_clk = {
2430 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
2431 .has_sibling = 1,
2432 .base = &virt_bases[MMSS_BASE],
2433 .c = {
2434 .dbg_name = "camss_vfe_vfe0_clk",
2435 .parent = &vfe0_clk_src.c,
2436 .ops = &clk_ops_branch,
2437 CLK_INIT(camss_vfe_vfe0_clk.c),
2438 },
2439};
2440
2441static struct branch_clk camss_vfe_vfe_ahb_clk = {
2442 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2443 .has_sibling = 1,
2444 .base = &virt_bases[MMSS_BASE],
2445 .c = {
2446 .dbg_name = "camss_vfe_vfe_ahb_clk",
2447 .ops = &clk_ops_branch,
2448 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2449 },
2450};
2451
2452static struct branch_clk camss_vfe_vfe_axi_clk = {
2453 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2454 .has_sibling = 1,
2455 .base = &virt_bases[MMSS_BASE],
2456 .c = {
2457 .dbg_name = "camss_vfe_vfe_axi_clk",
2458 .parent = &axi_clk_src.c,
2459 .ops = &clk_ops_branch,
2460 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2461 },
2462};
2463
2464static struct branch_clk mdss_ahb_clk = {
2465 .cbcr_reg = MDSS_AHB_CBCR,
2466 .has_sibling = 1,
2467 .base = &virt_bases[MMSS_BASE],
2468 .c = {
2469 .dbg_name = "mdss_ahb_clk",
2470 .ops = &clk_ops_branch,
2471 CLK_INIT(mdss_ahb_clk.c),
2472 },
2473};
2474
2475static struct branch_clk mdss_axi_clk = {
2476 .cbcr_reg = MDSS_AXI_CBCR,
2477 .has_sibling = 1,
2478 .base = &virt_bases[MMSS_BASE],
2479 .c = {
2480 .dbg_name = "mdss_axi_clk",
2481 .parent = &axi_clk_src.c,
2482 .ops = &clk_ops_branch,
2483 CLK_INIT(mdss_axi_clk.c),
2484 },
2485};
2486
2487static struct branch_clk mdss_byte0_clk = {
2488 .cbcr_reg = MDSS_BYTE0_CBCR,
2489 .has_sibling = 0,
2490 .base = &virt_bases[MMSS_BASE],
2491 .c = {
2492 .dbg_name = "mdss_byte0_clk",
2493 .parent = &byte0_clk_src.c,
2494 .ops = &clk_ops_branch,
2495 CLK_INIT(mdss_byte0_clk.c),
2496 },
2497};
2498
2499static struct branch_clk mdss_esc0_clk = {
2500 .cbcr_reg = MDSS_ESC0_CBCR,
2501 .has_sibling = 0,
2502 .base = &virt_bases[MMSS_BASE],
2503 .c = {
2504 .dbg_name = "mdss_esc0_clk",
2505 .parent = &esc0_clk_src.c,
2506 .ops = &clk_ops_branch,
2507 CLK_INIT(mdss_esc0_clk.c),
2508 },
2509};
2510
2511static struct branch_clk mdss_mdp_clk = {
2512 .cbcr_reg = MDSS_MDP_CBCR,
2513 .has_sibling = 1,
2514 .base = &virt_bases[MMSS_BASE],
2515 .c = {
2516 .dbg_name = "mdss_mdp_clk",
2517 .parent = &mdp_clk_src.c,
2518 .ops = &clk_ops_branch,
2519 CLK_INIT(mdss_mdp_clk.c),
2520 },
2521};
2522
2523static struct branch_clk mdss_mdp_lut_clk = {
2524 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2525 .has_sibling = 1,
2526 .base = &virt_bases[MMSS_BASE],
2527 .c = {
2528 .dbg_name = "mdss_mdp_lut_clk",
2529 .parent = &mdp_clk_src.c,
2530 .ops = &clk_ops_branch,
2531 CLK_INIT(mdss_mdp_lut_clk.c),
2532 },
2533};
2534
2535static struct branch_clk mdss_pclk0_clk = {
2536 .cbcr_reg = MDSS_PCLK0_CBCR,
2537 .has_sibling = 0,
2538 .base = &virt_bases[MMSS_BASE],
2539 .c = {
2540 .dbg_name = "mdss_pclk0_clk",
2541 .parent = &pclk0_clk_src.c,
2542 .ops = &clk_ops_branch,
2543 CLK_INIT(mdss_pclk0_clk.c),
2544 },
2545};
2546
2547static struct branch_clk mdss_vsync_clk = {
2548 .cbcr_reg = MDSS_VSYNC_CBCR,
2549 .has_sibling = 0,
2550 .base = &virt_bases[MMSS_BASE],
2551 .c = {
2552 .dbg_name = "mdss_vsync_clk",
2553 .parent = &vsync_clk_src.c,
2554 .ops = &clk_ops_branch,
2555 CLK_INIT(mdss_vsync_clk.c),
2556 },
2557};
2558
2559static struct branch_clk mmss_misc_ahb_clk = {
2560 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2561 .has_sibling = 1,
2562 .base = &virt_bases[MMSS_BASE],
2563 .c = {
2564 .dbg_name = "mmss_misc_ahb_clk",
2565 .ops = &clk_ops_branch,
2566 CLK_INIT(mmss_misc_ahb_clk.c),
2567 },
2568};
2569
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2570static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2571 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2572 .has_sibling = 1,
2573 .base = &virt_bases[MMSS_BASE],
2574 .c = {
2575 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2578 },
2579};
2580
2581static struct branch_clk mmss_mmssnoc_axi_clk = {
2582 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2583 .has_sibling = 1,
2584 .base = &virt_bases[MMSS_BASE],
2585 .c = {
2586 .dbg_name = "mmss_mmssnoc_axi_clk",
2587 .parent = &axi_clk_src.c,
2588 .ops = &clk_ops_branch,
2589 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2590 },
2591};
2592
2593static struct branch_clk mmss_s0_axi_clk = {
2594 .cbcr_reg = MMSS_S0_AXI_CBCR,
2595 .has_sibling = 0,
2596 .max_div = 0,
2597 .base = &virt_bases[MMSS_BASE],
2598 .c = {
2599 .dbg_name = "mmss_s0_axi_clk",
2600 .parent = &axi_clk_src.c,
2601 .ops = &clk_ops_branch,
2602 CLK_INIT(mmss_s0_axi_clk.c),
2603 .depends = &mmss_mmssnoc_axi_clk.c,
2604 },
2605};
2606
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2607static struct branch_clk oxili_gfx3d_clk = {
2608 .cbcr_reg = OXILI_GFX3D_CBCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2609 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2610 .max_div = 0,
2611 .base = &virt_bases[MMSS_BASE],
2612 .c = {
2613 .dbg_name = "oxili_gfx3d_clk",
2614 .parent = &gfx3d_clk_src.c,
2615 .ops = &clk_ops_branch,
2616 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2617 },
2618};
2619
2620static struct branch_clk oxilicx_ahb_clk = {
2621 .cbcr_reg = OXILICX_AHB_CBCR,
2622 .has_sibling = 1,
2623 .base = &virt_bases[MMSS_BASE],
2624 .c = {
2625 .dbg_name = "oxilicx_ahb_clk",
2626 .ops = &clk_ops_branch,
2627 CLK_INIT(oxilicx_ahb_clk.c),
2628 },
2629};
2630
2631static struct branch_clk oxilicx_axi_clk = {
2632 .cbcr_reg = OXILICX_AXI_CBCR,
2633 .has_sibling = 1,
2634 .base = &virt_bases[MMSS_BASE],
2635 .c = {
2636 .dbg_name = "oxilicx_axi_clk",
2637 .parent = &axi_clk_src.c,
2638 .ops = &clk_ops_branch,
2639 CLK_INIT(oxilicx_axi_clk.c),
2640 },
2641};
2642
2643static struct branch_clk venus0_ahb_clk = {
2644 .cbcr_reg = VENUS0_AHB_CBCR,
2645 .has_sibling = 1,
2646 .base = &virt_bases[MMSS_BASE],
2647 .c = {
2648 .dbg_name = "venus0_ahb_clk",
2649 .ops = &clk_ops_branch,
2650 CLK_INIT(venus0_ahb_clk.c),
2651 },
2652};
2653
2654static struct branch_clk venus0_axi_clk = {
2655 .cbcr_reg = VENUS0_AXI_CBCR,
2656 .has_sibling = 1,
2657 .base = &virt_bases[MMSS_BASE],
2658 .c = {
2659 .dbg_name = "venus0_axi_clk",
2660 .parent = &axi_clk_src.c,
2661 .ops = &clk_ops_branch,
2662 CLK_INIT(venus0_axi_clk.c),
2663 },
2664};
2665
2666static struct branch_clk venus0_vcodec0_clk = {
2667 .cbcr_reg = VENUS0_VCODEC0_CBCR,
2668 .has_sibling = 0,
2669 .base = &virt_bases[MMSS_BASE],
2670 .c = {
2671 .dbg_name = "venus0_vcodec0_clk",
2672 .parent = &vcodec0_clk_src.c,
2673 .ops = &clk_ops_branch,
2674 CLK_INIT(venus0_vcodec0_clk.c),
2675 },
2676};
2677
2678static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2679 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2680 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2681 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2682 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2683 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2684 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2685 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2686 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2687 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2688 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2689 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2690 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2691 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2692 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2693 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2694 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2695 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2696 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2697 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2698 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2699 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2700 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2701 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2702 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2703 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2704 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2705 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2706 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2707 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2708 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2709 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2710 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2711 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2712 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2713 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2714 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2715 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2716 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2717 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2718 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2719 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2720 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2721 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2722 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2723 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2724 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2725 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2726 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2727 {&dummy_clk, N_BASES, 0x0000},
2728};
2729
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2730static struct branch_clk q6ss_ahb_lfabif_clk = {
2731 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2732 .has_sibling = 1,
2733 .base = &virt_bases[LPASS_BASE],
2734 .c = {
2735 .dbg_name = "q6ss_ahb_lfabif_clk",
2736 .ops = &clk_ops_branch,
2737 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2738 },
2739};
2740
2741static struct branch_clk q6ss_ahbm_clk = {
2742 .cbcr_reg = Q6SS_AHBM_CBCR,
2743 .has_sibling = 1,
2744 .base = &virt_bases[LPASS_BASE],
2745 .c = {
2746 .dbg_name = "q6ss_ahbm_clk",
2747 .ops = &clk_ops_branch,
2748 CLK_INIT(q6ss_ahbm_clk.c),
2749 },
2750};
2751
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2752static struct branch_clk q6ss_xo_clk = {
2753 .cbcr_reg = Q6SS_XO_CBCR,
2754 .has_sibling = 1,
2755 .bcr_reg = Q6SS_BCR,
2756 .base = &virt_bases[LPASS_BASE],
2757 .c = {
2758 .dbg_name = "q6ss_xo_clk",
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2759 .ops = &clk_ops_branch,
2760 CLK_INIT(q6ss_xo_clk.c),
2761 },
2762};
2763
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2764static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2765 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2766 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2767 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2768 {&dummy_clk, N_BASES, 0x0000},
2769};
2770
2771
2772static DEFINE_CLK_MEASURE(apc0_m_clk);
2773static DEFINE_CLK_MEASURE(apc1_m_clk);
2774static DEFINE_CLK_MEASURE(apc2_m_clk);
2775static DEFINE_CLK_MEASURE(apc3_m_clk);
2776static DEFINE_CLK_MEASURE(l2_m_clk);
2777
2778static struct measure_mux_entry measure_mux_APSS[] = {
2779 {&apc0_m_clk, APCS_BASE, 0x00010},
2780 {&apc1_m_clk, APCS_BASE, 0x00114},
2781 {&apc2_m_clk, APCS_BASE, 0x00220},
2782 {&apc3_m_clk, APCS_BASE, 0x00324},
2783 {&l2_m_clk, APCS_BASE, 0x01000},
2784 {&dummy_clk, N_BASES, 0x0000}
2785};
2786
2787#define APCS_SH_PLL_MODE (0x000)
2788#define APCS_SH_PLL_L_VAL (0x004)
2789#define APCS_SH_PLL_M_VAL (0x008)
2790#define APCS_SH_PLL_N_VAL (0x00C)
2791#define APCS_SH_PLL_USER_CTL (0x010)
2792#define APCS_SH_PLL_CONFIG_CTL (0x014)
2793#define APCS_SH_PLL_STATUS (0x01C)
2794
2795enum vdd_sr2_pll_levels {
2796 VDD_SR2_PLL_OFF,
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2797 VDD_SR2_PLL_SVS,
2798 VDD_SR2_PLL_NOM,
2799 VDD_SR2_PLL_TUR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2800 VDD_SR2_PLL_NUM
2801};
2802
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]2803static int vdd_sr2_levels[] = {
2804 0, RPM_REGULATOR_CORNER_NONE, /* VDD_SR2_PLL_OFF */
2805 1800000, RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_SR2_PLL_SVS */
2806 1800000, RPM_REGULATOR_CORNER_NORMAL, /* VDD_SR2_PLL_NOM */
2807 1800000, RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_SR2_PLL_TUR */
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2808};
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2809
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]2810static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
2811 vdd_sr2_levels, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2812
2813static struct pll_freq_tbl apcs_pll_freq[] = {
Patrick Daly83806032013-03-25 15:18:24 -0700[diff] [blame]2814 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2815 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2816 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyf363c252013-03-21 12:08:37 -0700[diff] [blame]2817 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2818 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
2819 PLL_F_END
2820};
2821
2822static struct pll_clk a7sspll = {
2823 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2824 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2825 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2826 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2827 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2828 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2829 .freq_tbl = apcs_pll_freq,
2830 .masks = {
2831 .vco_mask = BM(29, 28),
2832 .pre_div_mask = BIT(12),
2833 .post_div_mask = BM(9, 8),
2834 .mn_en_mask = BIT(24),
2835 .main_output_mask = BIT(0),
2836 },
2837 .base = &virt_bases[APCS_PLL_BASE],
2838 .c = {
Patrick Daly9bdc8a52013-03-21 19:12:40 -0700[diff] [blame]2839 .parent = &xo_a_clk.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2840 .dbg_name = "a7sspll",
2841 .ops = &clk_ops_sr2_pll,
2842 .vdd_class = &vdd_sr2_pll,
2843 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2844 [VDD_SR2_PLL_SVS] = 1000000000,
2845 [VDD_SR2_PLL_NOM] = 1900000000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2846 },
2847 .num_fmax = VDD_SR2_PLL_NUM,
2848 CLK_INIT(a7sspll.c),
2849 /*
2850 * Need to skip handoff of the acpu pll to avoid
2851 * turning off the pll when the cpu is using it
2852 */
2853 .flags = CLKFLAG_SKIP_HANDOFF,
2854 },
2855};
2856
2857static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2858static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2859static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2860static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2861static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2862static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2863
2864static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2865static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2866static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2867static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2868static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2869static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2870static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2871
2872static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2873
Patrick Daly4aef16c2013-04-17 15:44:12 -0700[diff] [blame]2874static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, 100000000);
2875static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, 100000000);
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]2876
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2877static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c);
2878static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c);
2879static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c);
2880static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c);
2881static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c);
2882
2883
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2884#ifdef CONFIG_DEBUG_FS
2885static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2886{
2887 struct measure_clk *clk = to_measure_clk(c);
2888 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2889 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2890 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2891 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2892 measure_mux_GCC,
2893 measure_mux_MMSS,
2894 measure_mux_LPASS,
2895 measure_mux_APSS,
2896 NULL
2897 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2898 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2899
2900 if (!parent)
2901 return -EINVAL;
2902
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2903 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2904 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2905 if (mux->c == parent) {
2906 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2907 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2908 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2909 }
2910
2911 if (mux->c == &dummy_clk)
2912 return -EINVAL;
2913
2914 spin_lock_irqsave(&local_clock_reg_lock, flags);
2915 /*
2916 * Program the test vector, measurement period (sample_ticks)
2917 * and scaling multiplier.
2918 */
2919 clk->sample_ticks = 0x10000;
2920 clk->multiplier = 1;
2921
2922 switch (mux->base) {
2923
2924 case GCC_BASE:
2925 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2926 clk_sel = mux->debug_mux;
2927 break;
2928
2929 case MMSS_BASE:
2930 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2931 clk_sel = 0x02C;
2932 regval = BVAL(11, 0, mux->debug_mux);
2933 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2934
2935 /* Activate debug clock output */
2936 regval |= BIT(16);
2937 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2938 break;
2939
2940 case LPASS_BASE:
2941 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2942 clk_sel = 0x161;
2943 regval = BVAL(11, 0, mux->debug_mux);
2944 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2945
2946 /* Activate debug clock output */
2947 regval |= BIT(20);
2948 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2949 break;
2950
2951 case APCS_BASE:
2952 clk->multiplier = 4;
2953 clk_sel = 362;
2954 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2955 regval &= ~0xC0037335;
2956 /* configure a divider of 4 */
2957 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2958 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2959 break;
2960
2961 default:
2962 return -EINVAL;
2963 }
2964
2965 /* Set debug mux clock index */
2966 regval = BVAL(8, 0, clk_sel);
2967 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2968
2969 /* Activate debug clock output */
2970 regval |= BIT(16);
2971 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2972
2973 /* Make sure test vector is set before starting measurements. */
2974 mb();
2975 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2976
2977 return 0;
2978}
2979
2980/* Sample clock for 'ticks' reference clock ticks. */
2981static u32 run_measurement(unsigned ticks)
2982{
2983 /* Stop counters and set the XO4 counter start value. */
2984 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2985
2986 /* Wait for timer to become ready. */
2987 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2988 BIT(25)) != 0)
2989 cpu_relax();
2990
2991 /* Run measurement and wait for completion. */
2992 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2993 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2994 BIT(25)) == 0)
2995 cpu_relax();
2996
2997 /* Return measured ticks. */
2998 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2999 BM(24, 0);
3000}
3001
3002/*
3003 * Perform a hardware rate measurement for a given clock.
3004 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
3005 */
3006static unsigned long measure_clk_get_rate(struct clk *c)
3007{
3008 unsigned long flags;
3009 u32 gcc_xo4_reg_backup;
3010 u64 raw_count_short, raw_count_full;
3011 struct measure_clk *clk = to_measure_clk(c);
3012 unsigned ret;
3013
3014 ret = clk_prepare_enable(&xo.c);
3015 if (ret) {
3016 pr_warn("CXO clock failed to enable. Can't measure\n");
3017 return 0;
3018 }
3019
3020 spin_lock_irqsave(&local_clock_reg_lock, flags);
3021
3022 /* Enable CXO/4 and RINGOSC branch. */
3023 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3024 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3025
3026 /*
3027 * The ring oscillator counter will not reset if the measured clock
3028 * is not running. To detect this, run a short measurement before
3029 * the full measurement. If the raw results of the two are the same
3030 * then the clock must be off.
3031 */
3032
3033 /* Run a short measurement. (~1 ms) */
3034 raw_count_short = run_measurement(0x1000);
3035 /* Run a full measurement. (~14 ms) */
3036 raw_count_full = run_measurement(clk->sample_ticks);
3037
3038 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3039
3040 /* Return 0 if the clock is off. */
3041 if (raw_count_full == raw_count_short) {
3042 ret = 0;
3043 } else {
3044 /* Compute rate in Hz. */
3045 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
3046 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
3047 ret = (raw_count_full * clk->multiplier);
3048 }
3049
3050 writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG));
3051 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3052
3053 clk_disable_unprepare(&xo.c);
3054
3055 return ret;
3056}
3057
3058#else /* !CONFIG_DEBUG_FS */
3059static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3060{
3061 return -EINVAL;
3062}
3063
3064static unsigned long measure_clk_get_rate(struct clk *clk)
3065{
3066 return 0;
3067}
3068#endif /* CONFIG_DEBUG_FS */
3069
3070static struct clk_ops clk_ops_measure = {
3071 .set_parent = measure_clk_set_parent,
3072 .get_rate = measure_clk_get_rate,
3073};
3074
3075static struct measure_clk measure_clk = {
3076 .c = {
3077 .dbg_name = "measure_clk",
3078 .ops = &clk_ops_measure,
3079 CLK_INIT(measure_clk.c),
3080 },
3081 .multiplier = 1,
3082};
3083
3084static struct clk_lookup msm_clocks_8226[] = {
3085 /* Debug Clocks */
3086 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3087 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3088 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3089 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3090 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3091 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3092
3093 /* PIL-LPASS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3094 CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3095 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3096 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3097 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3098 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3099
3100 /* PIL-MODEM */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3101 CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3102 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3103 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3104 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
3105
3106 /* PIL-PRONTO */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3107 CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3108
3109 /* PIL-VENUS */
3110 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3111 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3112 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3113 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3114 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3115
3116 /* ACPUCLOCK */
3117 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3118 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3119 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
3120
3121 /* WCNSS CLOCKS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3122 CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"),
Vikram Mulukutla7e5b3112013-04-15 16:32:40 -0700[diff] [blame]3123 CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3124
3125 /* BUS DRIVER */
3126 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3127 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3128 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3129 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3130 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3131 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3132 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3133 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3134 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3135 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3136 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3137 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3138 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3139
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3140 /* CoreSight clocks */
3141 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3142 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3143 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3144 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3145 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3146 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3147 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3148 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3149 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3150 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3151 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3152 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3153 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3154 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3155 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3156 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3157 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3158 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3159 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3160 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3161 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3162 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3163 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3164 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3165 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3166 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3167 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3168 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3169 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3170 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3171 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3172 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3173 CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3174
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3175 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3176 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3177 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3178 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3179 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3180 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3181 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3182 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3183 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3184 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3185 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3186 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3187 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3188 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Aparna Das664239c2013-05-03 20:13:50 -0700[diff] [blame]3189 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.jtagmm"),
3190 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.jtagmm"),
3191 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.jtagmm"),
3192 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3193 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3194 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3195 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3196 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3197 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3198 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3199 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3200 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3201 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3202 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3203 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3204 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3205 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3206 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3207 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"),
3208
3209 CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3210
3211 /* HSUSB-OTG Clocks */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3212 CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3213 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3214 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3215
3216 /* SPS CLOCKS */
3217 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3218 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3219 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3220 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3221
3222 /* I2C Clocks */
3223 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3224 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3225
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3226 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3227 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3228
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3229 /* lsuart-v14 Clocks */
3230 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3231 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3232
3233 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3234 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3235
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3236 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3237 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3238
3239 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3240 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3241 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3242 CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3243
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3244 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3245 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3246 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3247 CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"),
3248
3249 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""),
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3250
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3251 /* SDCC */
3252 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3253 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3254 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3255 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3256
3257 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3258 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3259 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3260 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3261
3262 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3263 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3264
3265 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3266 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3267
3268
3269 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3270 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3271 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3272 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3273 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3274 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3275 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3276 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3277 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3278 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3279 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3280
3281 CLK_LOOKUP("gpll0", gpll0.c, ""),
3282 CLK_LOOKUP("gpll1", gpll1.c, ""),
3283 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3284 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3285
3286 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3287 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3288 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
3289 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""),
3290 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3291 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3292 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3293 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3294 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3295 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3296 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3297 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3298 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3299 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3300 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3301 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3302 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3303 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3304 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3305 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3306 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3307
3308 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3309 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3310 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3311 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3312 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3313 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3314 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3315 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3316
3317 /* Multimedia clocks */
3318 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3319 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3320 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
Aravind Venkateswaran6b6d9c42013-05-06 16:10:03 -0700[diff] [blame]3321 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922800.qcom,mdss_dsi"),
3322 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd922800.qcom,mdss_dsi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3323
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3324 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3325 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3326 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3327 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3328 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3329 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3330
3331 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3332 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3333
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]3334 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fd8c1024.qcom,gdsc"),
3335 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd8c2304.qcom,gdsc"),
3336 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd8c2304.qcom,gdsc"),
3337 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fd8c35a4.qcom,gdsc"),
3338 CLK_LOOKUP("core_clk", camss_vfe_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3339 CLK_LOOKUP("csi_clk", camss_csi_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3340 CLK_LOOKUP("cpp_clk", camss_vfe_cpp_clk.c, "fd8c36a4.qcom,gdsc"),
3341 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fd8c4034.qcom,gdsc"),
3342
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3343 /* MM sensor clocks */
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3344 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3345 CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3346 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"),
3347 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3348 CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3349 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3350
3351 /* CCI clocks */
3352 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3353 "fda0c000.qcom,cci"),
3354 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3355 "fda0c000.qcom,cci"),
3356 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3357 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3358
3359 /* CSIPHY clocks */
3360 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3361 "fda0ac00.qcom,csiphy"),
3362 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3363 "fda0ac00.qcom,csiphy"),
3364 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3365 "fda0ac00.qcom,csiphy"),
3366 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3367 "fda0ac00.qcom,csiphy"),
3368 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3369 "fda0b000.qcom,csiphy"),
3370 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3371 "fda0b000.qcom,csiphy"),
3372 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3373 "fda0b000.qcom,csiphy"),
3374 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3375 "fda0b000.qcom,csiphy"),
3376
3377 /* CSID clocks */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3378 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3379 "fda08000.qcom,csid"),
3380 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3381 "fda08000.qcom,csid"),
3382 CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c,
3383 "fda08000.qcom,csid"),
3384 CLK_LOOKUP("csi_src_clk", csi0_clk_src.c,
3385 "fda08000.qcom,csid"),
3386 CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c,
3387 "fda08000.qcom,csid"),
3388 CLK_LOOKUP("csi_clk", camss_csi0_clk.c,
3389 "fda08000.qcom,csid"),
3390 CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c,
3391 "fda08000.qcom,csid"),
3392 CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c,
3393 "fda08000.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3394
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3395
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3396 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3397 "fda08400.qcom,csid"),
3398 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3399 "fda08400.qcom,csid"),
3400 CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c,
3401 "fda08400.qcom,csid"),
3402 CLK_LOOKUP("csi_src_clk", csi1_clk_src.c,
3403 "fda08400.qcom,csid"),
3404 CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c,
3405 "fda08400.qcom,csid"),
3406 CLK_LOOKUP("csi_clk", camss_csi1_clk.c,
3407 "fda08400.qcom,csid"),
3408 CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c,
3409 "fda08400.qcom,csid"),
3410 CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c,
3411 "fda08400.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3412
3413 /* ISPIF clocks */
Sreesudhan Ramakrish Ramkumarecdcfce2013-04-17 12:58:26 -0700[diff] [blame]3414 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3415 "fda0a000.qcom,ispif"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3416 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3417 "fda0a000.qcom,ispif"),
3418 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3419 "fda0a000.qcom,ispif"),
3420
3421 /* VFE clocks */
3422 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3423 "fda10000.qcom,vfe"),
3424 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3425 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3426 "fda10000.qcom,vfe"),
3427 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3428 "fda10000.qcom,vfe"),
3429 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3430 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3431
3432 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3433 "fda44000.qcom,iommu"),
3434 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3435 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3436
3437 /* Jpeg Clocks */
3438 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3439 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3440 "fda1c000.qcom,jpeg"),
3441 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3442 "fda1c000.qcom,jpeg"),
3443 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3444 "fda1c000.qcom,jpeg"),
3445
3446 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3447 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3448 "fda64000.qcom,iommu"),
3449 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3450 "fda64000.qcom,iommu"),
3451
Su Liudb7b2062013-03-14 20:57:15 -0700[diff] [blame]3452 CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c,
3453 "fda04000.qcom,cpp"),
3454 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3455 "fda04000.qcom,cpp"),
3456 CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c,
3457 "fda04000.qcom,cpp"),
3458 CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"),
3459 CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"),
3460 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"),
3461 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3462 "fda04000.qcom,cpp"),
3463 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"),
3464
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3465 /* KGSL Clocks */
3466 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3467 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3468 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3469 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3470
3471 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3472 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3473 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3474
3475 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3476
3477 /* Venus Clocks */
3478 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3479 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3480 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3481
3482 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3483 "fdc84000.qcom,iommu"),
3484 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3485 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3486 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3487 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3488 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3489 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3490
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3491 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3492 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3493 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3494
3495 /* Audio clocks */
3496 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3497 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3498 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3499 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3500 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3501 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3502
Hariprasad Dhalinarasimha1fa54392013-03-21 15:57:51 -0700[diff] [blame]3503 /* Add QCEDEV clocks */
3504 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"),
3505 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"),
3506 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"),
3507 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"),
3508
3509 /* Add QCRYPTO clocks */
3510 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd404000.qcom,qcrypto"),
3511 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd404000.qcom,qcrypto"),
3512 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd404000.qcom,qcrypto"),
3513 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd404000.qcom,qcrypto"),
3514
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3515 /* DSI PLL clocks */
3516 CLK_LOOKUP("", dsi_vco_clk_8226.c, ""),
3517 CLK_LOOKUP("", analog_postdiv_clk_8226.c, ""),
3518 CLK_LOOKUP("", indirect_path_div2_clk_8226.c, ""),
3519 CLK_LOOKUP("", pixel_clk_src_8226.c, ""),
3520 CLK_LOOKUP("", byte_mux_8226.c, ""),
3521 CLK_LOOKUP("", byte_clk_src_8226.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3522};
3523
3524static struct clk_lookup msm_clocks_8226_rumi[] = {
3525 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3526 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3527 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3528 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3529 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3530 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3531 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3532 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3533 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3534 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3535};
3536
3537struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3538 .table = msm_clocks_8226_rumi,
3539 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3540};
3541
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3542static void __init reg_init(void)
3543{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3544 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3545
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3546 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3547 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3548 regval |= BIT(0);
3549 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3550
3551 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3552 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3553 */
3554 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3555}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3556
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3557static void __init msm8226_clock_post_init(void)
3558{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3559 /*
3560 * Hold an active set vote for CXO; this is because CXO is expected
3561 * to remain on whenever CPUs aren't power collapsed.
3562 */
3563 clk_prepare_enable(&xo_a_clk.c);
3564
Patrick Dalyfd3df102013-05-28 18:08:22 -0700[diff] [blame]3565 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3566 clk_set_rate(&axi_clk_src.c, 200000000);
3567
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3568 /* Set rates for single-rate clocks. */
3569 clk_set_rate(&usb_hs_system_clk_src.c,
3570 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3571 clk_set_rate(&usb_hsic_clk_src.c,
3572 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3573 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3574 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3575 clk_set_rate(&usb_hsic_system_clk_src.c,
3576 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3577 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3578 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3579 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3580 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3581 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3582 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3583}
3584
3585#define GCC_CC_PHYS 0xFC400000
3586#define GCC_CC_SIZE SZ_16K
3587
3588#define MMSS_CC_PHYS 0xFD8C0000
3589#define MMSS_CC_SIZE SZ_256K
3590
3591#define LPASS_CC_PHYS 0xFE000000
3592#define LPASS_CC_SIZE SZ_256K
3593
3594#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3595#define APCS_KPSS_SH_PLL_SIZE SZ_64
3596
3597#define APCS_KPSS_GLB_PHYS 0xF9011000
3598#define APCS_KPSS_GLB_SIZE SZ_4K
3599
3600
3601static void __init msm8226_clock_pre_init(void)
3602{
3603 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3604 if (!virt_bases[GCC_BASE])
3605 panic("clock-8226: Unable to ioremap GCC memory!");
3606
3607 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3608 if (!virt_bases[MMSS_BASE])
3609 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3610
3611 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3612 if (!virt_bases[LPASS_BASE])
3613 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3614
3615 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3616 APCS_KPSS_GLB_SIZE);
3617 if (!virt_bases[APCS_BASE])
3618 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3619
3620 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3621 APCS_KPSS_SH_PLL_SIZE);
3622 if (!virt_bases[APCS_PLL_BASE])
3623 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3624
3625 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3626
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3627 vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig");
3628 if (IS_ERR(vdd_dig.regulator[0]))
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3629 panic("clock-8226: Unable to get the vdd_dig regulator!");
3630
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3631 vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll");
3632 if (IS_ERR(vdd_sr2_pll.regulator[0]))
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3633 panic("clock-8226: Unable to get the sr2_pll regulator!");
3634
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]3635 vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig");
3636 if (IS_ERR(vdd_sr2_pll.regulator[1]))
3637 panic("clock-8226: Unable to get the vdd_sr2_dig regulator!");
3638
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3639 /*
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3640 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3641 * source. Sleep set vote is 0.
3642 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3643 * access mmss clock controller registers.
3644 */
3645 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3646
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3647 enable_rpm_scaling();
3648
3649 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3650
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]3651 /* v2 specific changes */
3652 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
3653 cpp_clk_src.c.fmax = camss_vfe_cpp_fmax_v2;
3654 vfe0_clk_src.c.fmax = camss_vfe_vfe0_fmax_v2;
3655 }
3656
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3657 clk_ops_pixel_clock = clk_ops_pixel;
3658 clk_ops_pixel_clock.set_rate = set_rate_pixel;
3659 clk_ops_pixel_clock.round_rate = round_rate_pixel;
3660
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3661 /*
3662 * MDSS needs the ahb clock and needs to init before we register the
3663 * lookup table.
3664 */
3665 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3666}
3667
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3668struct clock_init_data msm8226_clock_init_data __initdata = {
3669 .table = msm_clocks_8226,
3670 .size = ARRAY_SIZE(msm_clocks_8226),
3671 .pre_init = msm8226_clock_pre_init,
3672 .post_init = msm8226_clock_post_init,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3673};