blob: 49c7219826f918d10dae4f08d4c474988706a6ae [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7#undef DEBUG
8
9#ifdef DEBUG
10#define DBG(x...) printk(x)
11#else
12#define DBG(x...)
13#endif
14
15#define PCI_PROBE_BIOS 0x0001
16#define PCI_PROBE_CONF1 0x0002
17#define PCI_PROBE_CONF2 0x0004
18#define PCI_PROBE_MMCONF 0x0008
Linus Torvalds79e453d2006-09-19 08:15:22 -070019#define PCI_PROBE_MASK 0x000f
Andi Kleen0637a702006-09-26 10:52:41 +020020#define PCI_PROBE_NOEARLY 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#define PCI_NO_CHECKS 0x0400
23#define PCI_USE_PIRQ_MASK 0x0800
24#define PCI_ASSIGN_ROMS 0x1000
25#define PCI_BIOS_IRQ_SCAN 0x2000
26#define PCI_ASSIGN_ALL_BUSSES 0x4000
Gary Hade036fff42007-10-03 15:56:14 -070027#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
Linus Torvalds236e9462009-06-24 16:23:03 -070028#define PCI_USE__CRS 0x10000
Yinghai Lu5f0b2972008-04-14 16:08:25 -070029#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
Robert Richter3a27dd12008-06-12 20:19:23 +020030#define PCI_HAS_IO_ECS 0x40000
Linus Torvaldsdc7c65d2008-07-16 17:25:46 -070031#define PCI_NOASSIGN_ROMS 0x80000
Bjorn Helgaas7bc5e3f2010-02-23 10:24:41 -070032#define PCI_ROOT_NO_CRS 0x100000
Mike Habeck7bd1c362010-05-12 11:14:32 -070033#define PCI_NOASSIGN_BARS 0x200000
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
35extern unsigned int pci_probe;
jayalk@intworks.biz120bb422005-03-21 20:20:42 -080036extern unsigned long pirq_table_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Matt Domsch6b4b78f2006-09-29 15:23:23 -050038enum pci_bf_sort_state {
39 pci_bf_sort_default,
40 pci_force_nobf,
41 pci_force_bf,
42 pci_dmi_bf,
43};
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/* pci-i386.c */
46
47extern unsigned int pcibios_max_latency;
48
49void pcibios_resource_survey(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51/* pci-pc.c */
52
53extern int pcibios_last_bus;
54extern struct pci_bus *pci_root_bus;
55extern struct pci_ops pci_root_ops;
56
Aristeu Rozanski5707b242009-07-09 22:21:13 -030057void pcibios_scan_specific_bus(int busn);
58
Linus Torvalds1da177e2005-04-16 15:20:36 -070059/* pci-irq.c */
60
61struct irq_info {
62 u8 bus, devfn; /* Bus, device and function */
63 struct {
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +053064 u8 link; /* IRQ line ID, chipset dependent,
65 0 = not routed */
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 u16 bitmap; /* Available IRQs */
67 } __attribute__((packed)) irq[4];
68 u8 slot; /* Slot number, 0=onboard */
69 u8 rfu;
70} __attribute__((packed));
71
72struct irq_routing_table {
73 u32 signature; /* PIRQ_SIGNATURE should be here */
74 u16 version; /* PIRQ_VERSION */
75 u16 size; /* Table size in bytes */
76 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +053077 u16 exclusive_irqs; /* IRQs devoted exclusively to
78 PCI usage */
79 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
80 interrupt router */
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 u32 miniport_data; /* Crap */
82 u8 rfu[11];
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +053083 u8 checksum; /* Modulo 256 checksum must give 0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 struct irq_info slots[0];
85} __attribute__((packed));
86
87extern unsigned int pcibios_irq_mask;
88
Thomas Gleixnerd19f61f2010-02-17 14:35:25 +000089extern raw_spinlock_t pci_config_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -070090
91extern int (*pcibios_enable_irq)(struct pci_dev *dev);
David Shaohua Li87bec662005-07-27 23:02:00 -040092extern void (*pcibios_disable_irq)(struct pci_dev *dev);
Andi Kleen928cf8c2005-12-12 22:17:10 -080093
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -050094struct pci_raw_ops {
95 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
96 int reg, int len, u32 *val);
97 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
98 int reg, int len, u32 val);
99};
100
101extern struct pci_raw_ops *raw_pci_ops;
102extern struct pci_raw_ops *raw_pci_ext_ops;
103
104extern struct pci_raw_ops pci_direct_conf1;
H. Peter Anvin14d7ca52008-11-11 16:19:48 -0800105extern bool port_cf9_safe;
Andi Kleen928cf8c2005-12-12 22:17:10 -0800106
Robert Richter8dd779b2008-07-02 22:50:29 +0200107/* arch_initcall level */
Andi Kleen5e544d62006-09-26 10:52:40 +0200108extern int pci_direct_probe(void);
109extern void pci_direct_init(int type);
Andi Kleen92c05fc2006-03-23 14:35:12 -0800110extern void pci_pcbios_init(void);
Robert Richter8dd779b2008-07-02 22:50:29 +0200111extern void __init dmi_check_pciprobe(void);
112extern void __init dmi_check_skip_isa_align(void);
113
114/* some common used subsys_initcalls */
115extern int __init pci_acpi_init(void);
Thomas Gleixnerab3b3792009-08-29 17:47:33 +0200116extern void __init pcibios_irq_init(void);
Robert Richter8dd779b2008-07-02 22:50:29 +0200117extern int __init pcibios_init(void);
Thomas Gleixnerb72d0db2009-08-29 16:24:51 +0200118extern int pci_legacy_init(void);
Thomas Gleixner9325a282009-08-29 17:51:26 +0200119extern void pcibios_fixup_irqs(void);
Andi Kleen5e544d62006-09-26 10:52:40 +0200120
Olivier Galibertb7867392007-02-13 13:26:20 +0100121/* pci-mmconfig.c */
122
Bjorn Helgaas56ddf4d2009-11-13 17:34:29 -0700123/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
124#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
125
Bjorn Helgaasd215a9c2009-11-13 17:34:13 -0700126struct pci_mmcfg_region {
Bjorn Helgaasff097dd2009-11-13 17:34:49 -0700127 struct list_head list;
Bjorn Helgaas56ddf4d2009-11-13 17:34:29 -0700128 struct resource res;
Bjorn Helgaasd215a9c2009-11-13 17:34:13 -0700129 u64 address;
Bjorn Helgaas3f0f5502009-11-13 17:34:39 -0700130 char __iomem *virt;
Bjorn Helgaasd7e6b662009-11-13 17:34:18 -0700131 u16 segment;
132 u8 start_bus;
133 u8 end_bus;
Bjorn Helgaas56ddf4d2009-11-13 17:34:29 -0700134 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
Bjorn Helgaasd215a9c2009-11-13 17:34:13 -0700135};
136
OGAWA Hirofumi429d5122007-02-13 13:26:20 +0100137extern int __init pci_mmcfg_arch_init(void);
Yinghai Lu0b64ad72008-02-15 01:28:41 -0800138extern void __init pci_mmcfg_arch_free(void);
Bjorn Helgaasf6e1d8c2009-11-13 17:35:04 -0700139extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
dean gaudet3320ad92007-08-10 22:30:59 +0200140
Bjorn Helgaasff097dd2009-11-13 17:34:49 -0700141extern struct list_head pci_mmcfg_list;
Len Brownc4bf2f32009-06-11 23:53:55 -0400142
Bjorn Helgaasdf5eb1d2009-11-13 17:34:08 -0700143#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
144
dean gaudet3320ad92007-08-10 22:30:59 +0200145/*
146 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
147 * on their northbrige except through the * %eax register. As such, you MUST
148 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
149 * accessor functions.
150 * In fact just use pci_config_*, nothing else please.
151 */
152static inline unsigned char mmio_config_readb(void __iomem *pos)
153{
154 u8 val;
155 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
156 return val;
157}
158
159static inline unsigned short mmio_config_readw(void __iomem *pos)
160{
161 u16 val;
162 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
163 return val;
164}
165
166static inline unsigned int mmio_config_readl(void __iomem *pos)
167{
168 u32 val;
169 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
170 return val;
171}
172
173static inline void mmio_config_writeb(void __iomem *pos, u8 val)
174{
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +0530175 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
dean gaudet3320ad92007-08-10 22:30:59 +0200176}
177
178static inline void mmio_config_writew(void __iomem *pos, u16 val)
179{
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +0530180 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
dean gaudet3320ad92007-08-10 22:30:59 +0200181}
182
183static inline void mmio_config_writel(void __iomem *pos, u32 val)
184{
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +0530185 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
dean gaudet3320ad92007-08-10 22:30:59 +0200186}
Thomas Gleixnerb72d0db2009-08-29 16:24:51 +0200187
188#ifdef CONFIG_PCI
189# ifdef CONFIG_ACPI
190# define x86_default_pci_init pci_acpi_init
191# else
192# define x86_default_pci_init pci_legacy_init
193# endif
Thomas Gleixnerab3b3792009-08-29 17:47:33 +0200194# define x86_default_pci_init_irq pcibios_irq_init
Thomas Gleixner9325a282009-08-29 17:51:26 +0200195# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
Thomas Gleixnerb72d0db2009-08-29 16:24:51 +0200196#else
197# define x86_default_pci_init NULL
Thomas Gleixnerab3b3792009-08-29 17:47:33 +0200198# define x86_default_pci_init_irq NULL
Thomas Gleixner9325a282009-08-29 17:51:26 +0200199# define x86_default_pci_fixup_irqs NULL
Thomas Gleixnerb72d0db2009-08-29 16:24:51 +0200200#endif