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gerrit-public.fairphone.software / kernel / msm / 7dda18a44bf22ff0decb3c370114ccd73224f6bb / . / arch / arm / mach-msm / clock-8226.c
blob: cc478da584ad1328c83e2f095d4d72db96f16864 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
27
28#include "clock-local2.h"
29#include "clock-pll.h"
30#include "clock-rpm.h"
31#include "clock-voter.h"
32#include "clock-mdss-8974.h"
33#include "clock.h"
34
35enum {
36 GCC_BASE,
37 MMSS_BASE,
38 LPASS_BASE,
39 APCS_BASE,
40 APCS_PLL_BASE,
41 N_BASES,
42};
43
44static void __iomem *virt_bases[N_BASES];
45
46#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
47#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
48#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
49#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
50
51/* Mux source select values */
52#define xo_source_val 0
53#define gpll0_source_val 1
54#define gpll1_source_val 2
55
56#define xo_mm_source_val 0
57#define mmpll0_pll_mm_source_val 1
58#define mmpll1_pll_mm_source_val 2
59#define mmpll2_pll_mm_source_val 3
60#define gpll0_mm_source_val 5
61#define dsipll_750_mm_source_val 1
62#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]63#define dsipll0_byte_mm_source_val 1
64#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]65
66#define gpll1_hsic_source_val 4
67
68#define xo_lpass_source_val 0
69#define lpaaudio_pll_lpass_source_val 1
70#define gpll0_lpass_source_val 5
71
72/* Prevent a divider of -1 */
73#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
74
75#define F_GCC(f, s, div, m, n) \
76 { \
77 .freq_hz = (f), \
78 .src_clk = &s.c, \
79 .m_val = (m), \
80 .n_val = ~((n)-(m)) * !!(n), \
81 .d_val = ~(n),\
82 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
83 | BVAL(10, 8, s##_source_val), \
84 }
85
86#define F_MMSS(f, s, div, m, n) \
87 { \
88 .freq_hz = (f), \
89 .src_clk = &s.c, \
90 .m_val = (m), \
91 .n_val = ~((n)-(m)) * !!(n), \
92 .d_val = ~(n),\
93 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
94 | BVAL(10, 8, s##_mm_source_val), \
95 }
96
97#define F_MDSS(f, s, div, m, n) \
98 { \
99 .freq_hz = (f), \
100 .m_val = (m), \
101 .n_val = ~((n)-(m)) * !!(n), \
102 .d_val = ~(n),\
103 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
104 | BVAL(10, 8, s##_mm_source_val), \
105 }
106
107#define F_HSIC(f, s, div, m, n) \
108 { \
109 .freq_hz = (f), \
110 .src_clk = &s.c, \
111 .m_val = (m), \
112 .n_val = ~((n)-(m)) * !!(n), \
113 .d_val = ~(n),\
114 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
115 | BVAL(10, 8, s##_hsic_source_val), \
116 }
117
118#define F_LPASS(f, s, div, m, n) \
119 { \
120 .freq_hz = (f), \
121 .src_clk = &s.c, \
122 .m_val = (m), \
123 .n_val = ~((n)-(m)) * !!(n), \
124 .d_val = ~(n),\
125 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
126 | BVAL(10, 8, s##_lpass_source_val), \
127 }
128
129#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
130 { \
131 .freq_hz = (f), \
132 .l_val = (l), \
133 .m_val = (m), \
134 .n_val = (n), \
135 .pre_div_val = BVAL(12, 12, (pre_div)), \
136 .post_div_val = BVAL(9, 8, (post_div)), \
137 .vco_val = BVAL(29, 28, (vco)), \
138 }
139
140#define VDD_DIG_FMAX_MAP1(l1, f1) \
141 .vdd_class = &vdd_dig, \
142 .fmax = (unsigned long[VDD_DIG_NUM]) { \
143 [VDD_DIG_##l1] = (f1), \
144 }, \
145 .num_fmax = VDD_DIG_NUM
146
147#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
148 .vdd_class = &vdd_dig, \
149 .fmax = (unsigned long[VDD_DIG_NUM]) { \
150 [VDD_DIG_##l1] = (f1), \
151 [VDD_DIG_##l2] = (f2), \
152 }, \
153 .num_fmax = VDD_DIG_NUM
154
155#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
156 .vdd_class = &vdd_dig, \
157 .fmax = (unsigned long[VDD_DIG_NUM]) { \
158 [VDD_DIG_##l1] = (f1), \
159 [VDD_DIG_##l2] = (f2), \
160 [VDD_DIG_##l3] = (f3), \
161 }, \
162 .num_fmax = VDD_DIG_NUM
163
164enum vdd_dig_levels {
165 VDD_DIG_NONE,
166 VDD_DIG_LOW,
167 VDD_DIG_NOMINAL,
168 VDD_DIG_HIGH,
169 VDD_DIG_NUM
170};
171
172static const int vdd_corner[] = {
173 [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE,
174 [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC,
175 [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL,
176 [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO,
177};
178
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]179static struct regulator *vdd_dig_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]180
181static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
182{
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]183 return regulator_set_voltage(vdd_dig_reg, vdd_corner[level],
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]184 RPM_REGULATOR_CORNER_SUPER_TURBO);
185}
186
187static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig, VDD_DIG_NUM);
188
189#define RPM_MISC_CLK_TYPE 0x306b6c63
190#define RPM_BUS_CLK_TYPE 0x316b6c63
191#define RPM_MEM_CLK_TYPE 0x326b6c63
192
193#define RPM_SMD_KEY_ENABLE 0x62616E45
194
195#define CXO_ID 0x0
196#define QDSS_ID 0x1
197
198#define PNOC_ID 0x0
199#define SNOC_ID 0x1
200#define CNOC_ID 0x2
201#define MMSSNOC_AHB_ID 0x3
202
203#define BIMC_ID 0x0
204#define OXILI_ID 0x1
205#define OCMEM_ID 0x2
206
207#define D0_ID 1
208#define D1_ID 2
209#define A0_ID 4
210#define A1_ID 5
211#define A2_ID 6
212#define DIFF_CLK_ID 7
213#define DIV_CLK1_ID 11
214#define DIV_CLK2_ID 12
215
216DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
217DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
218DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
219DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
220 MMSSNOC_AHB_ID, NULL);
221
222DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
223DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
224 NULL);
225DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
226 NULL);
227
228DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
229 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
230DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
231
232DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
234DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
235DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
239DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
240
241DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
242DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
243DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
244DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
245DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
246
247struct measure_mux_entry {
248 struct clk *c;
249 int base;
250 u32 debug_mux;
251};
252
253static struct branch_clk oxilicx_axi_clk;
254
255#define MSS_DEBUG_CLOCK_CTL 0x0078
256#define LPASS_DEBUG_CLK_CTL 0x29000
257#define GLB_CLK_DIAG 0x01C
258#define GLB_TEST_BUS_SEL 0x020
259
260#define MMPLL0_PLL_MODE (0x0000)
261#define MMPLL0_PLL_L_VAL (0x0004)
262#define MMPLL0_PLL_M_VAL (0x0008)
263#define MMPLL0_PLL_N_VAL (0x000C)
264#define MMPLL0_PLL_USER_CTL (0x0010)
265#define MMPLL0_PLL_STATUS (0x001C)
266#define MMPLL1_PLL_MODE (0x0040)
267#define MMPLL1_PLL_L_VAL (0x0044)
268#define MMPLL1_PLL_M_VAL (0x0048)
269#define MMPLL1_PLL_N_VAL (0x004C)
270#define MMPLL1_PLL_USER_CTL (0x0050)
271#define MMPLL1_PLL_STATUS (0x005C)
272#define MMSS_PLL_VOTE_APCS (0x0100)
273#define VCODEC0_CMD_RCGR (0x1000)
274#define VENUS0_VCODEC0_CBCR (0x1028)
275#define VENUS0_AHB_CBCR (0x1030)
276#define VENUS0_AXI_CBCR (0x1034)
277#define PCLK0_CMD_RCGR (0x2000)
278#define MDP_CMD_RCGR (0x2040)
279#define VSYNC_CMD_RCGR (0x2080)
280#define BYTE0_CMD_RCGR (0x2120)
281#define ESC0_CMD_RCGR (0x2160)
282#define MDSS_AHB_CBCR (0x2308)
283#define MDSS_AXI_CBCR (0x2310)
284#define MDSS_PCLK0_CBCR (0x2314)
285#define MDSS_MDP_CBCR (0x231C)
286#define MDSS_MDP_LUT_CBCR (0x2320)
287#define MDSS_VSYNC_CBCR (0x2328)
288#define MDSS_BYTE0_CBCR (0x233C)
289#define MDSS_ESC0_CBCR (0x2344)
290#define CSI0PHYTIMER_CMD_RCGR (0x3000)
291#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
292#define CSI1PHYTIMER_CMD_RCGR (0x3030)
293#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
294#define CSI0_CMD_RCGR (0x3090)
295#define CAMSS_CSI0_CBCR (0x30B4)
296#define CAMSS_CSI0_AHB_CBCR (0x30BC)
297#define CAMSS_CSI0PHY_CBCR (0x30C4)
298#define CAMSS_CSI0RDI_CBCR (0x30D4)
299#define CAMSS_CSI0PIX_CBCR (0x30E4)
300#define CSI1_CMD_RCGR (0x3100)
301#define CAMSS_CSI1_CBCR (0x3124)
302#define CAMSS_CSI1_AHB_CBCR (0x3128)
303#define CAMSS_CSI1PHY_CBCR (0x3134)
304#define CAMSS_CSI1RDI_CBCR (0x3144)
305#define CAMSS_CSI1PIX_CBCR (0x3154)
306#define CAMSS_ISPIF_AHB_CBCR (0x3224)
307#define CCI_CMD_RCGR (0x3300)
308#define CAMSS_CCI_CCI_CBCR (0x3344)
309#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
310#define MCLK0_CMD_RCGR (0x3360)
311#define CAMSS_MCLK0_CBCR (0x3384)
312#define MCLK1_CMD_RCGR (0x3390)
313#define CAMSS_MCLK1_CBCR (0x33B4)
314#define MMSS_GP0_CMD_RCGR (0x3420)
315#define CAMSS_GP0_CBCR (0x3444)
316#define MMSS_GP1_CMD_RCGR (0x3450)
317#define CAMSS_GP1_CBCR (0x3474)
318#define CAMSS_TOP_AHB_CBCR (0x3484)
319#define CAMSS_MICRO_AHB_CBCR (0x3494)
320#define JPEG0_CMD_RCGR (0x3500)
321#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
322#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
323#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
324#define VFE0_CMD_RCGR (0x3600)
325#define CPP_CMD_RCGR (0x3640)
326#define CAMSS_VFE_VFE0_CBCR (0x36A8)
327#define CAMSS_VFE_CPP_CBCR (0x36B0)
328#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
329#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
330#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
331#define CAMSS_CSI_VFE0_CBCR (0x3704)
332#define OXILI_GFX3D_CBCR (0x4028)
333#define OXILICX_AXI_CBCR (0x4038)
334#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]335#define MMPLL2_PLL_MODE (0x4100)
336#define MMPLL2_PLL_STATUS (0x411C)
337#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
338#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
339#define MMSS_MISC_AHB_CBCR (0x502C)
340#define AXI_CMD_RCGR (0x5040)
341#define MMSS_S0_AXI_CBCR (0x5064)
342#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
343#define MMSS_DEBUG_CLK_CTL (0x0900)
344#define GPLL0_MODE (0x0000)
345#define GPLL0_L_VAL (0x0004)
346#define GPLL0_M_VAL (0x0008)
347#define GPLL0_N_VAL (0x000C)
348#define GPLL0_USER_CTL (0x0010)
349#define GPLL0_STATUS (0x001C)
350#define GPLL1_MODE (0x0040)
351#define GPLL1_L_VAL (0x0044)
352#define GPLL1_M_VAL (0x0048)
353#define GPLL1_N_VAL (0x004C)
354#define GPLL1_USER_CTL (0x0050)
355#define GPLL1_STATUS (0x005C)
356#define PERIPH_NOC_AHB_CBCR (0x0184)
357#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
358#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
359#define MSS_CFG_AHB_CBCR (0x0280)
360#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
361#define USB_HS_HSIC_BCR (0x0400)
362#define USB_HSIC_AHB_CBCR (0x0408)
363#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
364#define USB_HSIC_SYSTEM_CBCR (0x040C)
365#define USB_HSIC_CMD_RCGR (0x0440)
366#define USB_HSIC_CBCR (0x0410)
367#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
368#define USB_HSIC_IO_CAL_CBCR (0x0414)
369#define USB_HS_BCR (0x0480)
370#define USB_HS_SYSTEM_CBCR (0x0484)
371#define USB_HS_AHB_CBCR (0x0488)
372#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
373#define USB2A_PHY_SLEEP_CBCR (0x04AC)
374#define SDCC1_APPS_CMD_RCGR (0x04D0)
375#define SDCC1_APPS_CBCR (0x04C4)
376#define SDCC1_AHB_CBCR (0x04C8)
377#define SDCC2_APPS_CMD_RCGR (0x0510)
378#define SDCC2_APPS_CBCR (0x0504)
379#define SDCC2_AHB_CBCR (0x0508)
380#define SDCC3_APPS_CMD_RCGR (0x0550)
381#define SDCC3_APPS_CBCR (0x0544)
382#define SDCC3_AHB_CBCR (0x0548)
383#define BLSP1_AHB_CBCR (0x05C4)
384#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
385#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
386#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
387#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
388#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
389#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
390#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
391#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
392#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
393#define BLSP1_UART1_APPS_CBCR (0x0684)
394#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
395#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
396#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
397#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
398#define BLSP1_UART2_APPS_CBCR (0x0704)
399#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
400#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
401#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
402#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
403#define BLSP1_UART3_APPS_CBCR (0x0784)
404#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
405#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
406#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
407#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
408#define BLSP1_UART4_APPS_CBCR (0x0804)
409#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
410#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
411#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
412#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
413#define BLSP1_UART5_APPS_CBCR (0x0884)
414#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
415#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
416#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
417#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
418#define BLSP1_UART6_APPS_CBCR (0x0904)
419#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
420#define PDM_AHB_CBCR (0x0CC4)
421#define PDM_XO4_CBCR (0x0CC8)
422#define PDM2_CBCR (0x0CCC)
423#define PDM2_CMD_RCGR (0x0CD0)
424#define PRNG_AHB_CBCR (0x0D04)
425#define BAM_DMA_AHB_CBCR (0x0D44)
426#define BOOT_ROM_AHB_CBCR (0x0E04)
427#define CE1_CMD_RCGR (0x1050)
428#define CE1_CBCR (0x1044)
429#define CE1_AXI_CBCR (0x1048)
430#define CE1_AHB_CBCR (0x104C)
431#define GCC_XO_DIV4_CBCR (0x10C8)
432#define LPASS_Q6_AXI_CBCR (0x11C0)
433#define APCS_GPLL_ENA_VOTE (0x1480)
434#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
435#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
436#define GCC_DEBUG_CLK_CTL (0x1880)
437#define CLOCK_FRQ_MEASURE_CTL (0x1884)
438#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
439#define PLLTEST_PAD_CFG (0x188C)
440#define GP1_CBCR (0x1900)
441#define GP1_CMD_RCGR (0x1904)
442#define GP2_CBCR (0x1940)
443#define GP2_CMD_RCGR (0x1944)
444#define GP3_CBCR (0x1980)
445#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]446#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]447#define Q6SS_AHB_LFABIF_CBCR (0x22000)
448#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]449#define Q6SS_XO_CBCR (0x26000)
450
451static unsigned int soft_vote_gpll0;
452
453static struct pll_vote_clk gpll0 = {
454 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
455 .en_mask = BIT(0),
456 .status_reg = (void __iomem *)GPLL0_STATUS,
457 .status_mask = BIT(17),
458 .soft_vote = &soft_vote_gpll0,
459 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
460 .base = &virt_bases[GCC_BASE],
461 .c = {
462 .rate = 600000000,
463 .parent = &xo.c,
464 .dbg_name = "gpll0",
465 .ops = &clk_ops_pll_acpu_vote,
466 CLK_INIT(gpll0.c),
467 },
468};
469
470/*Don't vote for xo if using this clock to allow xo shutdown*/
471static struct pll_vote_clk gpll0_ao = {
472 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
473 .en_mask = BIT(0),
474 .status_reg = (void __iomem *)GPLL0_STATUS,
475 .status_mask = BIT(17),
476 .soft_vote = &soft_vote_gpll0,
477 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
478 .base = &virt_bases[GCC_BASE],
479 .c = {
480 .rate = 600000000,
481 .dbg_name = "gpll0_ao",
482 .ops = &clk_ops_pll_acpu_vote,
483 CLK_INIT(gpll0_ao.c),
484 },
485};
486
487static struct pll_vote_clk gpll1 = {
488 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
489 .en_mask = BIT(1),
490 .status_reg = (void __iomem *)GPLL1_STATUS,
491 .status_mask = BIT(17),
492 .base = &virt_bases[GCC_BASE],
493 .c = {
494 .rate = 480000000,
495 .parent = &xo.c,
496 .dbg_name = "gpll1",
497 .ops = &clk_ops_pll_vote,
498 CLK_INIT(gpll1.c),
499 },
500};
501
502static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]503 F_GCC( 19200000, xo, 1, 0, 0),
504 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]505 F_END
506};
507
508static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
509 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
510 .set_rate = set_rate_hid,
511 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
512 .current_freq = &rcg_dummy_freq,
513 .base = &virt_bases[GCC_BASE],
514 .c = {
515 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
516 .ops = &clk_ops_rcg,
517 VDD_DIG_FMAX_MAP1(LOW, 50000000),
518 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
519 },
520};
521
522static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
523 F_GCC( 960000, xo, 10, 1, 2),
524 F_GCC( 4800000, xo, 4, 0, 0),
525 F_GCC( 9600000, xo, 2, 0, 0),
526 F_GCC( 15000000, gpll0, 10, 1, 4),
527 F_GCC( 19200000, xo, 1, 0, 0),
528 F_GCC( 25000000, gpll0, 12, 1, 2),
529 F_GCC( 50000000, gpll0, 12, 0, 0),
530 F_END
531};
532
533static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
534 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
535 .set_rate = set_rate_mnd,
536 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
537 .current_freq = &rcg_dummy_freq,
538 .base = &virt_bases[GCC_BASE],
539 .c = {
540 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
541 .ops = &clk_ops_rcg_mnd,
542 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
543 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
544 },
545};
546
547static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
548 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
549 .set_rate = set_rate_hid,
550 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
551 .current_freq = &rcg_dummy_freq,
552 .base = &virt_bases[GCC_BASE],
553 .c = {
554 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
555 .ops = &clk_ops_rcg,
556 VDD_DIG_FMAX_MAP1(LOW, 50000000),
557 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
558 },
559};
560
561static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
562 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
563 .set_rate = set_rate_mnd,
564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
565 .current_freq = &rcg_dummy_freq,
566 .base = &virt_bases[GCC_BASE],
567 .c = {
568 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
569 .ops = &clk_ops_rcg_mnd,
570 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
571 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
572 },
573};
574
575static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
576 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
577 .set_rate = set_rate_hid,
578 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
579 .current_freq = &rcg_dummy_freq,
580 .base = &virt_bases[GCC_BASE],
581 .c = {
582 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
583 .ops = &clk_ops_rcg,
584 VDD_DIG_FMAX_MAP1(LOW, 50000000),
585 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
586 },
587};
588
589static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
590 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
591 .set_rate = set_rate_mnd,
592 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
593 .current_freq = &rcg_dummy_freq,
594 .base = &virt_bases[GCC_BASE],
595 .c = {
596 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
597 .ops = &clk_ops_rcg_mnd,
598 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
599 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
600 },
601};
602
603static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
604 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
605 .set_rate = set_rate_hid,
606 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
607 .current_freq = &rcg_dummy_freq,
608 .base = &virt_bases[GCC_BASE],
609 .c = {
610 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
611 .ops = &clk_ops_rcg,
612 VDD_DIG_FMAX_MAP1(LOW, 50000000),
613 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
614 },
615};
616
617static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
618 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
619 .set_rate = set_rate_mnd,
620 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
621 .current_freq = &rcg_dummy_freq,
622 .base = &virt_bases[GCC_BASE],
623 .c = {
624 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
625 .ops = &clk_ops_rcg_mnd,
626 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
627 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
628 },
629};
630
631static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
632 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
633 .set_rate = set_rate_hid,
634 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
635 .current_freq = &rcg_dummy_freq,
636 .base = &virt_bases[GCC_BASE],
637 .c = {
638 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
639 .ops = &clk_ops_rcg,
640 VDD_DIG_FMAX_MAP1(LOW, 50000000),
641 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
642 },
643};
644
645static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
646 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
647 .set_rate = set_rate_mnd,
648 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
649 .current_freq = &rcg_dummy_freq,
650 .base = &virt_bases[GCC_BASE],
651 .c = {
652 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
653 .ops = &clk_ops_rcg_mnd,
654 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
655 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
656 },
657};
658
659static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
660 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
661 .set_rate = set_rate_hid,
662 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
663 .current_freq = &rcg_dummy_freq,
664 .base = &virt_bases[GCC_BASE],
665 .c = {
666 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
667 .ops = &clk_ops_rcg,
668 VDD_DIG_FMAX_MAP1(LOW, 50000000),
669 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
670 },
671};
672
673static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
674 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
675 .set_rate = set_rate_mnd,
676 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
677 .current_freq = &rcg_dummy_freq,
678 .base = &virt_bases[GCC_BASE],
679 .c = {
680 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
681 .ops = &clk_ops_rcg_mnd,
682 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
683 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
684 },
685};
686
687static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
688 F_GCC( 3686400, gpll0, 1, 96, 15625),
689 F_GCC( 7372800, gpll0, 1, 192, 15625),
690 F_GCC( 14745600, gpll0, 1, 384, 15625),
691 F_GCC( 16000000, gpll0, 5, 2, 15),
692 F_GCC( 19200000, xo, 1, 0, 0),
693 F_GCC( 24000000, gpll0, 5, 1, 5),
694 F_GCC( 32000000, gpll0, 1, 4, 75),
695 F_GCC( 40000000, gpll0, 15, 0, 0),
696 F_GCC( 46400000, gpll0, 1, 29, 375),
697 F_GCC( 48000000, gpll0, 12.5, 0, 0),
698 F_GCC( 51200000, gpll0, 1, 32, 375),
699 F_GCC( 56000000, gpll0, 1, 7, 75),
700 F_GCC( 58982400, gpll0, 1, 1536, 15625),
701 F_GCC( 60000000, gpll0, 10, 0, 0),
702 F_END
703};
704
705static struct rcg_clk blsp1_uart1_apps_clk_src = {
706 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
707 .set_rate = set_rate_mnd,
708 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
709 .current_freq = &rcg_dummy_freq,
710 .base = &virt_bases[GCC_BASE],
711 .c = {
712 .dbg_name = "blsp1_uart1_apps_clk_src",
713 .ops = &clk_ops_rcg_mnd,
714 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
715 CLK_INIT(blsp1_uart1_apps_clk_src.c),
716 },
717};
718
719static struct rcg_clk blsp1_uart2_apps_clk_src = {
720 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
721 .set_rate = set_rate_mnd,
722 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
723 .current_freq = &rcg_dummy_freq,
724 .base = &virt_bases[GCC_BASE],
725 .c = {
726 .dbg_name = "blsp1_uart2_apps_clk_src",
727 .ops = &clk_ops_rcg_mnd,
728 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
729 CLK_INIT(blsp1_uart2_apps_clk_src.c),
730 },
731};
732
733static struct rcg_clk blsp1_uart3_apps_clk_src = {
734 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
735 .set_rate = set_rate_mnd,
736 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
737 .current_freq = &rcg_dummy_freq,
738 .base = &virt_bases[GCC_BASE],
739 .c = {
740 .dbg_name = "blsp1_uart3_apps_clk_src",
741 .ops = &clk_ops_rcg_mnd,
742 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
743 CLK_INIT(blsp1_uart3_apps_clk_src.c),
744 },
745};
746
747static struct rcg_clk blsp1_uart4_apps_clk_src = {
748 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
749 .set_rate = set_rate_mnd,
750 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
751 .current_freq = &rcg_dummy_freq,
752 .base = &virt_bases[GCC_BASE],
753 .c = {
754 .dbg_name = "blsp1_uart4_apps_clk_src",
755 .ops = &clk_ops_rcg_mnd,
756 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
757 CLK_INIT(blsp1_uart4_apps_clk_src.c),
758 },
759};
760
761static struct rcg_clk blsp1_uart5_apps_clk_src = {
762 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
763 .set_rate = set_rate_mnd,
764 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
765 .current_freq = &rcg_dummy_freq,
766 .base = &virt_bases[GCC_BASE],
767 .c = {
768 .dbg_name = "blsp1_uart5_apps_clk_src",
769 .ops = &clk_ops_rcg_mnd,
770 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
771 CLK_INIT(blsp1_uart5_apps_clk_src.c),
772 },
773};
774
775static struct rcg_clk blsp1_uart6_apps_clk_src = {
776 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
777 .set_rate = set_rate_mnd,
778 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
779 .current_freq = &rcg_dummy_freq,
780 .base = &virt_bases[GCC_BASE],
781 .c = {
782 .dbg_name = "blsp1_uart6_apps_clk_src",
783 .ops = &clk_ops_rcg_mnd,
784 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
785 CLK_INIT(blsp1_uart6_apps_clk_src.c),
786 },
787};
788
789static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
790 F_GCC( 50000000, gpll0, 12, 0, 0),
791 F_GCC( 100000000, gpll0, 6, 0, 0),
792 F_END
793};
794
795static struct rcg_clk ce1_clk_src = {
796 .cmd_rcgr_reg = CE1_CMD_RCGR,
797 .set_rate = set_rate_hid,
798 .freq_tbl = ftbl_gcc_ce1_clk,
799 .current_freq = &rcg_dummy_freq,
800 .base = &virt_bases[GCC_BASE],
801 .c = {
802 .dbg_name = "ce1_clk_src",
803 .ops = &clk_ops_rcg,
804 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
805 CLK_INIT(ce1_clk_src.c),
806 },
807};
808
809static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
810 F_GCC( 19200000, xo, 1, 0, 0),
811 F_END
812};
813
814static struct rcg_clk gp1_clk_src = {
815 .cmd_rcgr_reg = GP1_CMD_RCGR,
816 .set_rate = set_rate_mnd,
817 .freq_tbl = ftbl_gcc_gp1_3_clk,
818 .current_freq = &rcg_dummy_freq,
819 .base = &virt_bases[GCC_BASE],
820 .c = {
821 .dbg_name = "gp1_clk_src",
822 .ops = &clk_ops_rcg_mnd,
823 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
824 CLK_INIT(gp1_clk_src.c),
825 },
826};
827
828static struct rcg_clk gp2_clk_src = {
829 .cmd_rcgr_reg = GP2_CMD_RCGR,
830 .set_rate = set_rate_mnd,
831 .freq_tbl = ftbl_gcc_gp1_3_clk,
832 .current_freq = &rcg_dummy_freq,
833 .base = &virt_bases[GCC_BASE],
834 .c = {
835 .dbg_name = "gp2_clk_src",
836 .ops = &clk_ops_rcg_mnd,
837 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
838 CLK_INIT(gp2_clk_src.c),
839 },
840};
841
842static struct rcg_clk gp3_clk_src = {
843 .cmd_rcgr_reg = GP3_CMD_RCGR,
844 .set_rate = set_rate_mnd,
845 .freq_tbl = ftbl_gcc_gp1_3_clk,
846 .current_freq = &rcg_dummy_freq,
847 .base = &virt_bases[GCC_BASE],
848 .c = {
849 .dbg_name = "gp3_clk_src",
850 .ops = &clk_ops_rcg_mnd,
851 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
852 CLK_INIT(gp3_clk_src.c),
853 },
854};
855
856static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
857 F_GCC( 60000000, gpll0, 10, 0, 0),
858 F_END
859};
860
861static struct rcg_clk pdm2_clk_src = {
862 .cmd_rcgr_reg = PDM2_CMD_RCGR,
863 .set_rate = set_rate_hid,
864 .freq_tbl = ftbl_gcc_pdm2_clk,
865 .current_freq = &rcg_dummy_freq,
866 .base = &virt_bases[GCC_BASE],
867 .c = {
868 .dbg_name = "pdm2_clk_src",
869 .ops = &clk_ops_rcg,
870 VDD_DIG_FMAX_MAP1(LOW, 60000000),
871 CLK_INIT(pdm2_clk_src.c),
872 },
873};
874
875static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
876 F_GCC( 144000, xo, 16, 3, 25),
877 F_GCC( 400000, xo, 12, 1, 4),
878 F_GCC( 20000000, gpll0, 15, 1, 2),
879 F_GCC( 25000000, gpll0, 12, 1, 2),
880 F_GCC( 50000000, gpll0, 12, 0, 0),
881 F_GCC( 100000000, gpll0, 6, 0, 0),
882 F_GCC( 200000000, gpll0, 3, 0, 0),
883 F_END
884};
885
886static struct rcg_clk sdcc1_apps_clk_src = {
887 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
888 .set_rate = set_rate_mnd,
889 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
890 .current_freq = &rcg_dummy_freq,
891 .base = &virt_bases[GCC_BASE],
892 .c = {
893 .dbg_name = "sdcc1_apps_clk_src",
894 .ops = &clk_ops_rcg_mnd,
895 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
896 CLK_INIT(sdcc1_apps_clk_src.c),
897 },
898};
899
900static struct rcg_clk sdcc2_apps_clk_src = {
901 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
902 .set_rate = set_rate_mnd,
903 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
904 .current_freq = &rcg_dummy_freq,
905 .base = &virt_bases[GCC_BASE],
906 .c = {
907 .dbg_name = "sdcc2_apps_clk_src",
908 .ops = &clk_ops_rcg_mnd,
909 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
910 CLK_INIT(sdcc2_apps_clk_src.c),
911 },
912};
913
914static struct rcg_clk sdcc3_apps_clk_src = {
915 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
916 .set_rate = set_rate_mnd,
917 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
918 .current_freq = &rcg_dummy_freq,
919 .base = &virt_bases[GCC_BASE],
920 .c = {
921 .dbg_name = "sdcc3_apps_clk_src",
922 .ops = &clk_ops_rcg_mnd,
923 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
924 CLK_INIT(sdcc3_apps_clk_src.c),
925 },
926};
927
928static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
929 F_GCC( 75000000, gpll0, 8, 0, 0),
930 F_END
931};
932
933static struct rcg_clk usb_hs_system_clk_src = {
934 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
935 .set_rate = set_rate_hid,
936 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
937 .current_freq = &rcg_dummy_freq,
938 .base = &virt_bases[GCC_BASE],
939 .c = {
940 .dbg_name = "usb_hs_system_clk_src",
941 .ops = &clk_ops_rcg,
942 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
943 CLK_INIT(usb_hs_system_clk_src.c),
944 },
945};
946
947static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
948 F_HSIC( 480000000, gpll1, 0, 0, 0),
949 F_END
950};
951
952static struct rcg_clk usb_hsic_clk_src = {
953 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
954 .set_rate = set_rate_hid,
955 .freq_tbl = ftbl_gcc_usb_hsic_clk,
956 .current_freq = &rcg_dummy_freq,
957 .base = &virt_bases[GCC_BASE],
958 .c = {
959 .dbg_name = "usb_hsic_clk_src",
960 .ops = &clk_ops_rcg,
961 VDD_DIG_FMAX_MAP1(LOW, 480000000),
962 CLK_INIT(usb_hsic_clk_src.c),
963 },
964};
965
966static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
967 F_GCC( 9600000, xo, 2, 0, 0),
968 F_END
969};
970
971static struct rcg_clk usb_hsic_io_cal_clk_src = {
972 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
973 .set_rate = set_rate_hid,
974 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
975 .current_freq = &rcg_dummy_freq,
976 .base = &virt_bases[GCC_BASE],
977 .c = {
978 .dbg_name = "usb_hsic_io_cal_clk_src",
979 .ops = &clk_ops_rcg,
980 VDD_DIG_FMAX_MAP1(LOW, 9600000),
981 CLK_INIT(usb_hsic_io_cal_clk_src.c),
982 },
983};
984
985static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
986 F_GCC( 75000000, gpll0, 8, 0, 0),
987 F_END
988};
989
990static struct rcg_clk usb_hsic_system_clk_src = {
991 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
992 .set_rate = set_rate_hid,
993 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
994 .current_freq = &rcg_dummy_freq,
995 .base = &virt_bases[GCC_BASE],
996 .c = {
997 .dbg_name = "usb_hsic_system_clk_src",
998 .ops = &clk_ops_rcg,
999 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
1000 CLK_INIT(usb_hsic_system_clk_src.c),
1001 },
1002};
1003
1004static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1005 .cbcr_reg = BAM_DMA_AHB_CBCR,
1006 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1007 .en_mask = BIT(12),
1008 .base = &virt_bases[GCC_BASE],
1009 .c = {
1010 .dbg_name = "gcc_bam_dma_ahb_clk",
1011 .ops = &clk_ops_vote,
1012 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1013 },
1014};
1015
1016static struct local_vote_clk gcc_blsp1_ahb_clk = {
1017 .cbcr_reg = BLSP1_AHB_CBCR,
1018 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1019 .en_mask = BIT(17),
1020 .base = &virt_bases[GCC_BASE],
1021 .c = {
1022 .dbg_name = "gcc_blsp1_ahb_clk",
1023 .ops = &clk_ops_vote,
1024 CLK_INIT(gcc_blsp1_ahb_clk.c),
1025 },
1026};
1027
1028static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1029 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1030 .has_sibling = 0,
1031 .base = &virt_bases[GCC_BASE],
1032 .c = {
1033 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1034 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1035 .ops = &clk_ops_branch,
1036 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1037 },
1038};
1039
1040static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1041 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1042 .has_sibling = 0,
1043 .base = &virt_bases[GCC_BASE],
1044 .c = {
1045 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1046 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1047 .ops = &clk_ops_branch,
1048 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1049 },
1050};
1051
1052static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1053 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1054 .has_sibling = 0,
1055 .base = &virt_bases[GCC_BASE],
1056 .c = {
1057 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1058 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1059 .ops = &clk_ops_branch,
1060 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1061 },
1062};
1063
1064static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1065 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1066 .has_sibling = 0,
1067 .base = &virt_bases[GCC_BASE],
1068 .c = {
1069 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1070 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1071 .ops = &clk_ops_branch,
1072 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1073 },
1074};
1075
1076static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1077 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1078 .has_sibling = 0,
1079 .base = &virt_bases[GCC_BASE],
1080 .c = {
1081 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1082 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1083 .ops = &clk_ops_branch,
1084 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1085 },
1086};
1087
1088static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1089 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1090 .has_sibling = 0,
1091 .base = &virt_bases[GCC_BASE],
1092 .c = {
1093 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1094 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1095 .ops = &clk_ops_branch,
1096 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1097 },
1098};
1099
1100static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1101 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1102 .has_sibling = 0,
1103 .base = &virt_bases[GCC_BASE],
1104 .c = {
1105 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1106 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1107 .ops = &clk_ops_branch,
1108 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1109 },
1110};
1111
1112static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1113 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1114 .has_sibling = 0,
1115 .base = &virt_bases[GCC_BASE],
1116 .c = {
1117 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1118 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1119 .ops = &clk_ops_branch,
1120 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1121 },
1122};
1123
1124static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1125 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1126 .has_sibling = 0,
1127 .base = &virt_bases[GCC_BASE],
1128 .c = {
1129 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1130 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1131 .ops = &clk_ops_branch,
1132 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1133 },
1134};
1135
1136static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1137 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1138 .has_sibling = 0,
1139 .base = &virt_bases[GCC_BASE],
1140 .c = {
1141 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1142 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1143 .ops = &clk_ops_branch,
1144 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1145 },
1146};
1147
1148static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1149 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1150 .has_sibling = 0,
1151 .base = &virt_bases[GCC_BASE],
1152 .c = {
1153 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1154 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1155 .ops = &clk_ops_branch,
1156 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1157 },
1158};
1159
1160static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1161 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1162 .has_sibling = 0,
1163 .base = &virt_bases[GCC_BASE],
1164 .c = {
1165 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1166 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1167 .ops = &clk_ops_branch,
1168 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1169 },
1170};
1171
1172static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1173 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1174 .has_sibling = 0,
1175 .base = &virt_bases[GCC_BASE],
1176 .c = {
1177 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1178 .parent = &blsp1_uart1_apps_clk_src.c,
1179 .ops = &clk_ops_branch,
1180 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1181 },
1182};
1183
1184static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1185 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1186 .has_sibling = 0,
1187 .base = &virt_bases[GCC_BASE],
1188 .c = {
1189 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1190 .parent = &blsp1_uart2_apps_clk_src.c,
1191 .ops = &clk_ops_branch,
1192 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1193 },
1194};
1195
1196static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1197 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1198 .has_sibling = 0,
1199 .base = &virt_bases[GCC_BASE],
1200 .c = {
1201 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1202 .parent = &blsp1_uart3_apps_clk_src.c,
1203 .ops = &clk_ops_branch,
1204 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1205 },
1206};
1207
1208static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1209 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1210 .has_sibling = 0,
1211 .base = &virt_bases[GCC_BASE],
1212 .c = {
1213 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1214 .parent = &blsp1_uart4_apps_clk_src.c,
1215 .ops = &clk_ops_branch,
1216 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1217 },
1218};
1219
1220static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1221 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1222 .has_sibling = 0,
1223 .base = &virt_bases[GCC_BASE],
1224 .c = {
1225 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1226 .parent = &blsp1_uart5_apps_clk_src.c,
1227 .ops = &clk_ops_branch,
1228 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1229 },
1230};
1231
1232static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1233 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1234 .has_sibling = 0,
1235 .base = &virt_bases[GCC_BASE],
1236 .c = {
1237 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1238 .parent = &blsp1_uart6_apps_clk_src.c,
1239 .ops = &clk_ops_branch,
1240 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1241 },
1242};
1243
1244static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1245 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1246 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1247 .en_mask = BIT(10),
1248 .base = &virt_bases[GCC_BASE],
1249 .c = {
1250 .dbg_name = "gcc_boot_rom_ahb_clk",
1251 .ops = &clk_ops_vote,
1252 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1253 },
1254};
1255
1256static struct local_vote_clk gcc_ce1_ahb_clk = {
1257 .cbcr_reg = CE1_AHB_CBCR,
1258 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1259 .en_mask = BIT(3),
1260 .base = &virt_bases[GCC_BASE],
1261 .c = {
1262 .dbg_name = "gcc_ce1_ahb_clk",
1263 .ops = &clk_ops_vote,
1264 CLK_INIT(gcc_ce1_ahb_clk.c),
1265 },
1266};
1267
1268static struct local_vote_clk gcc_ce1_axi_clk = {
1269 .cbcr_reg = CE1_AXI_CBCR,
1270 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1271 .en_mask = BIT(4),
1272 .base = &virt_bases[GCC_BASE],
1273 .c = {
1274 .dbg_name = "gcc_ce1_axi_clk",
1275 .ops = &clk_ops_vote,
1276 CLK_INIT(gcc_ce1_axi_clk.c),
1277 },
1278};
1279
1280static struct local_vote_clk gcc_ce1_clk = {
1281 .cbcr_reg = CE1_CBCR,
1282 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1283 .en_mask = BIT(5),
1284 .base = &virt_bases[GCC_BASE],
1285 .c = {
1286 .dbg_name = "gcc_ce1_clk",
1287 .ops = &clk_ops_vote,
1288 CLK_INIT(gcc_ce1_clk.c),
1289 },
1290};
1291
1292static struct branch_clk gcc_gp1_clk = {
1293 .cbcr_reg = GP1_CBCR,
1294 .has_sibling = 0,
1295 .base = &virt_bases[GCC_BASE],
1296 .c = {
1297 .dbg_name = "gcc_gp1_clk",
1298 .parent = &gp1_clk_src.c,
1299 .ops = &clk_ops_branch,
1300 CLK_INIT(gcc_gp1_clk.c),
1301 },
1302};
1303
1304static struct branch_clk gcc_gp2_clk = {
1305 .cbcr_reg = GP2_CBCR,
1306 .has_sibling = 0,
1307 .base = &virt_bases[GCC_BASE],
1308 .c = {
1309 .dbg_name = "gcc_gp2_clk",
1310 .parent = &gp2_clk_src.c,
1311 .ops = &clk_ops_branch,
1312 CLK_INIT(gcc_gp2_clk.c),
1313 },
1314};
1315
1316static struct branch_clk gcc_gp3_clk = {
1317 .cbcr_reg = GP3_CBCR,
1318 .has_sibling = 0,
1319 .base = &virt_bases[GCC_BASE],
1320 .c = {
1321 .dbg_name = "gcc_gp3_clk",
1322 .parent = &gp3_clk_src.c,
1323 .ops = &clk_ops_branch,
1324 CLK_INIT(gcc_gp3_clk.c),
1325 },
1326};
1327
1328static struct branch_clk gcc_lpass_q6_axi_clk = {
1329 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1330 .has_sibling = 1,
1331 .base = &virt_bases[GCC_BASE],
1332 .c = {
1333 .dbg_name = "gcc_lpass_q6_axi_clk",
1334 .ops = &clk_ops_branch,
1335 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1336 },
1337};
1338
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1339static struct branch_clk gcc_mss_cfg_ahb_clk = {
1340 .cbcr_reg = MSS_CFG_AHB_CBCR,
1341 .has_sibling = 1,
1342 .base = &virt_bases[GCC_BASE],
1343 .c = {
1344 .dbg_name = "gcc_mss_cfg_ahb_clk",
1345 .ops = &clk_ops_branch,
1346 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1347 },
1348};
1349
1350static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1351 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1352 .has_sibling = 1,
1353 .base = &virt_bases[GCC_BASE],
1354 .c = {
1355 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1356 .ops = &clk_ops_branch,
1357 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1358 },
1359};
1360
1361static struct branch_clk gcc_noc_conf_xpu_ahb_clk = {
1362 .cbcr_reg = NOC_CONF_XPU_AHB_CBCR,
1363 .has_sibling = 1,
1364 .base = &virt_bases[GCC_BASE],
1365 .c = {
1366 .dbg_name = "gcc_noc_conf_xpu_ahb_clk",
1367 .ops = &clk_ops_branch,
1368 CLK_INIT(gcc_noc_conf_xpu_ahb_clk.c),
1369 },
1370};
1371
1372static struct branch_clk gcc_pdm2_clk = {
1373 .cbcr_reg = PDM2_CBCR,
1374 .has_sibling = 0,
1375 .base = &virt_bases[GCC_BASE],
1376 .c = {
1377 .dbg_name = "gcc_pdm2_clk",
1378 .parent = &pdm2_clk_src.c,
1379 .ops = &clk_ops_branch,
1380 CLK_INIT(gcc_pdm2_clk.c),
1381 },
1382};
1383
1384static struct branch_clk gcc_pdm_ahb_clk = {
1385 .cbcr_reg = PDM_AHB_CBCR,
1386 .has_sibling = 1,
1387 .base = &virt_bases[GCC_BASE],
1388 .c = {
1389 .dbg_name = "gcc_pdm_ahb_clk",
1390 .ops = &clk_ops_branch,
1391 CLK_INIT(gcc_pdm_ahb_clk.c),
1392 },
1393};
1394
1395static struct branch_clk gcc_pdm_xo4_clk = {
1396 .cbcr_reg = PDM_XO4_CBCR,
1397 .has_sibling = 1,
1398 .base = &virt_bases[GCC_BASE],
1399 .c = {
1400 .dbg_name = "gcc_pdm_xo4_clk",
1401 .parent = &xo.c,
1402 .ops = &clk_ops_branch,
1403 CLK_INIT(gcc_pdm_xo4_clk.c),
1404 },
1405};
1406
1407static struct branch_clk gcc_periph_noc_ahb_clk = {
1408 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1409 .has_sibling = 1,
1410 .base = &virt_bases[GCC_BASE],
1411 .c = {
1412 .dbg_name = "gcc_periph_noc_ahb_clk",
1413 .ops = &clk_ops_branch,
1414 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1415 },
1416};
1417
1418static struct local_vote_clk gcc_prng_ahb_clk = {
1419 .cbcr_reg = PRNG_AHB_CBCR,
1420 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1421 .en_mask = BIT(13),
1422 .base = &virt_bases[GCC_BASE],
1423 .c = {
1424 .dbg_name = "gcc_prng_ahb_clk",
1425 .ops = &clk_ops_vote,
1426 CLK_INIT(gcc_prng_ahb_clk.c),
1427 },
1428};
1429
1430static struct branch_clk gcc_sdcc1_ahb_clk = {
1431 .cbcr_reg = SDCC1_AHB_CBCR,
1432 .has_sibling = 1,
1433 .base = &virt_bases[GCC_BASE],
1434 .c = {
1435 .dbg_name = "gcc_sdcc1_ahb_clk",
1436 .ops = &clk_ops_branch,
1437 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1438 },
1439};
1440
1441static struct branch_clk gcc_sdcc1_apps_clk = {
1442 .cbcr_reg = SDCC1_APPS_CBCR,
1443 .has_sibling = 0,
1444 .base = &virt_bases[GCC_BASE],
1445 .c = {
1446 .dbg_name = "gcc_sdcc1_apps_clk",
1447 .parent = &sdcc1_apps_clk_src.c,
1448 .ops = &clk_ops_branch,
1449 CLK_INIT(gcc_sdcc1_apps_clk.c),
1450 },
1451};
1452
1453static struct branch_clk gcc_sdcc2_ahb_clk = {
1454 .cbcr_reg = SDCC2_AHB_CBCR,
1455 .has_sibling = 1,
1456 .base = &virt_bases[GCC_BASE],
1457 .c = {
1458 .dbg_name = "gcc_sdcc2_ahb_clk",
1459 .ops = &clk_ops_branch,
1460 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1461 },
1462};
1463
1464static struct branch_clk gcc_sdcc2_apps_clk = {
1465 .cbcr_reg = SDCC2_APPS_CBCR,
1466 .has_sibling = 0,
1467 .base = &virt_bases[GCC_BASE],
1468 .c = {
1469 .dbg_name = "gcc_sdcc2_apps_clk",
1470 .parent = &sdcc2_apps_clk_src.c,
1471 .ops = &clk_ops_branch,
1472 CLK_INIT(gcc_sdcc2_apps_clk.c),
1473 },
1474};
1475
1476static struct branch_clk gcc_sdcc3_ahb_clk = {
1477 .cbcr_reg = SDCC3_AHB_CBCR,
1478 .has_sibling = 1,
1479 .base = &virt_bases[GCC_BASE],
1480 .c = {
1481 .dbg_name = "gcc_sdcc3_ahb_clk",
1482 .ops = &clk_ops_branch,
1483 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1484 },
1485};
1486
1487static struct branch_clk gcc_sdcc3_apps_clk = {
1488 .cbcr_reg = SDCC3_APPS_CBCR,
1489 .has_sibling = 0,
1490 .base = &virt_bases[GCC_BASE],
1491 .c = {
1492 .dbg_name = "gcc_sdcc3_apps_clk",
1493 .parent = &sdcc3_apps_clk_src.c,
1494 .ops = &clk_ops_branch,
1495 CLK_INIT(gcc_sdcc3_apps_clk.c),
1496 },
1497};
1498
1499static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1500 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1501 .has_sibling = 1,
1502 .base = &virt_bases[GCC_BASE],
1503 .c = {
1504 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1505 .ops = &clk_ops_branch,
1506 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1507 },
1508};
1509
1510static struct branch_clk gcc_usb_hs_ahb_clk = {
1511 .cbcr_reg = USB_HS_AHB_CBCR,
1512 .has_sibling = 1,
1513 .base = &virt_bases[GCC_BASE],
1514 .c = {
1515 .dbg_name = "gcc_usb_hs_ahb_clk",
1516 .ops = &clk_ops_branch,
1517 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1518 },
1519};
1520
1521static struct branch_clk gcc_usb_hs_system_clk = {
1522 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1523 .has_sibling = 0,
1524 .bcr_reg = USB_HS_BCR,
1525 .base = &virt_bases[GCC_BASE],
1526 .c = {
1527 .dbg_name = "gcc_usb_hs_system_clk",
1528 .parent = &usb_hs_system_clk_src.c,
1529 .ops = &clk_ops_branch,
1530 CLK_INIT(gcc_usb_hs_system_clk.c),
1531 },
1532};
1533
1534static struct branch_clk gcc_usb_hsic_ahb_clk = {
1535 .cbcr_reg = USB_HSIC_AHB_CBCR,
1536 .has_sibling = 1,
1537 .base = &virt_bases[GCC_BASE],
1538 .c = {
1539 .dbg_name = "gcc_usb_hsic_ahb_clk",
1540 .ops = &clk_ops_branch,
1541 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1542 },
1543};
1544
1545static struct branch_clk gcc_usb_hsic_clk = {
1546 .cbcr_reg = USB_HSIC_CBCR,
1547 .has_sibling = 0,
1548 .bcr_reg = USB_HS_HSIC_BCR,
1549 .base = &virt_bases[GCC_BASE],
1550 .c = {
1551 .dbg_name = "gcc_usb_hsic_clk",
1552 .parent = &usb_hsic_clk_src.c,
1553 .ops = &clk_ops_branch,
1554 CLK_INIT(gcc_usb_hsic_clk.c),
1555 },
1556};
1557
1558static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1559 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1560 .has_sibling = 0,
1561 .base = &virt_bases[GCC_BASE],
1562 .c = {
1563 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1564 .parent = &usb_hsic_io_cal_clk_src.c,
1565 .ops = &clk_ops_branch,
1566 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1567 },
1568};
1569
1570static struct branch_clk gcc_usb_hsic_system_clk = {
1571 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1572 .has_sibling = 0,
1573 .bcr_reg = USB_HS_HSIC_BCR,
1574 .base = &virt_bases[GCC_BASE],
1575 .c = {
1576 .dbg_name = "gcc_usb_hsic_system_clk",
1577 .parent = &usb_hsic_system_clk_src.c,
1578 .ops = &clk_ops_branch,
1579 CLK_INIT(gcc_usb_hsic_system_clk.c),
1580 },
1581};
1582
1583static struct measure_mux_entry measure_mux_GCC[] = {
1584 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
1585 { &gcc_noc_conf_xpu_ahb_clk.c, GCC_BASE, 0x0018 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1586 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1587 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1588 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1589 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1590 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1591 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1592 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1593 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1594 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1595 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1596 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1597 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1598 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1599 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1600 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1601 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1602 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1603 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1604 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1605 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1606 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1607 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1608 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1609 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1610 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1611 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1612 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1613 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1614 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1615 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1616 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1617 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1618 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1619 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1620 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1621 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1622 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1623 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1624 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1625 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1626 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1627 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1628 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1629 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1630 {&dummy_clk, N_BASES, 0x0000},
1631};
1632
1633static struct pll_vote_clk mmpll0_pll = {
1634 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1635 .en_mask = BIT(0),
1636 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1637 .status_mask = BIT(17),
1638 .base = &virt_bases[MMSS_BASE],
1639 .c = {
1640 .rate = 800000000,
1641 .parent = &xo.c,
1642 .dbg_name = "mmpll0_pll",
1643 .ops = &clk_ops_pll_vote,
1644 CLK_INIT(mmpll0_pll.c),
1645 },
1646};
1647
1648static struct pll_vote_clk mmpll1_pll = {
1649 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1650 .en_mask = BIT(1),
1651 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1652 .status_mask = BIT(17),
1653 .base = &virt_bases[MMSS_BASE],
1654 .c = {
1655 .rate = 1000000000,
1656 .parent = &xo.c,
1657 .dbg_name = "mmpll1_pll",
1658 .ops = &clk_ops_pll_vote,
1659 CLK_INIT(mmpll1_pll.c),
1660 },
1661};
1662
1663static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1664 F_MMSS( 19200000, xo, 1, 0, 0),
1665 F_MMSS( 37500000, gpll0, 16, 0, 0),
1666 F_MMSS( 50000000, gpll0, 12, 0, 0),
1667 F_MMSS( 75000000, gpll0, 8, 0, 0),
1668 F_MMSS( 100000000, gpll0, 6, 0, 0),
1669 F_MMSS( 150000000, gpll0, 4, 0, 0),
1670 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1671 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1672 F_END
1673};
1674
1675static struct rcg_clk axi_clk_src = {
1676 .cmd_rcgr_reg = AXI_CMD_RCGR,
1677 .set_rate = set_rate_hid,
1678 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1679 .current_freq = &rcg_dummy_freq,
1680 .base = &virt_bases[MMSS_BASE],
1681 .c = {
1682 .dbg_name = "axi_clk_src",
1683 .ops = &clk_ops_rcg,
1684 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1685 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1686 CLK_INIT(axi_clk_src.c),
1687 },
1688};
1689
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1690static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1691 F_MMSS( 100000000, gpll0, 6, 0, 0),
1692 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1693 F_END
1694};
1695
1696static struct rcg_clk csi0_clk_src = {
1697 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1698 .set_rate = set_rate_hid,
1699 .freq_tbl = ftbl_camss_csi0_1_clk,
1700 .current_freq = &rcg_dummy_freq,
1701 .base = &virt_bases[MMSS_BASE],
1702 .c = {
1703 .dbg_name = "csi0_clk_src",
1704 .ops = &clk_ops_rcg,
1705 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1706 CLK_INIT(csi0_clk_src.c),
1707 },
1708};
1709
1710static struct rcg_clk csi1_clk_src = {
1711 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1712 .set_rate = set_rate_hid,
1713 .freq_tbl = ftbl_camss_csi0_1_clk,
1714 .current_freq = &rcg_dummy_freq,
1715 .base = &virt_bases[MMSS_BASE],
1716 .c = {
1717 .dbg_name = "csi1_clk_src",
1718 .ops = &clk_ops_rcg,
1719 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1720 CLK_INIT(csi1_clk_src.c),
1721 },
1722};
1723
1724static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1725 F_MMSS( 37500000, gpll0, 16, 0, 0),
1726 F_MMSS( 50000000, gpll0, 12, 0, 0),
1727 F_MMSS( 60000000, gpll0, 10, 0, 0),
1728 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1729 F_MMSS( 100000000, gpll0, 6, 0, 0),
1730 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1731 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1732 F_MMSS( 200000000, gpll0, 3, 0, 0),
1733 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1734 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1735 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1736 F_END
1737};
1738
1739static struct rcg_clk vfe0_clk_src = {
1740 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1741 .set_rate = set_rate_hid,
1742 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1743 .current_freq = &rcg_dummy_freq,
1744 .base = &virt_bases[MMSS_BASE],
1745 .c = {
1746 .dbg_name = "vfe0_clk_src",
1747 .ops = &clk_ops_rcg,
1748 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1749 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1750 CLK_INIT(vfe0_clk_src.c),
1751 },
1752};
1753
1754static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1755 F_MMSS( 37500000, gpll0, 16, 0, 0),
1756 F_MMSS( 60000000, gpll0, 10, 0, 0),
1757 F_MMSS( 75000000, gpll0, 8, 0, 0),
1758 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1759 F_MMSS( 100000000, gpll0, 6, 0, 0),
1760 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1761 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1762 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1763 F_END
1764};
1765
1766static struct rcg_clk mdp_clk_src = {
1767 .cmd_rcgr_reg = MDP_CMD_RCGR,
1768 .set_rate = set_rate_hid,
1769 .freq_tbl = ftbl_mdss_mdp_clk,
1770 .current_freq = &rcg_dummy_freq,
1771 .base = &virt_bases[MMSS_BASE],
1772 .c = {
1773 .dbg_name = "mdp_clk_src",
1774 .ops = &clk_ops_rcg,
1775 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1776 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1777 CLK_INIT(mdp_clk_src.c),
1778 },
1779};
1780
1781static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1782 F_MMSS( 75000000, gpll0, 8, 0, 0),
1783 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1784 F_MMSS( 200000000, gpll0, 3, 0, 0),
1785 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1786 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1787 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1788 F_END
1789};
1790
1791static struct rcg_clk jpeg0_clk_src = {
1792 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1793 .set_rate = set_rate_hid,
1794 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1795 .current_freq = &rcg_dummy_freq,
1796 .base = &virt_bases[MMSS_BASE],
1797 .c = {
1798 .dbg_name = "jpeg0_clk_src",
1799 .ops = &clk_ops_rcg,
1800 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1801 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1802 CLK_INIT(jpeg0_clk_src.c),
1803 },
1804};
1805
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1806static struct branch_clk mdss_ahb_clk;
1807static struct clk dsipll0_byte_clk_src = {
1808 .depends = &mdss_ahb_clk.c,
1809 .parent = &xo.c,
1810 .dbg_name = "dsipll0_byte_clk_src",
1811 .ops = &clk_ops_dsi_byte_pll,
1812 CLK_INIT(dsipll0_byte_clk_src),
1813};
1814
1815static struct clk dsipll0_pixel_clk_src = {
1816 .depends = &mdss_ahb_clk.c,
1817 .parent = &xo.c,
1818 .dbg_name = "dsipll0_pixel_clk_src",
1819 .ops = &clk_ops_dsi_pixel_pll,
1820 CLK_INIT(dsipll0_pixel_clk_src),
1821};
1822
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1823static struct clk_freq_tbl pixel_freq_tbl[] = {
1824 {
1825 .src_clk = &dsipll0_pixel_clk_src,
1826 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val),
1827 },
1828 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1829};
1830
1831static struct rcg_clk pclk0_clk_src = {
1832 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1833 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1834 .base = &virt_bases[MMSS_BASE],
1835 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1836 .parent = &dsipll0_pixel_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1837 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1838 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1839 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1840 CLK_INIT(pclk0_clk_src.c),
1841 },
1842};
1843
1844static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1845 F_MMSS( 66700000, gpll0, 9, 0, 0),
1846 F_MMSS( 100000000, gpll0, 6, 0, 0),
1847 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1848 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1849 F_END
1850};
1851
1852static struct rcg_clk vcodec0_clk_src = {
1853 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1854 .set_rate = set_rate_mnd,
1855 .freq_tbl = ftbl_venus0_vcodec0_clk,
1856 .current_freq = &rcg_dummy_freq,
1857 .base = &virt_bases[MMSS_BASE],
1858 .c = {
1859 .dbg_name = "vcodec0_clk_src",
1860 .ops = &clk_ops_rcg_mnd,
1861 VDD_DIG_FMAX_MAP3(LOW, 66670000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1862 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1863 CLK_INIT(vcodec0_clk_src.c),
1864 },
1865};
1866
1867static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1868 F_MMSS( 19200000, xo, 1, 0, 0),
1869 F_END
1870};
1871
1872static struct rcg_clk cci_clk_src = {
1873 .cmd_rcgr_reg = CCI_CMD_RCGR,
1874 .set_rate = set_rate_mnd,
1875 .freq_tbl = ftbl_camss_cci_cci_clk,
1876 .current_freq = &rcg_dummy_freq,
1877 .base = &virt_bases[MMSS_BASE],
1878 .c = {
1879 .dbg_name = "cci_clk_src",
1880 .ops = &clk_ops_rcg_mnd,
1881 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1882 CLK_INIT(cci_clk_src.c),
1883 },
1884};
1885
1886static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1887 F_MMSS( 10000, xo, 16, 1, 120),
1888 F_MMSS( 24000, xo, 16, 1, 50),
1889 F_MMSS( 6000000, gpll0, 10, 1, 10),
1890 F_MMSS( 12000000, gpll0, 10, 1, 5),
1891 F_MMSS( 13000000, gpll0, 4, 13, 150),
1892 F_MMSS( 24000000, gpll0, 5, 1, 5),
1893 F_END
1894};
1895
1896static struct rcg_clk mmss_gp0_clk_src = {
1897 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1898 .set_rate = set_rate_mnd,
1899 .freq_tbl = ftbl_camss_gp0_1_clk,
1900 .current_freq = &rcg_dummy_freq,
1901 .base = &virt_bases[MMSS_BASE],
1902 .c = {
1903 .dbg_name = "mmss_gp0_clk_src",
1904 .ops = &clk_ops_rcg_mnd,
1905 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1906 CLK_INIT(mmss_gp0_clk_src.c),
1907 },
1908};
1909
1910static struct rcg_clk mmss_gp1_clk_src = {
1911 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1912 .set_rate = set_rate_mnd,
1913 .freq_tbl = ftbl_camss_gp0_1_clk,
1914 .current_freq = &rcg_dummy_freq,
1915 .base = &virt_bases[MMSS_BASE],
1916 .c = {
1917 .dbg_name = "mmss_gp1_clk_src",
1918 .ops = &clk_ops_rcg_mnd,
1919 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1920 CLK_INIT(mmss_gp1_clk_src.c),
1921 },
1922};
1923
1924static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1925 F_MMSS( 19200000, xo, 1, 0, 0),
1926 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1927 F_MMSS( 66670000, gpll0, 9, 0, 0),
1928 F_END
1929};
1930
1931static struct rcg_clk mclk0_clk_src = {
1932 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1933 .set_rate = set_rate_mnd,
1934 .freq_tbl = ftbl_camss_mclk0_1_clk,
1935 .current_freq = &rcg_dummy_freq,
1936 .base = &virt_bases[MMSS_BASE],
1937 .c = {
1938 .dbg_name = "mclk0_clk_src",
1939 .ops = &clk_ops_rcg_mnd,
1940 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1941 CLK_INIT(mclk0_clk_src.c),
1942 },
1943};
1944
1945static struct rcg_clk mclk1_clk_src = {
1946 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1947 .set_rate = set_rate_mnd,
1948 .freq_tbl = ftbl_camss_mclk0_1_clk,
1949 .current_freq = &rcg_dummy_freq,
1950 .base = &virt_bases[MMSS_BASE],
1951 .c = {
1952 .dbg_name = "mclk1_clk_src",
1953 .ops = &clk_ops_rcg_mnd,
1954 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1955 CLK_INIT(mclk1_clk_src.c),
1956 },
1957};
1958
1959static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1960 F_MMSS( 100000000, gpll0, 6, 0, 0),
1961 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1962 F_END
1963};
1964
1965static struct rcg_clk csi0phytimer_clk_src = {
1966 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1967 .set_rate = set_rate_hid,
1968 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1969 .current_freq = &rcg_dummy_freq,
1970 .base = &virt_bases[MMSS_BASE],
1971 .c = {
1972 .dbg_name = "csi0phytimer_clk_src",
1973 .ops = &clk_ops_rcg,
1974 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1975 CLK_INIT(csi0phytimer_clk_src.c),
1976 },
1977};
1978
1979static struct rcg_clk csi1phytimer_clk_src = {
1980 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1981 .set_rate = set_rate_hid,
1982 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1983 .current_freq = &rcg_dummy_freq,
1984 .base = &virt_bases[MMSS_BASE],
1985 .c = {
1986 .dbg_name = "csi1phytimer_clk_src",
1987 .ops = &clk_ops_rcg,
1988 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1989 CLK_INIT(csi1phytimer_clk_src.c),
1990 },
1991};
1992
1993static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
1994 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1995 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1996 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1997 F_END
1998};
1999
2000static struct rcg_clk cpp_clk_src = {
2001 .cmd_rcgr_reg = CPP_CMD_RCGR,
2002 .set_rate = set_rate_hid,
2003 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2004 .current_freq = &rcg_dummy_freq,
2005 .base = &virt_bases[MMSS_BASE],
2006 .c = {
2007 .dbg_name = "cpp_clk_src",
2008 .ops = &clk_ops_rcg,
2009 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2010 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2011 CLK_INIT(cpp_clk_src.c),
2012 },
2013};
2014
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2015static struct clk_freq_tbl byte_freq_tbl[] = {
2016 {
2017 .src_clk = &dsipll0_byte_clk_src,
2018 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
2019 },
2020 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2021};
2022
2023static struct rcg_clk byte0_clk_src = {
2024 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2025 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2026 .base = &virt_bases[MMSS_BASE],
2027 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2028 .parent = &dsipll0_byte_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2029 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2030 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2031 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2032 CLK_INIT(byte0_clk_src.c),
2033 },
2034};
2035
2036static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2037 F_MDSS( 19200000, xo, 1, 0, 0),
2038 F_END
2039};
2040
2041static struct rcg_clk esc0_clk_src = {
2042 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2043 .set_rate = set_rate_hid,
2044 .freq_tbl = ftbl_mdss_esc0_clk,
2045 .current_freq = &rcg_dummy_freq,
2046 .base = &virt_bases[MMSS_BASE],
2047 .c = {
2048 .dbg_name = "esc0_clk_src",
2049 .ops = &clk_ops_rcg,
2050 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2051 CLK_INIT(esc0_clk_src.c),
2052 },
2053};
2054
2055static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2056 F_MDSS( 19200000, xo, 1, 0, 0),
2057 F_END
2058};
2059
2060static struct rcg_clk vsync_clk_src = {
2061 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2062 .set_rate = set_rate_hid,
2063 .freq_tbl = ftbl_mdss_vsync_clk,
2064 .current_freq = &rcg_dummy_freq,
2065 .base = &virt_bases[MMSS_BASE],
2066 .c = {
2067 .dbg_name = "vsync_clk_src",
2068 .ops = &clk_ops_rcg,
2069 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2070 CLK_INIT(vsync_clk_src.c),
2071 },
2072};
2073
2074static struct branch_clk camss_cci_cci_ahb_clk = {
2075 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2076 .has_sibling = 1,
2077 .base = &virt_bases[MMSS_BASE],
2078 .c = {
2079 .dbg_name = "camss_cci_cci_ahb_clk",
2080 .ops = &clk_ops_branch,
2081 CLK_INIT(camss_cci_cci_ahb_clk.c),
2082 },
2083};
2084
2085static struct branch_clk camss_cci_cci_clk = {
2086 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2087 .has_sibling = 0,
2088 .base = &virt_bases[MMSS_BASE],
2089 .c = {
2090 .dbg_name = "camss_cci_cci_clk",
2091 .parent = &cci_clk_src.c,
2092 .ops = &clk_ops_branch,
2093 CLK_INIT(camss_cci_cci_clk.c),
2094 },
2095};
2096
2097static struct branch_clk camss_csi0_ahb_clk = {
2098 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2099 .has_sibling = 1,
2100 .base = &virt_bases[MMSS_BASE],
2101 .c = {
2102 .dbg_name = "camss_csi0_ahb_clk",
2103 .ops = &clk_ops_branch,
2104 CLK_INIT(camss_csi0_ahb_clk.c),
2105 },
2106};
2107
2108static struct branch_clk camss_csi0_clk = {
2109 .cbcr_reg = CAMSS_CSI0_CBCR,
2110 .has_sibling = 1,
2111 .base = &virt_bases[MMSS_BASE],
2112 .c = {
2113 .dbg_name = "camss_csi0_clk",
2114 .parent = &csi0_clk_src.c,
2115 .ops = &clk_ops_branch,
2116 CLK_INIT(camss_csi0_clk.c),
2117 },
2118};
2119
2120static struct branch_clk camss_csi0phy_clk = {
2121 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2122 .has_sibling = 1,
2123 .base = &virt_bases[MMSS_BASE],
2124 .c = {
2125 .dbg_name = "camss_csi0phy_clk",
2126 .parent = &csi0_clk_src.c,
2127 .ops = &clk_ops_branch,
2128 CLK_INIT(camss_csi0phy_clk.c),
2129 },
2130};
2131
2132static struct branch_clk camss_csi0pix_clk = {
2133 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2134 .has_sibling = 1,
2135 .base = &virt_bases[MMSS_BASE],
2136 .c = {
2137 .dbg_name = "camss_csi0pix_clk",
2138 .parent = &csi0_clk_src.c,
2139 .ops = &clk_ops_branch,
2140 CLK_INIT(camss_csi0pix_clk.c),
2141 },
2142};
2143
2144static struct branch_clk camss_csi0rdi_clk = {
2145 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2146 .has_sibling = 1,
2147 .base = &virt_bases[MMSS_BASE],
2148 .c = {
2149 .dbg_name = "camss_csi0rdi_clk",
2150 .parent = &csi0_clk_src.c,
2151 .ops = &clk_ops_branch,
2152 CLK_INIT(camss_csi0rdi_clk.c),
2153 },
2154};
2155
2156static struct branch_clk camss_csi1_ahb_clk = {
2157 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2158 .has_sibling = 1,
2159 .base = &virt_bases[MMSS_BASE],
2160 .c = {
2161 .dbg_name = "camss_csi1_ahb_clk",
2162 .ops = &clk_ops_branch,
2163 CLK_INIT(camss_csi1_ahb_clk.c),
2164 },
2165};
2166
2167static struct branch_clk camss_csi1_clk = {
2168 .cbcr_reg = CAMSS_CSI1_CBCR,
2169 .has_sibling = 1,
2170 .base = &virt_bases[MMSS_BASE],
2171 .c = {
2172 .dbg_name = "camss_csi1_clk",
2173 .parent = &csi1_clk_src.c,
2174 .ops = &clk_ops_branch,
2175 CLK_INIT(camss_csi1_clk.c),
2176 },
2177};
2178
2179static struct branch_clk camss_csi1phy_clk = {
2180 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2181 .has_sibling = 1,
2182 .base = &virt_bases[MMSS_BASE],
2183 .c = {
2184 .dbg_name = "camss_csi1phy_clk",
2185 .parent = &csi1_clk_src.c,
2186 .ops = &clk_ops_branch,
2187 CLK_INIT(camss_csi1phy_clk.c),
2188 },
2189};
2190
2191static struct branch_clk camss_csi1pix_clk = {
2192 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2193 .has_sibling = 1,
2194 .base = &virt_bases[MMSS_BASE],
2195 .c = {
2196 .dbg_name = "camss_csi1pix_clk",
2197 .parent = &csi1_clk_src.c,
2198 .ops = &clk_ops_branch,
2199 CLK_INIT(camss_csi1pix_clk.c),
2200 },
2201};
2202
2203static struct branch_clk camss_csi1rdi_clk = {
2204 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2205 .has_sibling = 1,
2206 .base = &virt_bases[MMSS_BASE],
2207 .c = {
2208 .dbg_name = "camss_csi1rdi_clk",
2209 .parent = &csi1_clk_src.c,
2210 .ops = &clk_ops_branch,
2211 CLK_INIT(camss_csi1rdi_clk.c),
2212 },
2213};
2214
2215static struct branch_clk camss_csi_vfe0_clk = {
2216 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2217 .has_sibling = 1,
2218 .base = &virt_bases[MMSS_BASE],
2219 .c = {
2220 .dbg_name = "camss_csi_vfe0_clk",
2221 .parent = &vfe0_clk_src.c,
2222 .ops = &clk_ops_branch,
2223 CLK_INIT(camss_csi_vfe0_clk.c),
2224 },
2225};
2226
2227static struct branch_clk camss_gp0_clk = {
2228 .cbcr_reg = CAMSS_GP0_CBCR,
2229 .has_sibling = 0,
2230 .base = &virt_bases[MMSS_BASE],
2231 .c = {
2232 .dbg_name = "camss_gp0_clk",
2233 .parent = &mmss_gp0_clk_src.c,
2234 .ops = &clk_ops_branch,
2235 CLK_INIT(camss_gp0_clk.c),
2236 },
2237};
2238
2239static struct branch_clk camss_gp1_clk = {
2240 .cbcr_reg = CAMSS_GP1_CBCR,
2241 .has_sibling = 0,
2242 .base = &virt_bases[MMSS_BASE],
2243 .c = {
2244 .dbg_name = "camss_gp1_clk",
2245 .parent = &mmss_gp1_clk_src.c,
2246 .ops = &clk_ops_branch,
2247 CLK_INIT(camss_gp1_clk.c),
2248 },
2249};
2250
2251static struct branch_clk camss_ispif_ahb_clk = {
2252 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2253 .has_sibling = 1,
2254 .base = &virt_bases[MMSS_BASE],
2255 .c = {
2256 .dbg_name = "camss_ispif_ahb_clk",
2257 .ops = &clk_ops_branch,
2258 CLK_INIT(camss_ispif_ahb_clk.c),
2259 },
2260};
2261
2262static struct branch_clk camss_jpeg_jpeg0_clk = {
2263 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
2264 .has_sibling = 0,
2265 .base = &virt_bases[MMSS_BASE],
2266 .c = {
2267 .dbg_name = "camss_jpeg_jpeg0_clk",
2268 .parent = &jpeg0_clk_src.c,
2269 .ops = &clk_ops_branch,
2270 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2271 },
2272};
2273
2274static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2275 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2276 .has_sibling = 1,
2277 .base = &virt_bases[MMSS_BASE],
2278 .c = {
2279 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2280 .ops = &clk_ops_branch,
2281 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2282 },
2283};
2284
2285static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2286 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2287 .has_sibling = 1,
2288 .base = &virt_bases[MMSS_BASE],
2289 .c = {
2290 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2291 .parent = &axi_clk_src.c,
2292 .ops = &clk_ops_branch,
2293 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2294 },
2295};
2296
2297static struct branch_clk camss_mclk0_clk = {
2298 .cbcr_reg = CAMSS_MCLK0_CBCR,
2299 .has_sibling = 0,
2300 .base = &virt_bases[MMSS_BASE],
2301 .c = {
2302 .dbg_name = "camss_mclk0_clk",
2303 .parent = &mclk0_clk_src.c,
2304 .ops = &clk_ops_branch,
2305 CLK_INIT(camss_mclk0_clk.c),
2306 },
2307};
2308
2309static struct branch_clk camss_mclk1_clk = {
2310 .cbcr_reg = CAMSS_MCLK1_CBCR,
2311 .has_sibling = 0,
2312 .base = &virt_bases[MMSS_BASE],
2313 .c = {
2314 .dbg_name = "camss_mclk1_clk",
2315 .parent = &mclk1_clk_src.c,
2316 .ops = &clk_ops_branch,
2317 CLK_INIT(camss_mclk1_clk.c),
2318 },
2319};
2320
2321static struct branch_clk camss_micro_ahb_clk = {
2322 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2323 .has_sibling = 1,
2324 .base = &virt_bases[MMSS_BASE],
2325 .c = {
2326 .dbg_name = "camss_micro_ahb_clk",
2327 .ops = &clk_ops_branch,
2328 CLK_INIT(camss_micro_ahb_clk.c),
2329 },
2330};
2331
2332static struct branch_clk camss_phy0_csi0phytimer_clk = {
2333 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2334 .has_sibling = 0,
2335 .base = &virt_bases[MMSS_BASE],
2336 .c = {
2337 .dbg_name = "camss_phy0_csi0phytimer_clk",
2338 .parent = &csi0phytimer_clk_src.c,
2339 .ops = &clk_ops_branch,
2340 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2341 },
2342};
2343
2344static struct branch_clk camss_phy1_csi1phytimer_clk = {
2345 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2346 .has_sibling = 0,
2347 .base = &virt_bases[MMSS_BASE],
2348 .c = {
2349 .dbg_name = "camss_phy1_csi1phytimer_clk",
2350 .parent = &csi1phytimer_clk_src.c,
2351 .ops = &clk_ops_branch,
2352 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2353 },
2354};
2355
2356static struct branch_clk camss_top_ahb_clk = {
2357 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2358 .has_sibling = 1,
2359 .base = &virt_bases[MMSS_BASE],
2360 .c = {
2361 .dbg_name = "camss_top_ahb_clk",
2362 .ops = &clk_ops_branch,
2363 CLK_INIT(camss_top_ahb_clk.c),
2364 },
2365};
2366
2367static struct branch_clk camss_vfe_cpp_ahb_clk = {
2368 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2369 .has_sibling = 1,
2370 .base = &virt_bases[MMSS_BASE],
2371 .c = {
2372 .dbg_name = "camss_vfe_cpp_ahb_clk",
2373 .ops = &clk_ops_branch,
2374 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2375 },
2376};
2377
2378static struct branch_clk camss_vfe_cpp_clk = {
2379 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2380 .has_sibling = 0,
2381 .base = &virt_bases[MMSS_BASE],
2382 .c = {
2383 .dbg_name = "camss_vfe_cpp_clk",
2384 .parent = &cpp_clk_src.c,
2385 .ops = &clk_ops_branch,
2386 CLK_INIT(camss_vfe_cpp_clk.c),
2387 },
2388};
2389
2390static struct branch_clk camss_vfe_vfe0_clk = {
2391 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
2392 .has_sibling = 1,
2393 .base = &virt_bases[MMSS_BASE],
2394 .c = {
2395 .dbg_name = "camss_vfe_vfe0_clk",
2396 .parent = &vfe0_clk_src.c,
2397 .ops = &clk_ops_branch,
2398 CLK_INIT(camss_vfe_vfe0_clk.c),
2399 },
2400};
2401
2402static struct branch_clk camss_vfe_vfe_ahb_clk = {
2403 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2404 .has_sibling = 1,
2405 .base = &virt_bases[MMSS_BASE],
2406 .c = {
2407 .dbg_name = "camss_vfe_vfe_ahb_clk",
2408 .ops = &clk_ops_branch,
2409 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2410 },
2411};
2412
2413static struct branch_clk camss_vfe_vfe_axi_clk = {
2414 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2415 .has_sibling = 1,
2416 .base = &virt_bases[MMSS_BASE],
2417 .c = {
2418 .dbg_name = "camss_vfe_vfe_axi_clk",
2419 .parent = &axi_clk_src.c,
2420 .ops = &clk_ops_branch,
2421 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2422 },
2423};
2424
2425static struct branch_clk mdss_ahb_clk = {
2426 .cbcr_reg = MDSS_AHB_CBCR,
2427 .has_sibling = 1,
2428 .base = &virt_bases[MMSS_BASE],
2429 .c = {
2430 .dbg_name = "mdss_ahb_clk",
2431 .ops = &clk_ops_branch,
2432 CLK_INIT(mdss_ahb_clk.c),
2433 },
2434};
2435
2436static struct branch_clk mdss_axi_clk = {
2437 .cbcr_reg = MDSS_AXI_CBCR,
2438 .has_sibling = 1,
2439 .base = &virt_bases[MMSS_BASE],
2440 .c = {
2441 .dbg_name = "mdss_axi_clk",
2442 .parent = &axi_clk_src.c,
2443 .ops = &clk_ops_branch,
2444 CLK_INIT(mdss_axi_clk.c),
2445 },
2446};
2447
2448static struct branch_clk mdss_byte0_clk = {
2449 .cbcr_reg = MDSS_BYTE0_CBCR,
2450 .has_sibling = 0,
2451 .base = &virt_bases[MMSS_BASE],
2452 .c = {
2453 .dbg_name = "mdss_byte0_clk",
2454 .parent = &byte0_clk_src.c,
2455 .ops = &clk_ops_branch,
2456 CLK_INIT(mdss_byte0_clk.c),
2457 },
2458};
2459
2460static struct branch_clk mdss_esc0_clk = {
2461 .cbcr_reg = MDSS_ESC0_CBCR,
2462 .has_sibling = 0,
2463 .base = &virt_bases[MMSS_BASE],
2464 .c = {
2465 .dbg_name = "mdss_esc0_clk",
2466 .parent = &esc0_clk_src.c,
2467 .ops = &clk_ops_branch,
2468 CLK_INIT(mdss_esc0_clk.c),
2469 },
2470};
2471
2472static struct branch_clk mdss_mdp_clk = {
2473 .cbcr_reg = MDSS_MDP_CBCR,
2474 .has_sibling = 1,
2475 .base = &virt_bases[MMSS_BASE],
2476 .c = {
2477 .dbg_name = "mdss_mdp_clk",
2478 .parent = &mdp_clk_src.c,
2479 .ops = &clk_ops_branch,
2480 CLK_INIT(mdss_mdp_clk.c),
2481 },
2482};
2483
2484static struct branch_clk mdss_mdp_lut_clk = {
2485 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2486 .has_sibling = 1,
2487 .base = &virt_bases[MMSS_BASE],
2488 .c = {
2489 .dbg_name = "mdss_mdp_lut_clk",
2490 .parent = &mdp_clk_src.c,
2491 .ops = &clk_ops_branch,
2492 CLK_INIT(mdss_mdp_lut_clk.c),
2493 },
2494};
2495
2496static struct branch_clk mdss_pclk0_clk = {
2497 .cbcr_reg = MDSS_PCLK0_CBCR,
2498 .has_sibling = 0,
2499 .base = &virt_bases[MMSS_BASE],
2500 .c = {
2501 .dbg_name = "mdss_pclk0_clk",
2502 .parent = &pclk0_clk_src.c,
2503 .ops = &clk_ops_branch,
2504 CLK_INIT(mdss_pclk0_clk.c),
2505 },
2506};
2507
2508static struct branch_clk mdss_vsync_clk = {
2509 .cbcr_reg = MDSS_VSYNC_CBCR,
2510 .has_sibling = 0,
2511 .base = &virt_bases[MMSS_BASE],
2512 .c = {
2513 .dbg_name = "mdss_vsync_clk",
2514 .parent = &vsync_clk_src.c,
2515 .ops = &clk_ops_branch,
2516 CLK_INIT(mdss_vsync_clk.c),
2517 },
2518};
2519
2520static struct branch_clk mmss_misc_ahb_clk = {
2521 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2522 .has_sibling = 1,
2523 .base = &virt_bases[MMSS_BASE],
2524 .c = {
2525 .dbg_name = "mmss_misc_ahb_clk",
2526 .ops = &clk_ops_branch,
2527 CLK_INIT(mmss_misc_ahb_clk.c),
2528 },
2529};
2530
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2531static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2532 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2533 .has_sibling = 1,
2534 .base = &virt_bases[MMSS_BASE],
2535 .c = {
2536 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2537 .ops = &clk_ops_branch,
2538 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2539 },
2540};
2541
2542static struct branch_clk mmss_mmssnoc_axi_clk = {
2543 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2544 .has_sibling = 1,
2545 .base = &virt_bases[MMSS_BASE],
2546 .c = {
2547 .dbg_name = "mmss_mmssnoc_axi_clk",
2548 .parent = &axi_clk_src.c,
2549 .ops = &clk_ops_branch,
2550 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2551 },
2552};
2553
2554static struct branch_clk mmss_s0_axi_clk = {
2555 .cbcr_reg = MMSS_S0_AXI_CBCR,
2556 .has_sibling = 0,
2557 .max_div = 0,
2558 .base = &virt_bases[MMSS_BASE],
2559 .c = {
2560 .dbg_name = "mmss_s0_axi_clk",
2561 .parent = &axi_clk_src.c,
2562 .ops = &clk_ops_branch,
2563 CLK_INIT(mmss_s0_axi_clk.c),
2564 .depends = &mmss_mmssnoc_axi_clk.c,
2565 },
2566};
2567
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2568static struct branch_clk oxili_gfx3d_clk = {
2569 .cbcr_reg = OXILI_GFX3D_CBCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2570 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2571 .max_div = 0,
2572 .base = &virt_bases[MMSS_BASE],
2573 .c = {
2574 .dbg_name = "oxili_gfx3d_clk",
2575 .parent = &gfx3d_clk_src.c,
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2578 },
2579};
2580
2581static struct branch_clk oxilicx_ahb_clk = {
2582 .cbcr_reg = OXILICX_AHB_CBCR,
2583 .has_sibling = 1,
2584 .base = &virt_bases[MMSS_BASE],
2585 .c = {
2586 .dbg_name = "oxilicx_ahb_clk",
2587 .ops = &clk_ops_branch,
2588 CLK_INIT(oxilicx_ahb_clk.c),
2589 },
2590};
2591
2592static struct branch_clk oxilicx_axi_clk = {
2593 .cbcr_reg = OXILICX_AXI_CBCR,
2594 .has_sibling = 1,
2595 .base = &virt_bases[MMSS_BASE],
2596 .c = {
2597 .dbg_name = "oxilicx_axi_clk",
2598 .parent = &axi_clk_src.c,
2599 .ops = &clk_ops_branch,
2600 CLK_INIT(oxilicx_axi_clk.c),
2601 },
2602};
2603
2604static struct branch_clk venus0_ahb_clk = {
2605 .cbcr_reg = VENUS0_AHB_CBCR,
2606 .has_sibling = 1,
2607 .base = &virt_bases[MMSS_BASE],
2608 .c = {
2609 .dbg_name = "venus0_ahb_clk",
2610 .ops = &clk_ops_branch,
2611 CLK_INIT(venus0_ahb_clk.c),
2612 },
2613};
2614
2615static struct branch_clk venus0_axi_clk = {
2616 .cbcr_reg = VENUS0_AXI_CBCR,
2617 .has_sibling = 1,
2618 .base = &virt_bases[MMSS_BASE],
2619 .c = {
2620 .dbg_name = "venus0_axi_clk",
2621 .parent = &axi_clk_src.c,
2622 .ops = &clk_ops_branch,
2623 CLK_INIT(venus0_axi_clk.c),
2624 },
2625};
2626
2627static struct branch_clk venus0_vcodec0_clk = {
2628 .cbcr_reg = VENUS0_VCODEC0_CBCR,
2629 .has_sibling = 0,
2630 .base = &virt_bases[MMSS_BASE],
2631 .c = {
2632 .dbg_name = "venus0_vcodec0_clk",
2633 .parent = &vcodec0_clk_src.c,
2634 .ops = &clk_ops_branch,
2635 CLK_INIT(venus0_vcodec0_clk.c),
2636 },
2637};
2638
2639static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2640 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2641 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2642 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2643 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2644 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2645 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2646 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2647 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2648 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2649 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2650 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2651 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2652 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2653 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2654 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2655 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2656 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2657 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2658 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2659 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2660 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2661 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2662 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2663 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2664 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2665 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2666 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2667 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2668 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2669 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2670 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2671 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2672 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2673 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2674 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2675 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2676 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2677 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2678 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2679 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2680 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2681 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2682 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2683 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2684 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2685 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2686 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2687 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2688 {&dummy_clk, N_BASES, 0x0000},
2689};
2690
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2691static struct branch_clk q6ss_ahb_lfabif_clk = {
2692 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2693 .has_sibling = 1,
2694 .base = &virt_bases[LPASS_BASE],
2695 .c = {
2696 .dbg_name = "q6ss_ahb_lfabif_clk",
2697 .ops = &clk_ops_branch,
2698 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2699 },
2700};
2701
2702static struct branch_clk q6ss_ahbm_clk = {
2703 .cbcr_reg = Q6SS_AHBM_CBCR,
2704 .has_sibling = 1,
2705 .base = &virt_bases[LPASS_BASE],
2706 .c = {
2707 .dbg_name = "q6ss_ahbm_clk",
2708 .ops = &clk_ops_branch,
2709 CLK_INIT(q6ss_ahbm_clk.c),
2710 },
2711};
2712
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2713static struct branch_clk q6ss_xo_clk = {
2714 .cbcr_reg = Q6SS_XO_CBCR,
2715 .has_sibling = 1,
2716 .bcr_reg = Q6SS_BCR,
2717 .base = &virt_bases[LPASS_BASE],
2718 .c = {
2719 .dbg_name = "q6ss_xo_clk",
2720 .parent = &xo.c,
2721 .ops = &clk_ops_branch,
2722 CLK_INIT(q6ss_xo_clk.c),
2723 },
2724};
2725
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2726static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2727 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2728 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2729 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2730 {&dummy_clk, N_BASES, 0x0000},
2731};
2732
2733
2734static DEFINE_CLK_MEASURE(apc0_m_clk);
2735static DEFINE_CLK_MEASURE(apc1_m_clk);
2736static DEFINE_CLK_MEASURE(apc2_m_clk);
2737static DEFINE_CLK_MEASURE(apc3_m_clk);
2738static DEFINE_CLK_MEASURE(l2_m_clk);
2739
2740static struct measure_mux_entry measure_mux_APSS[] = {
2741 {&apc0_m_clk, APCS_BASE, 0x00010},
2742 {&apc1_m_clk, APCS_BASE, 0x00114},
2743 {&apc2_m_clk, APCS_BASE, 0x00220},
2744 {&apc3_m_clk, APCS_BASE, 0x00324},
2745 {&l2_m_clk, APCS_BASE, 0x01000},
2746 {&dummy_clk, N_BASES, 0x0000}
2747};
2748
2749#define APCS_SH_PLL_MODE (0x000)
2750#define APCS_SH_PLL_L_VAL (0x004)
2751#define APCS_SH_PLL_M_VAL (0x008)
2752#define APCS_SH_PLL_N_VAL (0x00C)
2753#define APCS_SH_PLL_USER_CTL (0x010)
2754#define APCS_SH_PLL_CONFIG_CTL (0x014)
2755#define APCS_SH_PLL_STATUS (0x01C)
2756
2757enum vdd_sr2_pll_levels {
2758 VDD_SR2_PLL_OFF,
2759 VDD_SR2_PLL_ON,
2760 VDD_SR2_PLL_NUM
2761};
2762
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2763static struct regulator *vdd_sr2_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2764static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level)
2765{
2766 if (level == VDD_SR2_PLL_ON) {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2767 return regulator_set_voltage(vdd_sr2_reg, 1800000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2768 1800000);
2769 } else {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2770 return regulator_set_voltage(vdd_sr2_reg, 0, 1800000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2771 }
2772}
2773
2774static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll,
2775 VDD_SR2_PLL_NUM);
2776
2777static struct pll_freq_tbl apcs_pll_freq[] = {
2778 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
2779 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2780 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
2781 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
2782 PLL_F_END
2783};
2784
2785static struct pll_clk a7sspll = {
2786 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2787 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2788 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2789 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2790 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2791 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2792 .freq_tbl = apcs_pll_freq,
2793 .masks = {
2794 .vco_mask = BM(29, 28),
2795 .pre_div_mask = BIT(12),
2796 .post_div_mask = BM(9, 8),
2797 .mn_en_mask = BIT(24),
2798 .main_output_mask = BIT(0),
2799 },
2800 .base = &virt_bases[APCS_PLL_BASE],
2801 .c = {
2802 .dbg_name = "a7sspll",
2803 .ops = &clk_ops_sr2_pll,
2804 .vdd_class = &vdd_sr2_pll,
2805 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
2806 [VDD_SR2_PLL_ON] = ULONG_MAX,
2807 },
2808 .num_fmax = VDD_SR2_PLL_NUM,
2809 CLK_INIT(a7sspll.c),
2810 /*
2811 * Need to skip handoff of the acpu pll to avoid
2812 * turning off the pll when the cpu is using it
2813 */
2814 .flags = CLKFLAG_SKIP_HANDOFF,
2815 },
2816};
2817
2818static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2819static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2820static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2821static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2822static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2823static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2824
2825static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2826static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2827static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2828static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2829static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2830static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2831static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2832
2833static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2834
2835#ifdef CONFIG_DEBUG_FS
2836static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2837{
2838 struct measure_clk *clk = to_measure_clk(c);
2839 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2840 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2841 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2842 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2843 measure_mux_GCC,
2844 measure_mux_MMSS,
2845 measure_mux_LPASS,
2846 measure_mux_APSS,
2847 NULL
2848 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2849 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2850
2851 if (!parent)
2852 return -EINVAL;
2853
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2854 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2855 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2856 if (mux->c == parent) {
2857 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2858 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2859 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2860 }
2861
2862 if (mux->c == &dummy_clk)
2863 return -EINVAL;
2864
2865 spin_lock_irqsave(&local_clock_reg_lock, flags);
2866 /*
2867 * Program the test vector, measurement period (sample_ticks)
2868 * and scaling multiplier.
2869 */
2870 clk->sample_ticks = 0x10000;
2871 clk->multiplier = 1;
2872
2873 switch (mux->base) {
2874
2875 case GCC_BASE:
2876 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2877 clk_sel = mux->debug_mux;
2878 break;
2879
2880 case MMSS_BASE:
2881 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2882 clk_sel = 0x02C;
2883 regval = BVAL(11, 0, mux->debug_mux);
2884 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2885
2886 /* Activate debug clock output */
2887 regval |= BIT(16);
2888 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2889 break;
2890
2891 case LPASS_BASE:
2892 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2893 clk_sel = 0x161;
2894 regval = BVAL(11, 0, mux->debug_mux);
2895 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2896
2897 /* Activate debug clock output */
2898 regval |= BIT(20);
2899 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2900 break;
2901
2902 case APCS_BASE:
2903 clk->multiplier = 4;
2904 clk_sel = 362;
2905 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2906 regval &= ~0xC0037335;
2907 /* configure a divider of 4 */
2908 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2909 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2910 break;
2911
2912 default:
2913 return -EINVAL;
2914 }
2915
2916 /* Set debug mux clock index */
2917 regval = BVAL(8, 0, clk_sel);
2918 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2919
2920 /* Activate debug clock output */
2921 regval |= BIT(16);
2922 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2923
2924 /* Make sure test vector is set before starting measurements. */
2925 mb();
2926 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2927
2928 return 0;
2929}
2930
2931/* Sample clock for 'ticks' reference clock ticks. */
2932static u32 run_measurement(unsigned ticks)
2933{
2934 /* Stop counters and set the XO4 counter start value. */
2935 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2936
2937 /* Wait for timer to become ready. */
2938 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2939 BIT(25)) != 0)
2940 cpu_relax();
2941
2942 /* Run measurement and wait for completion. */
2943 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2944 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2945 BIT(25)) == 0)
2946 cpu_relax();
2947
2948 /* Return measured ticks. */
2949 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2950 BM(24, 0);
2951}
2952
2953/*
2954 * Perform a hardware rate measurement for a given clock.
2955 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
2956 */
2957static unsigned long measure_clk_get_rate(struct clk *c)
2958{
2959 unsigned long flags;
2960 u32 gcc_xo4_reg_backup;
2961 u64 raw_count_short, raw_count_full;
2962 struct measure_clk *clk = to_measure_clk(c);
2963 unsigned ret;
2964
2965 ret = clk_prepare_enable(&xo.c);
2966 if (ret) {
2967 pr_warn("CXO clock failed to enable. Can't measure\n");
2968 return 0;
2969 }
2970
2971 spin_lock_irqsave(&local_clock_reg_lock, flags);
2972
2973 /* Enable CXO/4 and RINGOSC branch. */
2974 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2975 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2976
2977 /*
2978 * The ring oscillator counter will not reset if the measured clock
2979 * is not running. To detect this, run a short measurement before
2980 * the full measurement. If the raw results of the two are the same
2981 * then the clock must be off.
2982 */
2983
2984 /* Run a short measurement. (~1 ms) */
2985 raw_count_short = run_measurement(0x1000);
2986 /* Run a full measurement. (~14 ms) */
2987 raw_count_full = run_measurement(clk->sample_ticks);
2988
2989 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2990
2991 /* Return 0 if the clock is off. */
2992 if (raw_count_full == raw_count_short) {
2993 ret = 0;
2994 } else {
2995 /* Compute rate in Hz. */
2996 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
2997 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
2998 ret = (raw_count_full * clk->multiplier);
2999 }
3000
3001 writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG));
3002 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3003
3004 clk_disable_unprepare(&xo.c);
3005
3006 return ret;
3007}
3008
3009#else /* !CONFIG_DEBUG_FS */
3010static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3011{
3012 return -EINVAL;
3013}
3014
3015static unsigned long measure_clk_get_rate(struct clk *clk)
3016{
3017 return 0;
3018}
3019#endif /* CONFIG_DEBUG_FS */
3020
3021static struct clk_ops clk_ops_measure = {
3022 .set_parent = measure_clk_set_parent,
3023 .get_rate = measure_clk_get_rate,
3024};
3025
3026static struct measure_clk measure_clk = {
3027 .c = {
3028 .dbg_name = "measure_clk",
3029 .ops = &clk_ops_measure,
3030 CLK_INIT(measure_clk.c),
3031 },
3032 .multiplier = 1,
3033};
3034
3035static struct clk_lookup msm_clocks_8226[] = {
3036 /* Debug Clocks */
3037 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3038 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3039 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3040 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3041 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3042 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3043
3044 /* PIL-LPASS */
3045 CLK_LOOKUP("xo", xo.c, "fe200000.qcom,lpass"),
3046 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3047 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3048 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3049 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3050
3051 /* PIL-MODEM */
3052 CLK_LOOKUP("xo", xo.c, "fc880000.qcom,mss"),
3053 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3054 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3055 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
3056
3057 /* PIL-PRONTO */
3058 CLK_LOOKUP("xo", xo.c, "fb21b000.qcom,pronto"),
3059
3060 /* PIL-VENUS */
3061 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3062 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3063 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3064 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3065 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3066
3067 /* ACPUCLOCK */
3068 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3069 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3070 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
3071
3072 /* WCNSS CLOCKS */
Patrick Dalyc6355d22013-03-06 13:39:48 -0800[diff] [blame]3073 CLK_LOOKUP("xo", xo.c, "fb000000.qcom,wcnss-wlan"),
3074 CLK_LOOKUP("rf_clk", cxo_a2.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3075
3076 /* BUS DRIVER */
3077 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3078 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3079 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3080 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3081 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3082 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3083 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3084 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3085 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3086 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3087 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3088 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3089 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3090
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3091 /* CoreSight clocks */
3092 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3093 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3094 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3095 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3096 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3097 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3098 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3099 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3100 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3101 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3102 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3103 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3104 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3105 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3106 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3107 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3108 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3109 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3110 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3111 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3112 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3113 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3114 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3115 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3116 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3117 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3118 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3119 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3120 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3121 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3122 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3123 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3124
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3125 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3126 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3127 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3128 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3129 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3130 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3131 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3132 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3133 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3134 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3135 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3136 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3137 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3138 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3139 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33c000.jtagmm"),
3140 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33d000.jtagmm"),
3141 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33e000.jtagmm"),
3142 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3143 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3144 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3145 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3146 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3147 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3148 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3149 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3150 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3151 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3152 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3153 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3154 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3155 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3156 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3157
3158 /* HSUSB-OTG Clocks */
3159 CLK_LOOKUP("xo", xo.c, "f9a55000.usb"),
3160 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3161 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3162
3163 /* SPS CLOCKS */
3164 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3165 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3166 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3167 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3168
3169 /* I2C Clocks */
3170 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3171 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3172
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3173 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3174 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3175
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3176 /* lsuart-v14 Clocks */
3177 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3178 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3179
3180 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3181 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3182
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3183 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3184 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3185
3186 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3187 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3188 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
3189 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "qseecom"),
3190
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3191 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3192 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3193 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
3194 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "scm"),
3195
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3196 /* SDCC */
3197 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3198 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3199 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3200 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3201
3202 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3203 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3204 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3205 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3206
3207 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3208 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3209
3210 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3211 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3212
3213
3214 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3215 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3216 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3217 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3218 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3219 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3220 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3221 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3222 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3223 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3224 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3225
3226 CLK_LOOKUP("gpll0", gpll0.c, ""),
3227 CLK_LOOKUP("gpll1", gpll1.c, ""),
3228 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3229 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3230
3231 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3232 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3233 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
3234 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""),
3235 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3236 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3237 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3238 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3239 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3240 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3241 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3242 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3243 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3244 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3245 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3246 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3247 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3248 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3249 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3250 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3251 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3252
3253 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3254 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3255 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3256 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3257 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3258 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3259 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3260 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3261
3262 /* Multimedia clocks */
3263 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3264 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3265 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
3266 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdss_dsi_clk_ctrl"),
3267
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3268 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3269 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3270 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3271 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3272 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3273 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3274
3275 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3276 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3277
3278 /* MM sensor clocks */
3279 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6e.qcom,camera"),
3280 CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
3281 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6e.qcom,camera"),
3282 CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
3283
3284 /* CCI clocks */
3285 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3286 "fda0c000.qcom,cci"),
3287 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3288 "fda0c000.qcom,cci"),
3289 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3290 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3291
3292 /* CSIPHY clocks */
3293 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3294 "fda0ac00.qcom,csiphy"),
3295 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3296 "fda0ac00.qcom,csiphy"),
3297 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3298 "fda0ac00.qcom,csiphy"),
3299 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3300 "fda0ac00.qcom,csiphy"),
3301 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3302 "fda0b000.qcom,csiphy"),
3303 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3304 "fda0b000.qcom,csiphy"),
3305 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3306 "fda0b000.qcom,csiphy"),
3307 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3308 "fda0b000.qcom,csiphy"),
3309
3310 /* CSID clocks */
3311 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3312 "fda08000.qcom,csid"),
3313 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3314 "fda08000.qcom,csid"),
3315 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08000.qcom,csid"),
3316 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08000.qcom,csid"),
3317 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08000.qcom,csid"),
3318 CLK_LOOKUP("csi0_clk", camss_csi0_clk.c, "fda08000.qcom,csid"),
3319 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08000.qcom,csid"),
3320 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08000.qcom,csid"),
3321
3322 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3323 "fda08400.qcom,csid"),
3324 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3325 "fda08400.qcom,csid"),
3326 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08400.qcom,csid"),
3327 CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c, "fda08400.qcom,csid"),
3328 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08400.qcom,csid"),
3329 CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c, "fda08400.qcom,csid"),
3330 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08400.qcom,csid"),
3331 CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c, "fda08400.qcom,csid"),
3332 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08400.qcom,csid"),
3333 CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c, "fda08400.qcom,csid"),
3334 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08400.qcom,csid"),
3335 CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c, "fda08400.qcom,csid"),
3336
3337 /* ISPIF clocks */
3338 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3339 "fda0a000.qcom,ispif"),
3340 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3341 "fda0a000.qcom,ispif"),
3342
3343 /* VFE clocks */
3344 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3345 "fda10000.qcom,vfe"),
3346 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3347 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3348 "fda10000.qcom,vfe"),
3349 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3350 "fda10000.qcom,vfe"),
3351 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3352 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3353
3354 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3355 "fda44000.qcom,iommu"),
3356 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3357 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3358
3359 /* Jpeg Clocks */
3360 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3361 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3362 "fda1c000.qcom,jpeg"),
3363 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3364 "fda1c000.qcom,jpeg"),
3365 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3366 "fda1c000.qcom,jpeg"),
3367
3368 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3369 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3370 "fda64000.qcom,iommu"),
3371 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3372 "fda64000.qcom,iommu"),
3373
3374 /* KGSL Clocks */
3375 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3376 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3377 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3378 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3379
3380 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3381 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3382 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3383
3384 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3385
3386 /* Venus Clocks */
3387 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3388 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3389 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3390
3391 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3392 "fdc84000.qcom,iommu"),
3393 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3394 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3395 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3396 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3397 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3398 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3399
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3400 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3401 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3402 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3403
3404 /* Audio clocks */
3405 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3406 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3407 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3408 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3409 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3410 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3411
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3412};
3413
3414static struct clk_lookup msm_clocks_8226_rumi[] = {
3415 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3416 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3417 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3418 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3419 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3420 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3421 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3422 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3423 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3424 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3425};
3426
3427struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3428 .table = msm_clocks_8226_rumi,
3429 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3430};
3431
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3432static void __init reg_init(void)
3433{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3434 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3435
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3436 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3437 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3438 regval |= BIT(0);
3439 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3440
3441 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3442 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3443 */
3444 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3445}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3446
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3447static void __init msm8226_clock_post_init(void)
3448{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3449 /*
3450 * Hold an active set vote for CXO; this is because CXO is expected
3451 * to remain on whenever CPUs aren't power collapsed.
3452 */
3453 clk_prepare_enable(&xo_a_clk.c);
3454
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3455 /* Set rates for single-rate clocks. */
3456 clk_set_rate(&usb_hs_system_clk_src.c,
3457 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3458 clk_set_rate(&usb_hsic_clk_src.c,
3459 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3460 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3461 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3462 clk_set_rate(&usb_hsic_system_clk_src.c,
3463 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3464 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3465 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3466 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3467 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3468 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3469 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3470}
3471
3472#define GCC_CC_PHYS 0xFC400000
3473#define GCC_CC_SIZE SZ_16K
3474
3475#define MMSS_CC_PHYS 0xFD8C0000
3476#define MMSS_CC_SIZE SZ_256K
3477
3478#define LPASS_CC_PHYS 0xFE000000
3479#define LPASS_CC_SIZE SZ_256K
3480
3481#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3482#define APCS_KPSS_SH_PLL_SIZE SZ_64
3483
3484#define APCS_KPSS_GLB_PHYS 0xF9011000
3485#define APCS_KPSS_GLB_SIZE SZ_4K
3486
3487
3488static void __init msm8226_clock_pre_init(void)
3489{
3490 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3491 if (!virt_bases[GCC_BASE])
3492 panic("clock-8226: Unable to ioremap GCC memory!");
3493
3494 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3495 if (!virt_bases[MMSS_BASE])
3496 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3497
3498 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3499 if (!virt_bases[LPASS_BASE])
3500 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3501
3502 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3503 APCS_KPSS_GLB_SIZE);
3504 if (!virt_bases[APCS_BASE])
3505 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3506
3507 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3508 APCS_KPSS_SH_PLL_SIZE);
3509 if (!virt_bases[APCS_PLL_BASE])
3510 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3511
3512 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3513
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3514 vdd_dig_reg = regulator_get(NULL, "vdd_dig");
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3515 if (IS_ERR(vdd_dig_reg))
3516 panic("clock-8226: Unable to get the vdd_dig regulator!");
3517
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3518 vdd_sr2_reg = regulator_get(NULL, "vdd_sr2_pll");
3519 if (IS_ERR(vdd_dig_reg))
3520 panic("clock-8226: Unable to get the sr2_pll regulator!");
3521
3522 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3523 * These regulators are used at boot. Ensure they stay on
3524 * while the clock framework comes online.
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3525 */
3526 regulator_set_voltage(vdd_sr2_reg, 1800000, 1800000);
3527 regulator_enable(vdd_sr2_reg);
3528
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3529 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3530 regulator_enable(vdd_dig_reg);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3531
3532 /*
3533 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3534 * source. Sleep set vote is 0.
3535 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3536 * access mmss clock controller registers.
3537 */
3538 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3539
Vikram Mulukutla29a06a32013-03-14 10:54:02 -0700[diff] [blame]3540 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3541 clk_set_rate(&axi_clk_src.c, 200000000);
3542
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3543 enable_rpm_scaling();
3544
3545 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3546
3547 /*
3548 * MDSS needs the ahb clock and needs to init before we register the
3549 * lookup table.
3550 */
3551 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3552}
3553
3554static int __init msm8226_clock_late_init(void)
3555{
3556 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
3557}
3558
3559struct clock_init_data msm8226_clock_init_data __initdata = {
3560 .table = msm_clocks_8226,
3561 .size = ARRAY_SIZE(msm_clocks_8226),
3562 .pre_init = msm8226_clock_pre_init,
3563 .post_init = msm8226_clock_post_init,
3564 .late_init = msm8226_clock_late_init,
3565};