Pushkar Joshi | e0e8a7e | 2012-12-15 18:27:04 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/regulator/consumer.h> |
| 22 | #include <linux/iopoll.h> |
| 23 | |
| 24 | #include <mach/clk.h> |
| 25 | #include <mach/rpm-regulator-smd.h> |
| 26 | #include <mach/socinfo.h> |
| 27 | |
| 28 | #include "clock-local2.h" |
| 29 | #include "clock-pll.h" |
| 30 | #include "clock-rpm.h" |
| 31 | #include "clock-voter.h" |
| 32 | #include "clock.h" |
| 33 | |
| 34 | enum { |
| 35 | GCC_BASE, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 36 | APCS_BASE, |
| 37 | APCS_PLL_BASE, |
| 38 | N_BASES, |
| 39 | }; |
| 40 | |
| 41 | static void __iomem *virt_bases[N_BASES]; |
| 42 | |
| 43 | #define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x)) |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 44 | #define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x)) |
| 45 | #define APCS_PLL_REG_BASE(x) (void __iomem *)(virt_bases[APCS_PLL_BASE] + (x)) |
| 46 | |
| 47 | /* GCC registers */ |
| 48 | #define GPLL0_MODE_REG 0x0000 |
| 49 | #define GPLL0_L_REG 0x0004 |
| 50 | #define GPLL0_M_REG 0x0008 |
| 51 | #define GPLL0_N_REG 0x000C |
| 52 | #define GPLL0_USER_CTL_REG 0x0010 |
| 53 | #define GPLL0_CONFIG_CTL_REG 0x0014 |
| 54 | #define GPLL0_TEST_CTL_REG 0x0018 |
| 55 | #define GPLL0_STATUS_REG 0x001C |
| 56 | |
| 57 | #define GPLL1_MODE_REG 0x0040 |
| 58 | #define GPLL1_L_REG 0x0044 |
| 59 | #define GPLL1_M_REG 0x0048 |
| 60 | #define GPLL1_N_REG 0x004C |
| 61 | #define GPLL1_USER_CTL_REG 0x0050 |
| 62 | #define GPLL1_CONFIG_CTL_REG 0x0054 |
| 63 | #define GPLL1_TEST_CTL_REG 0x0058 |
| 64 | #define GPLL1_STATUS_REG 0x005C |
| 65 | |
| 66 | #define GCC_DEBUG_CLK_CTL_REG 0x1880 |
| 67 | #define CLOCK_FRQ_MEASURE_CTL_REG 0x1884 |
| 68 | #define CLOCK_FRQ_MEASURE_STATUS_REG 0x1888 |
| 69 | #define GCC_PLLTEST_PAD_CFG_REG 0x188C |
| 70 | #define GCC_XO_DIV4_CBCR_REG 0x10C8 |
| 71 | #define APCS_GPLL_ENA_VOTE_REG 0x1480 |
| 72 | #define APCS_CLOCK_BRANCH_ENA_VOTE 0x1484 |
| 73 | #define APCS_CLOCK_SLEEP_ENA_VOTE 0x1488 |
| 74 | |
| 75 | #define APCS_CLK_DIAG_REG 0x001C |
| 76 | |
| 77 | #define APCS_CPU_PLL_MODE_REG 0x0000 |
| 78 | #define APCS_CPU_PLL_L_REG 0x0004 |
| 79 | #define APCS_CPU_PLL_M_REG 0x0008 |
| 80 | #define APCS_CPU_PLL_N_REG 0x000C |
| 81 | #define APCS_CPU_PLL_USER_CTL_REG 0x0010 |
| 82 | #define APCS_CPU_PLL_CONFIG_CTL_REG 0x0014 |
| 83 | #define APCS_CPU_PLL_TEST_CTL_REG 0x0018 |
| 84 | #define APCS_CPU_PLL_STATUS_REG 0x001C |
| 85 | |
| 86 | #define USB_HSIC_SYSTEM_CMD_RCGR 0x041C |
| 87 | #define USB_HSIC_XCVR_FS_CMD_RCGR 0x0424 |
| 88 | #define USB_HSIC_CMD_RCGR 0x0440 |
| 89 | #define USB_HSIC_IO_CAL_CMD_RCGR 0x0458 |
| 90 | #define USB_HS_SYSTEM_CMD_RCGR 0x0490 |
| 91 | #define SDCC2_APPS_CMD_RCGR 0x0510 |
| 92 | #define SDCC3_APPS_CMD_RCGR 0x0550 |
| 93 | #define BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x064C |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 94 | #define BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x0660 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 95 | #define BLSP1_UART1_APPS_CMD_RCGR 0x068C |
| 96 | #define BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x06CC |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 97 | #define BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x06E0 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 98 | #define BLSP1_UART2_APPS_CMD_RCGR 0x070C |
| 99 | #define BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x074C |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 100 | #define BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x0760 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 101 | #define BLSP1_UART3_APPS_CMD_RCGR 0x078C |
| 102 | #define BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x07CC |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 103 | #define BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x07E0 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 104 | #define BLSP1_UART4_APPS_CMD_RCGR 0x080C |
| 105 | #define BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x084C |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 106 | #define BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x0860 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 107 | #define BLSP1_UART5_APPS_CMD_RCGR 0x088C |
| 108 | #define BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x08CC |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 109 | #define BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x08E0 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 110 | #define BLSP1_UART6_APPS_CMD_RCGR 0x090C |
| 111 | #define PDM2_CMD_RCGR 0x0CD0 |
| 112 | #define CE1_CMD_RCGR 0x1050 |
| 113 | #define GP1_CMD_RCGR 0x1904 |
| 114 | #define GP2_CMD_RCGR 0x1944 |
| 115 | #define GP3_CMD_RCGR 0x1984 |
| 116 | #define QPIC_CMD_RCGR 0x1A50 |
| 117 | #define IPA_CMD_RCGR 0x1A90 |
| 118 | |
| 119 | #define USB_HS_HSIC_BCR 0x0400 |
| 120 | #define USB_HS_BCR 0x0480 |
| 121 | #define SDCC2_BCR 0x0500 |
| 122 | #define SDCC3_BCR 0x0540 |
| 123 | #define BLSP1_BCR 0x05C0 |
| 124 | #define BLSP1_QUP1_BCR 0x0640 |
| 125 | #define BLSP1_UART1_BCR 0x0680 |
| 126 | #define BLSP1_QUP2_BCR 0x06C0 |
| 127 | #define BLSP1_UART2_BCR 0x0700 |
| 128 | #define BLSP1_QUP3_BCR 0x0740 |
| 129 | #define BLSP1_UART3_BCR 0x0780 |
| 130 | #define BLSP1_QUP4_BCR 0x07C0 |
| 131 | #define BLSP1_UART4_BCR 0x0800 |
| 132 | #define BLSP1_QUP5_BCR 0x0840 |
| 133 | #define BLSP1_UART5_BCR 0x0880 |
| 134 | #define BLSP1_QUP6_BCR 0x08C0 |
| 135 | #define BLSP1_UART6_BCR 0x0900 |
| 136 | #define PDM_BCR 0x0CC0 |
| 137 | #define PRNG_BCR 0x0D00 |
| 138 | #define BAM_DMA_BCR 0x0D40 |
| 139 | #define BOOT_ROM_BCR 0x0E00 |
| 140 | #define CE1_BCR 0x1040 |
| 141 | #define QPIC_BCR 0x1040 |
| 142 | #define IPA_BCR 0x1A80 |
| 143 | |
| 144 | |
| 145 | #define SYS_NOC_IPA_AXI_CBCR 0x0128 |
| 146 | #define USB_HSIC_AHB_CBCR 0x0408 |
| 147 | #define USB_HSIC_SYSTEM_CBCR 0x040C |
| 148 | #define USB_HSIC_CBCR 0x0410 |
| 149 | #define USB_HSIC_IO_CAL_CBCR 0x0414 |
| 150 | #define USB_HSIC_XCVR_FS_CBCR 0x042C |
| 151 | #define USB_HS_SYSTEM_CBCR 0x0484 |
| 152 | #define USB_HS_AHB_CBCR 0x0488 |
| 153 | #define SDCC2_APPS_CBCR 0x0504 |
| 154 | #define SDCC2_AHB_CBCR 0x0508 |
| 155 | #define SDCC3_APPS_CBCR 0x0544 |
| 156 | #define SDCC3_AHB_CBCR 0x0548 |
| 157 | #define BLSP1_AHB_CBCR 0x05C4 |
| 158 | #define BLSP1_QUP1_SPI_APPS_CBCR 0x0644 |
| 159 | #define BLSP1_QUP1_I2C_APPS_CBCR 0x0648 |
| 160 | #define BLSP1_UART1_APPS_CBCR 0x0684 |
| 161 | #define BLSP1_UART1_SIM_CBCR 0x0688 |
| 162 | #define BLSP1_QUP2_SPI_APPS_CBCR 0x06C4 |
| 163 | #define BLSP1_QUP2_I2C_APPS_CBCR 0x06C8 |
| 164 | #define BLSP1_UART2_APPS_CBCR 0x0704 |
| 165 | #define BLSP1_UART2_SIM_CBCR 0x0708 |
| 166 | #define BLSP1_QUP3_SPI_APPS_CBCR 0x0744 |
| 167 | #define BLSP1_QUP3_I2C_APPS_CBCR 0x0748 |
| 168 | #define BLSP1_UART3_APPS_CBCR 0x0784 |
| 169 | #define BLSP1_UART3_SIM_CBCR 0x0788 |
| 170 | #define BLSP1_QUP4_SPI_APPS_CBCR 0x07C4 |
| 171 | #define BLSP1_QUP4_I2C_APPS_CBCR 0x07C8 |
| 172 | #define BLSP1_UART4_APPS_CBCR 0x0804 |
| 173 | #define BLSP1_UART4_SIM_CBCR 0x0808 |
| 174 | #define BLSP1_QUP5_SPI_APPS_CBCR 0x0844 |
| 175 | #define BLSP1_QUP5_I2C_APPS_CBCR 0x0848 |
| 176 | #define BLSP1_UART5_APPS_CBCR 0x0884 |
| 177 | #define BLSP1_UART5_SIM_CBCR 0x0888 |
| 178 | #define BLSP1_QUP6_SPI_APPS_CBCR 0x08C4 |
| 179 | #define BLSP1_QUP6_I2C_APPS_CBCR 0x08C8 |
| 180 | #define BLSP1_UART6_APPS_CBCR 0x0904 |
| 181 | #define BLSP1_UART6_SIM_CBCR 0x0908 |
| 182 | #define BOOT_ROM_AHB_CBCR 0x0E04 |
| 183 | #define PDM_AHB_CBCR 0x0CC4 |
| 184 | #define PDM_XO4_CBCR 0x0CC8 |
| 185 | #define PDM_AHB_CBCR 0x0CC4 |
| 186 | #define PDM_XO4_CBCR 0x0CC8 |
| 187 | #define PDM2_CBCR 0x0CCC |
| 188 | #define PRNG_AHB_CBCR 0x0D04 |
| 189 | #define BAM_DMA_AHB_CBCR 0x0D44 |
| 190 | #define MSG_RAM_AHB_CBCR 0x0E44 |
| 191 | #define CE1_CBCR 0x1044 |
| 192 | #define CE1_AXI_CBCR 0x1048 |
| 193 | #define CE1_AHB_CBCR 0x104C |
| 194 | #define GCC_AHB_CBCR 0x10C0 |
| 195 | #define GP1_CBCR 0x1900 |
| 196 | #define GP2_CBCR 0x1940 |
| 197 | #define GP3_CBCR 0x1980 |
| 198 | #define QPIC_CBCR 0x1A44 |
| 199 | #define QPIC_AHB_CBCR 0x1A48 |
| 200 | #define IPA_CBCR 0x1A84 |
| 201 | #define IPA_CNOC_CBCR 0x1A88 |
| 202 | #define IPA_SLEEP_CBCR 0x1A8C |
| 203 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 204 | /* Mux source select values */ |
| 205 | #define cxo_source_val 0 |
| 206 | #define gpll0_source_val 1 |
| 207 | #define gpll1_hsic_source_val 4 |
| 208 | #define gnd_source_val 5 |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 209 | |
Vikram Mulukutla | d3dca65 | 2012-11-19 11:04:13 -0800 | [diff] [blame] | 210 | #define F_GCC_GND \ |
| 211 | { \ |
| 212 | .freq_hz = 0, \ |
| 213 | .m_val = 0, \ |
| 214 | .n_val = 0, \ |
| 215 | .div_src_val = BVAL(4, 0, 1) | BVAL(10, 8, gnd_source_val), \ |
| 216 | } |
| 217 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 218 | #define F(f, s, div, m, n) \ |
| 219 | { \ |
| 220 | .freq_hz = (f), \ |
| 221 | .src_clk = &s##_clk_src.c, \ |
| 222 | .m_val = (m), \ |
| 223 | .n_val = ~((n)-(m)) * !!(n), \ |
| 224 | .d_val = ~(n),\ |
| 225 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 226 | | BVAL(10, 8, s##_source_val), \ |
| 227 | } |
| 228 | |
| 229 | #define F_HSIC(f, s, div, m, n) \ |
| 230 | { \ |
| 231 | .freq_hz = (f), \ |
| 232 | .src_clk = &s##_clk_src.c, \ |
| 233 | .m_val = (m), \ |
| 234 | .n_val = ~((n)-(m)) * !!(n), \ |
| 235 | .d_val = ~(n),\ |
| 236 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 237 | | BVAL(10, 8, s##_hsic_source_val), \ |
| 238 | } |
| 239 | |
Tianyi Gou | a717ddd | 2012-10-05 17:06:24 -0700 | [diff] [blame] | 240 | #define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \ |
| 241 | { \ |
| 242 | .freq_hz = (f), \ |
| 243 | .l_val = (l), \ |
| 244 | .m_val = (m), \ |
| 245 | .n_val = (n), \ |
| 246 | .pre_div_val = BVAL(14, 12, (pre_div)), \ |
| 247 | .post_div_val = BVAL(9, 8, (post_div)), \ |
| 248 | .vco_val = BVAL(21, 20, (vco)), \ |
| 249 | } |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 250 | |
| 251 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
Saravana Kannan | 55e959d | 2012-10-15 22:16:04 -0700 | [diff] [blame] | 252 | .vdd_class = &vdd_dig, \ |
| 253 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 254 | [VDD_DIG_##l1] = (f1), \ |
| 255 | }, \ |
| 256 | .num_fmax = VDD_DIG_NUM |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 257 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
Saravana Kannan | 55e959d | 2012-10-15 22:16:04 -0700 | [diff] [blame] | 258 | .vdd_class = &vdd_dig, \ |
| 259 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 260 | [VDD_DIG_##l1] = (f1), \ |
| 261 | [VDD_DIG_##l2] = (f2), \ |
| 262 | }, \ |
| 263 | .num_fmax = VDD_DIG_NUM |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 264 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
Saravana Kannan | 55e959d | 2012-10-15 22:16:04 -0700 | [diff] [blame] | 265 | .vdd_class = &vdd_dig, \ |
| 266 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 267 | [VDD_DIG_##l1] = (f1), \ |
| 268 | [VDD_DIG_##l2] = (f2), \ |
| 269 | [VDD_DIG_##l3] = (f3), \ |
| 270 | }, \ |
| 271 | .num_fmax = VDD_DIG_NUM |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 272 | |
| 273 | enum vdd_dig_levels { |
| 274 | VDD_DIG_NONE, |
| 275 | VDD_DIG_LOW, |
| 276 | VDD_DIG_NOMINAL, |
Saravana Kannan | 55e959d | 2012-10-15 22:16:04 -0700 | [diff] [blame] | 277 | VDD_DIG_HIGH, |
| 278 | VDD_DIG_NUM |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | static const int vdd_corner[] = { |
| 282 | [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE, |
| 283 | [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC, |
| 284 | [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL, |
| 285 | [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO, |
| 286 | }; |
| 287 | |
| 288 | static struct regulator *vdd_dig_reg; |
| 289 | |
| 290 | int set_vdd_dig(struct clk_vdd_class *vdd_class, int level) |
| 291 | { |
| 292 | return regulator_set_voltage(vdd_dig_reg, vdd_corner[level], |
| 293 | RPM_REGULATOR_CORNER_SUPER_TURBO); |
| 294 | } |
| 295 | |
Saravana Kannan | 55e959d | 2012-10-15 22:16:04 -0700 | [diff] [blame] | 296 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig, VDD_DIG_NUM); |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 297 | |
| 298 | /* TODO: Needs to confirm the below values */ |
| 299 | #define RPM_MISC_CLK_TYPE 0x306b6c63 |
| 300 | #define RPM_BUS_CLK_TYPE 0x316b6c63 |
| 301 | #define RPM_MEM_CLK_TYPE 0x326b6c63 |
| 302 | |
| 303 | #define RPM_SMD_KEY_ENABLE 0x62616E45 |
| 304 | |
| 305 | #define CXO_ID 0x0 |
| 306 | #define QDSS_ID 0x1 |
| 307 | |
| 308 | #define PNOC_ID 0x0 |
| 309 | #define SNOC_ID 0x1 |
| 310 | #define CNOC_ID 0x2 |
| 311 | |
| 312 | #define BIMC_ID 0x0 |
| 313 | |
| 314 | #define D0_ID 1 |
| 315 | #define D1_ID 2 |
| 316 | #define A0_ID 3 |
| 317 | #define A1_ID 4 |
| 318 | #define A2_ID 5 |
| 319 | |
| 320 | DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_a_clk_src, |
| 321 | RPM_MISC_CLK_TYPE, CXO_ID, 19200000); |
| 322 | |
| 323 | DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL); |
| 324 | DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL); |
| 325 | DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL); |
| 326 | |
| 327 | DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL); |
| 328 | |
| 329 | DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID); |
| 330 | |
| 331 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID); |
| 332 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID); |
| 333 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID); |
| 334 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID); |
| 335 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID); |
| 336 | |
| 337 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID); |
| 338 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID); |
| 339 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID); |
| 340 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID); |
| 341 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID); |
| 342 | |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 343 | static unsigned int soft_vote_gpll0; |
| 344 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 345 | static struct pll_vote_clk gpll0_clk_src = { |
| 346 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG, |
Tianyi Gou | 2aee465 | 2013-03-11 19:15:22 -0700 | [diff] [blame] | 347 | .en_mask = BIT(0), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 348 | .status_reg = (void __iomem *)GPLL0_STATUS_REG, |
| 349 | .status_mask = BIT(17), |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 350 | .soft_vote = &soft_vote_gpll0, |
| 351 | .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 352 | .base = &virt_bases[GCC_BASE], |
| 353 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 354 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 355 | .rate = 600000000, |
| 356 | .dbg_name = "gpll0_clk_src", |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 357 | .ops = &clk_ops_pll_acpu_vote, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 358 | CLK_INIT(gpll0_clk_src.c), |
| 359 | }, |
| 360 | }; |
| 361 | |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 362 | static struct pll_vote_clk gpll0_activeonly_clk_src = { |
| 363 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG, |
Tianyi Gou | 2aee465 | 2013-03-11 19:15:22 -0700 | [diff] [blame] | 364 | .en_mask = BIT(0), |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 365 | .status_reg = (void __iomem *)GPLL0_STATUS_REG, |
| 366 | .status_mask = BIT(17), |
| 367 | .soft_vote = &soft_vote_gpll0, |
| 368 | .soft_vote_mask = PLL_SOFT_VOTE_ACPU, |
| 369 | .base = &virt_bases[GCC_BASE], |
| 370 | .c = { |
| 371 | .rate = 600000000, |
| 372 | .dbg_name = "gpll0_activeonly_clk_src", |
| 373 | .ops = &clk_ops_pll_acpu_vote, |
| 374 | CLK_INIT(gpll0_activeonly_clk_src.c), |
| 375 | }, |
| 376 | }; |
| 377 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 378 | static struct pll_vote_clk gpll1_clk_src = { |
| 379 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG, |
| 380 | .en_mask = BIT(1), |
| 381 | .status_reg = (void __iomem *)GPLL1_STATUS_REG, |
| 382 | .status_mask = BIT(17), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 383 | .base = &virt_bases[GCC_BASE], |
| 384 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 385 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 386 | .rate = 480000000, |
| 387 | .dbg_name = "gpll1_clk_src", |
| 388 | .ops = &clk_ops_pll_vote, |
| 389 | CLK_INIT(gpll1_clk_src.c), |
| 390 | }, |
| 391 | }; |
| 392 | |
Tianyi Gou | a717ddd | 2012-10-05 17:06:24 -0700 | [diff] [blame] | 393 | static struct pll_freq_tbl apcs_pll_freq[] = { |
| 394 | F_APCS_PLL(748800000, 0x27, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 395 | F_APCS_PLL(998400000, 0x34, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 396 | PLL_F_END |
| 397 | }; |
| 398 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 399 | /* |
| 400 | * Need to skip handoff of the acpu pll to avoid handoff code |
| 401 | * to turn off the pll when the acpu is running off this pll. |
| 402 | */ |
| 403 | static struct pll_clk apcspll_clk_src = { |
| 404 | .mode_reg = (void __iomem *)APCS_CPU_PLL_MODE_REG, |
Tianyi Gou | a717ddd | 2012-10-05 17:06:24 -0700 | [diff] [blame] | 405 | .l_reg = (void __iomem *)APCS_CPU_PLL_L_REG, |
| 406 | .m_reg = (void __iomem *)APCS_CPU_PLL_M_REG, |
| 407 | .n_reg = (void __iomem *)APCS_CPU_PLL_N_REG, |
| 408 | .config_reg = (void __iomem *)APCS_CPU_PLL_USER_CTL_REG, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 409 | .status_reg = (void __iomem *)APCS_CPU_PLL_STATUS_REG, |
Tianyi Gou | a717ddd | 2012-10-05 17:06:24 -0700 | [diff] [blame] | 410 | .freq_tbl = apcs_pll_freq, |
| 411 | .masks = { |
| 412 | .vco_mask = BM(21, 20), |
| 413 | .pre_div_mask = BM(14, 12), |
| 414 | .post_div_mask = BM(9, 8), |
| 415 | .mn_en_mask = BIT(24), |
| 416 | .main_output_mask = BIT(0), |
| 417 | }, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 418 | .base = &virt_bases[APCS_PLL_BASE], |
| 419 | .c = { |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 420 | .dbg_name = "apcspll_clk_src", |
| 421 | .ops = &clk_ops_local_pll, |
| 422 | CLK_INIT(apcspll_clk_src.c), |
| 423 | .flags = CLKFLAG_SKIP_HANDOFF, |
| 424 | }, |
| 425 | }; |
| 426 | |
| 427 | static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX); |
| 428 | static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX); |
| 429 | static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX); |
| 430 | static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX); |
| 431 | static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX); |
| 432 | static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX); |
| 433 | |
| 434 | static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX); |
| 435 | static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 436 | |
| 437 | static DEFINE_CLK_VOTER(pnoc_sdcc2_clk, &pnoc_clk.c, LONG_MAX); |
| 438 | static DEFINE_CLK_VOTER(pnoc_sdcc3_clk, &pnoc_clk.c, LONG_MAX); |
| 439 | |
| 440 | static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX); |
| 441 | |
| 442 | static struct clk_freq_tbl ftbl_gcc_ipa_clk[] = { |
| 443 | F( 50000000, gpll0, 12, 0, 0), |
| 444 | F( 92310000, gpll0, 6.5, 0, 0), |
| 445 | F(100000000, gpll0, 6, 0, 0), |
| 446 | F_END |
| 447 | }; |
| 448 | |
| 449 | static struct rcg_clk ipa_clk_src = { |
| 450 | .cmd_rcgr_reg = IPA_CMD_RCGR, |
| 451 | .set_rate = set_rate_mnd, |
| 452 | .freq_tbl = ftbl_gcc_ipa_clk, |
| 453 | .current_freq = &rcg_dummy_freq, |
| 454 | .base = &virt_bases[GCC_BASE], |
| 455 | .c = { |
| 456 | .dbg_name = "ipa_clk_src", |
| 457 | .ops = &clk_ops_rcg_mnd, |
| 458 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 459 | CLK_INIT(ipa_clk_src.c) |
| 460 | }, |
| 461 | }; |
| 462 | |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 463 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { |
| 464 | F(19200000, cxo, 1, 0, 0), |
| 465 | F(50000000, gpll0, 12, 0, 0), |
| 466 | F_END |
| 467 | }; |
| 468 | |
| 469 | static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = { |
| 470 | .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR, |
| 471 | .set_rate = set_rate_hid, |
| 472 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 473 | .current_freq = &rcg_dummy_freq, |
| 474 | .base = &virt_bases[GCC_BASE], |
| 475 | .c = { |
| 476 | .dbg_name = "blsp1_qup1_i2c_apps_clk_src", |
| 477 | .ops = &clk_ops_rcg, |
| 478 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 479 | CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c), |
| 480 | }, |
| 481 | }; |
| 482 | |
| 483 | static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = { |
| 484 | .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR, |
| 485 | .set_rate = set_rate_hid, |
| 486 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 487 | .current_freq = &rcg_dummy_freq, |
| 488 | .base = &virt_bases[GCC_BASE], |
| 489 | .c = { |
| 490 | .dbg_name = "blsp1_qup2_i2c_apps_clk_src", |
| 491 | .ops = &clk_ops_rcg, |
| 492 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 493 | CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c), |
| 494 | }, |
| 495 | }; |
| 496 | |
| 497 | static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = { |
| 498 | .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR, |
| 499 | .set_rate = set_rate_hid, |
| 500 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 501 | .current_freq = &rcg_dummy_freq, |
| 502 | .base = &virt_bases[GCC_BASE], |
| 503 | .c = { |
| 504 | .dbg_name = "blsp1_qup3_i2c_apps_clk_src", |
| 505 | .ops = &clk_ops_rcg, |
| 506 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 507 | CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c), |
| 508 | }, |
| 509 | }; |
| 510 | |
| 511 | static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = { |
| 512 | .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR, |
| 513 | .set_rate = set_rate_hid, |
| 514 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 515 | .current_freq = &rcg_dummy_freq, |
| 516 | .base = &virt_bases[GCC_BASE], |
| 517 | .c = { |
| 518 | .dbg_name = "blsp1_qup4_i2c_apps_clk_src", |
| 519 | .ops = &clk_ops_rcg, |
| 520 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 521 | CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c), |
| 522 | }, |
| 523 | }; |
| 524 | |
| 525 | static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = { |
| 526 | .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR, |
| 527 | .set_rate = set_rate_hid, |
| 528 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 529 | .current_freq = &rcg_dummy_freq, |
| 530 | .base = &virt_bases[GCC_BASE], |
| 531 | .c = { |
| 532 | .dbg_name = "blsp1_qup5_i2c_apps_clk_src", |
| 533 | .ops = &clk_ops_rcg, |
| 534 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 535 | CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c), |
| 536 | }, |
| 537 | }; |
| 538 | |
| 539 | static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { |
| 540 | .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR, |
| 541 | .set_rate = set_rate_hid, |
| 542 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 543 | .current_freq = &rcg_dummy_freq, |
| 544 | .base = &virt_bases[GCC_BASE], |
| 545 | .c = { |
| 546 | .dbg_name = "blsp1_qup6_i2c_apps_clk_src", |
| 547 | .ops = &clk_ops_rcg, |
| 548 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 549 | CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c), |
| 550 | }, |
| 551 | }; |
| 552 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 553 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { |
| 554 | F( 960000, cxo, 10, 1, 2), |
| 555 | F( 4800000, cxo, 4, 0, 0), |
| 556 | F( 9600000, cxo, 2, 0, 0), |
| 557 | F(15000000, gpll0, 10, 1, 4), |
| 558 | F(19200000, cxo, 1, 0, 0), |
| 559 | F(25000000, gpll0, 12, 1, 2), |
| 560 | F(50000000, gpll0, 12, 0, 0), |
| 561 | F_END |
| 562 | }; |
| 563 | |
| 564 | static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { |
| 565 | .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, |
| 566 | .set_rate = set_rate_mnd, |
| 567 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 568 | .current_freq = &rcg_dummy_freq, |
| 569 | .base = &virt_bases[GCC_BASE], |
| 570 | .c = { |
| 571 | .dbg_name = "blsp1_qup1_spi_apps_clk_src", |
| 572 | .ops = &clk_ops_rcg_mnd, |
| 573 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 574 | CLK_INIT(blsp1_qup1_spi_apps_clk_src.c) |
| 575 | }, |
| 576 | }; |
| 577 | |
| 578 | static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { |
| 579 | .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR, |
| 580 | .set_rate = set_rate_mnd, |
| 581 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 582 | .current_freq = &rcg_dummy_freq, |
| 583 | .base = &virt_bases[GCC_BASE], |
| 584 | .c = { |
| 585 | .dbg_name = "blsp1_qup2_spi_apps_clk_src", |
| 586 | .ops = &clk_ops_rcg_mnd, |
| 587 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 588 | CLK_INIT(blsp1_qup2_spi_apps_clk_src.c) |
| 589 | }, |
| 590 | }; |
| 591 | |
| 592 | static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { |
| 593 | .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR, |
| 594 | .set_rate = set_rate_mnd, |
| 595 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 596 | .current_freq = &rcg_dummy_freq, |
| 597 | .base = &virt_bases[GCC_BASE], |
| 598 | .c = { |
| 599 | .dbg_name = "blsp1_qup3_spi_apps_clk_src", |
| 600 | .ops = &clk_ops_rcg_mnd, |
| 601 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 602 | CLK_INIT(blsp1_qup3_spi_apps_clk_src.c) |
| 603 | }, |
| 604 | }; |
| 605 | |
| 606 | static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { |
| 607 | .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR, |
| 608 | .set_rate = set_rate_mnd, |
| 609 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 610 | .current_freq = &rcg_dummy_freq, |
| 611 | .base = &virt_bases[GCC_BASE], |
| 612 | .c = { |
| 613 | .dbg_name = "blsp1_qup4_spi_apps_clk_src", |
| 614 | .ops = &clk_ops_rcg_mnd, |
| 615 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 616 | CLK_INIT(blsp1_qup4_spi_apps_clk_src.c) |
| 617 | }, |
| 618 | }; |
| 619 | |
| 620 | static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { |
| 621 | .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR, |
| 622 | .set_rate = set_rate_mnd, |
| 623 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 624 | .current_freq = &rcg_dummy_freq, |
| 625 | .base = &virt_bases[GCC_BASE], |
| 626 | .c = { |
| 627 | .dbg_name = "blsp1_qup5_spi_apps_clk_src", |
| 628 | .ops = &clk_ops_rcg_mnd, |
| 629 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 630 | CLK_INIT(blsp1_qup5_spi_apps_clk_src.c) |
| 631 | }, |
| 632 | }; |
| 633 | |
| 634 | static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { |
| 635 | .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR, |
| 636 | .set_rate = set_rate_mnd, |
| 637 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 638 | .current_freq = &rcg_dummy_freq, |
| 639 | .base = &virt_bases[GCC_BASE], |
| 640 | .c = { |
| 641 | .dbg_name = "blsp1_qup6_spi_apps_clk_src", |
| 642 | .ops = &clk_ops_rcg_mnd, |
| 643 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 644 | CLK_INIT(blsp1_qup6_spi_apps_clk_src.c) |
| 645 | }, |
| 646 | }; |
| 647 | |
| 648 | static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { |
Vikram Mulukutla | d3dca65 | 2012-11-19 11:04:13 -0800 | [diff] [blame] | 649 | F_GCC_GND, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 650 | F( 3686400, gpll0, 1, 96, 15625), |
| 651 | F( 7372800, gpll0, 1, 192, 15625), |
| 652 | F(14745600, gpll0, 1, 384, 15625), |
| 653 | F(16000000, gpll0, 5, 2, 15), |
| 654 | F(19200000, cxo, 1, 0, 0), |
| 655 | F(24000000, gpll0, 5, 1, 5), |
| 656 | F(32000000, gpll0, 1, 4, 75), |
| 657 | F(40000000, gpll0, 15, 0, 0), |
| 658 | F(46400000, gpll0, 1, 29, 375), |
| 659 | F(48000000, gpll0, 12.5, 0, 0), |
| 660 | F(51200000, gpll0, 1, 32, 375), |
| 661 | F(56000000, gpll0, 1, 7, 75), |
| 662 | F(58982400, gpll0, 1, 1536, 15625), |
| 663 | F(60000000, gpll0, 10, 0, 0), |
| 664 | F_END |
| 665 | }; |
| 666 | |
| 667 | static struct rcg_clk blsp1_uart1_apps_clk_src = { |
| 668 | .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR, |
| 669 | .set_rate = set_rate_mnd, |
| 670 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 671 | .current_freq = &rcg_dummy_freq, |
| 672 | .base = &virt_bases[GCC_BASE], |
| 673 | .c = { |
| 674 | .dbg_name = "blsp1_uart1_apps_clk_src", |
| 675 | .ops = &clk_ops_rcg_mnd, |
| 676 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 677 | CLK_INIT(blsp1_uart1_apps_clk_src.c) |
| 678 | }, |
| 679 | }; |
| 680 | |
| 681 | static struct rcg_clk blsp1_uart2_apps_clk_src = { |
| 682 | .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR, |
| 683 | .set_rate = set_rate_mnd, |
| 684 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 685 | .current_freq = &rcg_dummy_freq, |
| 686 | .base = &virt_bases[GCC_BASE], |
| 687 | .c = { |
| 688 | .dbg_name = "blsp1_uart2_apps_clk_src", |
| 689 | .ops = &clk_ops_rcg_mnd, |
| 690 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 691 | CLK_INIT(blsp1_uart2_apps_clk_src.c) |
| 692 | }, |
| 693 | }; |
| 694 | |
| 695 | static struct rcg_clk blsp1_uart3_apps_clk_src = { |
| 696 | .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR, |
| 697 | .set_rate = set_rate_mnd, |
| 698 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 699 | .current_freq = &rcg_dummy_freq, |
| 700 | .base = &virt_bases[GCC_BASE], |
| 701 | .c = { |
| 702 | .dbg_name = "blsp1_uart3_apps_clk_src", |
| 703 | .ops = &clk_ops_rcg_mnd, |
| 704 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 705 | CLK_INIT(blsp1_uart3_apps_clk_src.c) |
| 706 | }, |
| 707 | }; |
| 708 | |
| 709 | static struct rcg_clk blsp1_uart4_apps_clk_src = { |
| 710 | .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR, |
| 711 | .set_rate = set_rate_mnd, |
| 712 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 713 | .current_freq = &rcg_dummy_freq, |
| 714 | .base = &virt_bases[GCC_BASE], |
| 715 | .c = { |
| 716 | .dbg_name = "blsp1_uart4_apps_clk_src", |
| 717 | .ops = &clk_ops_rcg_mnd, |
| 718 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 719 | CLK_INIT(blsp1_uart4_apps_clk_src.c) |
| 720 | }, |
| 721 | }; |
| 722 | |
| 723 | static struct rcg_clk blsp1_uart5_apps_clk_src = { |
| 724 | .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR, |
| 725 | .set_rate = set_rate_mnd, |
| 726 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 727 | .current_freq = &rcg_dummy_freq, |
| 728 | .base = &virt_bases[GCC_BASE], |
| 729 | .c = { |
| 730 | .dbg_name = "blsp1_uart5_apps_clk_src", |
| 731 | .ops = &clk_ops_rcg_mnd, |
| 732 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 733 | CLK_INIT(blsp1_uart5_apps_clk_src.c) |
| 734 | }, |
| 735 | }; |
| 736 | |
| 737 | static struct rcg_clk blsp1_uart6_apps_clk_src = { |
| 738 | .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR, |
| 739 | .set_rate = set_rate_mnd, |
| 740 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 741 | .current_freq = &rcg_dummy_freq, |
| 742 | .base = &virt_bases[GCC_BASE], |
| 743 | .c = { |
| 744 | .dbg_name = "blsp1_uart6_apps_clk_src", |
| 745 | .ops = &clk_ops_rcg_mnd, |
| 746 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 747 | CLK_INIT(blsp1_uart6_apps_clk_src.c) |
| 748 | }, |
| 749 | }; |
| 750 | |
| 751 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 752 | F( 50000000, gpll0, 12, 0, 0), |
| 753 | F(100000000, gpll0, 6, 0, 0), |
| 754 | F_END |
| 755 | }; |
| 756 | |
| 757 | static struct rcg_clk ce1_clk_src = { |
| 758 | .cmd_rcgr_reg = CE1_CMD_RCGR, |
| 759 | .set_rate = set_rate_hid, |
| 760 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 761 | .current_freq = &rcg_dummy_freq, |
| 762 | .base = &virt_bases[GCC_BASE], |
| 763 | .c = { |
| 764 | .dbg_name = "ce1_clk_src", |
| 765 | .ops = &clk_ops_rcg, |
| 766 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 767 | CLK_INIT(ce1_clk_src.c), |
| 768 | }, |
| 769 | }; |
| 770 | |
| 771 | static struct clk_freq_tbl ftbl_gcc_gp_clk[] = { |
| 772 | F(19200000, cxo, 1, 0, 0), |
| 773 | F_END |
| 774 | }; |
| 775 | |
| 776 | static struct rcg_clk gp1_clk_src = { |
| 777 | .cmd_rcgr_reg = GP1_CMD_RCGR, |
| 778 | .set_rate = set_rate_mnd, |
| 779 | .freq_tbl = ftbl_gcc_gp_clk, |
| 780 | .current_freq = &rcg_dummy_freq, |
| 781 | .base = &virt_bases[GCC_BASE], |
| 782 | .c = { |
| 783 | .dbg_name = "gp1_clk_src", |
| 784 | .ops = &clk_ops_rcg_mnd, |
| 785 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 786 | CLK_INIT(gp1_clk_src.c) |
| 787 | }, |
| 788 | }; |
| 789 | |
| 790 | static struct rcg_clk gp2_clk_src = { |
| 791 | .cmd_rcgr_reg = GP2_CMD_RCGR, |
| 792 | .set_rate = set_rate_mnd, |
| 793 | .freq_tbl = ftbl_gcc_gp_clk, |
| 794 | .current_freq = &rcg_dummy_freq, |
| 795 | .base = &virt_bases[GCC_BASE], |
| 796 | .c = { |
| 797 | .dbg_name = "gp2_clk_src", |
| 798 | .ops = &clk_ops_rcg_mnd, |
| 799 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 800 | CLK_INIT(gp2_clk_src.c) |
| 801 | }, |
| 802 | }; |
| 803 | |
| 804 | static struct rcg_clk gp3_clk_src = { |
| 805 | .cmd_rcgr_reg = GP3_CMD_RCGR, |
| 806 | .set_rate = set_rate_mnd, |
| 807 | .freq_tbl = ftbl_gcc_gp_clk, |
| 808 | .current_freq = &rcg_dummy_freq, |
| 809 | .base = &virt_bases[GCC_BASE], |
| 810 | .c = { |
| 811 | .dbg_name = "gp3_clk_src", |
| 812 | .ops = &clk_ops_rcg_mnd, |
| 813 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 814 | CLK_INIT(gp3_clk_src.c) |
| 815 | }, |
| 816 | }; |
| 817 | |
| 818 | static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = { |
| 819 | F(60000000, gpll0, 10, 0, 0), |
| 820 | F_END |
| 821 | }; |
| 822 | |
| 823 | static struct rcg_clk pdm2_clk_src = { |
| 824 | .cmd_rcgr_reg = PDM2_CMD_RCGR, |
| 825 | .set_rate = set_rate_hid, |
| 826 | .freq_tbl = ftbl_gcc_pdm2_clk, |
| 827 | .current_freq = &rcg_dummy_freq, |
| 828 | .base = &virt_bases[GCC_BASE], |
| 829 | .c = { |
| 830 | .dbg_name = "pdm2_clk_src", |
| 831 | .ops = &clk_ops_rcg, |
| 832 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
| 833 | CLK_INIT(pdm2_clk_src.c), |
| 834 | }, |
| 835 | }; |
| 836 | |
| 837 | static struct clk_freq_tbl ftbl_gcc_qpic_clk[] = { |
| 838 | F( 50000000, gpll0, 12, 0, 0), |
| 839 | F(100000000, gpll0, 6, 0, 0), |
| 840 | F_END |
| 841 | }; |
| 842 | |
| 843 | static struct rcg_clk qpic_clk_src = { |
| 844 | .cmd_rcgr_reg = QPIC_CMD_RCGR, |
| 845 | .set_rate = set_rate_mnd, |
| 846 | .freq_tbl = ftbl_gcc_qpic_clk, |
| 847 | .current_freq = &rcg_dummy_freq, |
| 848 | .base = &virt_bases[GCC_BASE], |
| 849 | .c = { |
| 850 | .dbg_name = "qpic_clk_src", |
| 851 | .ops = &clk_ops_rcg_mnd, |
| 852 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 853 | CLK_INIT(qpic_clk_src.c) |
| 854 | }, |
| 855 | }; |
| 856 | |
| 857 | static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { |
| 858 | F( 144000, cxo, 16, 3, 25), |
| 859 | F( 400000, cxo, 12, 1, 4), |
| 860 | F( 20000000, gpll0, 15, 1, 2), |
| 861 | F( 25000000, gpll0, 12, 1, 2), |
| 862 | F( 50000000, gpll0, 12, 0, 0), |
| 863 | F(100000000, gpll0, 6, 0, 0), |
| 864 | F(200000000, gpll0, 3, 0, 0), |
| 865 | F_END |
| 866 | }; |
| 867 | |
| 868 | static struct clk_freq_tbl ftbl_gcc_sdcc3_apps_clk[] = { |
| 869 | F( 144000, cxo, 16, 3, 25), |
| 870 | F( 400000, cxo, 12, 1, 4), |
| 871 | F( 20000000, gpll0, 15, 1, 2), |
| 872 | F( 25000000, gpll0, 12, 1, 2), |
| 873 | F( 50000000, gpll0, 12, 0, 0), |
| 874 | F(100000000, gpll0, 6, 0, 0), |
| 875 | F_END |
| 876 | }; |
| 877 | |
| 878 | static struct rcg_clk sdcc2_apps_clk_src = { |
| 879 | .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR, |
| 880 | .set_rate = set_rate_mnd, |
| 881 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk, |
| 882 | .current_freq = &rcg_dummy_freq, |
| 883 | .base = &virt_bases[GCC_BASE], |
| 884 | .c = { |
| 885 | .dbg_name = "sdcc2_apps_clk_src", |
| 886 | .ops = &clk_ops_rcg_mnd, |
| 887 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 888 | CLK_INIT(sdcc2_apps_clk_src.c) |
| 889 | }, |
| 890 | }; |
| 891 | |
| 892 | static struct rcg_clk sdcc3_apps_clk_src = { |
| 893 | .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR, |
| 894 | .set_rate = set_rate_mnd, |
| 895 | .freq_tbl = ftbl_gcc_sdcc3_apps_clk, |
| 896 | .current_freq = &rcg_dummy_freq, |
| 897 | .base = &virt_bases[GCC_BASE], |
| 898 | .c = { |
| 899 | .dbg_name = "sdcc3_apps_clk_src", |
| 900 | .ops = &clk_ops_rcg_mnd, |
| 901 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 902 | CLK_INIT(sdcc3_apps_clk_src.c) |
| 903 | }, |
| 904 | }; |
| 905 | |
| 906 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
| 907 | F(75000000, gpll0, 8, 0, 0), |
| 908 | F_END |
| 909 | }; |
| 910 | |
| 911 | static struct rcg_clk usb_hs_system_clk_src = { |
| 912 | .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR, |
| 913 | .set_rate = set_rate_hid, |
| 914 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 915 | .current_freq = &rcg_dummy_freq, |
| 916 | .base = &virt_bases[GCC_BASE], |
| 917 | .c = { |
| 918 | .dbg_name = "usb_hs_system_clk_src", |
| 919 | .ops = &clk_ops_rcg, |
| 920 | VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000), |
| 921 | CLK_INIT(usb_hs_system_clk_src.c), |
| 922 | }, |
| 923 | }; |
| 924 | |
| 925 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = { |
| 926 | F_HSIC(480000000, gpll1, 1, 0, 0), |
| 927 | F_END |
| 928 | }; |
| 929 | |
| 930 | static struct rcg_clk usb_hsic_clk_src = { |
| 931 | .cmd_rcgr_reg = USB_HSIC_CMD_RCGR, |
| 932 | .set_rate = set_rate_hid, |
| 933 | .freq_tbl = ftbl_gcc_usb_hsic_clk, |
| 934 | .current_freq = &rcg_dummy_freq, |
| 935 | .base = &virt_bases[GCC_BASE], |
| 936 | .c = { |
| 937 | .dbg_name = "usb_hsic_clk_src", |
| 938 | .ops = &clk_ops_rcg, |
| 939 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
| 940 | CLK_INIT(usb_hsic_clk_src.c), |
| 941 | }, |
| 942 | }; |
| 943 | |
| 944 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { |
| 945 | F(9600000, cxo, 2, 0, 0), |
| 946 | F_END |
| 947 | }; |
| 948 | |
| 949 | static struct rcg_clk usb_hsic_io_cal_clk_src = { |
| 950 | .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR, |
| 951 | .set_rate = set_rate_hid, |
| 952 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, |
| 953 | .current_freq = &rcg_dummy_freq, |
| 954 | .base = &virt_bases[GCC_BASE], |
| 955 | .c = { |
| 956 | .dbg_name = "usb_hsic_io_cal_clk_src", |
| 957 | .ops = &clk_ops_rcg, |
| 958 | VDD_DIG_FMAX_MAP1(LOW, 9600000), |
| 959 | CLK_INIT(usb_hsic_io_cal_clk_src.c), |
| 960 | }, |
| 961 | }; |
| 962 | |
| 963 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { |
| 964 | F(75000000, gpll0, 8, 0, 0), |
| 965 | F_END |
| 966 | }; |
| 967 | |
| 968 | static struct rcg_clk usb_hsic_system_clk_src = { |
| 969 | .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR, |
| 970 | .set_rate = set_rate_hid, |
| 971 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, |
| 972 | .current_freq = &rcg_dummy_freq, |
| 973 | .base = &virt_bases[GCC_BASE], |
| 974 | .c = { |
| 975 | .dbg_name = "usb_hsic_system_clk_src", |
| 976 | .ops = &clk_ops_rcg, |
| 977 | VDD_DIG_FMAX_MAP2(LOW, 60000000, NOMINAL, 75000000), |
| 978 | CLK_INIT(usb_hsic_system_clk_src.c), |
| 979 | }, |
| 980 | }; |
| 981 | |
| 982 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_xcvr_fs_clk[] = { |
| 983 | F(60000000, gpll0, 10, 0, 0), |
| 984 | F_END |
| 985 | }; |
| 986 | |
| 987 | static struct rcg_clk usb_hsic_xcvr_fs_clk_src = { |
| 988 | .cmd_rcgr_reg = USB_HSIC_XCVR_FS_CMD_RCGR, |
| 989 | .set_rate = set_rate_hid, |
| 990 | .freq_tbl = ftbl_gcc_usb_hsic_xcvr_fs_clk, |
| 991 | .current_freq = &rcg_dummy_freq, |
| 992 | .base = &virt_bases[GCC_BASE], |
| 993 | .c = { |
| 994 | .dbg_name = "usb_hsic_xcvr_fs_clk_src", |
| 995 | .ops = &clk_ops_rcg, |
| 996 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
| 997 | CLK_INIT(usb_hsic_xcvr_fs_clk_src.c), |
| 998 | }, |
| 999 | }; |
| 1000 | |
| 1001 | static struct local_vote_clk gcc_bam_dma_ahb_clk = { |
| 1002 | .cbcr_reg = BAM_DMA_AHB_CBCR, |
| 1003 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1004 | .en_mask = BIT(12), |
| 1005 | .base = &virt_bases[GCC_BASE], |
| 1006 | .c = { |
| 1007 | .dbg_name = "gcc_bam_dma_ahb_clk", |
| 1008 | .ops = &clk_ops_vote, |
| 1009 | CLK_INIT(gcc_bam_dma_ahb_clk.c), |
| 1010 | }, |
| 1011 | }; |
| 1012 | |
| 1013 | static struct local_vote_clk gcc_blsp1_ahb_clk = { |
| 1014 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 1015 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1016 | .en_mask = BIT(17), |
| 1017 | .base = &virt_bases[GCC_BASE], |
| 1018 | .c = { |
| 1019 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 1020 | .ops = &clk_ops_vote, |
| 1021 | CLK_INIT(gcc_blsp1_ahb_clk.c), |
| 1022 | }, |
| 1023 | }; |
| 1024 | |
| 1025 | static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { |
| 1026 | .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1027 | .base = &virt_bases[GCC_BASE], |
| 1028 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1029 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1030 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 1031 | .ops = &clk_ops_branch, |
| 1032 | CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), |
| 1033 | }, |
| 1034 | }; |
| 1035 | |
| 1036 | static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = { |
| 1037 | .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1038 | .has_sibling = 0, |
| 1039 | .base = &virt_bases[GCC_BASE], |
| 1040 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1041 | .parent = &blsp1_qup1_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1042 | .dbg_name = "gcc_blsp1_qup1_spi_apps_clk", |
| 1043 | .ops = &clk_ops_branch, |
| 1044 | CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c), |
| 1045 | }, |
| 1046 | }; |
| 1047 | |
| 1048 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 1049 | .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1050 | .base = &virt_bases[GCC_BASE], |
| 1051 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1052 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1053 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 1054 | .ops = &clk_ops_branch, |
| 1055 | CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c), |
| 1056 | }, |
| 1057 | }; |
| 1058 | |
| 1059 | static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = { |
| 1060 | .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1061 | .has_sibling = 0, |
| 1062 | .base = &virt_bases[GCC_BASE], |
| 1063 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1064 | .parent = &blsp1_qup2_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1065 | .dbg_name = "gcc_blsp1_qup2_spi_apps_clk", |
| 1066 | .ops = &clk_ops_branch, |
| 1067 | CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c), |
| 1068 | }, |
| 1069 | }; |
| 1070 | |
| 1071 | static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { |
| 1072 | .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1073 | .base = &virt_bases[GCC_BASE], |
| 1074 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1075 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1076 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 1077 | .ops = &clk_ops_branch, |
| 1078 | CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c), |
| 1079 | }, |
| 1080 | }; |
| 1081 | |
| 1082 | static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { |
| 1083 | .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1084 | .has_sibling = 0, |
| 1085 | .base = &virt_bases[GCC_BASE], |
| 1086 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1087 | .parent = &blsp1_qup3_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1088 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", |
| 1089 | .ops = &clk_ops_branch, |
| 1090 | CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c), |
| 1091 | }, |
| 1092 | }; |
| 1093 | |
| 1094 | static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { |
| 1095 | .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1096 | .base = &virt_bases[GCC_BASE], |
| 1097 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1098 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1099 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 1100 | .ops = &clk_ops_branch, |
| 1101 | CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c), |
| 1102 | }, |
| 1103 | }; |
| 1104 | |
| 1105 | static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { |
| 1106 | .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1107 | .has_sibling = 0, |
| 1108 | .base = &virt_bases[GCC_BASE], |
| 1109 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1110 | .parent = &blsp1_qup4_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1111 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", |
| 1112 | .ops = &clk_ops_branch, |
| 1113 | CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c), |
| 1114 | }, |
| 1115 | }; |
| 1116 | |
| 1117 | static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { |
| 1118 | .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1119 | .base = &virt_bases[GCC_BASE], |
| 1120 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1121 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1122 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", |
| 1123 | .ops = &clk_ops_branch, |
| 1124 | CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c), |
| 1125 | }, |
| 1126 | }; |
| 1127 | |
| 1128 | static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { |
| 1129 | .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1130 | .has_sibling = 0, |
| 1131 | .base = &virt_bases[GCC_BASE], |
| 1132 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1133 | .parent = &blsp1_qup5_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1134 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", |
| 1135 | .ops = &clk_ops_branch, |
| 1136 | CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c), |
| 1137 | }, |
| 1138 | }; |
| 1139 | |
| 1140 | static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { |
| 1141 | .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1142 | .base = &virt_bases[GCC_BASE], |
| 1143 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1144 | .parent = &cxo_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1145 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", |
| 1146 | .ops = &clk_ops_branch, |
| 1147 | CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), |
| 1148 | }, |
| 1149 | }; |
| 1150 | |
| 1151 | static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = { |
| 1152 | .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1153 | .has_sibling = 0, |
| 1154 | .base = &virt_bases[GCC_BASE], |
| 1155 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1156 | .parent = &blsp1_qup6_spi_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1157 | .dbg_name = "gcc_blsp1_qup6_spi_apps_clk", |
| 1158 | .ops = &clk_ops_branch, |
| 1159 | CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c), |
| 1160 | }, |
| 1161 | }; |
| 1162 | |
| 1163 | static struct branch_clk gcc_blsp1_uart1_apps_clk = { |
| 1164 | .cbcr_reg = BLSP1_UART1_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1165 | .has_sibling = 0, |
| 1166 | .base = &virt_bases[GCC_BASE], |
| 1167 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1168 | .parent = &blsp1_uart1_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1169 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 1170 | .ops = &clk_ops_branch, |
| 1171 | CLK_INIT(gcc_blsp1_uart1_apps_clk.c), |
| 1172 | }, |
| 1173 | }; |
| 1174 | |
| 1175 | static struct branch_clk gcc_blsp1_uart2_apps_clk = { |
| 1176 | .cbcr_reg = BLSP1_UART2_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1177 | .has_sibling = 0, |
| 1178 | .base = &virt_bases[GCC_BASE], |
| 1179 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1180 | .parent = &blsp1_uart2_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1181 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 1182 | .ops = &clk_ops_branch, |
| 1183 | CLK_INIT(gcc_blsp1_uart2_apps_clk.c), |
| 1184 | }, |
| 1185 | }; |
| 1186 | |
| 1187 | static struct branch_clk gcc_blsp1_uart3_apps_clk = { |
| 1188 | .cbcr_reg = BLSP1_UART3_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1189 | .has_sibling = 0, |
| 1190 | .base = &virt_bases[GCC_BASE], |
| 1191 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1192 | .parent = &blsp1_uart3_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1193 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 1194 | .ops = &clk_ops_branch, |
| 1195 | CLK_INIT(gcc_blsp1_uart3_apps_clk.c), |
| 1196 | }, |
| 1197 | }; |
| 1198 | |
| 1199 | static struct branch_clk gcc_blsp1_uart4_apps_clk = { |
| 1200 | .cbcr_reg = BLSP1_UART4_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1201 | .has_sibling = 0, |
| 1202 | .base = &virt_bases[GCC_BASE], |
| 1203 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1204 | .parent = &blsp1_uart4_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1205 | .dbg_name = "gcc_blsp1_uart4_apps_clk", |
| 1206 | .ops = &clk_ops_branch, |
| 1207 | CLK_INIT(gcc_blsp1_uart4_apps_clk.c), |
| 1208 | }, |
| 1209 | }; |
| 1210 | |
| 1211 | static struct branch_clk gcc_blsp1_uart5_apps_clk = { |
| 1212 | .cbcr_reg = BLSP1_UART5_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1213 | .has_sibling = 0, |
| 1214 | .base = &virt_bases[GCC_BASE], |
| 1215 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1216 | .parent = &blsp1_uart5_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1217 | .dbg_name = "gcc_blsp1_uart5_apps_clk", |
| 1218 | .ops = &clk_ops_branch, |
| 1219 | CLK_INIT(gcc_blsp1_uart5_apps_clk.c), |
| 1220 | }, |
| 1221 | }; |
| 1222 | |
| 1223 | static struct branch_clk gcc_blsp1_uart6_apps_clk = { |
| 1224 | .cbcr_reg = BLSP1_UART6_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1225 | .has_sibling = 0, |
| 1226 | .base = &virt_bases[GCC_BASE], |
| 1227 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1228 | .parent = &blsp1_uart6_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1229 | .dbg_name = "gcc_blsp1_uart6_apps_clk", |
| 1230 | .ops = &clk_ops_branch, |
| 1231 | CLK_INIT(gcc_blsp1_uart6_apps_clk.c), |
| 1232 | }, |
| 1233 | }; |
| 1234 | |
| 1235 | static struct local_vote_clk gcc_boot_rom_ahb_clk = { |
| 1236 | .cbcr_reg = BOOT_ROM_AHB_CBCR, |
| 1237 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1238 | .en_mask = BIT(10), |
| 1239 | .base = &virt_bases[GCC_BASE], |
| 1240 | .c = { |
| 1241 | .dbg_name = "gcc_boot_rom_ahb_clk", |
| 1242 | .ops = &clk_ops_vote, |
| 1243 | CLK_INIT(gcc_boot_rom_ahb_clk.c), |
| 1244 | }, |
| 1245 | }; |
| 1246 | |
| 1247 | static struct local_vote_clk gcc_ce1_ahb_clk = { |
| 1248 | .cbcr_reg = CE1_AHB_CBCR, |
| 1249 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1250 | .en_mask = BIT(3), |
| 1251 | .base = &virt_bases[GCC_BASE], |
| 1252 | .c = { |
| 1253 | .dbg_name = "gcc_ce1_ahb_clk", |
| 1254 | .ops = &clk_ops_vote, |
| 1255 | CLK_INIT(gcc_ce1_ahb_clk.c), |
| 1256 | }, |
| 1257 | }; |
| 1258 | |
| 1259 | static struct local_vote_clk gcc_ce1_axi_clk = { |
| 1260 | .cbcr_reg = CE1_AXI_CBCR, |
| 1261 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1262 | .en_mask = BIT(4), |
| 1263 | .base = &virt_bases[GCC_BASE], |
| 1264 | .c = { |
| 1265 | .dbg_name = "gcc_ce1_axi_clk", |
| 1266 | .ops = &clk_ops_vote, |
| 1267 | CLK_INIT(gcc_ce1_axi_clk.c), |
| 1268 | }, |
| 1269 | }; |
| 1270 | |
| 1271 | static struct local_vote_clk gcc_ce1_clk = { |
| 1272 | .cbcr_reg = CE1_CBCR, |
| 1273 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1274 | .en_mask = BIT(5), |
| 1275 | .base = &virt_bases[GCC_BASE], |
| 1276 | .c = { |
| 1277 | .dbg_name = "gcc_ce1_clk", |
| 1278 | .ops = &clk_ops_vote, |
| 1279 | CLK_INIT(gcc_ce1_clk.c), |
| 1280 | }, |
| 1281 | }; |
| 1282 | |
| 1283 | static struct branch_clk gcc_gp1_clk = { |
| 1284 | .cbcr_reg = GP1_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1285 | .has_sibling = 0, |
| 1286 | .base = &virt_bases[GCC_BASE], |
| 1287 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1288 | .parent = &gp1_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1289 | .dbg_name = "gcc_gp1_clk", |
| 1290 | .ops = &clk_ops_branch, |
| 1291 | CLK_INIT(gcc_gp1_clk.c), |
| 1292 | }, |
| 1293 | }; |
| 1294 | |
| 1295 | static struct branch_clk gcc_gp2_clk = { |
| 1296 | .cbcr_reg = GP2_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1297 | .has_sibling = 0, |
| 1298 | .base = &virt_bases[GCC_BASE], |
| 1299 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1300 | .parent = &gp2_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1301 | .dbg_name = "gcc_gp2_clk", |
| 1302 | .ops = &clk_ops_branch, |
| 1303 | CLK_INIT(gcc_gp2_clk.c), |
| 1304 | }, |
| 1305 | }; |
| 1306 | |
| 1307 | static struct branch_clk gcc_gp3_clk = { |
| 1308 | .cbcr_reg = GP3_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1309 | .has_sibling = 0, |
| 1310 | .base = &virt_bases[GCC_BASE], |
| 1311 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1312 | .parent = &gp3_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1313 | .dbg_name = "gcc_gp3_clk", |
| 1314 | .ops = &clk_ops_branch, |
| 1315 | CLK_INIT(gcc_gp3_clk.c), |
| 1316 | }, |
| 1317 | }; |
| 1318 | |
| 1319 | static struct branch_clk gcc_ipa_clk = { |
| 1320 | .cbcr_reg = IPA_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1321 | .has_sibling = 1, |
| 1322 | .base = &virt_bases[GCC_BASE], |
| 1323 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1324 | .parent = &ipa_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1325 | .dbg_name = "gcc_ipa_clk", |
| 1326 | .ops = &clk_ops_branch, |
| 1327 | CLK_INIT(gcc_ipa_clk.c), |
| 1328 | }, |
| 1329 | }; |
| 1330 | |
| 1331 | static struct branch_clk gcc_ipa_cnoc_clk = { |
| 1332 | .cbcr_reg = IPA_CNOC_CBCR, |
| 1333 | .has_sibling = 1, |
| 1334 | .base = &virt_bases[GCC_BASE], |
| 1335 | .c = { |
| 1336 | .dbg_name = "gcc_ipa_cnoc_clk", |
| 1337 | .ops = &clk_ops_branch, |
| 1338 | CLK_INIT(gcc_ipa_cnoc_clk.c), |
| 1339 | }, |
| 1340 | }; |
| 1341 | |
Tianyi Gou | 0e10e79 | 2012-11-29 18:28:32 -0800 | [diff] [blame] | 1342 | static struct branch_clk gcc_ipa_sleep_clk = { |
| 1343 | .cbcr_reg = IPA_SLEEP_CBCR, |
| 1344 | .has_sibling = 1, |
| 1345 | .base = &virt_bases[GCC_BASE], |
| 1346 | .c = { |
| 1347 | .dbg_name = "gcc_ipa_sleep_clk", |
| 1348 | .ops = &clk_ops_branch, |
| 1349 | CLK_INIT(gcc_ipa_sleep_clk.c), |
| 1350 | }, |
| 1351 | }; |
| 1352 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1353 | static struct branch_clk gcc_pdm2_clk = { |
| 1354 | .cbcr_reg = PDM2_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1355 | .has_sibling = 0, |
| 1356 | .base = &virt_bases[GCC_BASE], |
| 1357 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1358 | .parent = &pdm2_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1359 | .dbg_name = "gcc_pdm2_clk", |
| 1360 | .ops = &clk_ops_branch, |
| 1361 | CLK_INIT(gcc_pdm2_clk.c), |
| 1362 | }, |
| 1363 | }; |
| 1364 | |
| 1365 | static struct branch_clk gcc_pdm_ahb_clk = { |
| 1366 | .cbcr_reg = PDM_AHB_CBCR, |
| 1367 | .has_sibling = 1, |
| 1368 | .base = &virt_bases[GCC_BASE], |
| 1369 | .c = { |
| 1370 | .dbg_name = "gcc_pdm_ahb_clk", |
| 1371 | .ops = &clk_ops_branch, |
| 1372 | CLK_INIT(gcc_pdm_ahb_clk.c), |
| 1373 | }, |
| 1374 | }; |
| 1375 | |
| 1376 | static struct local_vote_clk gcc_prng_ahb_clk = { |
| 1377 | .cbcr_reg = PRNG_AHB_CBCR, |
| 1378 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1379 | .en_mask = BIT(13), |
| 1380 | .base = &virt_bases[GCC_BASE], |
| 1381 | .c = { |
| 1382 | .dbg_name = "gcc_prng_ahb_clk", |
| 1383 | .ops = &clk_ops_vote, |
| 1384 | CLK_INIT(gcc_prng_ahb_clk.c), |
| 1385 | }, |
| 1386 | }; |
| 1387 | |
| 1388 | static struct branch_clk gcc_qpic_ahb_clk = { |
| 1389 | .cbcr_reg = QPIC_AHB_CBCR, |
| 1390 | .has_sibling = 1, |
| 1391 | .base = &virt_bases[GCC_BASE], |
| 1392 | .c = { |
| 1393 | .dbg_name = "gcc_qpic_ahb_clk", |
| 1394 | .ops = &clk_ops_branch, |
| 1395 | CLK_INIT(gcc_qpic_ahb_clk.c), |
| 1396 | }, |
| 1397 | }; |
| 1398 | |
| 1399 | static struct branch_clk gcc_qpic_clk = { |
| 1400 | .cbcr_reg = QPIC_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1401 | .has_sibling = 0, |
| 1402 | .base = &virt_bases[GCC_BASE], |
| 1403 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1404 | .parent = &qpic_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1405 | .dbg_name = "gcc_qpic_clk", |
| 1406 | .ops = &clk_ops_branch, |
| 1407 | CLK_INIT(gcc_qpic_clk.c), |
| 1408 | }, |
| 1409 | }; |
| 1410 | |
| 1411 | static struct branch_clk gcc_sdcc2_ahb_clk = { |
| 1412 | .cbcr_reg = SDCC2_AHB_CBCR, |
| 1413 | .has_sibling = 1, |
| 1414 | .base = &virt_bases[GCC_BASE], |
| 1415 | .c = { |
| 1416 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 1417 | .ops = &clk_ops_branch, |
| 1418 | CLK_INIT(gcc_sdcc2_ahb_clk.c), |
| 1419 | }, |
| 1420 | }; |
| 1421 | |
| 1422 | static struct branch_clk gcc_sdcc2_apps_clk = { |
| 1423 | .cbcr_reg = SDCC2_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1424 | .has_sibling = 0, |
| 1425 | .base = &virt_bases[GCC_BASE], |
| 1426 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1427 | .parent = &sdcc2_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1428 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 1429 | .ops = &clk_ops_branch, |
| 1430 | CLK_INIT(gcc_sdcc2_apps_clk.c), |
| 1431 | }, |
| 1432 | }; |
| 1433 | |
| 1434 | static struct branch_clk gcc_sdcc3_ahb_clk = { |
| 1435 | .cbcr_reg = SDCC3_AHB_CBCR, |
| 1436 | .has_sibling = 1, |
| 1437 | .base = &virt_bases[GCC_BASE], |
| 1438 | .c = { |
| 1439 | .dbg_name = "gcc_sdcc3_ahb_clk", |
| 1440 | .ops = &clk_ops_branch, |
| 1441 | CLK_INIT(gcc_sdcc3_ahb_clk.c), |
| 1442 | }, |
| 1443 | }; |
| 1444 | |
| 1445 | static struct branch_clk gcc_sdcc3_apps_clk = { |
| 1446 | .cbcr_reg = SDCC3_APPS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1447 | .has_sibling = 0, |
| 1448 | .base = &virt_bases[GCC_BASE], |
| 1449 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1450 | .parent = &sdcc3_apps_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1451 | .dbg_name = "gcc_sdcc3_apps_clk", |
| 1452 | .ops = &clk_ops_branch, |
| 1453 | CLK_INIT(gcc_sdcc3_apps_clk.c), |
| 1454 | }, |
| 1455 | }; |
| 1456 | |
| 1457 | static struct branch_clk gcc_sys_noc_ipa_axi_clk = { |
| 1458 | .cbcr_reg = SYS_NOC_IPA_AXI_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1459 | .has_sibling = 1, |
| 1460 | .base = &virt_bases[GCC_BASE], |
| 1461 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1462 | .parent = &ipa_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1463 | .dbg_name = "gcc_sys_noc_ipa_axi_clk", |
| 1464 | .ops = &clk_ops_branch, |
| 1465 | CLK_INIT(gcc_sys_noc_ipa_axi_clk.c), |
| 1466 | }, |
| 1467 | }; |
| 1468 | |
| 1469 | static struct branch_clk gcc_usb_hs_ahb_clk = { |
| 1470 | .cbcr_reg = USB_HS_AHB_CBCR, |
| 1471 | .has_sibling = 1, |
| 1472 | .base = &virt_bases[GCC_BASE], |
| 1473 | .c = { |
| 1474 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 1475 | .ops = &clk_ops_branch, |
| 1476 | CLK_INIT(gcc_usb_hs_ahb_clk.c), |
| 1477 | }, |
| 1478 | }; |
| 1479 | |
| 1480 | static struct branch_clk gcc_usb_hs_system_clk = { |
| 1481 | .cbcr_reg = USB_HS_SYSTEM_CBCR, |
| 1482 | .bcr_reg = USB_HS_BCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1483 | .has_sibling = 0, |
| 1484 | .base = &virt_bases[GCC_BASE], |
| 1485 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1486 | .parent = &usb_hs_system_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1487 | .dbg_name = "gcc_usb_hs_system_clk", |
| 1488 | .ops = &clk_ops_branch, |
| 1489 | CLK_INIT(gcc_usb_hs_system_clk.c), |
| 1490 | }, |
| 1491 | }; |
| 1492 | |
| 1493 | static struct branch_clk gcc_usb_hsic_ahb_clk = { |
| 1494 | .cbcr_reg = USB_HSIC_AHB_CBCR, |
| 1495 | .has_sibling = 1, |
| 1496 | .base = &virt_bases[GCC_BASE], |
| 1497 | .c = { |
| 1498 | .dbg_name = "gcc_usb_hsic_ahb_clk", |
| 1499 | .ops = &clk_ops_branch, |
| 1500 | CLK_INIT(gcc_usb_hsic_ahb_clk.c), |
| 1501 | }, |
| 1502 | }; |
| 1503 | |
| 1504 | static struct branch_clk gcc_usb_hsic_clk = { |
| 1505 | .cbcr_reg = USB_HSIC_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1506 | .has_sibling = 0, |
| 1507 | .base = &virt_bases[GCC_BASE], |
| 1508 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1509 | .parent = &usb_hsic_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1510 | .dbg_name = "gcc_usb_hsic_clk", |
| 1511 | .ops = &clk_ops_branch, |
| 1512 | CLK_INIT(gcc_usb_hsic_clk.c), |
| 1513 | }, |
| 1514 | }; |
| 1515 | |
| 1516 | static struct branch_clk gcc_usb_hsic_io_cal_clk = { |
| 1517 | .cbcr_reg = USB_HSIC_IO_CAL_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1518 | .has_sibling = 0, |
| 1519 | .base = &virt_bases[GCC_BASE], |
| 1520 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1521 | .parent = &usb_hsic_io_cal_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1522 | .dbg_name = "gcc_usb_hsic_io_cal_clk", |
| 1523 | .ops = &clk_ops_branch, |
| 1524 | CLK_INIT(gcc_usb_hsic_io_cal_clk.c), |
| 1525 | }, |
| 1526 | }; |
| 1527 | |
| 1528 | static struct branch_clk gcc_usb_hsic_system_clk = { |
| 1529 | .cbcr_reg = USB_HSIC_SYSTEM_CBCR, |
| 1530 | .bcr_reg = USB_HS_HSIC_BCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1531 | .has_sibling = 0, |
| 1532 | .base = &virt_bases[GCC_BASE], |
| 1533 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1534 | .parent = &usb_hsic_system_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1535 | .dbg_name = "gcc_usb_hsic_system_clk", |
| 1536 | .ops = &clk_ops_branch, |
| 1537 | CLK_INIT(gcc_usb_hsic_system_clk.c), |
| 1538 | }, |
| 1539 | }; |
| 1540 | |
| 1541 | static struct branch_clk gcc_usb_hsic_xcvr_fs_clk = { |
| 1542 | .cbcr_reg = USB_HSIC_XCVR_FS_CBCR, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1543 | .has_sibling = 0, |
| 1544 | .base = &virt_bases[GCC_BASE], |
| 1545 | .c = { |
Saravana Kannan | 7a6532e | 2012-10-18 20:51:13 -0700 | [diff] [blame] | 1546 | .parent = &usb_hsic_xcvr_fs_clk_src.c, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1547 | .dbg_name = "gcc_usb_hsic_xcvr_fs_clk", |
| 1548 | .ops = &clk_ops_branch, |
| 1549 | CLK_INIT(gcc_usb_hsic_xcvr_fs_clk.c), |
| 1550 | }, |
| 1551 | }; |
| 1552 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1553 | static DEFINE_CLK_MEASURE(a5_m_clk); |
| 1554 | |
| 1555 | #ifdef CONFIG_DEBUG_FS |
| 1556 | |
| 1557 | struct measure_mux_entry { |
| 1558 | struct clk *c; |
| 1559 | int base; |
| 1560 | u32 debug_mux; |
| 1561 | }; |
| 1562 | |
Tianyi Gou | abcddb7 | 2013-02-23 18:10:11 -0800 | [diff] [blame] | 1563 | struct measure_mux_entry measure_mux_common[] __initdata = { |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1564 | {&gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0}, |
| 1565 | {&gcc_usb_hsic_xcvr_fs_clk.c, GCC_BASE, 0x005d}, |
| 1566 | {&gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059}, |
| 1567 | {&gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b}, |
| 1568 | {&gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079}, |
| 1569 | {&gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d}, |
| 1570 | {&gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a}, |
| 1571 | {&gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091}, |
| 1572 | {&gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098}, |
| 1573 | {&gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093}, |
| 1574 | {&gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2}, |
| 1575 | {&gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0}, |
| 1576 | {&gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078}, |
| 1577 | {&gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060}, |
| 1578 | {&gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088}, |
| 1579 | {&gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a}, |
| 1580 | {&gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e}, |
| 1581 | {&gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058}, |
| 1582 | {&gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095}, |
| 1583 | {&gcc_ce1_axi_clk.c, GCC_BASE, 0x0139}, |
| 1584 | {&gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c}, |
| 1585 | {&gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061}, |
| 1586 | {&gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1}, |
| 1587 | {&gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8}, |
| 1588 | {&gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094}, |
| 1589 | {&gcc_usb_hsic_clk.c, GCC_BASE, 0x005a}, |
| 1590 | {&gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3}, |
| 1591 | {&gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070}, |
| 1592 | {&gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c}, |
| 1593 | {&gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099}, |
| 1594 | {&gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8}, |
| 1595 | {&gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a}, |
| 1596 | {&gcc_pdm2_clk.c, GCC_BASE, 0x00d2}, |
| 1597 | {&gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e}, |
| 1598 | {&gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090}, |
| 1599 | {&gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b}, |
| 1600 | {&gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071}, |
| 1601 | {&gcc_ce1_clk.c, GCC_BASE, 0x0138}, |
| 1602 | {&gcc_sys_noc_ipa_axi_clk.c, GCC_BASE, 0x0007}, |
Tianyi Gou | 8512ac4 | 2013-01-23 18:32:04 -0800 | [diff] [blame] | 1603 | {&gcc_ipa_clk.c, GCC_BASE, 0x01E0}, |
| 1604 | {&gcc_ipa_cnoc_clk.c, GCC_BASE, 0x01E1}, |
| 1605 | {&gcc_ipa_sleep_clk.c, GCC_BASE, 0x01E2}, |
| 1606 | {&gcc_qpic_clk.c, GCC_BASE, 0x01D8}, |
| 1607 | {&gcc_qpic_ahb_clk.c, GCC_BASE, 0x01D9}, |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1608 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1609 | {&a5_m_clk, APCS_BASE, 0x3}, |
| 1610 | |
| 1611 | {&dummy_clk, N_BASES, 0x0000}, |
| 1612 | }; |
| 1613 | |
Tianyi Gou | abcddb7 | 2013-02-23 18:10:11 -0800 | [diff] [blame] | 1614 | struct measure_mux_entry measure_mux_v2_only[] __initdata = { |
| 1615 | {&gcc_ipa_clk.c, GCC_BASE, 0x01E0}, |
| 1616 | {&gcc_ipa_cnoc_clk.c, GCC_BASE, 0x01E1}, |
| 1617 | {&gcc_ipa_sleep_clk.c, GCC_BASE, 0x01E2}, |
| 1618 | {&gcc_qpic_clk.c, GCC_BASE, 0x01D8}, |
| 1619 | {&gcc_qpic_ahb_clk.c, GCC_BASE, 0x01D9}, |
| 1620 | }; |
| 1621 | |
| 1622 | struct measure_mux_entry measure_mux[ARRAY_SIZE(measure_mux_common) |
| 1623 | + ARRAY_SIZE(measure_mux_v2_only)]; |
| 1624 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1625 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
| 1626 | { |
| 1627 | struct measure_clk *clk = to_measure_clk(c); |
| 1628 | unsigned long flags; |
| 1629 | u32 regval, clk_sel, i; |
| 1630 | |
| 1631 | if (!parent) |
| 1632 | return -EINVAL; |
| 1633 | |
| 1634 | for (i = 0; i < (ARRAY_SIZE(measure_mux) - 1); i++) |
| 1635 | if (measure_mux[i].c == parent) |
| 1636 | break; |
| 1637 | |
| 1638 | if (measure_mux[i].c == &dummy_clk) |
| 1639 | return -EINVAL; |
| 1640 | |
| 1641 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 1642 | /* |
| 1643 | * Program the test vector, measurement period (sample_ticks) |
| 1644 | * and scaling multiplier. |
| 1645 | */ |
| 1646 | clk->sample_ticks = 0x10000; |
| 1647 | clk->multiplier = 1; |
| 1648 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1649 | writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
| 1650 | |
| 1651 | switch (measure_mux[i].base) { |
| 1652 | |
| 1653 | case GCC_BASE: |
| 1654 | clk_sel = measure_mux[i].debug_mux; |
| 1655 | break; |
| 1656 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1657 | case APCS_BASE: |
| 1658 | clk_sel = 0x16A; |
| 1659 | regval = BVAL(5, 3, measure_mux[i].debug_mux); |
| 1660 | writel_relaxed(regval, APCS_REG_BASE(APCS_CLK_DIAG_REG)); |
| 1661 | |
| 1662 | /* Activate debug clock output */ |
| 1663 | regval |= BIT(7); |
| 1664 | writel_relaxed(regval, APCS_REG_BASE(APCS_CLK_DIAG_REG)); |
| 1665 | break; |
| 1666 | |
| 1667 | default: |
| 1668 | return -EINVAL; |
| 1669 | } |
| 1670 | |
| 1671 | /* Set debug mux clock index */ |
| 1672 | regval = BVAL(8, 0, clk_sel); |
| 1673 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
| 1674 | |
| 1675 | /* Activate debug clock output */ |
| 1676 | regval |= BIT(16); |
| 1677 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL_REG)); |
| 1678 | |
| 1679 | /* Make sure test vector is set before starting measurements. */ |
| 1680 | mb(); |
| 1681 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 1682 | |
| 1683 | return 0; |
| 1684 | } |
| 1685 | |
| 1686 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 1687 | static u32 run_measurement(unsigned ticks) |
| 1688 | { |
| 1689 | /* Stop counters and set the XO4 counter start value. */ |
| 1690 | writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL_REG)); |
| 1691 | |
| 1692 | /* Wait for timer to become ready. */ |
| 1693 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 1694 | BIT(25)) != 0) |
| 1695 | cpu_relax(); |
| 1696 | |
| 1697 | /* Run measurement and wait for completion. */ |
| 1698 | writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL_REG)); |
| 1699 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 1700 | BIT(25)) == 0) |
| 1701 | cpu_relax(); |
| 1702 | |
| 1703 | /* Return measured ticks. */ |
| 1704 | return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS_REG)) & |
| 1705 | BM(24, 0); |
| 1706 | } |
| 1707 | |
| 1708 | /* |
| 1709 | * Perform a hardware rate measurement for a given clock. |
| 1710 | * FOR DEBUG USE ONLY: Measurements take ~15 ms! |
| 1711 | */ |
| 1712 | static unsigned long measure_clk_get_rate(struct clk *c) |
| 1713 | { |
| 1714 | unsigned long flags; |
| 1715 | u32 gcc_xo4_reg_backup; |
| 1716 | u64 raw_count_short, raw_count_full; |
| 1717 | struct measure_clk *clk = to_measure_clk(c); |
| 1718 | unsigned ret; |
| 1719 | |
| 1720 | ret = clk_prepare_enable(&cxo_clk_src.c); |
| 1721 | if (ret) { |
| 1722 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 1723 | return 0; |
| 1724 | } |
| 1725 | |
| 1726 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 1727 | |
| 1728 | /* Enable CXO/4 and RINGOSC branch. */ |
| 1729 | gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 1730 | writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 1731 | |
| 1732 | /* |
| 1733 | * The ring oscillator counter will not reset if the measured clock |
| 1734 | * is not running. To detect this, run a short measurement before |
| 1735 | * the full measurement. If the raw results of the two are the same |
| 1736 | * then the clock must be off. |
| 1737 | */ |
| 1738 | |
| 1739 | /* Run a short measurement. (~1 ms) */ |
| 1740 | raw_count_short = run_measurement(0x1000); |
| 1741 | /* Run a full measurement. (~14 ms) */ |
| 1742 | raw_count_full = run_measurement(clk->sample_ticks); |
| 1743 | |
| 1744 | writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR_REG)); |
| 1745 | |
| 1746 | /* Return 0 if the clock is off. */ |
| 1747 | if (raw_count_full == raw_count_short) { |
| 1748 | ret = 0; |
| 1749 | } else { |
| 1750 | /* Compute rate in Hz. */ |
| 1751 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
| 1752 | do_div(raw_count_full, ((clk->sample_ticks * 10) + 35)); |
| 1753 | ret = (raw_count_full * clk->multiplier); |
| 1754 | } |
| 1755 | |
| 1756 | writel_relaxed(0x51A00, GCC_REG_BASE(GCC_PLLTEST_PAD_CFG_REG)); |
| 1757 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 1758 | |
| 1759 | clk_disable_unprepare(&cxo_clk_src.c); |
| 1760 | |
| 1761 | return ret; |
| 1762 | } |
| 1763 | #else /* !CONFIG_DEBUG_FS */ |
| 1764 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 1765 | { |
| 1766 | return -EINVAL; |
| 1767 | } |
| 1768 | |
| 1769 | static unsigned long measure_clk_get_rate(struct clk *clk) |
| 1770 | { |
| 1771 | return 0; |
| 1772 | } |
| 1773 | #endif /* CONFIG_DEBUG_FS */ |
| 1774 | |
| 1775 | static struct clk_ops clk_ops_measure = { |
| 1776 | .set_parent = measure_clk_set_parent, |
| 1777 | .get_rate = measure_clk_get_rate, |
| 1778 | }; |
| 1779 | |
| 1780 | static struct measure_clk measure_clk = { |
| 1781 | .c = { |
| 1782 | .dbg_name = "measure_clk", |
| 1783 | .ops = &clk_ops_measure, |
| 1784 | CLK_INIT(measure_clk.c), |
| 1785 | }, |
| 1786 | .multiplier = 1, |
| 1787 | }; |
| 1788 | |
| 1789 | static struct clk_lookup msm_clocks_9625[] = { |
| 1790 | CLK_LOOKUP("xo", cxo_clk_src.c, ""), |
| 1791 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 1792 | |
Tianyi Gou | 27df1bb | 2012-10-11 14:44:01 -0700 | [diff] [blame] | 1793 | CLK_LOOKUP("pll0", gpll0_activeonly_clk_src.c, "f9010008.qcom,acpuclk"), |
| 1794 | CLK_LOOKUP("pll14", apcspll_clk_src.c, "f9010008.qcom,acpuclk"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1795 | |
| 1796 | CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"), |
| 1797 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "msm_serial_hsl.0"), |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 1798 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9924000.spi"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1799 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"), |
Saket Saurabh | d72ee92 | 2013-01-22 16:56:52 +0530 | [diff] [blame] | 1800 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991d000.uart"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1801 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""), |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 1802 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, ""), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1803 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""), |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 1804 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, "f9924000.spi"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1805 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"), |
| 1806 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""), |
| 1807 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""), |
| 1808 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""), |
| 1809 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""), |
| 1810 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""), |
| 1811 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""), |
| 1812 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""), |
Saket Saurabh | d72ee92 | 2013-01-22 16:56:52 +0530 | [diff] [blame] | 1813 | CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, "f991d000.uart"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1814 | CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, ""), |
| 1815 | CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "msm_serial_hsl.0"), |
| 1816 | CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""), |
| 1817 | CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""), |
| 1818 | CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""), |
| 1819 | |
| 1820 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""), |
| 1821 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, ""), |
| 1822 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, ""), |
| 1823 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, ""), |
| 1824 | |
| 1825 | CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""), |
| 1826 | CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""), |
| 1827 | CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""), |
| 1828 | |
Hariprasad Dhalinarasimha | 9abfe78 | 2012-11-07 19:40:14 -0800 | [diff] [blame] | 1829 | CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1830 | CLK_LOOKUP("core_src_clk", ipa_clk_src.c, "fd4c0000.qcom,ipa"), |
| 1831 | CLK_LOOKUP("core_clk", gcc_ipa_clk.c, "fd4c0000.qcom,ipa"), |
| 1832 | CLK_LOOKUP("bus_clk", gcc_sys_noc_ipa_axi_clk.c, "fd4c0000.qcom,ipa"), |
| 1833 | CLK_LOOKUP("iface_clk", gcc_ipa_cnoc_clk.c, "fd4c0000.qcom,ipa"), |
Tianyi Gou | 0e10e79 | 2012-11-29 18:28:32 -0800 | [diff] [blame] | 1834 | CLK_LOOKUP("inactivity_clk", gcc_ipa_sleep_clk.c, "fd4c0000.qcom,ipa"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1835 | |
| 1836 | CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""), |
| 1837 | CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""), |
| 1838 | |
Oluwafemi Adeyemi | 61df118 | 2012-10-12 18:51:11 -0700 | [diff] [blame] | 1839 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"), |
| 1840 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"), |
| 1841 | CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"), |
| 1842 | CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"), |
| 1843 | CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"), |
| 1844 | CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1845 | |
| 1846 | CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"), |
| 1847 | CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"), |
Ido Shayevitz | d2b722b | 2013-01-09 13:08:54 +0200 | [diff] [blame] | 1848 | CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"), |
| 1849 | CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"), |
| 1850 | CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"), |
| 1851 | CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"), |
Ofir Cohen | b512a5f | 2012-12-13 09:46:34 +0200 | [diff] [blame] | 1852 | CLK_LOOKUP("alt_core_clk", gcc_usb_hsic_xcvr_fs_clk.c, ""), |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1853 | |
Hariprasad Dhalinarasimha | 96252de | 2012-11-21 17:52:36 -0800 | [diff] [blame] | 1854 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"), |
| 1855 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"), |
| 1856 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"), |
| 1857 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"), |
| 1858 | |
| 1859 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcrypto"), |
| 1860 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcrypto"), |
| 1861 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcrypto"), |
| 1862 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcrypto"), |
| 1863 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1864 | /* RPM and voter clocks */ |
| 1865 | CLK_LOOKUP("bus_clk", snoc_clk.c, ""), |
| 1866 | CLK_LOOKUP("bus_clk", pnoc_clk.c, ""), |
| 1867 | CLK_LOOKUP("bus_clk", cnoc_clk.c, ""), |
| 1868 | CLK_LOOKUP("mem_clk", bimc_clk.c, ""), |
| 1869 | CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""), |
| 1870 | CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""), |
| 1871 | CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""), |
| 1872 | CLK_LOOKUP("mem_clk", bimc_a_clk.c, ""), |
| 1873 | |
| 1874 | CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"), |
| 1875 | CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"), |
| 1876 | CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"), |
| 1877 | CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"), |
| 1878 | CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"), |
| 1879 | CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"), |
| 1880 | CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"), |
| 1881 | CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"), |
| 1882 | |
| 1883 | CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"), |
| 1884 | |
| 1885 | CLK_LOOKUP("a5_m_clk", a5_m_clk, ""), |
Pushkar Joshi | 4e48304 | 2012-10-29 18:10:08 -0700 | [diff] [blame] | 1886 | |
Pratik Patel | 2d15d56 | 2013-02-07 19:10:35 -0800 | [diff] [blame] | 1887 | /* CoreSight clocks */ |
Pushkar Joshi | 4e48304 | 2012-10-29 18:10:08 -0700 | [diff] [blame] | 1888 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"), |
| 1889 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"), |
| 1890 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"), |
| 1891 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"), |
| 1892 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"), |
| 1893 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"), |
| 1894 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"), |
| 1895 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"), |
Pushkar Joshi | 2a51a12 | 2012-12-06 10:49:07 -0800 | [diff] [blame] | 1896 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc332000.etm"), |
Pushkar Joshi | e0e8a7e | 2012-12-15 18:27:04 -0800 | [diff] [blame] | 1897 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc332000.jtagmm"), |
Pratik Patel | 9332c38 | 2013-02-08 11:54:28 -0800 | [diff] [blame] | 1898 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"), |
| 1899 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"), |
| 1900 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"), |
| 1901 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"), |
| 1902 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"), |
| 1903 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"), |
| 1904 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"), |
| 1905 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"), |
| 1906 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"), |
| 1907 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc333000.cti"), |
Pushkar Joshi | 4e48304 | 2012-10-29 18:10:08 -0700 | [diff] [blame] | 1908 | |
Pratik Patel | 2d15d56 | 2013-02-07 19:10:35 -0800 | [diff] [blame] | 1909 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"), |
| 1910 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"), |
| 1911 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"), |
| 1912 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"), |
| 1913 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"), |
| 1914 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"), |
| 1915 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"), |
| 1916 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"), |
| 1917 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc332000.etm"), |
| 1918 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc332000.jtagmm"), |
Pratik Patel | 9332c38 | 2013-02-08 11:54:28 -0800 | [diff] [blame] | 1919 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"), |
| 1920 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"), |
| 1921 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"), |
| 1922 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"), |
| 1923 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"), |
| 1924 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"), |
| 1925 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"), |
| 1926 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"), |
| 1927 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"), |
| 1928 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc333000.cti"), |
Pushkar Joshi | 4e48304 | 2012-10-29 18:10:08 -0700 | [diff] [blame] | 1929 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1930 | }; |
| 1931 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1932 | #define PLL_AUX_OUTPUT_BIT 1 |
| 1933 | #define PLL_AUX2_OUTPUT_BIT 2 |
| 1934 | |
| 1935 | /* |
| 1936 | * TODO: Need to remove this function when the v2 hardware |
| 1937 | * fix the broken lock status bit. |
| 1938 | */ |
| 1939 | #define PLL_OUTCTRL BIT(0) |
| 1940 | #define PLL_BYPASSNL BIT(1) |
| 1941 | #define PLL_RESET_N BIT(2) |
| 1942 | |
| 1943 | static DEFINE_SPINLOCK(sr_pll_reg_lock); |
| 1944 | |
| 1945 | static int sr_pll_clk_enable_9625(struct clk *c) |
| 1946 | { |
| 1947 | unsigned long flags; |
| 1948 | struct pll_clk *pll = to_pll_clk(c); |
| 1949 | u32 mode; |
| 1950 | void __iomem *mode_reg = *pll->base + (u32)pll->mode_reg; |
| 1951 | |
| 1952 | spin_lock_irqsave(&sr_pll_reg_lock, flags); |
| 1953 | |
| 1954 | /* Disable PLL bypass mode and de-assert reset. */ |
| 1955 | mode = readl_relaxed(mode_reg); |
| 1956 | mode |= PLL_BYPASSNL | PLL_RESET_N; |
| 1957 | writel_relaxed(mode, mode_reg); |
| 1958 | |
| 1959 | /* Wait for pll to lock. */ |
| 1960 | udelay(100); |
| 1961 | |
| 1962 | /* Enable PLL output. */ |
| 1963 | mode |= PLL_OUTCTRL; |
| 1964 | writel_relaxed(mode, mode_reg); |
| 1965 | |
| 1966 | /* Ensure the write above goes through before returning. */ |
| 1967 | mb(); |
| 1968 | |
| 1969 | spin_unlock_irqrestore(&sr_pll_reg_lock, flags); |
| 1970 | return 0; |
| 1971 | } |
| 1972 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1973 | static void __init reg_init(void) |
| 1974 | { |
Tianyi Gou | 781ff67 | 2013-02-21 15:29:40 -0800 | [diff] [blame] | 1975 | u32 regval; |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1976 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1977 | /* Vote for GPLL0 to turn on. Needed by acpuclock. */ |
| 1978 | regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE_REG)); |
| 1979 | regval |= BIT(0); |
| 1980 | writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE_REG)); |
| 1981 | |
| 1982 | /* |
| 1983 | * TODO: Confirm that no clocks need to be voted on in this sleep vote |
| 1984 | * register. |
| 1985 | */ |
| 1986 | writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE)); |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 1987 | } |
| 1988 | |
| 1989 | static void __init msm9625_clock_post_init(void) |
| 1990 | { |
| 1991 | /* |
| 1992 | * Hold an active set vote for CXO; this is because CXO is expected |
| 1993 | * to remain on whenever CPUs aren't power collapsed. |
| 1994 | */ |
| 1995 | clk_prepare_enable(&cxo_a_clk_src.c); |
| 1996 | |
| 1997 | /* |
| 1998 | * TODO: This call is to prevent sending 0Hz to rpm to turn off pnoc. |
| 1999 | * Needs to remove this after vote of pnoc from sdcc driver is ready. |
| 2000 | */ |
| 2001 | clk_prepare_enable(&pnoc_msmbus_a_clk.c); |
| 2002 | |
| 2003 | /* Set rates for single-rate clocks. */ |
| 2004 | clk_set_rate(&usb_hs_system_clk_src.c, |
| 2005 | usb_hs_system_clk_src.freq_tbl[0].freq_hz); |
| 2006 | clk_set_rate(&usb_hsic_clk_src.c, |
| 2007 | usb_hsic_clk_src.freq_tbl[0].freq_hz); |
| 2008 | clk_set_rate(&usb_hsic_io_cal_clk_src.c, |
| 2009 | usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz); |
| 2010 | clk_set_rate(&usb_hsic_system_clk_src.c, |
| 2011 | usb_hsic_system_clk_src.freq_tbl[0].freq_hz); |
| 2012 | clk_set_rate(&usb_hsic_xcvr_fs_clk_src.c, |
| 2013 | usb_hsic_xcvr_fs_clk_src.freq_tbl[0].freq_hz); |
| 2014 | clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz); |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 2015 | /* |
| 2016 | * TODO: set rate on behalf of the i2c driver until the i2c driver |
| 2017 | * distinguish v1/v2 and call set rate accordingly. |
| 2018 | */ |
| 2019 | if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) |
| 2020 | clk_set_rate(&blsp1_qup3_i2c_apps_clk_src.c, |
| 2021 | blsp1_qup3_i2c_apps_clk_src.freq_tbl[0].freq_hz); |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2022 | } |
| 2023 | |
| 2024 | #define GCC_CC_PHYS 0xFC400000 |
| 2025 | #define GCC_CC_SIZE SZ_16K |
| 2026 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2027 | #define APCS_GCC_CC_PHYS 0xF9011000 |
| 2028 | #define APCS_GCC_CC_SIZE SZ_4K |
| 2029 | |
| 2030 | #define APCS_PLL_PHYS 0xF9008018 |
| 2031 | #define APCS_PLL_SIZE 0x18 |
| 2032 | |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 2033 | static struct clk *i2c_apps_clks[][2] __initdata = { |
| 2034 | {&gcc_blsp1_qup1_i2c_apps_clk.c, &blsp1_qup1_i2c_apps_clk_src.c}, |
| 2035 | {&gcc_blsp1_qup2_i2c_apps_clk.c, &blsp1_qup2_i2c_apps_clk_src.c}, |
| 2036 | {&gcc_blsp1_qup3_i2c_apps_clk.c, &blsp1_qup3_i2c_apps_clk_src.c}, |
| 2037 | {&gcc_blsp1_qup4_i2c_apps_clk.c, &blsp1_qup4_i2c_apps_clk_src.c}, |
| 2038 | {&gcc_blsp1_qup5_i2c_apps_clk.c, &blsp1_qup5_i2c_apps_clk_src.c}, |
| 2039 | {&gcc_blsp1_qup6_i2c_apps_clk.c, &blsp1_qup6_i2c_apps_clk_src.c}, |
| 2040 | }; |
| 2041 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2042 | static void __init msm9625_clock_pre_init(void) |
| 2043 | { |
| 2044 | virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE); |
| 2045 | if (!virt_bases[GCC_BASE]) |
| 2046 | panic("clock-9625: Unable to ioremap GCC memory!"); |
| 2047 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2048 | virt_bases[APCS_BASE] = ioremap(APCS_GCC_CC_PHYS, APCS_GCC_CC_SIZE); |
| 2049 | if (!virt_bases[APCS_BASE]) |
| 2050 | panic("clock-9625: Unable to ioremap APCS_GCC_CC memory!"); |
| 2051 | |
| 2052 | virt_bases[APCS_PLL_BASE] = ioremap(APCS_PLL_PHYS, APCS_PLL_SIZE); |
| 2053 | if (!virt_bases[APCS_PLL_BASE]) |
| 2054 | panic("clock-9625: Unable to ioremap APCS_PLL memory!"); |
| 2055 | |
Tianyi Gou | b1d1397 | 2013-01-23 22:55:22 -0800 | [diff] [blame] | 2056 | /* The parent of each of the QUP I2C APPS clocks is an RCG on v2 */ |
| 2057 | if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) { |
| 2058 | int i, num_cores = ARRAY_SIZE(i2c_apps_clks); |
| 2059 | for (i = 0; i < num_cores; i++) |
| 2060 | i2c_apps_clks[i][0]->parent = i2c_apps_clks[i][1]; |
| 2061 | } |
| 2062 | |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2063 | clk_ops_local_pll.enable = sr_pll_clk_enable_9625; |
| 2064 | |
| 2065 | vdd_dig_reg = regulator_get(NULL, "vdd_dig"); |
| 2066 | if (IS_ERR(vdd_dig_reg)) |
| 2067 | panic("clock-9625: Unable to get the vdd_dig regulator!"); |
| 2068 | |
| 2069 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 2070 | regulator_enable(vdd_dig_reg); |
| 2071 | |
| 2072 | enable_rpm_scaling(); |
| 2073 | |
| 2074 | reg_init(); |
Tianyi Gou | abcddb7 | 2013-02-23 18:10:11 -0800 | [diff] [blame] | 2075 | |
| 2076 | /* Construct measurement mux array */ |
| 2077 | if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) { |
| 2078 | memcpy(measure_mux, |
| 2079 | measure_mux_v2_only, sizeof(measure_mux_v2_only)); |
| 2080 | memcpy(measure_mux + ARRAY_SIZE(measure_mux_v2_only), |
| 2081 | measure_mux_common, sizeof(measure_mux_common)); |
| 2082 | } else |
| 2083 | memcpy(measure_mux, |
| 2084 | measure_mux_common, sizeof(measure_mux_common)); |
Tianyi Gou | 389ba43 | 2012-10-01 13:58:38 -0700 | [diff] [blame] | 2085 | } |
| 2086 | |
| 2087 | static int __init msm9625_clock_late_init(void) |
| 2088 | { |
| 2089 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 2090 | } |
| 2091 | |
| 2092 | struct clock_init_data msm9625_clock_init_data __initdata = { |
| 2093 | .table = msm_clocks_9625, |
| 2094 | .size = ARRAY_SIZE(msm_clocks_9625), |
| 2095 | .pre_init = msm9625_clock_pre_init, |
| 2096 | .post_init = msm9625_clock_post_init, |
| 2097 | .late_init = msm9625_clock_late_init, |
| 2098 | }; |