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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/flush.c
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/mm.h>
12#include <linux/pagemap.h>
13
14#include <asm/cacheflush.h>
Russell King46097c72008-08-10 18:10:19 +010015#include <asm/cachetype.h>
Nicolas Pitre7e5a69e2010-03-29 21:46:02 +010016#include <asm/highmem.h>
Russell King2ef7f3d2009-11-05 13:29:36 +000017#include <asm/smp_plat.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/system.h>
Russell King8d802d22005-05-10 17:31:43 +010019#include <asm/tlbflush.h>
Catalin Marinas85848dd2010-09-13 15:58:37 +010020#include <asm/smp_plat.h>
Russell King8d802d22005-05-10 17:31:43 +010021
Russell King1b2e2b72006-08-21 17:06:38 +010022#include "mm.h"
23
Russell King8d802d22005-05-10 17:31:43 +010024#ifdef CONFIG_CPU_CACHE_VIPT
Russell Kingd7b6b352005-09-08 15:32:23 +010025
Catalin Marinas481467d2005-09-30 16:07:04 +010026#define ALIAS_FLUSH_START 0xffff4000
27
Catalin Marinas481467d2005-09-30 16:07:04 +010028static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
29{
30 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
Catalin Marinas141fa402006-03-10 22:26:47 +000031 const int zero = 0;
Catalin Marinas481467d2005-09-30 16:07:04 +010032
Russell Kingad1ae2f2006-12-13 14:34:43 +000033 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0);
Catalin Marinas481467d2005-09-30 16:07:04 +010034 flush_tlb_kernel_page(to);
35
36 asm( "mcrr p15, 0, %1, %0, c14\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010037 " mcr p15, 0, %2, c7, c10, 4"
Catalin Marinas481467d2005-09-30 16:07:04 +010038 :
Catalin Marinas141fa402006-03-10 22:26:47 +000039 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
Catalin Marinas481467d2005-09-30 16:07:04 +010040 : "cc");
41}
42
Russell Kingd7b6b352005-09-08 15:32:23 +010043void flush_cache_mm(struct mm_struct *mm)
44{
45 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000046 vivt_flush_cache_mm(mm);
Russell Kingd7b6b352005-09-08 15:32:23 +010047 return;
48 }
49
50 if (cache_is_vipt_aliasing()) {
51 asm( "mcr p15, 0, %0, c7, c14, 0\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010052 " mcr p15, 0, %0, c7, c10, 4"
Russell Kingd7b6b352005-09-08 15:32:23 +010053 :
54 : "r" (0)
55 : "cc");
56 }
57}
58
59void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
60{
61 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000062 vivt_flush_cache_range(vma, start, end);
Russell Kingd7b6b352005-09-08 15:32:23 +010063 return;
64 }
65
66 if (cache_is_vipt_aliasing()) {
67 asm( "mcr p15, 0, %0, c7, c14, 0\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010068 " mcr p15, 0, %0, c7, c10, 4"
Russell Kingd7b6b352005-09-08 15:32:23 +010069 :
70 : "r" (0)
71 : "cc");
72 }
Russell King9e959222009-10-25 13:35:13 +000073
Russell King6060e8d2009-10-25 14:12:27 +000074 if (vma->vm_flags & VM_EXEC)
Russell King9e959222009-10-25 13:35:13 +000075 __flush_icache_all();
Russell Kingd7b6b352005-09-08 15:32:23 +010076}
77
78void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
79{
80 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000081 vivt_flush_cache_page(vma, user_addr, pfn);
Russell Kingd7b6b352005-09-08 15:32:23 +010082 return;
83 }
84
Russell King2df341e2009-10-24 22:58:40 +010085 if (cache_is_vipt_aliasing()) {
Russell Kingd7b6b352005-09-08 15:32:23 +010086 flush_pfn_alias(pfn, user_addr);
Russell King2df341e2009-10-24 22:58:40 +010087 __flush_icache_all();
88 }
Russell King9e959222009-10-25 13:35:13 +000089
90 if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
91 __flush_icache_all();
Russell Kingd7b6b352005-09-08 15:32:23 +010092}
Russell King2ef7f3d2009-11-05 13:29:36 +000093#else
94#define flush_pfn_alias(pfn,vaddr) do { } while (0)
95#endif
George G. Davisa188ad22006-09-02 18:43:20 +010096
Russell King2ef7f3d2009-11-05 13:29:36 +000097static void flush_ptrace_access_other(void *args)
98{
99 __flush_icache_all();
100}
Russell King2ef7f3d2009-11-05 13:29:36 +0000101
102static
George G. Davisa188ad22006-09-02 18:43:20 +0100103void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
Russell King2ef7f3d2009-11-05 13:29:36 +0000104 unsigned long uaddr, void *kaddr, unsigned long len)
George G. Davisa188ad22006-09-02 18:43:20 +0100105{
106 if (cache_is_vivt()) {
Russell King2ef7f3d2009-11-05 13:29:36 +0000107 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
108 unsigned long addr = (unsigned long)kaddr;
109 __cpuc_coherent_kern_range(addr, addr + len);
110 }
George G. Davisa188ad22006-09-02 18:43:20 +0100111 return;
112 }
113
114 if (cache_is_vipt_aliasing()) {
115 flush_pfn_alias(page_to_pfn(page), uaddr);
Russell King2df341e2009-10-24 22:58:40 +0100116 __flush_icache_all();
George G. Davisa188ad22006-09-02 18:43:20 +0100117 return;
118 }
119
120 /* VIPT non-aliasing cache */
Russell King2ef7f3d2009-11-05 13:29:36 +0000121 if (vma->vm_flags & VM_EXEC) {
George G. Davisa188ad22006-09-02 18:43:20 +0100122 unsigned long addr = (unsigned long)kaddr;
George G. Davisa188ad22006-09-02 18:43:20 +0100123 __cpuc_coherent_kern_range(addr, addr + len);
Russell King2ef7f3d2009-11-05 13:29:36 +0000124 if (cache_ops_need_broadcast())
125 smp_call_function(flush_ptrace_access_other,
126 NULL, 1);
George G. Davisa188ad22006-09-02 18:43:20 +0100127 }
128}
Russell King2ef7f3d2009-11-05 13:29:36 +0000129
130/*
131 * Copy user data from/to a page which is mapped into a different
132 * processes address space. Really, we want to allow our "user
133 * space" model to handle this.
134 *
135 * Note that this code needs to run on the current CPU.
136 */
137void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
138 unsigned long uaddr, void *dst, const void *src,
139 unsigned long len)
140{
141#ifdef CONFIG_SMP
142 preempt_disable();
Russell King8d802d22005-05-10 17:31:43 +0100143#endif
Russell King2ef7f3d2009-11-05 13:29:36 +0000144 memcpy(dst, src, len);
145 flush_ptrace_access(vma, page, uaddr, dst, len);
146#ifdef CONFIG_SMP
147 preempt_enable();
148#endif
149}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150
Russell King8830f042005-06-20 09:51:03 +0100151void __flush_dcache_page(struct address_space *mapping, struct page *page)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 /*
154 * Writeback any data associated with the kernel mapping of this
155 * page. This ensures that data in the physical page is mutually
156 * coherent with the kernels mapping.
157 */
Nicolas Pitre7e5a69e2010-03-29 21:46:02 +0100158 if (!PageHighMem(page)) {
159 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
160 } else {
161 void *addr = kmap_high_get(page);
162 if (addr) {
163 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
164 kunmap_high(page);
165 } else if (cache_is_vipt()) {
166 pte_t saved_pte;
167 addr = kmap_high_l1_vipt(page, &saved_pte);
168 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
169 kunmap_high_l1_vipt(page, saved_pte);
170 }
171 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173 /*
Russell King8830f042005-06-20 09:51:03 +0100174 * If this is a page cache page, and we have an aliasing VIPT cache,
175 * we only need to do one flush - which would be at the relevant
Russell King8d802d22005-05-10 17:31:43 +0100176 * userspace colour, which is congruent with page->index.
177 */
Russell Kingf91fb052009-10-24 23:05:34 +0100178 if (mapping && cache_is_vipt_aliasing())
Russell King8830f042005-06-20 09:51:03 +0100179 flush_pfn_alias(page_to_pfn(page),
180 page->index << PAGE_CACHE_SHIFT);
181}
182
183static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
184{
185 struct mm_struct *mm = current->active_mm;
186 struct vm_area_struct *mpnt;
187 struct prio_tree_iter iter;
188 pgoff_t pgoff;
Russell King8d802d22005-05-10 17:31:43 +0100189
190 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 * There are possible user space mappings of this page:
192 * - VIVT cache: we need to also write back and invalidate all user
193 * data in the current VM view associated with this page.
194 * - aliasing VIPT: we only need to find one mapping of this page.
195 */
196 pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
197
198 flush_dcache_mmap_lock(mapping);
199 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
200 unsigned long offset;
201
202 /*
203 * If this VMA is not in our MM, we can ignore it.
204 */
205 if (mpnt->vm_mm != mm)
206 continue;
207 if (!(mpnt->vm_flags & VM_MAYSHARE))
208 continue;
209 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
210 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 }
212 flush_dcache_mmap_unlock(mapping);
213}
214
Catalin Marinas60121912010-09-13 15:58:06 +0100215#if __LINUX_ARM_ARCH__ >= 6
216void __sync_icache_dcache(pte_t pteval)
217{
218 unsigned long pfn;
219 struct page *page;
220 struct address_space *mapping;
221
222 if (!pte_present_user(pteval))
223 return;
224 if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
225 /* only flush non-aliasing VIPT caches for exec mappings */
226 return;
227 pfn = pte_pfn(pteval);
228 if (!pfn_valid(pfn))
229 return;
230
231 page = pfn_to_page(pfn);
232 if (cache_is_vipt_aliasing())
233 mapping = page_mapping(page);
234 else
235 mapping = NULL;
236
237 if (!test_and_set_bit(PG_dcache_clean, &page->flags))
238 __flush_dcache_page(mapping, page);
239 /* pte_exec() already checked above for non-aliasing VIPT cache */
240 if (cache_is_vipt_nonaliasing() || pte_exec(pteval))
241 __flush_icache_all();
242}
243#endif
244
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245/*
246 * Ensure cache coherency between kernel mapping and userspace mapping
247 * of this page.
248 *
249 * We have three cases to consider:
250 * - VIPT non-aliasing cache: fully coherent so nothing required.
251 * - VIVT: fully aliasing, so we need to handle every alias in our
252 * current VM view.
253 * - VIPT aliasing: need to handle one alias in our current VM view.
254 *
255 * If we need to handle aliasing:
256 * If the page only exists in the page cache and there are no user
257 * space mappings, we can be lazy and remember that we may have dirty
258 * kernel cache lines for later. Otherwise, we assume we have
259 * aliasing mappings.
Russell Kingdf2f5e72005-11-30 16:02:54 +0000260 *
261 * Note that we disable the lazy flush for SMP.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 */
263void flush_dcache_page(struct page *page)
264{
Russell King421fe932009-10-25 10:23:04 +0000265 struct address_space *mapping;
266
267 /*
268 * The zero page is never written to, so never has any dirty
269 * cache lines, and therefore never needs to be flushed.
270 */
271 if (page == ZERO_PAGE(0))
272 return;
273
274 mapping = page_mapping(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
Catalin Marinas85848dd2010-09-13 15:58:37 +0100276 if (!cache_ops_need_broadcast() &&
277 mapping && !mapping_mapped(mapping))
Catalin Marinasc0177802010-09-13 15:57:36 +0100278 clear_bit(PG_dcache_clean, &page->flags);
Catalin Marinas85848dd2010-09-13 15:58:37 +0100279 else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 __flush_dcache_page(mapping, page);
Russell King8830f042005-06-20 09:51:03 +0100281 if (mapping && cache_is_vivt())
282 __flush_dcache_aliases(mapping, page);
Catalin Marinas826cbda2008-06-13 10:28:36 +0100283 else if (mapping)
284 __flush_icache_all();
Catalin Marinasc0177802010-09-13 15:57:36 +0100285 set_bit(PG_dcache_clean, &page->flags);
Russell King8830f042005-06-20 09:51:03 +0100286 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287}
288EXPORT_SYMBOL(flush_dcache_page);
Russell King6020dff2006-12-30 23:17:40 +0000289
290/*
291 * Flush an anonymous page so that users of get_user_pages()
292 * can safely access the data. The expected sequence is:
293 *
294 * get_user_pages()
295 * -> flush_anon_page
296 * memcpy() to/from page
297 * if written to page, flush_dcache_page()
298 */
299void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
300{
301 unsigned long pfn;
302
303 /* VIPT non-aliasing caches need do nothing */
304 if (cache_is_vipt_nonaliasing())
305 return;
306
307 /*
308 * Write back and invalidate userspace mapping.
309 */
310 pfn = page_to_pfn(page);
311 if (cache_is_vivt()) {
312 flush_cache_page(vma, vmaddr, pfn);
313 } else {
314 /*
315 * For aliasing VIPT, we can flush an alias of the
316 * userspace address only.
317 */
318 flush_pfn_alias(pfn, vmaddr);
Russell King2df341e2009-10-24 22:58:40 +0100319 __flush_icache_all();
Russell King6020dff2006-12-30 23:17:40 +0000320 }
321
322 /*
323 * Invalidate kernel mapping. No data should be contained
324 * in this mapping of the page. FIXME: this is overkill
325 * since we actually ask for a write-back and invalidate.
326 */
Russell King2c9b9c82009-11-26 12:56:21 +0000327 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
Russell King6020dff2006-12-30 23:17:40 +0000328}