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gerrit-public.fairphone.software / kernel / msm / 8bad3055e902a16b7cf47777fc3e78a965d0b57a / . / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blob: d237ab8028c8ab07117efdd74ea1b979a0a3a5bf [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]2 * Copyright (c) 2000-2011 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]9 * mpi2_cnfg.h Version: 02.00.20
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
116 * in the array.
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
125 * define.
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
Kashyap, Desai9af05d92011-01-04 11:35:41 +0530[diff] [blame]128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
129 * defines.
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
132 * the Pinout field.
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]143 * 05-25-11 02.00.20 Cleaned up a few comments.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]144 * --------------------------------------------------------------------------
145 */
146
147#ifndef MPI2_CNFG_H
148#define MPI2_CNFG_H
149
150/*****************************************************************************
151* Configuration Page Header and defines
152*****************************************************************************/
153
154/* Config Page Header */
155typedef struct _MPI2_CONFIG_PAGE_HEADER
156{
157 U8 PageVersion; /* 0x00 */
158 U8 PageLength; /* 0x01 */
159 U8 PageNumber; /* 0x02 */
160 U8 PageType; /* 0x03 */
161} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
162 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
163
164typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
165{
166 MPI2_CONFIG_PAGE_HEADER Struct;
167 U8 Bytes[4];
168 U16 Word16[2];
169 U32 Word32;
170} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
171 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
172
173/* Extended Config Page Header */
174typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
175{
176 U8 PageVersion; /* 0x00 */
177 U8 Reserved1; /* 0x01 */
178 U8 PageNumber; /* 0x02 */
179 U8 PageType; /* 0x03 */
180 U16 ExtPageLength; /* 0x04 */
181 U8 ExtPageType; /* 0x06 */
182 U8 Reserved2; /* 0x07 */
183} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
184 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
185 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
186
187typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
188{
189 MPI2_CONFIG_PAGE_HEADER Struct;
190 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
191 U8 Bytes[8];
192 U16 Word16[4];
193 U32 Word32[2];
194} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
195 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
196
197
198/* PageType field values */
199#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
200#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
201#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
202#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
203
204#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
205#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
206#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
207#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
208#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
209#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
210#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
211#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
212
213#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
214
215
216/* ExtPageType field values */
217#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
218#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
219#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
220#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
221#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
222#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
223#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
224#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
225#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]226#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]227#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]228
229
230/*****************************************************************************
231* PageAddress defines
232*****************************************************************************/
233
234/* RAID Volume PageAddress format */
235#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
236#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
237#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
238
239#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
240
241
242/* RAID Physical Disk PageAddress format */
243#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
244#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
245#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
246#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
247
248#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
249#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
250
251
252/* SAS Expander PageAddress format */
253#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
254#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
255#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
256#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
257
258#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
259#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
260#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
261
262
263/* SAS Device PageAddress format */
264#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
265#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
266#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
267
268#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
269
270
271/* SAS PHY PageAddress format */
272#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
273#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
274#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
275
276#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
277#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
278
279
280/* SAS Port PageAddress format */
281#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
282#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
283#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
284
285#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
286
287
288/* SAS Enclosure PageAddress format */
289#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
290#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
291#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
292
293#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
294
295
296/* RAID Configuration PageAddress format */
297#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
298#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
299#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
300#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
301
302#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
303
304
305/* Driver Persistent Mapping PageAddress format */
306#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
307#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
308
309#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
310#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
311#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
312
313
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]314/* Ethernet PageAddress format */
315#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
316#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
317
318#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
319
320
321
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]322/****************************************************************************
323* Configuration messages
324****************************************************************************/
325
326/* Configuration Request Message */
327typedef struct _MPI2_CONFIG_REQUEST
328{
329 U8 Action; /* 0x00 */
330 U8 SGLFlags; /* 0x01 */
331 U8 ChainOffset; /* 0x02 */
332 U8 Function; /* 0x03 */
333 U16 ExtPageLength; /* 0x04 */
334 U8 ExtPageType; /* 0x06 */
335 U8 MsgFlags; /* 0x07 */
336 U8 VP_ID; /* 0x08 */
337 U8 VF_ID; /* 0x09 */
338 U16 Reserved1; /* 0x0A */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]339 U8 Reserved2; /* 0x0C */
340 U8 ProxyVF_ID; /* 0x0D */
341 U16 Reserved4; /* 0x0E */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]342 U32 Reserved3; /* 0x10 */
343 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
344 U32 PageAddress; /* 0x18 */
345 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
346} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
347 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
348
349/* values for the Action field */
350#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
351#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
352#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
353#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
354#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
355#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
356#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
357#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
358
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]359/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]360
361
362/* Config Reply Message */
363typedef struct _MPI2_CONFIG_REPLY
364{
365 U8 Action; /* 0x00 */
366 U8 SGLFlags; /* 0x01 */
367 U8 MsgLength; /* 0x02 */
368 U8 Function; /* 0x03 */
369 U16 ExtPageLength; /* 0x04 */
370 U8 ExtPageType; /* 0x06 */
371 U8 MsgFlags; /* 0x07 */
372 U8 VP_ID; /* 0x08 */
373 U8 VF_ID; /* 0x09 */
374 U16 Reserved1; /* 0x0A */
375 U16 Reserved2; /* 0x0C */
376 U16 IOCStatus; /* 0x0E */
377 U32 IOCLogInfo; /* 0x10 */
378 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
379} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
380 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
381
382
383
384/*****************************************************************************
385*
386* C o n f i g u r a t i o n P a g e s
387*
388*****************************************************************************/
389
390/****************************************************************************
391* Manufacturing Config pages
392****************************************************************************/
393
394#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
395
396/* SAS */
397#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
398#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
399#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
400#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
401#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
402#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
403#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]404
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]405#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
406
Kashyap, Desaidb271362009-09-23 17:24:27 +0530[diff] [blame]407#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
408#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
409#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
410#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
411#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
412#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]413#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
414#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
415#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]416
417
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]418
419
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]420/* Manufacturing Page 0 */
421
422typedef struct _MPI2_CONFIG_PAGE_MAN_0
423{
424 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
425 U8 ChipName[16]; /* 0x04 */
426 U8 ChipRevision[8]; /* 0x14 */
427 U8 BoardName[16]; /* 0x1C */
428 U8 BoardAssembly[16]; /* 0x2C */
429 U8 BoardTracerNumber[16]; /* 0x3C */
430} MPI2_CONFIG_PAGE_MAN_0,
431 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
432 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
433
434#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
435
436
437/* Manufacturing Page 1 */
438
439typedef struct _MPI2_CONFIG_PAGE_MAN_1
440{
441 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
442 U8 VPD[256]; /* 0x04 */
443} MPI2_CONFIG_PAGE_MAN_1,
444 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
445 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
446
447#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
448
449
450typedef struct _MPI2_CHIP_REVISION_ID
451{
452 U16 DeviceID; /* 0x00 */
453 U8 PCIRevisionID; /* 0x02 */
454 U8 Reserved; /* 0x03 */
455} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
456 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
457
458
459/* Manufacturing Page 2 */
460
461/*
462 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
463 * one and check Header.PageLength at runtime.
464 */
465#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
466#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
467#endif
468
469typedef struct _MPI2_CONFIG_PAGE_MAN_2
470{
471 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
472 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
473 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
474} MPI2_CONFIG_PAGE_MAN_2,
475 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
476 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
477
478#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
479
480
481/* Manufacturing Page 3 */
482
483/*
484 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
485 * one and check Header.PageLength at runtime.
486 */
487#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
488#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
489#endif
490
491typedef struct _MPI2_CONFIG_PAGE_MAN_3
492{
493 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
494 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
495 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
496} MPI2_CONFIG_PAGE_MAN_3,
497 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
498 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
499
500#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
501
502
503/* Manufacturing Page 4 */
504
505typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
506{
507 U8 PowerSaveFlags; /* 0x00 */
508 U8 InternalOperationsSleepTime; /* 0x01 */
509 U8 InternalOperationsRunTime; /* 0x02 */
510 U8 HostIdleTime; /* 0x03 */
511} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
512 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
513 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
514
515/* defines for the PowerSaveFlags field */
516#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
517#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
518#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
519#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
520
521typedef struct _MPI2_CONFIG_PAGE_MAN_4
522{
523 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
524 U32 Reserved1; /* 0x04 */
525 U32 Flags; /* 0x08 */
526 U8 InquirySize; /* 0x0C */
527 U8 Reserved2; /* 0x0D */
528 U16 Reserved3; /* 0x0E */
529 U8 InquiryData[56]; /* 0x10 */
530 U32 RAID0VolumeSettings; /* 0x48 */
531 U32 RAID1EVolumeSettings; /* 0x4C */
532 U32 RAID1VolumeSettings; /* 0x50 */
533 U32 RAID10VolumeSettings; /* 0x54 */
534 U32 Reserved4; /* 0x58 */
535 U32 Reserved5; /* 0x5C */
536 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
537 U8 MaxOCEDisks; /* 0x64 */
538 U8 ResyncRate; /* 0x65 */
539 U16 DataScrubDuration; /* 0x66 */
540 U8 MaxHotSpares; /* 0x68 */
541 U8 MaxPhysDisksPerVol; /* 0x69 */
542 U8 MaxPhysDisks; /* 0x6A */
543 U8 MaxVolumes; /* 0x6B */
544} MPI2_CONFIG_PAGE_MAN_4,
545 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
546 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
547
548#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
549
550/* Manufacturing Page 4 Flags field */
551#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
552#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
553
554#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
555#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
556#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
557
558#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
559#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
560#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
561#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
562#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
563
564#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
565#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
566#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
567#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
568
569#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
570#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
571#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
572#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
573#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
574#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
575#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
576#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
577
578
579/* Manufacturing Page 5 */
580
581/*
582 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]583 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]584 */
585#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
586#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
587#endif
588
589typedef struct _MPI2_MANUFACTURING5_ENTRY
590{
591 U64 WWID; /* 0x00 */
592 U64 DeviceName; /* 0x08 */
593} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
594 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
595
596typedef struct _MPI2_CONFIG_PAGE_MAN_5
597{
598 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
599 U8 NumPhys; /* 0x04 */
600 U8 Reserved1; /* 0x05 */
601 U16 Reserved2; /* 0x06 */
602 U32 Reserved3; /* 0x08 */
603 U32 Reserved4; /* 0x0C */
604 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
605} MPI2_CONFIG_PAGE_MAN_5,
606 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
607 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
608
609#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
610
611
612/* Manufacturing Page 6 */
613
614typedef struct _MPI2_CONFIG_PAGE_MAN_6
615{
616 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
617 U32 ProductSpecificInfo;/* 0x04 */
618} MPI2_CONFIG_PAGE_MAN_6,
619 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
620 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
621
622#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
623
624
625/* Manufacturing Page 7 */
626
627typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
628{
629 U32 Pinout; /* 0x00 */
630 U8 Connector[16]; /* 0x04 */
631 U8 Location; /* 0x14 */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]632 U8 ReceptacleID; /* 0x15 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]633 U16 Slot; /* 0x16 */
634 U32 Reserved2; /* 0x18 */
635} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
636 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
637
638/* defines for the Pinout field */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]639#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
640#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
641
642#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
643#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
644#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
645#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
646#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
647#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
648#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
649#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
650#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
651#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
652#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
653#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
654#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
655#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
656#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]657
658/* defines for the Location field */
659#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
660#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
661#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
662#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
663#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
664#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
665#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
666
667/*
668 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]669 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]670 */
671#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
672#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
673#endif
674
675typedef struct _MPI2_CONFIG_PAGE_MAN_7
676{
677 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
678 U32 Reserved1; /* 0x04 */
679 U32 Reserved2; /* 0x08 */
680 U32 Flags; /* 0x0C */
681 U8 EnclosureName[16]; /* 0x10 */
682 U8 NumPhys; /* 0x20 */
683 U8 Reserved3; /* 0x21 */
684 U16 Reserved4; /* 0x22 */
685 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
686} MPI2_CONFIG_PAGE_MAN_7,
687 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
688 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
689
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]690#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]691
692/* defines for the Flags field */
693#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
694
695
696/*
697 * Generic structure to use for product-specific manufacturing pages
698 * (currently Manufacturing Page 8 through Manufacturing Page 31).
699 */
700
701typedef struct _MPI2_CONFIG_PAGE_MAN_PS
702{
703 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
704 U32 ProductSpecificInfo;/* 0x04 */
705} MPI2_CONFIG_PAGE_MAN_PS,
706 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
707 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
708
709#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
710#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
711#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
712#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
713#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
714#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
715#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
716#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
717#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
718#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
719#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
720#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
721#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
722#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
723#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
724#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
725#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
726#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
727#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
728#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
729#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
730#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
731#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
732#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
733
734
735/****************************************************************************
736* IO Unit Config Pages
737****************************************************************************/
738
739/* IO Unit Page 0 */
740
741typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
742{
743 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
744 U64 UniqueValue; /* 0x04 */
745 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
746 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
747} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
748 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
749
750#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
751
752
753/* IO Unit Page 1 */
754
755typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
756{
757 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
758 U32 Flags; /* 0x04 */
759} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
760 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
761
762#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
763
764/* IO Unit Page 1 Flags defines */
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]765#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]766#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]767#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]768#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
769#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
770#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
771#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
772#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
773#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
774#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]775
776
777/* IO Unit Page 3 */
778
779/*
780 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]781 * one and check the value returned for GPIOCount at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]782 */
783#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
784#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
785#endif
786
787typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
788{
789 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
790 U8 GPIOCount; /* 0x04 */
791 U8 Reserved1; /* 0x05 */
792 U16 Reserved2; /* 0x06 */
793 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
794} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
795 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
796
797#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
798
799/* defines for IO Unit Page 3 GPIOVal field */
800#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
801#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
802#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
803#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
804
805
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]806/* IO Unit Page 5 */
807
808/*
809 * Upper layer code (drivers, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]810 * one and check the value returned for NumDmaEngines at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]811 */
812#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
813#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
814#endif
815
816typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
817 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
818 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
819 U64 RaidAcceleratorBufferSize; /* 0x0C */
820 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
821 U8 RAControlSize; /* 0x1C */
822 U8 NumDmaEngines; /* 0x1D */
823 U8 RAMinControlSize; /* 0x1E */
824 U8 RAMaxControlSize; /* 0x1F */
825 U32 Reserved1; /* 0x20 */
826 U32 Reserved2; /* 0x24 */
827 U32 Reserved3; /* 0x28 */
828 U32 DmaEngineCapabilities
829 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
830} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
831 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
832
833#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
834
835/* defines for IO Unit Page 5 DmaEngineCapabilities field */
836#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
837#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
838
839#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
840#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
841#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
842#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
843
844
845/* IO Unit Page 6 */
846
847typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
848 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
849 U16 Flags; /* 0x04 */
850 U8 RAHostControlSize; /* 0x06 */
851 U8 Reserved0; /* 0x07 */
852 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
853 U32 Reserved1; /* 0x10 */
854 U32 Reserved2; /* 0x14 */
855 U32 Reserved3; /* 0x18 */
856} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
857 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
858
859#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
860
861/* defines for IO Unit Page 6 Flags field */
862#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
863
864
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]865/* IO Unit Page 7 */
866
867typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
868 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
869 U16 Reserved1; /* 0x04 */
870 U8 PCIeWidth; /* 0x06 */
871 U8 PCIeSpeed; /* 0x07 */
872 U32 ProcessorState; /* 0x08 */
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]873 U32 PowerManagementCapabilities; /* 0x0C */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]874 U16 IOCTemperature; /* 0x10 */
875 U8 IOCTemperatureUnits; /* 0x12 */
876 U8 IOCSpeed; /* 0x13 */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]877 U16 BoardTemperature; /* 0x14 */
878 U8 BoardTemperatureUnits; /* 0x16 */
879 U8 Reserved3; /* 0x17 */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]880} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
881 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
882
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]883#define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]884
885/* defines for IO Unit Page 7 PCIeWidth field */
886#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
887#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
888#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
889#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
890
891/* defines for IO Unit Page 7 PCIeSpeed field */
892#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
893#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
894#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
895
896/* defines for IO Unit Page 7 ProcessorState field */
897#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
898#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
899
900#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
901#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
902#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
903
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]904/* defines for IO Unit Page 7 PowerManagementCapabilities field */
905#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
906#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
907#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
908#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
909#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
910
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]911/* defines for IO Unit Page 7 IOCTemperatureUnits field */
912#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
913#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
914#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
915
916/* defines for IO Unit Page 7 IOCSpeed field */
917#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
918#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
919#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
920#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
921
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]922/* defines for IO Unit Page 7 BoardTemperatureUnits field */
923#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
924#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
925#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
926
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]927/* IO Unit Page 8 */
928
929#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
930
931typedef struct _MPI2_IOUNIT8_SENSOR {
932 U16 Flags; /* 0x00 */
933 U16 Reserved1; /* 0x02 */
934 U16
935 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
936 U32 Reserved2; /* 0x0C */
937 U32 Reserved3; /* 0x10 */
938 U32 Reserved4; /* 0x14 */
939} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
940Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
941
942/* defines for IO Unit Page 8 Sensor Flags field */
943#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
944#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
945#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
946#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
947
948/*
949 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
950 * one and check the value returned for NumSensors at runtime.
951 */
952#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
953#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
954#endif
955
956typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
957 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
958 U32 Reserved1; /* 0x04 */
959 U32 Reserved2; /* 0x08 */
960 U8 NumSensors; /* 0x0C */
961 U8 PollingInterval; /* 0x0D */
962 U16 Reserved3; /* 0x0E */
963 MPI2_IOUNIT8_SENSOR
964 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
965} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
966Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
967
968#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
969
970
971/* IO Unit Page 9 */
972
973typedef struct _MPI2_IOUNIT9_SENSOR {
974 U16 CurrentTemperature; /* 0x00 */
975 U16 Reserved1; /* 0x02 */
976 U8 Flags; /* 0x04 */
977 U8 Reserved2; /* 0x05 */
978 U16 Reserved3; /* 0x06 */
979 U32 Reserved4; /* 0x08 */
980 U32 Reserved5; /* 0x0C */
981} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
982Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
983
984/* defines for IO Unit Page 9 Sensor Flags field */
985#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
986
987/*
988 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
989 * one and check the value returned for NumSensors at runtime.
990 */
991#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
992#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
993#endif
994
995typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
996 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
997 U32 Reserved1; /* 0x04 */
998 U32 Reserved2; /* 0x08 */
999 U8 NumSensors; /* 0x0C */
1000 U8 Reserved4; /* 0x0D */
1001 U16 Reserved3; /* 0x0E */
1002 MPI2_IOUNIT9_SENSOR
1003 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1004} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1005Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1006
1007#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1008
1009
1010/* IO Unit Page 10 */
1011
1012typedef struct _MPI2_IOUNIT10_FUNCTION {
1013 U8 CreditPercent; /* 0x00 */
1014 U8 Reserved1; /* 0x01 */
1015 U16 Reserved2; /* 0x02 */
1016} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1017Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1018
1019/*
1020 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1021 * one and check the value returned for NumFunctions at runtime.
1022 */
1023#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1024#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1025#endif
1026
1027typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1028 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1029 U8 NumFunctions; /* 0x04 */
1030 U8 Reserved1; /* 0x05 */
1031 U16 Reserved2; /* 0x06 */
1032 U32 Reserved3; /* 0x08 */
1033 U32 Reserved4; /* 0x0C */
1034 MPI2_IOUNIT10_FUNCTION
1035 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1036} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1037Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1038
1039#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1040
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1041
1042
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1043/****************************************************************************
1044* IOC Config Pages
1045****************************************************************************/
1046
1047/* IOC Page 0 */
1048
1049typedef struct _MPI2_CONFIG_PAGE_IOC_0
1050{
1051 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1052 U32 Reserved1; /* 0x04 */
1053 U32 Reserved2; /* 0x08 */
1054 U16 VendorID; /* 0x0C */
1055 U16 DeviceID; /* 0x0E */
1056 U8 RevisionID; /* 0x10 */
1057 U8 Reserved3; /* 0x11 */
1058 U16 Reserved4; /* 0x12 */
1059 U32 ClassCode; /* 0x14 */
1060 U16 SubsystemVendorID; /* 0x18 */
1061 U16 SubsystemID; /* 0x1A */
1062} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1063 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1064
1065#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1066
1067
1068/* IOC Page 1 */
1069
1070typedef struct _MPI2_CONFIG_PAGE_IOC_1
1071{
1072 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1073 U32 Flags; /* 0x04 */
1074 U32 CoalescingTimeout; /* 0x08 */
1075 U8 CoalescingDepth; /* 0x0C */
1076 U8 PCISlotNum; /* 0x0D */
1077 U8 PCIBusNum; /* 0x0E */
1078 U8 PCIDomainSegment; /* 0x0F */
1079 U32 Reserved1; /* 0x10 */
1080 U32 Reserved2; /* 0x14 */
1081} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1082 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1083
1084#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1085
1086/* defines for IOC Page 1 Flags field */
1087#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1088
1089#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1090#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1091#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1092
1093/* IOC Page 6 */
1094
1095typedef struct _MPI2_CONFIG_PAGE_IOC_6
1096{
1097 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1098 U32 CapabilitiesFlags; /* 0x04 */
1099 U8 MaxDrivesRAID0; /* 0x08 */
1100 U8 MaxDrivesRAID1; /* 0x09 */
1101 U8 MaxDrivesRAID1E; /* 0x0A */
1102 U8 MaxDrivesRAID10; /* 0x0B */
1103 U8 MinDrivesRAID0; /* 0x0C */
1104 U8 MinDrivesRAID1; /* 0x0D */
1105 U8 MinDrivesRAID1E; /* 0x0E */
1106 U8 MinDrivesRAID10; /* 0x0F */
1107 U32 Reserved1; /* 0x10 */
1108 U8 MaxGlobalHotSpares; /* 0x14 */
1109 U8 MaxPhysDisks; /* 0x15 */
1110 U8 MaxVolumes; /* 0x16 */
1111 U8 MaxConfigs; /* 0x17 */
1112 U8 MaxOCEDisks; /* 0x18 */
1113 U8 Reserved2; /* 0x19 */
1114 U16 Reserved3; /* 0x1A */
1115 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1116 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1117 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1118 U32 Reserved4; /* 0x28 */
1119 U32 Reserved5; /* 0x2C */
1120 U16 DefaultMetadataSize; /* 0x30 */
1121 U16 Reserved6; /* 0x32 */
1122 U16 MaxBadBlockTableEntries; /* 0x34 */
1123 U16 Reserved7; /* 0x36 */
1124 U32 IRNvsramVersion; /* 0x38 */
1125} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1126 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1127
1128#define MPI2_IOCPAGE6_PAGEVERSION (0x04)
1129
1130/* defines for IOC Page 6 CapabilitiesFlags */
1131#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1132#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1133#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1134#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1135#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1136
1137
1138/* IOC Page 7 */
1139
1140#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1141
1142typedef struct _MPI2_CONFIG_PAGE_IOC_7
1143{
1144 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1145 U32 Reserved1; /* 0x04 */
1146 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1147 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]1148 U16 SASNotifyPrimitiveMasks; /* 0x1A */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1149 U32 Reserved3; /* 0x1C */
1150} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1151 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1152
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]1153#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1154
1155
1156/* IOC Page 8 */
1157
1158typedef struct _MPI2_CONFIG_PAGE_IOC_8
1159{
1160 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1161 U8 NumDevsPerEnclosure; /* 0x04 */
1162 U8 Reserved1; /* 0x05 */
1163 U16 Reserved2; /* 0x06 */
1164 U16 MaxPersistentEntries; /* 0x08 */
1165 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1166 U16 Flags; /* 0x0C */
1167 U16 Reserved3; /* 0x0E */
1168 U16 IRVolumeMappingFlags; /* 0x10 */
1169 U16 Reserved4; /* 0x12 */
1170 U32 Reserved5; /* 0x14 */
1171} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1172 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1173
1174#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1175
1176/* defines for IOC Page 8 Flags field */
1177#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1178#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1179
1180#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1181#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1182#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1183
1184#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1185#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1186
1187/* defines for IOC Page 8 IRVolumeMappingFlags */
1188#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1189#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1190#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1191
1192
1193/****************************************************************************
1194* BIOS Config Pages
1195****************************************************************************/
1196
1197/* BIOS Page 1 */
1198
1199typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1200{
1201 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1202 U32 BiosOptions; /* 0x04 */
1203 U32 IOCSettings; /* 0x08 */
1204 U32 Reserved1; /* 0x0C */
1205 U32 DeviceSettings; /* 0x10 */
1206 U16 NumberOfDevices; /* 0x14 */
1207 U16 Reserved2; /* 0x16 */
1208 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1209 U16 IOTimeoutSequential; /* 0x1A */
1210 U16 IOTimeoutOther; /* 0x1C */
1211 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1212} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1213 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1214
1215#define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1216
1217/* values for BIOS Page 1 BiosOptions field */
1218#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1219
1220/* values for BIOS Page 1 IOCSettings field */
1221#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1222#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1223#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1224
1225#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1226#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1227#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1228#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1229
1230#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1231#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1232#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1233#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1234#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1235
1236#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1237
1238/* values for BIOS Page 1 DeviceSettings field */
1239#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1240#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1241#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1242#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1243#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1244
1245
1246/* BIOS Page 2 */
1247
1248typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1249{
1250 U32 Reserved1; /* 0x00 */
1251 U32 Reserved2; /* 0x04 */
1252 U32 Reserved3; /* 0x08 */
1253 U32 Reserved4; /* 0x0C */
1254 U32 Reserved5; /* 0x10 */
1255 U32 Reserved6; /* 0x14 */
1256} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1257 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1258 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1259
1260typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1261{
1262 U64 SASAddress; /* 0x00 */
1263 U8 LUN[8]; /* 0x08 */
1264 U32 Reserved1; /* 0x10 */
1265 U32 Reserved2; /* 0x14 */
1266} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1267 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1268
1269typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1270{
1271 U64 EnclosureLogicalID; /* 0x00 */
1272 U32 Reserved1; /* 0x08 */
1273 U32 Reserved2; /* 0x0C */
1274 U16 SlotNumber; /* 0x10 */
1275 U16 Reserved3; /* 0x12 */
1276 U32 Reserved4; /* 0x14 */
1277} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1278 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1279 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1280
1281typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1282{
1283 U64 DeviceName; /* 0x00 */
1284 U8 LUN[8]; /* 0x08 */
1285 U32 Reserved1; /* 0x10 */
1286 U32 Reserved2; /* 0x14 */
1287} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1288 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1289
1290typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1291{
1292 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1293 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1294 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1295 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1296} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1297 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1298
1299typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1300{
1301 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1302 U32 Reserved1; /* 0x04 */
1303 U32 Reserved2; /* 0x08 */
1304 U32 Reserved3; /* 0x0C */
1305 U32 Reserved4; /* 0x10 */
1306 U32 Reserved5; /* 0x14 */
1307 U32 Reserved6; /* 0x18 */
1308 U8 ReqBootDeviceForm; /* 0x1C */
1309 U8 Reserved7; /* 0x1D */
1310 U16 Reserved8; /* 0x1E */
1311 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1312 U8 ReqAltBootDeviceForm; /* 0x38 */
1313 U8 Reserved9; /* 0x39 */
1314 U16 Reserved10; /* 0x3A */
1315 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1316 U8 CurrentBootDeviceForm; /* 0x58 */
1317 U8 Reserved11; /* 0x59 */
1318 U16 Reserved12; /* 0x5A */
1319 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1320} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1321 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1322
1323#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1324
1325/* values for BIOS Page 2 BootDeviceForm fields */
1326#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1327#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1328#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1329#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1330#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1331
1332
1333/* BIOS Page 3 */
1334
1335typedef struct _MPI2_ADAPTER_INFO
1336{
1337 U8 PciBusNumber; /* 0x00 */
1338 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1339 U16 AdapterFlags; /* 0x02 */
1340} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1341 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1342
1343#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1344#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1345
1346typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1347{
1348 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1349 U32 GlobalFlags; /* 0x04 */
1350 U32 BiosVersion; /* 0x08 */
1351 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1352 U32 Reserved1; /* 0x1C */
1353} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1354 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1355
1356#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1357
1358/* values for BIOS Page 3 GlobalFlags */
1359#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1360#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1361#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1362
1363#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1364#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1365#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1366#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1367
1368
1369/* BIOS Page 4 */
1370
1371/*
1372 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1373 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1374 */
1375#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1376#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1377#endif
1378
1379typedef struct _MPI2_BIOS4_ENTRY
1380{
1381 U64 ReassignmentWWID; /* 0x00 */
1382 U64 ReassignmentDeviceName; /* 0x08 */
1383} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1384 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1385
1386typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1387{
1388 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1389 U8 NumPhys; /* 0x04 */
1390 U8 Reserved1; /* 0x05 */
1391 U16 Reserved2; /* 0x06 */
1392 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1393} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1394 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1395
1396#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1397
1398
1399/****************************************************************************
1400* RAID Volume Config Pages
1401****************************************************************************/
1402
1403/* RAID Volume Page 0 */
1404
1405typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1406{
1407 U8 RAIDSetNum; /* 0x00 */
1408 U8 PhysDiskMap; /* 0x01 */
1409 U8 PhysDiskNum; /* 0x02 */
1410 U8 Reserved; /* 0x03 */
1411} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1412 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1413
1414/* defines for the PhysDiskMap field */
1415#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1416#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1417
1418typedef struct _MPI2_RAIDVOL0_SETTINGS
1419{
1420 U16 Settings; /* 0x00 */
1421 U8 HotSparePool; /* 0x01 */
1422 U8 Reserved; /* 0x02 */
1423} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1424 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1425
1426/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1427#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1428#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1429#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1430#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1431#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1432#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1433#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1434#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1435
1436/* RAID Volume Page 0 VolumeSettings defines */
1437#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1438#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1439
1440#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1441#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1442#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1443#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1444
1445/*
1446 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1447 * one and check the value returned for NumPhysDisks at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1448 */
1449#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1450#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1451#endif
1452
1453typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1454{
1455 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1456 U16 DevHandle; /* 0x04 */
1457 U8 VolumeState; /* 0x06 */
1458 U8 VolumeType; /* 0x07 */
1459 U32 VolumeStatusFlags; /* 0x08 */
1460 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1461 U64 MaxLBA; /* 0x10 */
1462 U32 StripeSize; /* 0x18 */
1463 U16 BlockSize; /* 0x1C */
1464 U16 Reserved1; /* 0x1E */
1465 U8 SupportedPhysDisks; /* 0x20 */
1466 U8 ResyncRate; /* 0x21 */
1467 U16 DataScrubDuration; /* 0x22 */
1468 U8 NumPhysDisks; /* 0x24 */
1469 U8 Reserved2; /* 0x25 */
1470 U8 Reserved3; /* 0x26 */
1471 U8 InactiveStatus; /* 0x27 */
1472 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1473} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1474 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1475
1476#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1477
1478/* values for RAID VolumeState */
1479#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1480#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1481#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1482#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1483#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1484#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1485
1486/* values for RAID VolumeType */
1487#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1488#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1489#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1490#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1491#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1492
1493/* values for RAID Volume Page 0 VolumeStatusFlags field */
1494#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1495#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1496#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1497#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1498#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1499#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1500#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1501#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1502#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1503#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1504#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1505#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1506#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1507#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1508#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1509#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1510#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1511#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1512#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1513
1514/* values for RAID Volume Page 0 SupportedPhysDisks field */
1515#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1516#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1517#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1518#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1519
1520/* values for RAID Volume Page 0 InactiveStatus field */
1521#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1522#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1523#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1524#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1525#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1526#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1527#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1528
1529
1530/* RAID Volume Page 1 */
1531
1532typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1533{
1534 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1535 U16 DevHandle; /* 0x04 */
1536 U16 Reserved0; /* 0x06 */
1537 U8 GUID[24]; /* 0x08 */
1538 U8 Name[16]; /* 0x20 */
1539 U64 WWID; /* 0x30 */
1540 U32 Reserved1; /* 0x38 */
1541 U32 Reserved2; /* 0x3C */
1542} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1543 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1544
1545#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1546
1547
1548/****************************************************************************
1549* RAID Physical Disk Config Pages
1550****************************************************************************/
1551
1552/* RAID Physical Disk Page 0 */
1553
1554typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1555{
1556 U16 Reserved1; /* 0x00 */
1557 U8 HotSparePool; /* 0x02 */
1558 U8 Reserved2; /* 0x03 */
1559} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1560 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1561
1562/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1563
1564typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1565{
1566 U8 VendorID[8]; /* 0x00 */
1567 U8 ProductID[16]; /* 0x08 */
1568 U8 ProductRevLevel[4]; /* 0x18 */
1569 U8 SerialNum[32]; /* 0x1C */
1570} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1571 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1572 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1573
1574typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1575{
1576 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1577 U16 DevHandle; /* 0x04 */
1578 U8 Reserved1; /* 0x06 */
1579 U8 PhysDiskNum; /* 0x07 */
1580 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1581 U32 Reserved2; /* 0x0C */
1582 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1583 U32 Reserved3; /* 0x4C */
1584 U8 PhysDiskState; /* 0x50 */
1585 U8 OfflineReason; /* 0x51 */
1586 U8 IncompatibleReason; /* 0x52 */
1587 U8 PhysDiskAttributes; /* 0x53 */
1588 U32 PhysDiskStatusFlags; /* 0x54 */
1589 U64 DeviceMaxLBA; /* 0x58 */
1590 U64 HostMaxLBA; /* 0x60 */
1591 U64 CoercedMaxLBA; /* 0x68 */
1592 U16 BlockSize; /* 0x70 */
1593 U16 Reserved5; /* 0x72 */
1594 U32 Reserved6; /* 0x74 */
1595} MPI2_CONFIG_PAGE_RD_PDISK_0,
1596 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1597 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1598
1599#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1600
1601/* PhysDiskState defines */
1602#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1603#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1604#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1605#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1606#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1607#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1608#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1609#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1610
1611/* OfflineReason defines */
1612#define MPI2_PHYSDISK0_ONLINE (0x00)
1613#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1614#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1615#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1616#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1617#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1618#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1619
1620/* IncompatibleReason defines */
1621#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1622#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1623#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1624#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1625#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1626#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1627#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1628#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1629
1630/* PhysDiskAttributes defines */
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1631#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1632#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1633#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1634
1635#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1636#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1637#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1638
1639/* PhysDiskStatusFlags defines */
1640#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1641#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1642#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1643#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1644#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1645#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1646#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1647#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1648
1649
1650/* RAID Physical Disk Page 1 */
1651
1652/*
1653 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1654 * one and check the value returned for NumPhysDiskPaths at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1655 */
1656#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1657#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1658#endif
1659
1660typedef struct _MPI2_RAIDPHYSDISK1_PATH
1661{
1662 U16 DevHandle; /* 0x00 */
1663 U16 Reserved1; /* 0x02 */
1664 U64 WWID; /* 0x04 */
1665 U64 OwnerWWID; /* 0x0C */
1666 U8 OwnerIdentifier; /* 0x14 */
1667 U8 Reserved2; /* 0x15 */
1668 U16 Flags; /* 0x16 */
1669} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1670 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1671
1672/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1673#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1674#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1675#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1676
1677typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1678{
1679 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1680 U8 NumPhysDiskPaths; /* 0x04 */
1681 U8 PhysDiskNum; /* 0x05 */
1682 U16 Reserved1; /* 0x06 */
1683 U32 Reserved2; /* 0x08 */
1684 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1685} MPI2_CONFIG_PAGE_RD_PDISK_1,
1686 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1687 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1688
1689#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1690
1691
1692/****************************************************************************
1693* values for fields used by several types of SAS Config Pages
1694****************************************************************************/
1695
1696/* values for NegotiatedLinkRates fields */
1697#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1698#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1699#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1700/* link rates used for Negotiated Physical and Logical Link Rate */
1701#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1702#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1703#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1704#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1705#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1706#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1707#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1708#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1709#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1710#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1711
1712
1713/* values for AttachedPhyInfo fields */
1714#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1715#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1716#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1717
1718#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1719#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1720#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1721#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1722#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1723#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1724#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1725#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1726#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1727#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1728
1729
1730/* values for PhyInfo fields */
1731#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1732
1733#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1734#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1735#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1736#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1737#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1738
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1739#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1740#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1741#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1742#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1743#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1744#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1745
1746#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1747#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1748#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1749#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1750#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1751#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1752#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1753#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1754#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1755#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1756
1757#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1758#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1759#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1760#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1761
1762#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1763#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1764
1765#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1766#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1767#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1768#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1769
1770
1771/* values for SAS ProgrammedLinkRate fields */
1772#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1773#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1774#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1775#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1776#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1777#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1778#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1779#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1780#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1781#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1782
1783
1784/* values for SAS HwLinkRate fields */
1785#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1786#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1787#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1788#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1789#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1790#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1791#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1792#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1793
1794
1795
1796/****************************************************************************
1797* SAS IO Unit Config Pages
1798****************************************************************************/
1799
1800/* SAS IO Unit Page 0 */
1801
1802typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1803{
1804 U8 Port; /* 0x00 */
1805 U8 PortFlags; /* 0x01 */
1806 U8 PhyFlags; /* 0x02 */
1807 U8 NegotiatedLinkRate; /* 0x03 */
1808 U32 ControllerPhyDeviceInfo;/* 0x04 */
1809 U16 AttachedDevHandle; /* 0x08 */
1810 U16 ControllerDevHandle; /* 0x0A */
1811 U32 DiscoveryStatus; /* 0x0C */
1812 U32 Reserved; /* 0x10 */
1813} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1814 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1815
1816/*
1817 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1818 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1819 */
1820#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1821#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1822#endif
1823
1824typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1825{
1826 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1827 U32 Reserved1; /* 0x08 */
1828 U8 NumPhys; /* 0x0C */
1829 U8 Reserved2; /* 0x0D */
1830 U16 Reserved3; /* 0x0E */
1831 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1832} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1833 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1834 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1835
1836#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1837
1838/* values for SAS IO Unit Page 0 PortFlags */
1839#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1840#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1841
1842/* values for SAS IO Unit Page 0 PhyFlags */
1843#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1844#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1845
1846/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1847
1848/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1849
1850/* values for SAS IO Unit Page 0 DiscoveryStatus */
1851#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1852#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1853#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1854#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1855#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1856#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1857#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1858#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1859#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1860#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1861#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1862#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1863#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1864#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1865#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1866#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1867#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1868#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1869#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1870#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1871
1872
1873/* SAS IO Unit Page 1 */
1874
1875typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1876{
1877 U8 Port; /* 0x00 */
1878 U8 PortFlags; /* 0x01 */
1879 U8 PhyFlags; /* 0x02 */
1880 U8 MaxMinLinkRate; /* 0x03 */
1881 U32 ControllerPhyDeviceInfo; /* 0x04 */
1882 U16 MaxTargetPortConnectTime; /* 0x08 */
1883 U16 Reserved1; /* 0x0A */
1884} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1885 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1886
1887/*
1888 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1889 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1890 */
1891#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1892#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1893#endif
1894
1895typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1896{
1897 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1898 U16 ControlFlags; /* 0x08 */
1899 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1900 U16 AdditionalControlFlags; /* 0x0C */
1901 U16 SASWideMaxQueueDepth; /* 0x0E */
1902 U8 NumPhys; /* 0x10 */
1903 U8 SATAMaxQDepth; /* 0x11 */
1904 U8 ReportDeviceMissingDelay; /* 0x12 */
1905 U8 IODeviceMissingDelay; /* 0x13 */
1906 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1907} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1908 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1909 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1910
1911#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1912
1913/* values for SAS IO Unit Page 1 ControlFlags */
1914#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1915#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1916#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1917#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1918
1919#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1920#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1921#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1922#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1923#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1924
1925#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1926#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1927#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1928#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1929#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1930#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1931#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1932#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1933
1934/* values for SAS IO Unit Page 1 AdditionalControlFlags */
1935#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1936#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1937#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1938#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1939#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1940#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1941#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1942#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1943
1944/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1945#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1946#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1947
1948/* values for SAS IO Unit Page 1 PortFlags */
1949#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1950
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1951/* values for SAS IO Unit Page 1 PhyFlags */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1952#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1953#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1954
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1955/* values for SAS IO Unit Page 1 MaxMinLinkRate */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1956#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1957#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1958#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1959#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1960#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1961#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1962#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1963#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1964
1965/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1966
1967
1968/* SAS IO Unit Page 4 */
1969
1970typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1971{
1972 U8 MaxTargetSpinup; /* 0x00 */
1973 U8 SpinupDelay; /* 0x01 */
1974 U16 Reserved1; /* 0x02 */
1975} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1976 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1977
1978/*
1979 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1980 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1981 */
1982#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1983#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1984#endif
1985
1986typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1987{
1988 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1989 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1990 U32 Reserved1; /* 0x18 */
1991 U32 Reserved2; /* 0x1C */
1992 U32 Reserved3; /* 0x20 */
1993 U8 BootDeviceWaitTime; /* 0x24 */
1994 U8 Reserved4; /* 0x25 */
1995 U16 Reserved5; /* 0x26 */
1996 U8 NumPhys; /* 0x28 */
1997 U8 PEInitialSpinupDelay; /* 0x29 */
1998 U8 PEReplyDelay; /* 0x2A */
1999 U8 Flags; /* 0x2B */
2000 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2001} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2002 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2003 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2004
2005#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2006
2007/* defines for Flags field */
2008#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2009
2010/* defines for PHY field */
2011#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2012
2013
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2014/* SAS IO Unit Page 5 */
2015
2016typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2017 U8 ControlFlags; /* 0x00 */
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2018 U8 PortWidthModGroup; /* 0x01 */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2019 U16 InactivityTimerExponent; /* 0x02 */
2020 U8 SATAPartialTimeout; /* 0x04 */
2021 U8 Reserved2; /* 0x05 */
2022 U8 SATASlumberTimeout; /* 0x06 */
2023 U8 Reserved3; /* 0x07 */
2024 U8 SASPartialTimeout; /* 0x08 */
2025 U8 Reserved4; /* 0x09 */
2026 U8 SASSlumberTimeout; /* 0x0A */
2027 U8 Reserved5; /* 0x0B */
2028} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2029 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2030 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2031
2032/* defines for ControlFlags field */
2033#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2034#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2035#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2036#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2037
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2038/* defines for PortWidthModeGroup field */
2039#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2040
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2041/* defines for InactivityTimerExponent field */
2042#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2043#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2044#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2045#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2046#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2047#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2048#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2049#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2050
2051#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2052#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2053#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2054#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2055#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2056#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2057#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2058#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2059
2060/*
2061 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2062 * one and check the value returned for NumPhys at runtime.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2063 */
2064#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2065#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2066#endif
2067
2068typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2069 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2070 U8 NumPhys; /* 0x08 */
2071 U8 Reserved1; /* 0x09 */
2072 U16 Reserved2; /* 0x0A */
2073 U32 Reserved3; /* 0x0C */
2074 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2075 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2076} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2077 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2078 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2079
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2080#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2081
2082
2083/* SAS IO Unit Page 6 */
2084
2085typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2086 U8 CurrentStatus; /* 0x00 */
2087 U8 CurrentModulation; /* 0x01 */
2088 U8 CurrentUtilization; /* 0x02 */
2089 U8 Reserved1; /* 0x03 */
2090 U32 Reserved2; /* 0x04 */
2091} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2092 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2093 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2094 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2095
2096/* defines for CurrentStatus field */
2097#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2098#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2099#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2100#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2101#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2102#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2103#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2104#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2105
2106/* defines for CurrentModulation field */
2107#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2108#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2109#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2110#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2111
2112/*
2113 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2114 * one and check the value returned for NumGroups at runtime.
2115 */
2116#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2117#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2118#endif
2119
2120typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2121 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2122 U32 Reserved1; /* 0x08 */
2123 U32 Reserved2; /* 0x0C */
2124 U8 NumGroups; /* 0x10 */
2125 U8 Reserved3; /* 0x11 */
2126 U16 Reserved4; /* 0x12 */
2127 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2128 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2129} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2130 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2131 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2132
2133#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2134
2135
2136/* SAS IO Unit Page 7 */
2137
2138typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2139 U8 Flags; /* 0x00 */
2140 U8 Reserved1; /* 0x01 */
2141 U16 Reserved2; /* 0x02 */
2142 U8 Threshold75Pct; /* 0x04 */
2143 U8 Threshold50Pct; /* 0x05 */
2144 U8 Threshold25Pct; /* 0x06 */
2145 U8 Reserved3; /* 0x07 */
2146} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2147 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2148 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2149 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2150
2151/* defines for Flags field */
2152#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2153
2154
2155/*
2156 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2157 * one and check the value returned for NumGroups at runtime.
2158 */
2159#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2160#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2161#endif
2162
2163typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2164 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2165 U8 SamplingInterval; /* 0x08 */
2166 U8 WindowLength; /* 0x09 */
2167 U16 Reserved1; /* 0x0A */
2168 U32 Reserved2; /* 0x0C */
2169 U32 Reserved3; /* 0x10 */
2170 U8 NumGroups; /* 0x14 */
2171 U8 Reserved4; /* 0x15 */
2172 U16 Reserved5; /* 0x16 */
2173 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2174 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2175} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2176 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2177 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2178
2179#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2180
2181
2182/* SAS IO Unit Page 8 */
2183
2184typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2185 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2186 U32 Reserved1; /* 0x08 */
2187 U32 PowerManagementCapabilities;/* 0x0C */
2188 U32 Reserved2; /* 0x10 */
2189} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2190 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2191 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2192
2193#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2194
2195/* defines for PowerManagementCapabilities field */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]2196#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2197#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2198#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2199#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2200#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2201#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2202#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2203#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2204#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2205#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2206
2207
2208
2209
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2210/****************************************************************************
2211* SAS Expander Config Pages
2212****************************************************************************/
2213
2214/* SAS Expander Page 0 */
2215
2216typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2217{
2218 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2219 U8 PhysicalPort; /* 0x08 */
2220 U8 ReportGenLength; /* 0x09 */
2221 U16 EnclosureHandle; /* 0x0A */
2222 U64 SASAddress; /* 0x0C */
2223 U32 DiscoveryStatus; /* 0x14 */
2224 U16 DevHandle; /* 0x18 */
2225 U16 ParentDevHandle; /* 0x1A */
2226 U16 ExpanderChangeCount; /* 0x1C */
2227 U16 ExpanderRouteIndexes; /* 0x1E */
2228 U8 NumPhys; /* 0x20 */
2229 U8 SASLevel; /* 0x21 */
2230 U16 Flags; /* 0x22 */
2231 U16 STPBusInactivityTimeLimit; /* 0x24 */
2232 U16 STPMaxConnectTimeLimit; /* 0x26 */
2233 U16 STP_SMP_NexusLossTime; /* 0x28 */
2234 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2235 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2236 U16 ZoneLockInactivityLimit; /* 0x34 */
2237 U16 Reserved1; /* 0x36 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2238 U8 TimeToReducedFunc; /* 0x38 */
2239 U8 InitialTimeToReducedFunc; /* 0x39 */
2240 U8 MaxReducedFuncTime; /* 0x3A */
2241 U8 Reserved2; /* 0x3B */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2242} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2243 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2244
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2245#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2246
2247/* values for SAS Expander Page 0 DiscoveryStatus field */
2248#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2249#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2250#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2251#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2252#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2253#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2254#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2255#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2256#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2257#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2258#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2259#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2260#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2261#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2262#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2263#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2264#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2265#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2266#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2267#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2268
2269/* values for SAS Expander Page 0 Flags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2270#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2271#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2272#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2273#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2274#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2275#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2276#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2277#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2278#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2279#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2280#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2281
2282
2283/* SAS Expander Page 1 */
2284
2285typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2286{
2287 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2288 U8 PhysicalPort; /* 0x08 */
2289 U8 Reserved1; /* 0x09 */
2290 U16 Reserved2; /* 0x0A */
2291 U8 NumPhys; /* 0x0C */
2292 U8 Phy; /* 0x0D */
2293 U16 NumTableEntriesProgrammed; /* 0x0E */
2294 U8 ProgrammedLinkRate; /* 0x10 */
2295 U8 HwLinkRate; /* 0x11 */
2296 U16 AttachedDevHandle; /* 0x12 */
2297 U32 PhyInfo; /* 0x14 */
2298 U32 AttachedDeviceInfo; /* 0x18 */
2299 U16 ExpanderDevHandle; /* 0x1C */
2300 U8 ChangeCount; /* 0x1E */
2301 U8 NegotiatedLinkRate; /* 0x1F */
2302 U8 PhyIdentifier; /* 0x20 */
2303 U8 AttachedPhyIdentifier; /* 0x21 */
2304 U8 Reserved3; /* 0x22 */
2305 U8 DiscoveryInfo; /* 0x23 */
2306 U32 AttachedPhyInfo; /* 0x24 */
2307 U8 ZoneGroup; /* 0x28 */
2308 U8 SelfConfigStatus; /* 0x29 */
2309 U16 Reserved4; /* 0x2A */
2310} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2311 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2312
2313#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2314
2315/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2316
2317/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2318
2319/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2320
2321/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2322
2323/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2324
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2325/* values for SAS Expander Page 1 DiscoveryInfo field */
2326#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2327#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2328#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2329
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]2330/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2331
2332/****************************************************************************
2333* SAS Device Config Pages
2334****************************************************************************/
2335
2336/* SAS Device Page 0 */
2337
2338typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2339{
2340 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2341 U16 Slot; /* 0x08 */
2342 U16 EnclosureHandle; /* 0x0A */
2343 U64 SASAddress; /* 0x0C */
2344 U16 ParentDevHandle; /* 0x14 */
2345 U8 PhyNum; /* 0x16 */
2346 U8 AccessStatus; /* 0x17 */
2347 U16 DevHandle; /* 0x18 */
2348 U8 AttachedPhyIdentifier; /* 0x1A */
2349 U8 ZoneGroup; /* 0x1B */
2350 U32 DeviceInfo; /* 0x1C */
2351 U16 Flags; /* 0x20 */
2352 U8 PhysicalPort; /* 0x22 */
2353 U8 MaxPortConnections; /* 0x23 */
2354 U64 DeviceName; /* 0x24 */
2355 U8 PortGroups; /* 0x2C */
2356 U8 DmaGroup; /* 0x2D */
2357 U8 ControlGroup; /* 0x2E */
2358 U8 Reserved1; /* 0x2F */
2359 U32 Reserved2; /* 0x30 */
2360 U32 Reserved3; /* 0x34 */
2361} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2362 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2363
2364#define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2365
2366/* values for SAS Device Page 0 AccessStatus field */
2367#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2368#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2369#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2370#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2371#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2372#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2373#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2374#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2375/* specific values for SATA Init failures */
2376#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2377#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2378#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2379#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2380#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2381#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2382#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2383#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2384#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2385#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2386#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2387
2388/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2389
2390/* values for SAS Device Page 0 Flags field */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]2391#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2392#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2393#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2394#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2395#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2396#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2397#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2398#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2399#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2400#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2401#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2402#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2403
2404
2405/* SAS Device Page 1 */
2406
2407typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2408{
2409 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2410 U32 Reserved1; /* 0x08 */
2411 U64 SASAddress; /* 0x0C */
2412 U32 Reserved2; /* 0x14 */
2413 U16 DevHandle; /* 0x18 */
2414 U16 Reserved3; /* 0x1A */
2415 U8 InitialRegDeviceFIS[20];/* 0x1C */
2416} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2417 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2418
2419#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2420
2421
2422/****************************************************************************
2423* SAS PHY Config Pages
2424****************************************************************************/
2425
2426/* SAS PHY Page 0 */
2427
2428typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2429{
2430 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2431 U16 OwnerDevHandle; /* 0x08 */
2432 U16 Reserved1; /* 0x0A */
2433 U16 AttachedDevHandle; /* 0x0C */
2434 U8 AttachedPhyIdentifier; /* 0x0E */
2435 U8 Reserved2; /* 0x0F */
2436 U32 AttachedPhyInfo; /* 0x10 */
2437 U8 ProgrammedLinkRate; /* 0x14 */
2438 U8 HwLinkRate; /* 0x15 */
2439 U8 ChangeCount; /* 0x16 */
2440 U8 Flags; /* 0x17 */
2441 U32 PhyInfo; /* 0x18 */
2442 U8 NegotiatedLinkRate; /* 0x1C */
2443 U8 Reserved3; /* 0x1D */
2444 U16 Reserved4; /* 0x1E */
2445} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2446 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2447
2448#define MPI2_SASPHY0_PAGEVERSION (0x03)
2449
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]2450/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2451
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2452/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2453
2454/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2455
2456/* values for SAS PHY Page 0 Flags field */
2457#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2458
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]2459/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2460
2461/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2462
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2463
2464/* SAS PHY Page 1 */
2465
2466typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2467{
2468 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2469 U32 Reserved1; /* 0x08 */
2470 U32 InvalidDwordCount; /* 0x0C */
2471 U32 RunningDisparityErrorCount; /* 0x10 */
2472 U32 LossDwordSynchCount; /* 0x14 */
2473 U32 PhyResetProblemCount; /* 0x18 */
2474} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2475 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2476
2477#define MPI2_SASPHY1_PAGEVERSION (0x01)
2478
2479
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2480/* SAS PHY Page 2 */
2481
2482typedef struct _MPI2_SASPHY2_PHY_EVENT {
2483 U8 PhyEventCode; /* 0x00 */
2484 U8 Reserved1; /* 0x01 */
2485 U16 Reserved2; /* 0x02 */
2486 U32 PhyEventInfo; /* 0x04 */
2487} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2488 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2489
2490/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2491
2492
2493/*
2494 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2495 * one and check the value returned for NumPhyEvents at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2496 */
2497#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2498#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2499#endif
2500
2501typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2502 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2503 U32 Reserved1; /* 0x08 */
2504 U8 NumPhyEvents; /* 0x0C */
2505 U8 Reserved2; /* 0x0D */
2506 U16 Reserved3; /* 0x0E */
2507 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2508 /* 0x10 */
2509} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2510 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2511
2512#define MPI2_SASPHY2_PAGEVERSION (0x00)
2513
2514
2515/* SAS PHY Page 3 */
2516
2517typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2518 U8 PhyEventCode; /* 0x00 */
2519 U8 Reserved1; /* 0x01 */
2520 U16 Reserved2; /* 0x02 */
2521 U8 CounterType; /* 0x04 */
2522 U8 ThresholdWindow; /* 0x05 */
2523 U8 TimeUnits; /* 0x06 */
2524 U8 Reserved3; /* 0x07 */
2525 U32 EventThreshold; /* 0x08 */
2526 U16 ThresholdFlags; /* 0x0C */
2527 U16 Reserved4; /* 0x0E */
2528} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2529 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2530
2531/* values for PhyEventCode field */
2532#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2533#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2534#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2535#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2536#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2537#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2538#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2539#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2540#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2541#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2542#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2543#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2544#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2545#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2546#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2547#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2548#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2549#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2550#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2551#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2552#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2553#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2554#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2555#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2556#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2557#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2558#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2559#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2560#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2561#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2562#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2563#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2564#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2565#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2566#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2567#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2568#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2569
2570/* values for the CounterType field */
2571#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2572#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2573#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2574
2575/* values for the TimeUnits field */
2576#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2577#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2578#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2579#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2580
2581/* values for the ThresholdFlags field */
2582#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2583#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2584
2585/*
2586 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2587 * one and check the value returned for NumPhyEvents at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2588 */
2589#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2590#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2591#endif
2592
2593typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2594 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2595 U32 Reserved1; /* 0x08 */
2596 U8 NumPhyEvents; /* 0x0C */
2597 U8 Reserved2; /* 0x0D */
2598 U16 Reserved3; /* 0x0E */
2599 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2600 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2601} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2602 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2603
2604#define MPI2_SASPHY3_PAGEVERSION (0x00)
2605
2606
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]2607/* SAS PHY Page 4 */
2608
2609typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2610 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2611 U16 Reserved1; /* 0x08 */
2612 U8 Reserved2; /* 0x0A */
2613 U8 Flags; /* 0x0B */
2614 U8 InitialFrame[28]; /* 0x0C */
2615} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2616 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2617
2618#define MPI2_SASPHY4_PAGEVERSION (0x00)
2619
2620/* values for the Flags field */
2621#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2622#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2623
2624
2625
2626
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2627/****************************************************************************
2628* SAS Port Config Pages
2629****************************************************************************/
2630
2631/* SAS Port Page 0 */
2632
2633typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2634{
2635 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2636 U8 PortNumber; /* 0x08 */
2637 U8 PhysicalPort; /* 0x09 */
2638 U8 PortWidth; /* 0x0A */
2639 U8 PhysicalPortWidth; /* 0x0B */
2640 U8 ZoneGroup; /* 0x0C */
2641 U8 Reserved1; /* 0x0D */
2642 U16 Reserved2; /* 0x0E */
2643 U64 SASAddress; /* 0x10 */
2644 U32 DeviceInfo; /* 0x18 */
2645 U32 Reserved3; /* 0x1C */
2646 U32 Reserved4; /* 0x20 */
2647} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2648 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2649
2650#define MPI2_SASPORT0_PAGEVERSION (0x00)
2651
2652/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2653
2654
2655/****************************************************************************
2656* SAS Enclosure Config Pages
2657****************************************************************************/
2658
2659/* SAS Enclosure Page 0 */
2660
2661typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2662{
2663 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2664 U32 Reserved1; /* 0x08 */
2665 U64 EnclosureLogicalID; /* 0x0C */
2666 U16 Flags; /* 0x14 */
2667 U16 EnclosureHandle; /* 0x16 */
2668 U16 NumSlots; /* 0x18 */
2669 U16 StartSlot; /* 0x1A */
2670 U16 Reserved2; /* 0x1C */
2671 U16 SEPDevHandle; /* 0x1E */
2672 U32 Reserved3; /* 0x20 */
2673 U32 Reserved4; /* 0x24 */
2674} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2675 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2676 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2677
2678#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2679
2680/* values for SAS Enclosure Page 0 Flags field */
2681#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2682#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2683#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2684#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2685#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2686#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2687#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2688
2689
2690/****************************************************************************
2691* Log Config Page
2692****************************************************************************/
2693
2694/* Log Page 0 */
2695
2696/*
2697 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2698 * one and check the value returned for NumLogEntries at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2699 */
2700#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2701#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2702#endif
2703
2704#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2705
2706typedef struct _MPI2_LOG_0_ENTRY
2707{
2708 U64 TimeStamp; /* 0x00 */
2709 U32 Reserved1; /* 0x08 */
2710 U16 LogSequence; /* 0x0C */
2711 U16 LogEntryQualifier; /* 0x0E */
2712 U8 VP_ID; /* 0x10 */
2713 U8 VF_ID; /* 0x11 */
2714 U16 Reserved2; /* 0x12 */
2715 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2716} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2717 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2718
2719/* values for Log Page 0 LogEntry LogEntryQualifier field */
2720#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2721#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2722#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2723#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2724#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2725
2726typedef struct _MPI2_CONFIG_PAGE_LOG_0
2727{
2728 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2729 U32 Reserved1; /* 0x08 */
2730 U32 Reserved2; /* 0x0C */
2731 U16 NumLogEntries; /* 0x10 */
2732 U16 Reserved3; /* 0x12 */
2733 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2734} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2735 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2736
2737#define MPI2_LOG_0_PAGEVERSION (0x02)
2738
2739
2740/****************************************************************************
2741* RAID Config Page
2742****************************************************************************/
2743
2744/* RAID Page 0 */
2745
2746/*
2747 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2748 * one and check the value returned for NumElements at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2749 */
2750#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2751#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2752#endif
2753
2754typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2755{
2756 U16 ElementFlags; /* 0x00 */
2757 U16 VolDevHandle; /* 0x02 */
2758 U8 HotSparePool; /* 0x04 */
2759 U8 PhysDiskNum; /* 0x05 */
2760 U16 PhysDiskDevHandle; /* 0x06 */
2761} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2762 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2763 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2764
2765/* values for the ElementFlags field */
2766#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2767#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2768#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2769#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2770#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2771
2772
2773typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2774{
2775 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2776 U8 NumHotSpares; /* 0x08 */
2777 U8 NumPhysDisks; /* 0x09 */
2778 U8 NumVolumes; /* 0x0A */
2779 U8 ConfigNum; /* 0x0B */
2780 U32 Flags; /* 0x0C */
2781 U8 ConfigGUID[24]; /* 0x10 */
2782 U32 Reserved1; /* 0x28 */
2783 U8 NumElements; /* 0x2C */
2784 U8 Reserved2; /* 0x2D */
2785 U16 Reserved3; /* 0x2E */
2786 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2787} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2788 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2789 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2790
2791#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2792
2793/* values for RAID Configuration Page 0 Flags field */
2794#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2795
2796
2797/****************************************************************************
2798* Driver Persistent Mapping Config Pages
2799****************************************************************************/
2800
2801/* Driver Persistent Mapping Page 0 */
2802
2803typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2804{
2805 U64 PhysicalIdentifier; /* 0x00 */
2806 U16 MappingInformation; /* 0x08 */
2807 U16 DeviceIndex; /* 0x0A */
2808 U32 PhysicalBitsMapping; /* 0x0C */
2809 U32 Reserved1; /* 0x10 */
2810} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2811 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2812 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2813
2814typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2815{
2816 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2817 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2818} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2819 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2820 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2821
2822#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2823
2824/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2825#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2826#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2827#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2828
2829
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2830/****************************************************************************
2831* Ethernet Config Pages
2832****************************************************************************/
2833
2834/* Ethernet Page 0 */
2835
2836/* IP address (union of IPv4 and IPv6) */
2837typedef union _MPI2_ETHERNET_IP_ADDR {
2838 U32 IPv4Addr;
2839 U32 IPv6Addr[4];
2840} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2841 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2842
2843#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2844
2845typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2846 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2847 U8 NumInterfaces; /* 0x08 */
2848 U8 Reserved0; /* 0x09 */
2849 U16 Reserved1; /* 0x0A */
2850 U32 Status; /* 0x0C */
2851 U8 MediaState; /* 0x10 */
2852 U8 Reserved2; /* 0x11 */
2853 U16 Reserved3; /* 0x12 */
2854 U8 MacAddress[6]; /* 0x14 */
2855 U8 Reserved4; /* 0x1A */
2856 U8 Reserved5; /* 0x1B */
2857 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2858 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2859 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2860 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2861 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2862 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2863 U8 HostName
2864 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2865} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2866 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2867
2868#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2869
2870/* values for Ethernet Page 0 Status field */
2871#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2872#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2873#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2874#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2875#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2876#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2877#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2878#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2879#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2880#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2881#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2882#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2883
2884/* values for Ethernet Page 0 MediaState field */
2885#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2886#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2887#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2888
2889#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2890#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2891#define MPI2_ETHPG0_MS_10MBIT (0x01)
2892#define MPI2_ETHPG0_MS_100MBIT (0x02)
2893#define MPI2_ETHPG0_MS_1GBIT (0x03)
2894
2895
2896/* Ethernet Page 1 */
2897
2898typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2899 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2900 U32 Reserved0; /* 0x08 */
2901 U32 Flags; /* 0x0C */
2902 U8 MediaState; /* 0x10 */
2903 U8 Reserved1; /* 0x11 */
2904 U16 Reserved2; /* 0x12 */
2905 U8 MacAddress[6]; /* 0x14 */
2906 U8 Reserved3; /* 0x1A */
2907 U8 Reserved4; /* 0x1B */
2908 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2909 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2910 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2911 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2912 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2913 U32 Reserved5; /* 0x6C */
2914 U32 Reserved6; /* 0x70 */
2915 U32 Reserved7; /* 0x74 */
2916 U32 Reserved8; /* 0x78 */
2917 U8 HostName
2918 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2919} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2920 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2921
2922#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2923
2924/* values for Ethernet Page 1 Flags field */
2925#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2926#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2927#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2928#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2929#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2930#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2931#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2932#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2933#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2934
2935/* values for Ethernet Page 1 MediaState field */
2936#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2937#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2938#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2939
2940#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2941#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2942#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2943#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2944#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2945
2946
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]2947/****************************************************************************
2948* Extended Manufacturing Config Pages
2949****************************************************************************/
2950
2951/*
2952 * Generic structure to use for product-specific extended manufacturing pages
2953 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2954 * Page 60).
2955 */
2956
2957typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
2958 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2959 U32 ProductSpecificInfo; /* 0x08 */
2960} MPI2_CONFIG_PAGE_EXT_MAN_PS,
2961 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2962 Mpi2ExtManufacturingPagePS_t,
2963 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2964
2965/* PageVersion should be provided by product-specific code */
2966
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2967#endif
2968