blob: 7fc06bd3021aecce50598b1db52fc4b3a05e2ca6 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053019#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080021
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <linux/input/pmic8058-keypad.h>
23#include <linux/pmic8058-batt-alarm.h>
24#include <linux/pmic8058-pwrkey.h>
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +053025#include <linux/rtc/rtc-pm8058.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070026#include <linux/pmic8058-vibrator.h>
27#include <linux/leds.h>
28#include <linux/pmic8058-othc.h>
29#include <linux/mfd/pmic8901.h>
30#include <linux/regulator/pmic8058-regulator.h>
31#include <linux/regulator/pmic8901-regulator.h>
32#include <linux/bootmem.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/leds-pmic8058.h>
36#include <linux/pmic8058-xoadc.h>
37#include <linux/msm_adc.h>
38#include <linux/m_adcproc.h>
39#include <linux/mfd/marimba.h>
40#include <linux/msm-charger.h>
41#include <linux/i2c.h>
42#include <linux/i2c/sx150x.h>
43#include <linux/smsc911x.h>
44#include <linux/spi/spi.h>
45#include <linux/input/tdisc_shinetsu.h>
46#include <linux/input/cy8c_ts.h>
47#include <linux/cyttsp.h>
48#include <linux/i2c/isa1200.h>
49#include <linux/dma-mapping.h>
50#include <linux/i2c/bq27520.h>
51
52#ifdef CONFIG_ANDROID_PMEM
53#include <linux/android_pmem.h>
54#endif
55
56#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
57#include <linux/i2c/smb137b.h>
58#endif
Lei Zhou338cab82011-08-19 13:38:17 -040059#ifdef CONFIG_SND_SOC_WM8903
60#include <sound/wm8903.h>
61#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080062#include <asm/mach-types.h>
63#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080065
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#include <mach/dma.h>
67#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080068#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#include <mach/irqs.h>
70#include <mach/msm_spi.h>
71#include <mach/msm_serial_hs.h>
72#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080073#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#include <mach/msm_memtypes.h>
75#include <asm/mach/mmc.h>
76#include <mach/msm_battery.h>
77#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070078#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070079#ifdef CONFIG_MSM_DSPS
80#include <mach/msm_dsps.h>
81#endif
82#include <mach/msm_xo.h>
83#include <mach/msm_bus_board.h>
84#include <mach/socinfo.h>
85#include <linux/i2c/isl9519.h>
86#ifdef CONFIG_USB_G_ANDROID
87#include <linux/usb/android.h>
88#include <mach/usbdiag.h>
89#endif
90#include <linux/regulator/consumer.h>
91#include <linux/regulator/machine.h>
92#include <mach/sdio_al.h>
93#include <mach/rpm.h>
94#include <mach/rpm-regulator.h>
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070095#include <mach/restart.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080096
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070097#include "devices.h"
98#include "devices-msm8x60.h"
99#include "cpuidle.h"
100#include "pm.h"
101#include "mpm.h"
102#include "spm.h"
103#include "rpm_log.h"
104#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700105#include "gpiomux-8x60.h"
106#include "rpm_stats.h"
107#include "peripheral-loader.h"
108#include <linux/platform_data/qcom_crypto_device.h>
109#include "rpm_resources.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -0700110#include "acpuclock.h"
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -0600111#include "pm-boot.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700112#define MSM_SHARED_RAM_PHYS 0x40000000
113
114/* Macros assume PMIC GPIOs start at 0 */
115#define PM8058_GPIO_BASE NR_MSM_GPIOS
116#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
117#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
118#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
119#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
120#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
121#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
122
123#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
124 PM8058_GPIOS + PM8058_MPPS)
125#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
126#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
127#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
128 NR_PMIC8058_IRQS)
129
130#define MDM2AP_SYNC 129
131
Terence Hampson1c73fef2011-07-19 17:10:49 -0400132#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700133#define LCDC_SPI_GPIO_CLK 73
134#define LCDC_SPI_GPIO_CS 72
135#define LCDC_SPI_GPIO_MOSI 70
136#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
137#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
138#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
139#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
140#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400141#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -0700143#define PANEL_NAME_MAX_LEN 30
144#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
145#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
146#define MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME "mipi_video_toshiba_wvga"
147#define HDMI_PANEL_NAME "hdmi_msm"
148#define TVOUT_PANEL_NAME "tvout_msm"
149
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150#define DSPS_PIL_GENERIC_NAME "dsps"
151#define DSPS_PIL_FLUID_NAME "dsps_fluid"
152
153enum {
154 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
155 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
156 /* CORE expander */
157 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
158 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
159 GPIO_WLAN_DEEP_SLEEP_N,
160 GPIO_LVDS_SHUTDOWN_N,
161 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
162 GPIO_MS_SYS_RESET_N,
163 GPIO_CAP_TS_RESOUT_N,
164 GPIO_CAP_GAUGE_BI_TOUT,
165 GPIO_ETHERNET_PME,
166 GPIO_EXT_GPS_LNA_EN,
167 GPIO_MSM_WAKES_BT,
168 GPIO_ETHERNET_RESET_N,
169 GPIO_HEADSET_DET_N,
170 GPIO_USB_UICC_EN,
171 GPIO_BACKLIGHT_EN,
172 GPIO_EXT_CAMIF_PWR_EN,
173 GPIO_BATT_GAUGE_INT_N,
174 GPIO_BATT_GAUGE_EN,
175 /* DOCKING expander */
176 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
177 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
178 GPIO_AUX_JTAG_DET_N,
179 GPIO_DONGLE_DET_N,
180 GPIO_SVIDEO_LOAD_DET,
181 GPIO_SVID_AMP_SHUTDOWN1_N,
182 GPIO_SVID_AMP_SHUTDOWN0_N,
183 GPIO_SDC_WP,
184 GPIO_IRDA_PWDN,
185 GPIO_IRDA_RESET_N,
186 GPIO_DONGLE_GPIO0,
187 GPIO_DONGLE_GPIO1,
188 GPIO_DONGLE_GPIO2,
189 GPIO_DONGLE_GPIO3,
190 GPIO_DONGLE_PWR_EN,
191 GPIO_EMMC_RESET_N,
192 GPIO_TP_EXP2_IO15,
193 /* SURF expander */
194 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
195 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
196 GPIO_SD_CARD_DET_2,
197 GPIO_SD_CARD_DET_4,
198 GPIO_SD_CARD_DET_5,
199 GPIO_UIM3_RST,
200 GPIO_SURF_EXPANDER_IO5,
201 GPIO_SURF_EXPANDER_IO6,
202 GPIO_ADC_I2C_EN,
203 GPIO_SURF_EXPANDER_IO8,
204 GPIO_SURF_EXPANDER_IO9,
205 GPIO_SURF_EXPANDER_IO10,
206 GPIO_SURF_EXPANDER_IO11,
207 GPIO_SURF_EXPANDER_IO12,
208 GPIO_SURF_EXPANDER_IO13,
209 GPIO_SURF_EXPANDER_IO14,
210 GPIO_SURF_EXPANDER_IO15,
211 /* LEFT KB IO expander */
212 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
213 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
214 GPIO_LEFT_LED_2,
215 GPIO_LEFT_LED_3,
216 GPIO_LEFT_LED_WLAN,
217 GPIO_JOYSTICK_EN,
218 GPIO_CAP_TS_SLEEP,
219 GPIO_LEFT_KB_IO6,
220 GPIO_LEFT_LED_5,
221 /* RIGHT KB IO expander */
222 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
223 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
224 GPIO_RIGHT_LED_2,
225 GPIO_RIGHT_LED_3,
226 GPIO_RIGHT_LED_BT,
227 GPIO_WEB_CAMIF_STANDBY,
228 GPIO_COMPASS_RST_N,
229 GPIO_WEB_CAMIF_RESET_N,
230 GPIO_RIGHT_LED_5,
231 GPIO_R_ALTIMETER_RESET_N,
232 /* FLUID S IO expander */
233 GPIO_SOUTH_EXPANDER_BASE,
234 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
235 GPIO_MIC1_ANCL_SEL,
236 GPIO_HS_MIC4_SEL,
237 GPIO_FML_MIC3_SEL,
238 GPIO_FMR_MIC5_SEL,
239 GPIO_TS_SLEEP,
240 GPIO_HAP_SHIFT_LVL_OE,
241 GPIO_HS_SW_DIR,
242 /* FLUID N IO expander */
243 GPIO_NORTH_EXPANDER_BASE,
244 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
245 GPIO_EPM_5V_BOOST_EN,
246 GPIO_AUX_CAM_2P7_EN,
247 GPIO_LED_FLASH_EN,
248 GPIO_LED1_GREEN_N,
249 GPIO_LED2_RED_N,
250 GPIO_FRONT_CAM_RESET_N,
251 GPIO_EPM_LVLSFT_EN,
252 GPIO_N_ALTIMETER_RESET_N,
253 /* EPM expander */
254 GPIO_EPM_EXPANDER_BASE,
255 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
256 GPIO_PWR_MON_RESET_N,
257 GPIO_ADC1_PWDN_N,
258 GPIO_ADC2_PWDN_N,
259 GPIO_EPM_EXPANDER_IO4,
260 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
261 GPIO_ADC2_MUX_SPI_INT_N,
262 GPIO_EPM_EXPANDER_IO7,
263 GPIO_PWR_MON_ENABLE,
264 GPIO_EPM_SPI_ADC1_CS_N,
265 GPIO_EPM_SPI_ADC2_CS_N,
266 GPIO_EPM_EXPANDER_IO11,
267 GPIO_EPM_EXPANDER_IO12,
268 GPIO_EPM_EXPANDER_IO13,
269 GPIO_EPM_EXPANDER_IO14,
270 GPIO_EPM_EXPANDER_IO15,
271};
272
273/*
274 * The UI_INTx_N lines are pmic gpio lines which connect i2c
275 * gpio expanders to the pm8058.
276 */
277#define UI_INT1_N 25
278#define UI_INT2_N 34
279#define UI_INT3_N 14
280/*
281FM GPIO is GPIO 18 on PMIC 8058.
282As the index starts from 0 in the PMIC driver, and hence 17
283corresponds to GPIO 18 on PMIC 8058.
284*/
285#define FM_GPIO 17
286
287#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
288static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
289static void *sdc2_status_notify_cb_devid;
290#endif
291
292#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
293static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
294static void *sdc5_status_notify_cb_devid;
295#endif
296
297static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
298 [0] = {
299 .reg_base_addr = MSM_SAW0_BASE,
300
301#ifdef CONFIG_MSM_AVS_HW
302 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
303#endif
304 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
305 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
306 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
307 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
308
309 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
310 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
311 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
312
313 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
314 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
315 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
316
317 .awake_vlevel = 0x94,
318 .retention_vlevel = 0x81,
319 .collapse_vlevel = 0x20,
320 .retention_mid_vlevel = 0x94,
321 .collapse_mid_vlevel = 0x8C,
322
323 .vctl_timeout_us = 50,
324 },
325
326 [1] = {
327 .reg_base_addr = MSM_SAW1_BASE,
328
329#ifdef CONFIG_MSM_AVS_HW
330 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
331#endif
332 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
333 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
334 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
335 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
336
337 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
338 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
339 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
340
341 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
342 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
343 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
344
345 .awake_vlevel = 0x94,
346 .retention_vlevel = 0x81,
347 .collapse_vlevel = 0x20,
348 .retention_mid_vlevel = 0x94,
349 .collapse_mid_vlevel = 0x8C,
350
351 .vctl_timeout_us = 50,
352 },
353};
354
355static struct msm_spm_platform_data msm_spm_data[] __initdata = {
356 [0] = {
357 .reg_base_addr = MSM_SAW0_BASE,
358
359#ifdef CONFIG_MSM_AVS_HW
360 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
361#endif
362 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
363 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
364 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
365 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
366
367 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
368 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
369 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
370
371 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
372 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
373 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
374
375 .awake_vlevel = 0xA0,
376 .retention_vlevel = 0x89,
377 .collapse_vlevel = 0x20,
378 .retention_mid_vlevel = 0x89,
379 .collapse_mid_vlevel = 0x89,
380
381 .vctl_timeout_us = 50,
382 },
383
384 [1] = {
385 .reg_base_addr = MSM_SAW1_BASE,
386
387#ifdef CONFIG_MSM_AVS_HW
388 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
389#endif
390 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
391 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
392 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
393 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
394
395 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
396 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
397 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
398
399 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
400 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
401 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
402
403 .awake_vlevel = 0xA0,
404 .retention_vlevel = 0x89,
405 .collapse_vlevel = 0x20,
406 .retention_mid_vlevel = 0x89,
407 .collapse_mid_vlevel = 0x89,
408
409 .vctl_timeout_us = 50,
410 },
411};
412
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700413/*
414 * Consumer specific regulator names:
415 * regulator name consumer dev_name
416 */
417static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
418 REGULATOR_SUPPLY("8901_s0", NULL),
419};
420static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
421 REGULATOR_SUPPLY("8901_s1", NULL),
422};
423
424static struct regulator_init_data saw_s0_init_data = {
425 .constraints = {
426 .name = "8901_s0",
427 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700428 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700429 .max_uV = 1250000,
430 },
431 .consumer_supplies = vreg_consumers_8901_S0,
432 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
433};
434
435static struct regulator_init_data saw_s1_init_data = {
436 .constraints = {
437 .name = "8901_s1",
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700439 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700440 .max_uV = 1250000,
441 },
442 .consumer_supplies = vreg_consumers_8901_S1,
443 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
444};
445
446static struct platform_device msm_device_saw_s0 = {
447 .name = "saw-regulator",
448 .id = 0,
449 .dev = {
450 .platform_data = &saw_s0_init_data,
451 },
452};
453
454static struct platform_device msm_device_saw_s1 = {
455 .name = "saw-regulator",
456 .id = 1,
457 .dev = {
458 .platform_data = &saw_s1_init_data,
459 },
460};
461
462/*
463 * The smc91x configuration varies depending on platform.
464 * The resources data structure is filled in at runtime.
465 */
466static struct resource smc91x_resources[] = {
467 [0] = {
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device smc91x_device = {
476 .name = "smc91x",
477 .id = 0,
478 .num_resources = ARRAY_SIZE(smc91x_resources),
479 .resource = smc91x_resources,
480};
481
482static struct resource smsc911x_resources[] = {
483 [0] = {
484 .flags = IORESOURCE_MEM,
485 .start = 0x1b800000,
486 .end = 0x1b8000ff
487 },
488 [1] = {
489 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
490 },
491};
492
493static struct smsc911x_platform_config smsc911x_config = {
494 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
495 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
496 .flags = SMSC911X_USE_16BIT,
497 .has_reset_gpio = 1,
498 .reset_gpio = GPIO_ETHERNET_RESET_N
499};
500
501static struct platform_device smsc911x_device = {
502 .name = "smsc911x",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(smsc911x_resources),
505 .resource = smsc911x_resources,
506 .dev = {
507 .platform_data = &smsc911x_config
508 }
509};
510
511#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
512 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
513 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
514 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
515
516#define QCE_SIZE 0x10000
517#define QCE_0_BASE 0x18500000
518
519#define QCE_HW_KEY_SUPPORT 0
520#define QCE_SHA_HMAC_SUPPORT 0
521#define QCE_SHARE_CE_RESOURCE 2
522#define QCE_CE_SHARED 1
523
524static struct resource qcrypto_resources[] = {
525 [0] = {
526 .start = QCE_0_BASE,
527 .end = QCE_0_BASE + QCE_SIZE - 1,
528 .flags = IORESOURCE_MEM,
529 },
530 [1] = {
531 .name = "crypto_channels",
532 .start = DMOV_CE_IN_CHAN,
533 .end = DMOV_CE_OUT_CHAN,
534 .flags = IORESOURCE_DMA,
535 },
536 [2] = {
537 .name = "crypto_crci_in",
538 .start = DMOV_CE_IN_CRCI,
539 .end = DMOV_CE_IN_CRCI,
540 .flags = IORESOURCE_DMA,
541 },
542 [3] = {
543 .name = "crypto_crci_out",
544 .start = DMOV_CE_OUT_CRCI,
545 .end = DMOV_CE_OUT_CRCI,
546 .flags = IORESOURCE_DMA,
547 },
548 [4] = {
549 .name = "crypto_crci_hash",
550 .start = DMOV_CE_HASH_CRCI,
551 .end = DMOV_CE_HASH_CRCI,
552 .flags = IORESOURCE_DMA,
553 },
554};
555
556static struct resource qcedev_resources[] = {
557 [0] = {
558 .start = QCE_0_BASE,
559 .end = QCE_0_BASE + QCE_SIZE - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .name = "crypto_channels",
564 .start = DMOV_CE_IN_CHAN,
565 .end = DMOV_CE_OUT_CHAN,
566 .flags = IORESOURCE_DMA,
567 },
568 [2] = {
569 .name = "crypto_crci_in",
570 .start = DMOV_CE_IN_CRCI,
571 .end = DMOV_CE_IN_CRCI,
572 .flags = IORESOURCE_DMA,
573 },
574 [3] = {
575 .name = "crypto_crci_out",
576 .start = DMOV_CE_OUT_CRCI,
577 .end = DMOV_CE_OUT_CRCI,
578 .flags = IORESOURCE_DMA,
579 },
580 [4] = {
581 .name = "crypto_crci_hash",
582 .start = DMOV_CE_HASH_CRCI,
583 .end = DMOV_CE_HASH_CRCI,
584 .flags = IORESOURCE_DMA,
585 },
586};
587
588#endif
589
590#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
591 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
592
593static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
594 .ce_shared = QCE_CE_SHARED,
595 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
596 .hw_key_support = QCE_HW_KEY_SUPPORT,
597 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
598};
599
600static struct platform_device qcrypto_device = {
601 .name = "qcrypto",
602 .id = 0,
603 .num_resources = ARRAY_SIZE(qcrypto_resources),
604 .resource = qcrypto_resources,
605 .dev = {
606 .coherent_dma_mask = DMA_BIT_MASK(32),
607 .platform_data = &qcrypto_ce_hw_suppport,
608 },
609};
610#endif
611
612#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
613 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
614
615static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
616 .ce_shared = QCE_CE_SHARED,
617 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
618 .hw_key_support = QCE_HW_KEY_SUPPORT,
619 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
620};
621
622static struct platform_device qcedev_device = {
623 .name = "qce",
624 .id = 0,
625 .num_resources = ARRAY_SIZE(qcedev_resources),
626 .resource = qcedev_resources,
627 .dev = {
628 .coherent_dma_mask = DMA_BIT_MASK(32),
629 .platform_data = &qcedev_ce_hw_suppport,
630 },
631};
632#endif
633
634#if defined(CONFIG_HAPTIC_ISA1200) || \
635 defined(CONFIG_HAPTIC_ISA1200_MODULE)
636
637static const char *vregs_isa1200_name[] = {
638 "8058_s3",
639 "8901_l4",
640};
641
642static const int vregs_isa1200_val[] = {
643 1800000,/* uV */
644 2600000,
645};
646static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
647static struct msm_xo_voter *xo_handle_a1;
648
649static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800650{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700651 int i, rc = 0;
652
653 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
654 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
655 regulator_disable(vregs_isa1200[i]);
656 if (rc < 0) {
657 pr_err("%s: vreg %s %s failed (%d)\n",
658 __func__, vregs_isa1200_name[i],
659 vreg_on ? "enable" : "disable", rc);
660 goto vreg_fail;
661 }
662 }
663
664 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
665 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
666 if (rc < 0) {
667 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
668 __func__, vreg_on ? "" : "de-", rc);
669 goto vreg_fail;
670 }
671 return 0;
672
673vreg_fail:
674 while (i--)
675 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
676 regulator_disable(vregs_isa1200[i]);
677 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800678}
679
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700680static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800681{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700682 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800683
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700684 if (enable == true) {
685 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
686 vregs_isa1200[i] = regulator_get(NULL,
687 vregs_isa1200_name[i]);
688 if (IS_ERR(vregs_isa1200[i])) {
689 pr_err("%s: regulator get of %s failed (%ld)\n",
690 __func__, vregs_isa1200_name[i],
691 PTR_ERR(vregs_isa1200[i]));
692 rc = PTR_ERR(vregs_isa1200[i]);
693 goto vreg_get_fail;
694 }
695 rc = regulator_set_voltage(vregs_isa1200[i],
696 vregs_isa1200_val[i], vregs_isa1200_val[i]);
697 if (rc) {
698 pr_err("%s: regulator_set_voltage(%s) failed\n",
699 __func__, vregs_isa1200_name[i]);
700 goto vreg_get_fail;
701 }
702 }
Steve Muckle9161d302010-02-11 11:50:40 -0800703
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700704 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
705 if (rc) {
706 pr_err("%s: unable to request gpio %d (%d)\n",
707 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
708 goto vreg_get_fail;
709 }
Steve Muckle9161d302010-02-11 11:50:40 -0800710
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700711 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
712 if (rc) {
713 pr_err("%s: Unable to set direction\n", __func__);;
714 goto free_gpio;
715 }
716
717 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
718 if (IS_ERR(xo_handle_a1)) {
719 rc = PTR_ERR(xo_handle_a1);
720 pr_err("%s: failed to get the handle for A1(%d)\n",
721 __func__, rc);
722 goto gpio_set_dir;
723 }
724 } else {
725 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
726 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
727
728 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
729 regulator_put(vregs_isa1200[i]);
730
731 msm_xo_put(xo_handle_a1);
732 }
733
734 return 0;
735gpio_set_dir:
736 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
737free_gpio:
738 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
739vreg_get_fail:
740 while (i)
741 regulator_put(vregs_isa1200[--i]);
742 return rc;
743}
744
745#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
746static struct isa1200_platform_data isa1200_1_pdata = {
747 .name = "vibrator",
748 .power_on = isa1200_power,
749 .dev_setup = isa1200_dev_setup,
750 /*gpio to enable haptic*/
751 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
752 .max_timeout = 15000,
753 .mode_ctrl = PWM_GEN_MODE,
754 .pwm_fd = {
755 .pwm_div = 256,
756 },
757 .is_erm = false,
758 .smart_en = true,
759 .ext_clk_en = true,
760 .chip_en = 1,
761};
762
763static struct i2c_board_info msm_isa1200_board_info[] = {
764 {
765 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
766 .platform_data = &isa1200_1_pdata,
767 },
768};
769#endif
770
771#if defined(CONFIG_BATTERY_BQ27520) || \
772 defined(CONFIG_BATTERY_BQ27520_MODULE)
773static struct bq27520_platform_data bq27520_pdata = {
774 .name = "fuel-gauge",
775 .vreg_name = "8058_s3",
776 .vreg_value = 1800000,
777 .soc_int = GPIO_BATT_GAUGE_INT_N,
778 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
779 .chip_en = GPIO_BATT_GAUGE_EN,
780 .enable_dlog = 0, /* if enable coulomb counter logger */
781};
782
783static struct i2c_board_info msm_bq27520_board_info[] = {
784 {
785 I2C_BOARD_INFO("bq27520", 0xaa>>1),
786 .platform_data = &bq27520_pdata,
787 },
788};
789#endif
790
791static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
792 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
793 .idle_supported = 1,
794 .suspend_supported = 1,
795 .idle_enabled = 0,
796 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700797 },
798
799 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
800 .idle_supported = 1,
801 .suspend_supported = 1,
802 .idle_enabled = 0,
803 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700804 },
805
806 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
807 .idle_supported = 1,
808 .suspend_supported = 1,
809 .idle_enabled = 1,
810 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700811 },
812
813 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
814 .idle_supported = 1,
815 .suspend_supported = 1,
816 .idle_enabled = 0,
817 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700818 },
819
820 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
821 .idle_supported = 1,
822 .suspend_supported = 1,
823 .idle_enabled = 0,
824 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700825 },
826
827 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
828 .idle_supported = 1,
829 .suspend_supported = 1,
830 .idle_enabled = 1,
831 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700832 },
833};
834
835static struct msm_cpuidle_state msm_cstates[] __initdata = {
836 {0, 0, "C0", "WFI",
837 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
838
839 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
840 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
841
842 {0, 2, "C2", "POWER_COLLAPSE",
843 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
844
845 {1, 0, "C0", "WFI",
846 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
847
848 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
849 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
850};
851
852static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
853 {
854 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
855 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
856 true,
857 1, 8000, 100000, 1,
858 },
859
860 {
861 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
862 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
863 true,
864 1500, 5000, 60100000, 3000,
865 },
866
867 {
868 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
869 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
870 false,
871 1800, 5000, 60350000, 3500,
872 },
873 {
874 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
875 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
876 false,
877 3800, 4500, 65350000, 5500,
878 },
879
880 {
881 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
882 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
883 false,
884 2800, 2500, 66850000, 4800,
885 },
886
887 {
888 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
889 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
890 false,
891 4800, 2000, 71850000, 6800,
892 },
893
894 {
895 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
896 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
897 false,
898 6800, 500, 75850000, 8800,
899 },
900
901 {
902 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
903 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
904 false,
905 7800, 0, 76350000, 9800,
906 },
907};
908
909#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
910
911#define ISP1763_INT_GPIO 117
912#define ISP1763_RST_GPIO 152
913static struct resource isp1763_resources[] = {
914 [0] = {
915 .flags = IORESOURCE_MEM,
916 .start = 0x1D000000,
917 .end = 0x1D005FFF, /* 24KB */
918 },
919 [1] = {
920 .flags = IORESOURCE_IRQ,
921 },
922};
923static void __init msm8x60_cfg_isp1763(void)
924{
925 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
926 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
927}
928
929static int isp1763_setup_gpio(int enable)
930{
931 int status = 0;
932
933 if (enable) {
934 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
935 if (status) {
936 pr_err("%s:Failed to request GPIO %d\n",
937 __func__, ISP1763_INT_GPIO);
938 return status;
939 }
940 status = gpio_direction_input(ISP1763_INT_GPIO);
941 if (status) {
942 pr_err("%s:Failed to configure GPIO %d\n",
943 __func__, ISP1763_INT_GPIO);
944 goto gpio_free_int;
945 }
946 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
947 if (status) {
948 pr_err("%s:Failed to request GPIO %d\n",
949 __func__, ISP1763_RST_GPIO);
950 goto gpio_free_int;
951 }
952 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
953 if (status) {
954 pr_err("%s:Failed to configure GPIO %d\n",
955 __func__, ISP1763_RST_GPIO);
956 goto gpio_free_rst;
957 }
958 pr_debug("\nISP GPIO configuration done\n");
959 return status;
960 }
961
962gpio_free_rst:
963 gpio_free(ISP1763_RST_GPIO);
964gpio_free_int:
965 gpio_free(ISP1763_INT_GPIO);
966
967 return status;
968}
969static struct isp1763_platform_data isp1763_pdata = {
970 .reset_gpio = ISP1763_RST_GPIO,
971 .setup_gpio = isp1763_setup_gpio
972};
973
974static struct platform_device isp1763_device = {
975 .name = "isp1763_usb",
976 .num_resources = ARRAY_SIZE(isp1763_resources),
977 .resource = isp1763_resources,
978 .dev = {
979 .platform_data = &isp1763_pdata
980 }
981};
982#endif
983
984#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
Anji jonnalaeb9e60d2011-10-05 12:19:46 +0530985static struct msm_otg_platform_data msm_otg_pdata;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700986static struct regulator *ldo6_3p3;
987static struct regulator *ldo7_1p8;
988static struct regulator *vdd_cx;
989#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
990notify_vbus_state notify_vbus_state_func_ptr;
991static int usb_phy_susp_dig_vol = 750000;
992static int pmic_id_notif_supported;
993
994#ifdef CONFIG_USB_EHCI_MSM_72K
995#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
996struct delayed_work pmic_id_det;
997
998static int __init usb_id_pin_rework_setup(char *support)
999{
1000 if (strncmp(support, "true", 4) == 0)
1001 pmic_id_notif_supported = 1;
1002
1003 return 1;
1004}
1005__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1006
1007static void pmic_id_detect(struct work_struct *w)
1008{
1009 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1010 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1011
1012 if (notify_vbus_state_func_ptr)
1013 (*notify_vbus_state_func_ptr) (val);
1014}
1015
1016static irqreturn_t pmic_id_on_irq(int irq, void *data)
1017{
1018 /*
1019 * Spurious interrupts are observed on pmic gpio line
1020 * even though there is no state change on USB ID. Schedule the
1021 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001022 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001023 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001024
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001025 return IRQ_HANDLED;
1026}
1027
1028static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1029{
1030 unsigned ret = -ENODEV;
1031
1032 if (!callback)
1033 return -EINVAL;
1034
1035 if (machine_is_msm8x60_fluid())
1036 return -ENOTSUPP;
1037
1038 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1039 pr_debug("%s: USB_ID pin is not routed to PMIC"
1040 "on V1 surf/ffa\n", __func__);
1041 return -ENOTSUPP;
1042 }
1043
1044 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1045 !pmic_id_notif_supported) {
1046 pr_debug("%s: USB_ID is not routed to PMIC"
1047 "on V2 ffa\n", __func__);
1048 return -ENOTSUPP;
1049 }
1050
1051 usb_phy_susp_dig_vol = 500000;
1052
1053 if (init) {
1054 notify_vbus_state_func_ptr = callback;
1055 ret = pm8901_mpp_config_digital_out(1,
1056 PM8901_MPP_DIG_LEVEL_L5, 1);
1057 if (ret) {
1058 pr_err("%s: MPP2 configuration failed\n", __func__);
1059 return -ENODEV;
1060 }
1061 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
1062 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1063 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1064 "msm_otg_id", NULL);
1065 if (ret) {
1066 pm8901_mpp_config_digital_out(1,
1067 PM8901_MPP_DIG_LEVEL_L5, 0);
1068 pr_err("%s:pmic_usb_id interrupt registration failed",
1069 __func__);
1070 return ret;
1071 }
1072 /* Notify the initial Id status */
1073 pmic_id_detect(&pmic_id_det.work);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301074 msm_otg_pdata.pmic_id_irq = PMICID_INT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001075 } else {
1076 free_irq(PMICID_INT, 0);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301077 msm_otg_pdata.pmic_id_irq = 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001078 cancel_delayed_work_sync(&pmic_id_det);
1079 notify_vbus_state_func_ptr = NULL;
1080 ret = pm8901_mpp_config_digital_out(1,
1081 PM8901_MPP_DIG_LEVEL_L5, 0);
1082 if (ret) {
1083 pr_err("%s:MPP2 configuration failed\n", __func__);
1084 return -ENODEV;
1085 }
1086 }
1087 return 0;
1088}
1089#endif
1090
1091#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1092#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1093static int msm_hsusb_init_vddcx(int init)
1094{
1095 int ret = 0;
1096
1097 if (init) {
1098 vdd_cx = regulator_get(NULL, "8058_s1");
1099 if (IS_ERR(vdd_cx)) {
1100 return PTR_ERR(vdd_cx);
1101 }
1102
1103 ret = regulator_set_voltage(vdd_cx,
1104 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1105 USB_PHY_MAX_VDD_DIG_VOL);
1106 if (ret) {
1107 pr_err("%s: unable to set the voltage for regulator"
1108 "vdd_cx\n", __func__);
1109 regulator_put(vdd_cx);
1110 return ret;
1111 }
1112
1113 ret = regulator_enable(vdd_cx);
1114 if (ret) {
1115 pr_err("%s: unable to enable regulator"
1116 "vdd_cx\n", __func__);
1117 regulator_put(vdd_cx);
1118 }
1119 } else {
1120 ret = regulator_disable(vdd_cx);
1121 if (ret) {
1122 pr_err("%s: Unable to disable the regulator:"
1123 "vdd_cx\n", __func__);
1124 return ret;
1125 }
1126
1127 regulator_put(vdd_cx);
1128 }
1129
1130 return ret;
1131}
1132
1133static int msm_hsusb_config_vddcx(int high)
1134{
1135 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1136 int min_vol;
1137 int ret;
1138
1139 if (high)
1140 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1141 else
1142 min_vol = usb_phy_susp_dig_vol;
1143
1144 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1145 if (ret) {
1146 pr_err("%s: unable to set the voltage for regulator"
1147 "vdd_cx\n", __func__);
1148 return ret;
1149 }
1150
1151 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1152
1153 return ret;
1154}
1155
1156#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1157#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1158#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1159#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1160
1161#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1162#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1163#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1164#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1165static int msm_hsusb_ldo_init(int init)
1166{
1167 int rc = 0;
1168
1169 if (init) {
1170 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1171 if (IS_ERR(ldo6_3p3))
1172 return PTR_ERR(ldo6_3p3);
1173
1174 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1175 if (IS_ERR(ldo7_1p8)) {
1176 rc = PTR_ERR(ldo7_1p8);
1177 goto put_3p3;
1178 }
1179
1180 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1181 USB_PHY_3P3_VOL_MAX);
1182 if (rc) {
1183 pr_err("%s: Unable to set voltage level for"
1184 "ldo6_3p3 regulator\n", __func__);
1185 goto put_1p8;
1186 }
1187 rc = regulator_enable(ldo6_3p3);
1188 if (rc) {
1189 pr_err("%s: Unable to enable the regulator:"
1190 "ldo6_3p3\n", __func__);
1191 goto put_1p8;
1192 }
1193 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1194 USB_PHY_1P8_VOL_MAX);
1195 if (rc) {
1196 pr_err("%s: Unable to set voltage level for"
1197 "ldo7_1p8 regulator\n", __func__);
1198 goto disable_3p3;
1199 }
1200 rc = regulator_enable(ldo7_1p8);
1201 if (rc) {
1202 pr_err("%s: Unable to enable the regulator:"
1203 "ldo7_1p8\n", __func__);
1204 goto disable_3p3;
1205 }
1206
1207 return 0;
1208 }
1209
1210 regulator_disable(ldo7_1p8);
1211disable_3p3:
1212 regulator_disable(ldo6_3p3);
1213put_1p8:
1214 regulator_put(ldo7_1p8);
1215put_3p3:
1216 regulator_put(ldo6_3p3);
1217 return rc;
1218}
1219
1220static int msm_hsusb_ldo_enable(int on)
1221{
1222 int ret = 0;
1223
1224 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1225 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1226 return -ENODEV;
1227 }
1228
1229 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1230 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1231 return -ENODEV;
1232 }
1233
1234 if (on) {
1235 ret = regulator_set_optimum_mode(ldo7_1p8,
1236 USB_PHY_1P8_HPM_LOAD);
1237 if (ret < 0) {
1238 pr_err("%s: Unable to set HPM of the regulator:"
1239 "ldo7_1p8\n", __func__);
1240 return ret;
1241 }
1242 ret = regulator_set_optimum_mode(ldo6_3p3,
1243 USB_PHY_3P3_HPM_LOAD);
1244 if (ret < 0) {
1245 pr_err("%s: Unable to set HPM of the regulator:"
1246 "ldo6_3p3\n", __func__);
1247 regulator_set_optimum_mode(ldo7_1p8,
1248 USB_PHY_1P8_LPM_LOAD);
1249 return ret;
1250 }
1251 } else {
1252 ret = regulator_set_optimum_mode(ldo7_1p8,
1253 USB_PHY_1P8_LPM_LOAD);
1254 if (ret < 0)
1255 pr_err("%s: Unable to set LPM of the regulator:"
1256 "ldo7_1p8\n", __func__);
1257 ret = regulator_set_optimum_mode(ldo6_3p3,
1258 USB_PHY_3P3_LPM_LOAD);
1259 if (ret < 0)
1260 pr_err("%s: Unable to set LPM of the regulator:"
1261 "ldo6_3p3\n", __func__);
1262 }
1263
1264 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1265 return ret < 0 ? ret : 0;
1266 }
1267#endif
1268#ifdef CONFIG_USB_EHCI_MSM_72K
1269#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1270static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1271{
1272 static int vbus_is_on;
1273
1274 /* If VBUS is already on (or off), do nothing. */
1275 if (on == vbus_is_on)
1276 return;
1277 smb137b_otg_power(on);
1278 vbus_is_on = on;
1279}
1280#endif
1281static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1282{
1283 static struct regulator *votg_5v_switch;
1284 static struct regulator *ext_5v_reg;
1285 static int vbus_is_on;
1286
1287 /* If VBUS is already on (or off), do nothing. */
1288 if (on == vbus_is_on)
1289 return;
1290
1291 if (!votg_5v_switch) {
1292 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1293 if (IS_ERR(votg_5v_switch)) {
1294 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1295 return;
1296 }
1297 }
1298 if (!ext_5v_reg) {
1299 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1300 if (IS_ERR(ext_5v_reg)) {
1301 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1302 return;
1303 }
1304 }
1305 if (on) {
1306 if (regulator_enable(ext_5v_reg)) {
1307 pr_err("%s: Unable to enable the regulator:"
1308 " ext_5v_reg\n", __func__);
1309 return;
1310 }
1311 if (regulator_enable(votg_5v_switch)) {
1312 pr_err("%s: Unable to enable the regulator:"
1313 " votg_5v_switch\n", __func__);
1314 return;
1315 }
1316 } else {
1317 if (regulator_disable(votg_5v_switch))
1318 pr_err("%s: Unable to enable the regulator:"
1319 " votg_5v_switch\n", __func__);
1320 if (regulator_disable(ext_5v_reg))
1321 pr_err("%s: Unable to enable the regulator:"
1322 " ext_5v_reg\n", __func__);
1323 }
1324
1325 vbus_is_on = on;
1326}
1327
1328static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1329 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1330 .power_budget = 390,
1331};
1332#endif
1333
1334#ifdef CONFIG_BATTERY_MSM8X60
1335static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1336 int init)
1337{
1338 int ret = -ENOTSUPP;
1339
1340#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1341 if (machine_is_msm8x60_fluid()) {
1342 if (init)
1343 msm_charger_register_vbus_sn(callback);
1344 else
1345 msm_charger_unregister_vbus_sn(callback);
1346 return 0;
1347 }
1348#endif
1349 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1350 * hence, irrespective of either peripheral only mode or
1351 * OTG (host and peripheral) modes, can depend on pmic for
1352 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001353 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001354 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1355 && (machine_is_msm8x60_surf() ||
1356 pmic_id_notif_supported)) {
1357 if (init)
1358 ret = msm_charger_register_vbus_sn(callback);
1359 else {
1360 msm_charger_unregister_vbus_sn(callback);
1361 ret = 0;
1362 }
1363 } else {
1364#if !defined(CONFIG_USB_EHCI_MSM_72K)
1365 if (init)
1366 ret = msm_charger_register_vbus_sn(callback);
1367 else {
1368 msm_charger_unregister_vbus_sn(callback);
1369 ret = 0;
1370 }
1371#endif
1372 }
1373 return ret;
1374}
1375#endif
1376
1377#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1378static struct msm_otg_platform_data msm_otg_pdata = {
1379 /* if usb link is in sps there is no need for
1380 * usb pclk as dayatona fabric clock will be
1381 * used instead
1382 */
1383 .pclk_src_name = "dfab_usb_hs_clk",
1384 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1385 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1386 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301387 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001388#ifdef CONFIG_USB_EHCI_MSM_72K
1389 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
1390#endif
1391#ifdef CONFIG_USB_EHCI_MSM_72K
1392 .vbus_power = msm_hsusb_vbus_power,
1393#endif
1394#ifdef CONFIG_BATTERY_MSM8X60
1395 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1396#endif
1397 .ldo_init = msm_hsusb_ldo_init,
1398 .ldo_enable = msm_hsusb_ldo_enable,
1399 .config_vddcx = msm_hsusb_config_vddcx,
1400 .init_vddcx = msm_hsusb_init_vddcx,
1401#ifdef CONFIG_BATTERY_MSM8X60
1402 .chg_vbus_draw = msm_charger_vbus_draw,
1403#endif
1404};
1405#endif
1406
1407#ifdef CONFIG_USB_GADGET_MSM_72K
1408static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1409 .is_phy_status_timer_on = 1,
1410};
1411#endif
1412
1413#ifdef CONFIG_USB_G_ANDROID
1414
1415#define PID_MAGIC_ID 0x71432909
1416#define SERIAL_NUM_MAGIC_ID 0x61945374
1417#define SERIAL_NUMBER_LENGTH 127
1418#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1419
1420struct magic_num_struct {
1421 uint32_t pid;
1422 uint32_t serial_num;
1423};
1424
1425struct dload_struct {
1426 uint32_t reserved1;
1427 uint32_t reserved2;
1428 uint32_t reserved3;
1429 uint16_t reserved4;
1430 uint16_t pid;
1431 char serial_number[SERIAL_NUMBER_LENGTH];
1432 uint16_t reserved5;
1433 struct magic_num_struct
1434 magic_struct;
1435};
1436
1437static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1438{
1439 struct dload_struct __iomem *dload = 0;
1440
1441 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1442 if (!dload) {
1443 pr_err("%s: cannot remap I/O memory region: %08x\n",
1444 __func__, DLOAD_USB_BASE_ADD);
1445 return -ENXIO;
1446 }
1447
1448 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1449 __func__, dload, pid, snum);
1450 /* update pid */
1451 dload->magic_struct.pid = PID_MAGIC_ID;
1452 dload->pid = pid;
1453
1454 /* update serial number */
1455 dload->magic_struct.serial_num = 0;
1456 if (!snum)
1457 return 0;
1458
1459 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1460 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1461 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1462
1463 iounmap(dload);
1464
1465 return 0;
1466}
1467
1468static struct android_usb_platform_data android_usb_pdata = {
1469 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1470};
1471
1472static struct platform_device android_usb_device = {
1473 .name = "android_usb",
1474 .id = -1,
1475 .dev = {
1476 .platform_data = &android_usb_pdata,
1477 },
1478};
1479
1480
1481#endif
1482
1483#ifdef CONFIG_MSM_VPE
1484static struct resource msm_vpe_resources[] = {
1485 {
1486 .start = 0x05300000,
1487 .end = 0x05300000 + SZ_1M - 1,
1488 .flags = IORESOURCE_MEM,
1489 },
1490 {
1491 .start = INT_VPE,
1492 .end = INT_VPE,
1493 .flags = IORESOURCE_IRQ,
1494 },
1495};
1496
1497static struct platform_device msm_vpe_device = {
1498 .name = "msm_vpe",
1499 .id = 0,
1500 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1501 .resource = msm_vpe_resources,
1502};
1503#endif
1504
1505#ifdef CONFIG_MSM_CAMERA
1506#ifdef CONFIG_MSM_CAMERA_FLASH
1507#define VFE_CAMIF_TIMER1_GPIO 29
1508#define VFE_CAMIF_TIMER2_GPIO 30
1509#define VFE_CAMIF_TIMER3_GPIO_INT 31
1510#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1511static struct msm_camera_sensor_flash_src msm_flash_src = {
1512 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1513 ._fsrc.pmic_src.num_of_src = 2,
1514 ._fsrc.pmic_src.low_current = 100,
1515 ._fsrc.pmic_src.high_current = 300,
1516 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1517 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1518 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1519};
1520#ifdef CONFIG_IMX074
1521static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1522 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1523 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1524 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1525 .flash_recharge_duration = 50000,
1526 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1527};
1528#endif
1529#endif
1530
1531int msm_cam_gpio_tbl[] = {
1532 32,/*CAMIF_MCLK*/
1533 47,/*CAMIF_I2C_DATA*/
1534 48,/*CAMIF_I2C_CLK*/
1535 105,/*STANDBY*/
1536};
1537
1538enum msm_cam_stat{
1539 MSM_CAM_OFF,
1540 MSM_CAM_ON,
1541};
1542
1543static int config_gpio_table(enum msm_cam_stat stat)
1544{
1545 int rc = 0, i = 0;
1546 if (stat == MSM_CAM_ON) {
1547 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1548 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1549 if (unlikely(rc < 0)) {
1550 pr_err("%s not able to get gpio\n", __func__);
1551 for (i--; i >= 0; i--)
1552 gpio_free(msm_cam_gpio_tbl[i]);
1553 break;
1554 }
1555 }
1556 } else {
1557 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1558 gpio_free(msm_cam_gpio_tbl[i]);
1559 }
1560 return rc;
1561}
1562
1563static struct msm_camera_sensor_platform_info sensor_board_info = {
1564 .mount_angle = 0
1565};
1566
1567/*external regulator VREG_5V*/
1568static struct regulator *reg_flash_5V;
1569
1570static int config_camera_on_gpios_fluid(void)
1571{
1572 int rc = 0;
1573
1574 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1575 if (IS_ERR(reg_flash_5V)) {
1576 pr_err("'%s' regulator not found, rc=%ld\n",
1577 "8901_mpp0", IS_ERR(reg_flash_5V));
1578 return -ENODEV;
1579 }
1580
1581 rc = regulator_enable(reg_flash_5V);
1582 if (rc) {
1583 pr_err("'%s' regulator enable failed, rc=%d\n",
1584 "8901_mpp0", rc);
1585 regulator_put(reg_flash_5V);
1586 return rc;
1587 }
1588
1589#ifdef CONFIG_IMX074
1590 sensor_board_info.mount_angle = 90;
1591#endif
1592 rc = config_gpio_table(MSM_CAM_ON);
1593 if (rc < 0) {
1594 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1595 "failed\n", __func__);
1596 return rc;
1597 }
1598
1599 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1600 if (rc < 0) {
1601 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1602 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1603 regulator_disable(reg_flash_5V);
1604 regulator_put(reg_flash_5V);
1605 return rc;
1606 }
1607 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1608 msleep(20);
1609 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1610
1611
1612 /*Enable LED_FLASH_EN*/
1613 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1614 if (rc < 0) {
1615 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1616 "failed\n", __func__, GPIO_LED_FLASH_EN);
1617
1618 regulator_disable(reg_flash_5V);
1619 regulator_put(reg_flash_5V);
1620 config_gpio_table(MSM_CAM_OFF);
1621 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1622 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1623 return rc;
1624 }
1625 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1626 msleep(20);
1627 return rc;
1628}
1629
1630
1631static void config_camera_off_gpios_fluid(void)
1632{
1633 regulator_disable(reg_flash_5V);
1634 regulator_put(reg_flash_5V);
1635
1636 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1637 gpio_free(GPIO_LED_FLASH_EN);
1638
1639 config_gpio_table(MSM_CAM_OFF);
1640
1641 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1642 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1643}
1644static int config_camera_on_gpios(void)
1645{
1646 int rc = 0;
1647
1648 if (machine_is_msm8x60_fluid())
1649 return config_camera_on_gpios_fluid();
1650
1651 rc = config_gpio_table(MSM_CAM_ON);
1652 if (rc < 0) {
1653 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1654 "failed\n", __func__);
1655 return rc;
1656 }
1657
Jilai Wang971f97f2011-07-13 14:25:25 -04001658 if (!machine_is_msm8x60_dragon()) {
1659 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1660 if (rc < 0) {
1661 config_gpio_table(MSM_CAM_OFF);
1662 pr_err("%s: CAMSENSOR gpio %d request"
1663 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1664 return rc;
1665 }
1666 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1667 msleep(20);
1668 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001669 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001670
1671#ifdef CONFIG_MSM_CAMERA_FLASH
1672#ifdef CONFIG_IMX074
1673 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1674 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1675#endif
1676#endif
1677 return rc;
1678}
1679
1680static void config_camera_off_gpios(void)
1681{
1682 if (machine_is_msm8x60_fluid())
1683 return config_camera_off_gpios_fluid();
1684
1685
1686 config_gpio_table(MSM_CAM_OFF);
1687
Jilai Wang971f97f2011-07-13 14:25:25 -04001688 if (!machine_is_msm8x60_dragon()) {
1689 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1690 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1691 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001692}
1693
1694#ifdef CONFIG_QS_S5K4E1
1695
1696#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1697
1698static int config_camera_on_gpios_qs_cam_fluid(void)
1699{
1700 int rc = 0;
1701
1702 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1703 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1704 if (rc < 0) {
1705 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1706 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1707 return rc;
1708 }
1709 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1710 msleep(20);
1711 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1712 msleep(20);
1713
1714 /*
1715 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1716 * to enable 2.7V power to Camera
1717 */
1718 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1719 if (rc < 0) {
1720 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1721 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1722 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1723 gpio_free(QS_CAM_HC37_CAM_PD);
1724 return rc;
1725 }
1726 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1727 msleep(20);
1728 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1729 msleep(20);
1730
1731 rc = config_camera_on_gpios_fluid();
1732 if (rc < 0) {
1733 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1734 " failed\n", __func__);
1735 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1736 gpio_free(QS_CAM_HC37_CAM_PD);
1737 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1738 gpio_free(GPIO_AUX_CAM_2P7_EN);
1739 return rc;
1740 }
1741 return rc;
1742}
1743
1744static void config_camera_off_gpios_qs_cam_fluid(void)
1745{
1746 /*
1747 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1748 * to disable 2.7V power to Camera
1749 */
1750 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1751 gpio_free(GPIO_AUX_CAM_2P7_EN);
1752
1753 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1754 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1755 gpio_free(QS_CAM_HC37_CAM_PD);
1756
1757 config_camera_off_gpios_fluid();
1758 return;
1759}
1760
1761static int config_camera_on_gpios_qs_cam(void)
1762{
1763 int rc = 0;
1764
1765 if (machine_is_msm8x60_fluid())
1766 return config_camera_on_gpios_qs_cam_fluid();
1767
1768 rc = config_camera_on_gpios();
1769 return rc;
1770}
1771
1772static void config_camera_off_gpios_qs_cam(void)
1773{
1774 if (machine_is_msm8x60_fluid())
1775 return config_camera_off_gpios_qs_cam_fluid();
1776
1777 config_camera_off_gpios();
1778 return;
1779}
1780#endif
1781
1782static int config_camera_on_gpios_web_cam(void)
1783{
1784 int rc = 0;
1785 rc = config_gpio_table(MSM_CAM_ON);
1786 if (rc < 0) {
1787 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1788 "failed\n", __func__);
1789 return rc;
1790 }
1791
Jilai Wang53d27a82011-07-13 14:32:58 -04001792 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001793 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1794 if (rc < 0) {
1795 config_gpio_table(MSM_CAM_OFF);
1796 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1797 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1798 return rc;
1799 }
1800 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1801 }
1802 return rc;
1803}
1804
1805static void config_camera_off_gpios_web_cam(void)
1806{
1807 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001808 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001809 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1810 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1811 }
1812 return;
1813}
1814
1815#ifdef CONFIG_MSM_BUS_SCALING
1816static struct msm_bus_vectors cam_init_vectors[] = {
1817 {
1818 .src = MSM_BUS_MASTER_VFE,
1819 .dst = MSM_BUS_SLAVE_SMI,
1820 .ab = 0,
1821 .ib = 0,
1822 },
1823 {
1824 .src = MSM_BUS_MASTER_VFE,
1825 .dst = MSM_BUS_SLAVE_EBI_CH0,
1826 .ab = 0,
1827 .ib = 0,
1828 },
1829 {
1830 .src = MSM_BUS_MASTER_VPE,
1831 .dst = MSM_BUS_SLAVE_SMI,
1832 .ab = 0,
1833 .ib = 0,
1834 },
1835 {
1836 .src = MSM_BUS_MASTER_VPE,
1837 .dst = MSM_BUS_SLAVE_EBI_CH0,
1838 .ab = 0,
1839 .ib = 0,
1840 },
1841 {
1842 .src = MSM_BUS_MASTER_JPEG_ENC,
1843 .dst = MSM_BUS_SLAVE_SMI,
1844 .ab = 0,
1845 .ib = 0,
1846 },
1847 {
1848 .src = MSM_BUS_MASTER_JPEG_ENC,
1849 .dst = MSM_BUS_SLAVE_EBI_CH0,
1850 .ab = 0,
1851 .ib = 0,
1852 },
1853};
1854
1855static struct msm_bus_vectors cam_preview_vectors[] = {
1856 {
1857 .src = MSM_BUS_MASTER_VFE,
1858 .dst = MSM_BUS_SLAVE_SMI,
1859 .ab = 0,
1860 .ib = 0,
1861 },
1862 {
1863 .src = MSM_BUS_MASTER_VFE,
1864 .dst = MSM_BUS_SLAVE_EBI_CH0,
1865 .ab = 283115520,
1866 .ib = 452984832,
1867 },
1868 {
1869 .src = MSM_BUS_MASTER_VPE,
1870 .dst = MSM_BUS_SLAVE_SMI,
1871 .ab = 0,
1872 .ib = 0,
1873 },
1874 {
1875 .src = MSM_BUS_MASTER_VPE,
1876 .dst = MSM_BUS_SLAVE_EBI_CH0,
1877 .ab = 0,
1878 .ib = 0,
1879 },
1880 {
1881 .src = MSM_BUS_MASTER_JPEG_ENC,
1882 .dst = MSM_BUS_SLAVE_SMI,
1883 .ab = 0,
1884 .ib = 0,
1885 },
1886 {
1887 .src = MSM_BUS_MASTER_JPEG_ENC,
1888 .dst = MSM_BUS_SLAVE_EBI_CH0,
1889 .ab = 0,
1890 .ib = 0,
1891 },
1892};
1893
1894static struct msm_bus_vectors cam_video_vectors[] = {
1895 {
1896 .src = MSM_BUS_MASTER_VFE,
1897 .dst = MSM_BUS_SLAVE_SMI,
1898 .ab = 283115520,
1899 .ib = 452984832,
1900 },
1901 {
1902 .src = MSM_BUS_MASTER_VFE,
1903 .dst = MSM_BUS_SLAVE_EBI_CH0,
1904 .ab = 283115520,
1905 .ib = 452984832,
1906 },
1907 {
1908 .src = MSM_BUS_MASTER_VPE,
1909 .dst = MSM_BUS_SLAVE_SMI,
1910 .ab = 319610880,
1911 .ib = 511377408,
1912 },
1913 {
1914 .src = MSM_BUS_MASTER_VPE,
1915 .dst = MSM_BUS_SLAVE_EBI_CH0,
1916 .ab = 0,
1917 .ib = 0,
1918 },
1919 {
1920 .src = MSM_BUS_MASTER_JPEG_ENC,
1921 .dst = MSM_BUS_SLAVE_SMI,
1922 .ab = 0,
1923 .ib = 0,
1924 },
1925 {
1926 .src = MSM_BUS_MASTER_JPEG_ENC,
1927 .dst = MSM_BUS_SLAVE_EBI_CH0,
1928 .ab = 0,
1929 .ib = 0,
1930 },
1931};
1932
1933static struct msm_bus_vectors cam_snapshot_vectors[] = {
1934 {
1935 .src = MSM_BUS_MASTER_VFE,
1936 .dst = MSM_BUS_SLAVE_SMI,
1937 .ab = 566231040,
1938 .ib = 905969664,
1939 },
1940 {
1941 .src = MSM_BUS_MASTER_VFE,
1942 .dst = MSM_BUS_SLAVE_EBI_CH0,
1943 .ab = 69984000,
1944 .ib = 111974400,
1945 },
1946 {
1947 .src = MSM_BUS_MASTER_VPE,
1948 .dst = MSM_BUS_SLAVE_SMI,
1949 .ab = 0,
1950 .ib = 0,
1951 },
1952 {
1953 .src = MSM_BUS_MASTER_VPE,
1954 .dst = MSM_BUS_SLAVE_EBI_CH0,
1955 .ab = 0,
1956 .ib = 0,
1957 },
1958 {
1959 .src = MSM_BUS_MASTER_JPEG_ENC,
1960 .dst = MSM_BUS_SLAVE_SMI,
1961 .ab = 320864256,
1962 .ib = 513382810,
1963 },
1964 {
1965 .src = MSM_BUS_MASTER_JPEG_ENC,
1966 .dst = MSM_BUS_SLAVE_EBI_CH0,
1967 .ab = 320864256,
1968 .ib = 513382810,
1969 },
1970};
1971
1972static struct msm_bus_vectors cam_zsl_vectors[] = {
1973 {
1974 .src = MSM_BUS_MASTER_VFE,
1975 .dst = MSM_BUS_SLAVE_SMI,
1976 .ab = 566231040,
1977 .ib = 905969664,
1978 },
1979 {
1980 .src = MSM_BUS_MASTER_VFE,
1981 .dst = MSM_BUS_SLAVE_EBI_CH0,
1982 .ab = 706199040,
1983 .ib = 1129918464,
1984 },
1985 {
1986 .src = MSM_BUS_MASTER_VPE,
1987 .dst = MSM_BUS_SLAVE_SMI,
1988 .ab = 0,
1989 .ib = 0,
1990 },
1991 {
1992 .src = MSM_BUS_MASTER_VPE,
1993 .dst = MSM_BUS_SLAVE_EBI_CH0,
1994 .ab = 0,
1995 .ib = 0,
1996 },
1997 {
1998 .src = MSM_BUS_MASTER_JPEG_ENC,
1999 .dst = MSM_BUS_SLAVE_SMI,
2000 .ab = 320864256,
2001 .ib = 513382810,
2002 },
2003 {
2004 .src = MSM_BUS_MASTER_JPEG_ENC,
2005 .dst = MSM_BUS_SLAVE_EBI_CH0,
2006 .ab = 320864256,
2007 .ib = 513382810,
2008 },
2009};
2010
2011static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2012 {
2013 .src = MSM_BUS_MASTER_VFE,
2014 .dst = MSM_BUS_SLAVE_SMI,
2015 .ab = 212336640,
2016 .ib = 339738624,
2017 },
2018 {
2019 .src = MSM_BUS_MASTER_VFE,
2020 .dst = MSM_BUS_SLAVE_EBI_CH0,
2021 .ab = 25090560,
2022 .ib = 40144896,
2023 },
2024 {
2025 .src = MSM_BUS_MASTER_VPE,
2026 .dst = MSM_BUS_SLAVE_SMI,
2027 .ab = 239708160,
2028 .ib = 383533056,
2029 },
2030 {
2031 .src = MSM_BUS_MASTER_VPE,
2032 .dst = MSM_BUS_SLAVE_EBI_CH0,
2033 .ab = 79902720,
2034 .ib = 127844352,
2035 },
2036 {
2037 .src = MSM_BUS_MASTER_JPEG_ENC,
2038 .dst = MSM_BUS_SLAVE_SMI,
2039 .ab = 0,
2040 .ib = 0,
2041 },
2042 {
2043 .src = MSM_BUS_MASTER_JPEG_ENC,
2044 .dst = MSM_BUS_SLAVE_EBI_CH0,
2045 .ab = 0,
2046 .ib = 0,
2047 },
2048};
2049
2050static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2051 {
2052 .src = MSM_BUS_MASTER_VFE,
2053 .dst = MSM_BUS_SLAVE_SMI,
2054 .ab = 0,
2055 .ib = 0,
2056 },
2057 {
2058 .src = MSM_BUS_MASTER_VFE,
2059 .dst = MSM_BUS_SLAVE_EBI_CH0,
2060 .ab = 300902400,
2061 .ib = 481443840,
2062 },
2063 {
2064 .src = MSM_BUS_MASTER_VPE,
2065 .dst = MSM_BUS_SLAVE_SMI,
2066 .ab = 230307840,
2067 .ib = 368492544,
2068 },
2069 {
2070 .src = MSM_BUS_MASTER_VPE,
2071 .dst = MSM_BUS_SLAVE_EBI_CH0,
2072 .ab = 245113344,
2073 .ib = 392181351,
2074 },
2075 {
2076 .src = MSM_BUS_MASTER_JPEG_ENC,
2077 .dst = MSM_BUS_SLAVE_SMI,
2078 .ab = 106536960,
2079 .ib = 170459136,
2080 },
2081 {
2082 .src = MSM_BUS_MASTER_JPEG_ENC,
2083 .dst = MSM_BUS_SLAVE_EBI_CH0,
2084 .ab = 106536960,
2085 .ib = 170459136,
2086 },
2087};
2088
2089static struct msm_bus_paths cam_bus_client_config[] = {
2090 {
2091 ARRAY_SIZE(cam_init_vectors),
2092 cam_init_vectors,
2093 },
2094 {
2095 ARRAY_SIZE(cam_preview_vectors),
2096 cam_preview_vectors,
2097 },
2098 {
2099 ARRAY_SIZE(cam_video_vectors),
2100 cam_video_vectors,
2101 },
2102 {
2103 ARRAY_SIZE(cam_snapshot_vectors),
2104 cam_snapshot_vectors,
2105 },
2106 {
2107 ARRAY_SIZE(cam_zsl_vectors),
2108 cam_zsl_vectors,
2109 },
2110 {
2111 ARRAY_SIZE(cam_stereo_video_vectors),
2112 cam_stereo_video_vectors,
2113 },
2114 {
2115 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2116 cam_stereo_snapshot_vectors,
2117 },
2118};
2119
2120static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2121 cam_bus_client_config,
2122 ARRAY_SIZE(cam_bus_client_config),
2123 .name = "msm_camera",
2124};
2125#endif
2126
2127struct msm_camera_device_platform_data msm_camera_device_data = {
2128 .camera_gpio_on = config_camera_on_gpios,
2129 .camera_gpio_off = config_camera_off_gpios,
2130 .ioext.csiphy = 0x04800000,
2131 .ioext.csisz = 0x00000400,
2132 .ioext.csiirq = CSI_0_IRQ,
2133 .ioclk.mclk_clk_rate = 24000000,
2134 .ioclk.vfe_clk_rate = 228570000,
2135#ifdef CONFIG_MSM_BUS_SCALING
2136 .cam_bus_scale_table = &cam_bus_client_pdata,
2137#endif
2138};
2139
2140#ifdef CONFIG_QS_S5K4E1
2141struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2142 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2143 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2144 .ioext.csiphy = 0x04800000,
2145 .ioext.csisz = 0x00000400,
2146 .ioext.csiirq = CSI_0_IRQ,
2147 .ioclk.mclk_clk_rate = 24000000,
2148 .ioclk.vfe_clk_rate = 228570000,
2149#ifdef CONFIG_MSM_BUS_SCALING
2150 .cam_bus_scale_table = &cam_bus_client_pdata,
2151#endif
2152};
2153#endif
2154
2155struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2156 .camera_gpio_on = config_camera_on_gpios_web_cam,
2157 .camera_gpio_off = config_camera_off_gpios_web_cam,
2158 .ioext.csiphy = 0x04900000,
2159 .ioext.csisz = 0x00000400,
2160 .ioext.csiirq = CSI_1_IRQ,
2161 .ioclk.mclk_clk_rate = 24000000,
2162 .ioclk.vfe_clk_rate = 228570000,
2163#ifdef CONFIG_MSM_BUS_SCALING
2164 .cam_bus_scale_table = &cam_bus_client_pdata,
2165#endif
2166};
2167
2168struct resource msm_camera_resources[] = {
2169 {
2170 .start = 0x04500000,
2171 .end = 0x04500000 + SZ_1M - 1,
2172 .flags = IORESOURCE_MEM,
2173 },
2174 {
2175 .start = VFE_IRQ,
2176 .end = VFE_IRQ,
2177 .flags = IORESOURCE_IRQ,
2178 },
2179};
2180#ifdef CONFIG_MT9E013
2181static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2182 .mount_angle = 0
2183};
2184
2185static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2186 .flash_type = MSM_CAMERA_FLASH_LED,
2187 .flash_src = &msm_flash_src
2188};
2189
2190static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2191 .sensor_name = "mt9e013",
2192 .sensor_reset = 106,
2193 .sensor_pwd = 85,
2194 .vcm_pwd = 1,
2195 .vcm_enable = 0,
2196 .pdata = &msm_camera_device_data,
2197 .resource = msm_camera_resources,
2198 .num_resources = ARRAY_SIZE(msm_camera_resources),
2199 .flash_data = &flash_mt9e013,
2200 .strobe_flash_data = &strobe_flash_xenon,
2201 .sensor_platform_info = &mt9e013_sensor_8660_info,
2202 .csi_if = 1
2203};
2204struct platform_device msm_camera_sensor_mt9e013 = {
2205 .name = "msm_camera_mt9e013",
2206 .dev = {
2207 .platform_data = &msm_camera_sensor_mt9e013_data,
2208 },
2209};
2210#endif
2211
2212#ifdef CONFIG_IMX074
2213static struct msm_camera_sensor_flash_data flash_imx074 = {
2214 .flash_type = MSM_CAMERA_FLASH_LED,
2215 .flash_src = &msm_flash_src
2216};
2217
2218static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2219 .sensor_name = "imx074",
2220 .sensor_reset = 106,
2221 .sensor_pwd = 85,
2222 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2223 .vcm_enable = 1,
2224 .pdata = &msm_camera_device_data,
2225 .resource = msm_camera_resources,
2226 .num_resources = ARRAY_SIZE(msm_camera_resources),
2227 .flash_data = &flash_imx074,
2228 .strobe_flash_data = &strobe_flash_xenon,
2229 .sensor_platform_info = &sensor_board_info,
2230 .csi_if = 1
2231};
2232struct platform_device msm_camera_sensor_imx074 = {
2233 .name = "msm_camera_imx074",
2234 .dev = {
2235 .platform_data = &msm_camera_sensor_imx074_data,
2236 },
2237};
2238#endif
2239#ifdef CONFIG_WEBCAM_OV9726
2240
2241static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2242 .mount_angle = 0
2243};
2244
2245static struct msm_camera_sensor_flash_data flash_ov9726 = {
2246 .flash_type = MSM_CAMERA_FLASH_LED,
2247 .flash_src = &msm_flash_src
2248};
2249static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2250 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002251 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002252 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2253 .sensor_pwd = 85,
2254 .vcm_pwd = 1,
2255 .vcm_enable = 0,
2256 .pdata = &msm_camera_device_data_web_cam,
2257 .resource = msm_camera_resources,
2258 .num_resources = ARRAY_SIZE(msm_camera_resources),
2259 .flash_data = &flash_ov9726,
2260 .sensor_platform_info = &ov9726_sensor_8660_info,
2261 .csi_if = 1
2262};
2263struct platform_device msm_camera_sensor_webcam_ov9726 = {
2264 .name = "msm_camera_ov9726",
2265 .dev = {
2266 .platform_data = &msm_camera_sensor_ov9726_data,
2267 },
2268};
2269#endif
2270#ifdef CONFIG_WEBCAM_OV7692
2271static struct msm_camera_sensor_flash_data flash_ov7692 = {
2272 .flash_type = MSM_CAMERA_FLASH_LED,
2273 .flash_src = &msm_flash_src
2274};
2275static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2276 .sensor_name = "ov7692",
2277 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2278 .sensor_pwd = 85,
2279 .vcm_pwd = 1,
2280 .vcm_enable = 0,
2281 .pdata = &msm_camera_device_data_web_cam,
2282 .resource = msm_camera_resources,
2283 .num_resources = ARRAY_SIZE(msm_camera_resources),
2284 .flash_data = &flash_ov7692,
2285 .csi_if = 1
2286};
2287
2288static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2289 .name = "msm_camera_ov7692",
2290 .dev = {
2291 .platform_data = &msm_camera_sensor_ov7692_data,
2292 },
2293};
2294#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002295#ifdef CONFIG_VX6953
2296static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2297 .mount_angle = 270
2298};
2299
2300static struct msm_camera_sensor_flash_data flash_vx6953 = {
2301 .flash_type = MSM_CAMERA_FLASH_NONE,
2302 .flash_src = &msm_flash_src
2303};
2304
2305static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2306 .sensor_name = "vx6953",
2307 .sensor_reset = 63,
2308 .sensor_pwd = 63,
2309 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2310 .vcm_enable = 1,
2311 .pdata = &msm_camera_device_data,
2312 .resource = msm_camera_resources,
2313 .num_resources = ARRAY_SIZE(msm_camera_resources),
2314 .flash_data = &flash_vx6953,
2315 .sensor_platform_info = &vx6953_sensor_8660_info,
2316 .csi_if = 1
2317};
2318struct platform_device msm_camera_sensor_vx6953 = {
2319 .name = "msm_camera_vx6953",
2320 .dev = {
2321 .platform_data = &msm_camera_sensor_vx6953_data,
2322 },
2323};
2324#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002325#ifdef CONFIG_QS_S5K4E1
2326
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302327static struct msm_camera_sensor_platform_info qs_s5k4e1_sensor_8660_info = {
2328#ifdef CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
2329 .mount_angle = 90
2330#else
2331 .mount_angle = 0
2332#endif
2333};
2334
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002335static char eeprom_data[864];
2336static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2337 .flash_type = MSM_CAMERA_FLASH_LED,
2338 .flash_src = &msm_flash_src
2339};
2340
2341static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2342 .sensor_name = "qs_s5k4e1",
2343 .sensor_reset = 106,
2344 .sensor_pwd = 85,
2345 .vcm_pwd = 1,
2346 .vcm_enable = 0,
2347 .pdata = &msm_camera_device_data_qs_cam,
2348 .resource = msm_camera_resources,
2349 .num_resources = ARRAY_SIZE(msm_camera_resources),
2350 .flash_data = &flash_qs_s5k4e1,
2351 .strobe_flash_data = &strobe_flash_xenon,
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302352 .sensor_platform_info = &qs_s5k4e1_sensor_8660_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002353 .csi_if = 1,
2354 .eeprom_data = eeprom_data,
2355};
2356struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2357 .name = "msm_camera_qs_s5k4e1",
2358 .dev = {
2359 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2360 },
2361};
2362#endif
2363static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2364 #ifdef CONFIG_MT9E013
2365 {
2366 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2367 },
2368 #endif
2369 #ifdef CONFIG_IMX074
2370 {
2371 I2C_BOARD_INFO("imx074", 0x1A),
2372 },
2373 #endif
2374 #ifdef CONFIG_WEBCAM_OV7692
2375 {
2376 I2C_BOARD_INFO("ov7692", 0x78),
2377 },
2378 #endif
2379 #ifdef CONFIG_WEBCAM_OV9726
2380 {
2381 I2C_BOARD_INFO("ov9726", 0x10),
2382 },
2383 #endif
2384 #ifdef CONFIG_QS_S5K4E1
2385 {
2386 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2387 },
2388 #endif
2389};
Jilai Wang971f97f2011-07-13 14:25:25 -04002390
2391static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002392 #ifdef CONFIG_WEBCAM_OV9726
2393 {
2394 I2C_BOARD_INFO("ov9726", 0x10),
2395 },
2396 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002397 #ifdef CONFIG_VX6953
2398 {
2399 I2C_BOARD_INFO("vx6953", 0x20),
2400 },
2401 #endif
2402};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002403#endif
2404
2405#ifdef CONFIG_MSM_GEMINI
2406static struct resource msm_gemini_resources[] = {
2407 {
2408 .start = 0x04600000,
2409 .end = 0x04600000 + SZ_1M - 1,
2410 .flags = IORESOURCE_MEM,
2411 },
2412 {
2413 .start = INT_JPEG,
2414 .end = INT_JPEG,
2415 .flags = IORESOURCE_IRQ,
2416 },
2417};
2418
2419static struct platform_device msm_gemini_device = {
2420 .name = "msm_gemini",
2421 .resource = msm_gemini_resources,
2422 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2423};
2424#endif
2425
2426#ifdef CONFIG_I2C_QUP
2427static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2428{
2429}
2430
2431static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2432 .clk_freq = 384000,
2433 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002434 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2435};
2436
2437static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2438 .clk_freq = 100000,
2439 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002440 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2441};
2442
2443static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2444 .clk_freq = 100000,
2445 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002446 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2447};
2448
2449static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2450 .clk_freq = 100000,
2451 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002452 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2453};
2454
2455static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2456 .clk_freq = 100000,
2457 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002458 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2459};
2460
2461static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2462 .clk_freq = 100000,
2463 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002464 .use_gsbi_shared_mode = 1,
2465 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2466};
2467#endif
2468
2469#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2470static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2471 .max_clock_speed = 24000000,
2472};
2473
2474static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2475 .max_clock_speed = 24000000,
2476};
2477#endif
2478
2479#ifdef CONFIG_I2C_SSBI
2480/* PMIC SSBI */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002481static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2482 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2483};
2484
2485/* CODEC/TSSC SSBI */
2486static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2487 .controller_type = MSM_SBI_CTRL_SSBI,
2488};
2489#endif
2490
2491#ifdef CONFIG_BATTERY_MSM
2492/* Use basic value for fake MSM battery */
2493static struct msm_psy_batt_pdata msm_psy_batt_data = {
2494 .avail_chg_sources = AC_CHG,
2495};
2496
2497static struct platform_device msm_batt_device = {
2498 .name = "msm-battery",
2499 .id = -1,
2500 .dev.platform_data = &msm_psy_batt_data,
2501};
2502#endif
2503
2504#ifdef CONFIG_FB_MSM_LCDC_DSUB
2505/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2506 prim = 1024 x 600 x 4(bpp) x 2(pages)
2507 This is the difference. */
2508#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2509#else
2510#define MSM_FB_DSUB_PMEM_ADDER (0)
2511#endif
2512
2513/* Sensors DSPS platform data */
2514#ifdef CONFIG_MSM_DSPS
2515
2516static struct dsps_gpio_info dsps_surf_gpios[] = {
2517 {
2518 .name = "compass_rst_n",
2519 .num = GPIO_COMPASS_RST_N,
2520 .on_val = 1, /* device not in reset */
2521 .off_val = 0, /* device in reset */
2522 },
2523 {
2524 .name = "gpio_r_altimeter_reset_n",
2525 .num = GPIO_R_ALTIMETER_RESET_N,
2526 .on_val = 1, /* device not in reset */
2527 .off_val = 0, /* device in reset */
2528 }
2529};
2530
2531static struct dsps_gpio_info dsps_fluid_gpios[] = {
2532 {
2533 .name = "gpio_n_altimeter_reset_n",
2534 .num = GPIO_N_ALTIMETER_RESET_N,
2535 .on_val = 1, /* device not in reset */
2536 .off_val = 0, /* device in reset */
2537 }
2538};
2539
2540static void __init msm8x60_init_dsps(void)
2541{
2542 struct msm_dsps_platform_data *pdata =
2543 msm_dsps_device.dev.platform_data;
2544 /*
2545 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2546 * to the power supply and not controled via GPIOs. Fluid uses a
2547 * different IO-Expender (north) than used on surf/ffa.
2548 */
2549 if (machine_is_msm8x60_fluid()) {
2550 /* fluid has different firmware, gpios */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002551 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2552 pdata->gpios = dsps_fluid_gpios;
2553 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2554 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002555 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2556 pdata->gpios = dsps_surf_gpios;
2557 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2558 }
2559
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002560 platform_device_register(&msm_dsps_device);
2561}
2562#endif /* CONFIG_MSM_DSPS */
2563
2564#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002565#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002566#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002567#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002568#endif
2569
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002570#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2571#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
2572#elif defined(CONFIG_FB_MSM_TVOUT)
2573#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
2574#else
2575#define MSM_FB_EXT_BUFT_SIZE 0
2576#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002577
2578#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002579/* width x height x 3 bpp x 2 frame buffer */
2580#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002581#define MSM_FB_WRITEBACK_OFFSET \
2582 (MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002583#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002584#define MSM_FB_WRITEBACK_SIZE 0
2585#define MSM_FB_WRITEBACK_OFFSET 0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002586#endif
2587
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002588#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2589/* 4 bpp x 2 page HDMI case */
2590#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
2591#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002592/* Note: must be multiple of 4096 */
2593#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
2594 MSM_FB_WRITEBACK_SIZE + \
2595 MSM_FB_DSUB_PMEM_ADDER, 4096)
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002596#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002597
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002598#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2599#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
2600#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002601#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002602#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002603
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002604static int writeback_offset(void)
2605{
2606 return MSM_FB_WRITEBACK_OFFSET;
2607}
2608
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002609#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2610#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002611#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002612
2613#define MSM_SMI_BASE 0x38000000
2614#define MSM_SMI_SIZE 0x4000000
2615
2616#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2617#define KERNEL_SMI_SIZE 0x300000
2618
2619#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2620#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2621#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2622
2623static unsigned fb_size;
2624static int __init fb_size_setup(char *p)
2625{
2626 fb_size = memparse(p, NULL);
2627 return 0;
2628}
2629early_param("fb_size", fb_size_setup);
2630
2631static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2632static int __init pmem_kernel_ebi1_size_setup(char *p)
2633{
2634 pmem_kernel_ebi1_size = memparse(p, NULL);
2635 return 0;
2636}
2637early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2638
2639#ifdef CONFIG_ANDROID_PMEM
2640static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2641static int __init pmem_sf_size_setup(char *p)
2642{
2643 pmem_sf_size = memparse(p, NULL);
2644 return 0;
2645}
2646early_param("pmem_sf_size", pmem_sf_size_setup);
2647
2648static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2649
2650static int __init pmem_adsp_size_setup(char *p)
2651{
2652 pmem_adsp_size = memparse(p, NULL);
2653 return 0;
2654}
2655early_param("pmem_adsp_size", pmem_adsp_size_setup);
2656
2657static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2658
2659static int __init pmem_audio_size_setup(char *p)
2660{
2661 pmem_audio_size = memparse(p, NULL);
2662 return 0;
2663}
2664early_param("pmem_audio_size", pmem_audio_size_setup);
2665#endif
2666
2667static struct resource msm_fb_resources[] = {
2668 {
2669 .flags = IORESOURCE_DMA,
2670 }
2671};
2672
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002673static int msm_fb_detect_panel(const char *name)
2674{
2675 if (machine_is_msm8x60_fluid()) {
2676 uint32_t soc_platform_version = socinfo_get_platform_version();
2677 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2678#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2679 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002680 strnlen(LCDC_SAMSUNG_OLED_PANEL_NAME,
2681 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002682 return 0;
2683#endif
2684 } else { /*P3 and up use AUO panel */
2685#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2686 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002687 strnlen(LCDC_AUO_PANEL_NAME,
2688 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002689 return 0;
2690#endif
2691 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002692#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2693 } else if machine_is_msm8x60_dragon() {
2694 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002695 strnlen(LCDC_NT35582_PANEL_NAME,
2696 PANEL_NAME_MAX_LEN)))
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002697 return 0;
2698#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002699 } else {
2700 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002701 strnlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2702 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002703 return 0;
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002704
2705#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
2706 !defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
2707 !defined(CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT)
2708 if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2709 strnlen(MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2710 PANEL_NAME_MAX_LEN)))
2711 return 0;
2712
2713 if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2714 strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2715 PANEL_NAME_MAX_LEN)))
2716 return 0;
2717
2718 if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2719 strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2720 PANEL_NAME_MAX_LEN)))
2721 return 0;
2722#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002723 }
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002724
2725 if (!strncmp(name, HDMI_PANEL_NAME,
2726 strnlen(HDMI_PANEL_NAME,
2727 PANEL_NAME_MAX_LEN)))
2728 return 0;
2729
2730 if (!strncmp(name, TVOUT_PANEL_NAME,
2731 strnlen(TVOUT_PANEL_NAME,
2732 PANEL_NAME_MAX_LEN)))
2733 return 0;
2734
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002735 pr_warning("%s: not supported '%s'", __func__, name);
2736 return -ENODEV;
2737}
2738
2739static struct msm_fb_platform_data msm_fb_pdata = {
2740 .detect_client = msm_fb_detect_panel,
2741};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002742
2743static struct platform_device msm_fb_device = {
2744 .name = "msm_fb",
2745 .id = 0,
2746 .num_resources = ARRAY_SIZE(msm_fb_resources),
2747 .resource = msm_fb_resources,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002748 .dev.platform_data = &msm_fb_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002749};
2750
2751#ifdef CONFIG_ANDROID_PMEM
2752static struct android_pmem_platform_data android_pmem_pdata = {
2753 .name = "pmem",
2754 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2755 .cached = 1,
2756 .memory_type = MEMTYPE_EBI1,
2757};
2758
2759static struct platform_device android_pmem_device = {
2760 .name = "android_pmem",
2761 .id = 0,
2762 .dev = {.platform_data = &android_pmem_pdata},
2763};
2764
2765static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2766 .name = "pmem_adsp",
2767 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2768 .cached = 0,
2769 .memory_type = MEMTYPE_EBI1,
2770};
2771
2772static struct platform_device android_pmem_adsp_device = {
2773 .name = "android_pmem",
2774 .id = 2,
2775 .dev = { .platform_data = &android_pmem_adsp_pdata },
2776};
2777
2778static struct android_pmem_platform_data android_pmem_audio_pdata = {
2779 .name = "pmem_audio",
2780 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2781 .cached = 0,
2782 .memory_type = MEMTYPE_EBI1,
2783};
2784
2785static struct platform_device android_pmem_audio_device = {
2786 .name = "android_pmem",
2787 .id = 4,
2788 .dev = { .platform_data = &android_pmem_audio_pdata },
2789};
2790
Laura Abbott1e36a022011-06-22 17:08:13 -07002791#define PMEM_BUS_WIDTH(_bw) \
2792 { \
2793 .vectors = &(struct msm_bus_vectors){ \
2794 .src = MSM_BUS_MASTER_AMPSS_M0, \
2795 .dst = MSM_BUS_SLAVE_SMI, \
2796 .ib = (_bw), \
2797 .ab = 0, \
2798 }, \
2799 .num_paths = 1, \
2800 }
2801static struct msm_bus_paths pmem_smi_table[] = {
2802 [0] = PMEM_BUS_WIDTH(0), /* Off */
2803 [1] = PMEM_BUS_WIDTH(1), /* On */
2804};
2805
2806static struct msm_bus_scale_pdata smi_client_pdata = {
2807 .usecase = pmem_smi_table,
2808 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2809 .name = "pmem_smi",
2810};
2811
2812void pmem_request_smi_region(void *data)
2813{
2814 int bus_id = (int) data;
2815
2816 msm_bus_scale_client_update_request(bus_id, 1);
2817}
2818
2819void pmem_release_smi_region(void *data)
2820{
2821 int bus_id = (int) data;
2822
2823 msm_bus_scale_client_update_request(bus_id, 0);
2824}
2825
2826void *pmem_setup_smi_region(void)
2827{
2828 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2829}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002830static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2831 .name = "pmem_smipool",
2832 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2833 .cached = 0,
2834 .memory_type = MEMTYPE_SMI,
Laura Abbott1e36a022011-06-22 17:08:13 -07002835 .request_region = pmem_request_smi_region,
2836 .release_region = pmem_release_smi_region,
2837 .setup_region = pmem_setup_smi_region,
2838 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002839};
2840static struct platform_device android_pmem_smipool_device = {
2841 .name = "android_pmem",
2842 .id = 7,
2843 .dev = { .platform_data = &android_pmem_smipool_pdata },
2844};
2845
2846#endif
2847
2848#define GPIO_DONGLE_PWR_EN 258
2849static void setup_display_power(void);
2850static int lcdc_vga_enabled;
2851static int vga_enable_request(int enable)
2852{
2853 if (enable)
2854 lcdc_vga_enabled = 1;
2855 else
2856 lcdc_vga_enabled = 0;
2857 setup_display_power();
2858
2859 return 0;
2860}
2861
2862#define GPIO_BACKLIGHT_PWM0 0
2863#define GPIO_BACKLIGHT_PWM1 1
2864
2865static int pmic_backlight_gpio[2]
2866 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2867static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2868 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2869 .vga_switch = vga_enable_request,
2870};
2871
2872static struct platform_device lcdc_samsung_panel_device = {
2873 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2874 .id = 0,
2875 .dev = {
2876 .platform_data = &lcdc_samsung_panel_data,
2877 }
2878};
2879#if (!defined(CONFIG_SPI_QUP)) && \
2880 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2881 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2882
2883static int lcdc_spi_gpio_array_num[] = {
2884 LCDC_SPI_GPIO_CLK,
2885 LCDC_SPI_GPIO_CS,
2886 LCDC_SPI_GPIO_MOSI,
2887};
2888
2889static uint32_t lcdc_spi_gpio_config_data[] = {
2890 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2891 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2892 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2893 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2894 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2895 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2896};
2897
2898static void lcdc_config_spi_gpios(int enable)
2899{
2900 int n;
2901 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2902 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2903}
2904#endif
2905
2906#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2907#ifdef CONFIG_SPI_QUP
2908static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2909 {
2910 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2911 .mode = SPI_MODE_3,
2912 .bus_num = 1,
2913 .chip_select = 0,
2914 .max_speed_hz = 10800000,
2915 }
2916};
2917#endif /* CONFIG_SPI_QUP */
2918
2919static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2920#ifndef CONFIG_SPI_QUP
2921 .panel_config_gpio = lcdc_config_spi_gpios,
2922 .gpio_num = lcdc_spi_gpio_array_num,
2923#endif
2924};
2925
2926static struct platform_device lcdc_samsung_oled_panel_device = {
2927 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2928 .id = 0,
2929 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2930};
2931#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2932
2933#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2934#ifdef CONFIG_SPI_QUP
2935static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2936 {
2937 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2938 .mode = SPI_MODE_3,
2939 .bus_num = 1,
2940 .chip_select = 0,
2941 .max_speed_hz = 10800000,
2942 }
2943};
2944#endif
2945
2946static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
2947#ifndef CONFIG_SPI_QUP
2948 .panel_config_gpio = lcdc_config_spi_gpios,
2949 .gpio_num = lcdc_spi_gpio_array_num,
2950#endif
2951};
2952
2953static struct platform_device lcdc_auo_wvga_panel_device = {
2954 .name = LCDC_AUO_PANEL_NAME,
2955 .id = 0,
2956 .dev.platform_data = &lcdc_auo_wvga_panel_data,
2957};
2958#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
2959
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002960#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2961
2962#define GPIO_NT35582_RESET 94
2963#define GPIO_NT35582_BL_EN_HW_PIN 24
2964#define GPIO_NT35582_BL_EN \
2965 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
2966
2967static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
2968
2969static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
2970 .gpio_num = lcdc_nt35582_pmic_gpio,
2971};
2972
2973static struct platform_device lcdc_nt35582_panel_device = {
2974 .name = LCDC_NT35582_PANEL_NAME,
2975 .id = 0,
2976 .dev = {
2977 .platform_data = &lcdc_nt35582_panel_data,
2978 }
2979};
2980
2981static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
2982 {
2983 .modalias = "lcdc_nt35582_spi",
2984 .mode = SPI_MODE_0,
2985 .bus_num = 0,
2986 .chip_select = 0,
2987 .max_speed_hz = 1100000,
2988 }
2989};
2990#endif
2991
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002992#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2993static struct resource hdmi_msm_resources[] = {
2994 {
2995 .name = "hdmi_msm_qfprom_addr",
2996 .start = 0x00700000,
2997 .end = 0x007060FF,
2998 .flags = IORESOURCE_MEM,
2999 },
3000 {
3001 .name = "hdmi_msm_hdmi_addr",
3002 .start = 0x04A00000,
3003 .end = 0x04A00FFF,
3004 .flags = IORESOURCE_MEM,
3005 },
3006 {
3007 .name = "hdmi_msm_irq",
3008 .start = HDMI_IRQ,
3009 .end = HDMI_IRQ,
3010 .flags = IORESOURCE_IRQ,
3011 },
3012};
3013
3014static int hdmi_enable_5v(int on);
3015static int hdmi_core_power(int on, int show);
3016static int hdmi_cec_power(int on);
3017
3018static struct msm_hdmi_platform_data hdmi_msm_data = {
3019 .irq = HDMI_IRQ,
3020 .enable_5v = hdmi_enable_5v,
3021 .core_power = hdmi_core_power,
3022 .cec_power = hdmi_cec_power,
3023};
3024
3025static struct platform_device hdmi_msm_device = {
3026 .name = "hdmi_msm",
3027 .id = 0,
3028 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
3029 .resource = hdmi_msm_resources,
3030 .dev.platform_data = &hdmi_msm_data,
3031};
3032#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
3033
3034#ifdef CONFIG_FB_MSM_MIPI_DSI
3035static struct platform_device mipi_dsi_toshiba_panel_device = {
3036 .name = "mipi_toshiba",
3037 .id = 0,
3038};
3039
3040#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3041
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003042static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003043 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
Chandan Uddaraju83eac3c2011-09-11 18:32:23 -07003044 .fpga_ctrl_mode = FPGA_EBI2_INTF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003045};
3046
3047static struct platform_device mipi_dsi_novatek_panel_device = {
3048 .name = "mipi_novatek",
3049 .id = 0,
3050 .dev = {
3051 .platform_data = &novatek_pdata,
3052 }
3053};
3054#endif
3055
3056static void __init msm8x60_allocate_memory_regions(void)
3057{
3058 void *addr;
3059 unsigned long size;
3060
3061 size = MSM_FB_SIZE;
3062 addr = alloc_bootmem_align(size, 0x1000);
3063 msm_fb_resources[0].start = __pa(addr);
3064 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3065 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3066 size, addr, __pa(addr));
3067
3068}
3069
3070#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3071 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3072/*virtual key support */
3073static ssize_t tma300_vkeys_show(struct kobject *kobj,
3074 struct kobj_attribute *attr, char *buf)
3075{
3076 return sprintf(buf,
3077 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3078 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3079 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3080 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3081 "\n");
3082}
3083
3084static struct kobj_attribute tma300_vkeys_attr = {
3085 .attr = {
3086 .mode = S_IRUGO,
3087 },
3088 .show = &tma300_vkeys_show,
3089};
3090
3091static struct attribute *tma300_properties_attrs[] = {
3092 &tma300_vkeys_attr.attr,
3093 NULL
3094};
3095
3096static struct attribute_group tma300_properties_attr_group = {
3097 .attrs = tma300_properties_attrs,
3098};
3099
3100static struct kobject *properties_kobj;
3101
3102
3103
3104#define CYTTSP_TS_GPIO_IRQ 61
3105static int cyttsp_platform_init(struct i2c_client *client)
3106{
3107 int rc = -EINVAL;
3108 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3109
3110 if (machine_is_msm8x60_fluid()) {
3111 pm8058_l5 = regulator_get(NULL, "8058_l5");
3112 if (IS_ERR(pm8058_l5)) {
3113 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3114 __func__, PTR_ERR(pm8058_l5));
3115 rc = PTR_ERR(pm8058_l5);
3116 return rc;
3117 }
3118 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3119 if (rc) {
3120 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3121 __func__, rc);
3122 goto reg_l5_put;
3123 }
3124
3125 rc = regulator_enable(pm8058_l5);
3126 if (rc) {
3127 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3128 __func__, rc);
3129 goto reg_l5_put;
3130 }
3131 }
3132 /* vote for s3 to enable i2c communication lines */
3133 pm8058_s3 = regulator_get(NULL, "8058_s3");
3134 if (IS_ERR(pm8058_s3)) {
3135 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3136 __func__, PTR_ERR(pm8058_s3));
3137 rc = PTR_ERR(pm8058_s3);
3138 goto reg_l5_disable;
3139 }
3140
3141 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3142 if (rc) {
3143 pr_err("%s: regulator_set_voltage() = %d\n",
3144 __func__, rc);
3145 goto reg_s3_put;
3146 }
3147
3148 rc = regulator_enable(pm8058_s3);
3149 if (rc) {
3150 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3151 __func__, rc);
3152 goto reg_s3_put;
3153 }
3154
3155 /* wait for vregs to stabilize */
3156 usleep_range(10000, 10000);
3157
3158 /* check this device active by reading first byte/register */
3159 rc = i2c_smbus_read_byte_data(client, 0x01);
3160 if (rc < 0) {
3161 pr_err("%s: i2c sanity check failed\n", __func__);
3162 goto reg_s3_disable;
3163 }
3164
3165 /* virtual keys */
3166 if (machine_is_msm8x60_fluid()) {
3167 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3168 properties_kobj = kobject_create_and_add("board_properties",
3169 NULL);
3170 if (properties_kobj)
3171 rc = sysfs_create_group(properties_kobj,
3172 &tma300_properties_attr_group);
3173 if (!properties_kobj || rc)
3174 pr_err("%s: failed to create board_properties\n",
3175 __func__);
3176 }
3177 return CY_OK;
3178
3179reg_s3_disable:
3180 regulator_disable(pm8058_s3);
3181reg_s3_put:
3182 regulator_put(pm8058_s3);
3183reg_l5_disable:
3184 if (machine_is_msm8x60_fluid())
3185 regulator_disable(pm8058_l5);
3186reg_l5_put:
3187 if (machine_is_msm8x60_fluid())
3188 regulator_put(pm8058_l5);
3189 return rc;
3190}
3191
3192static int cyttsp_platform_resume(struct i2c_client *client)
3193{
3194 /* add any special code to strobe a wakeup pin or chip reset */
3195 msleep(10);
3196
3197 return CY_OK;
3198}
3199
3200static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3201 .flags = 0x04,
3202 .gen = CY_GEN3, /* or */
3203 .use_st = CY_USE_ST,
3204 .use_mt = CY_USE_MT,
3205 .use_hndshk = CY_SEND_HNDSHK,
3206 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303207 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003208 .use_gestures = CY_USE_GESTURES,
3209 /* activate up to 4 groups
3210 * and set active distance
3211 */
3212 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3213 CY_GEST_GRP3 | CY_GEST_GRP4 |
3214 CY_ACT_DIST,
3215 /* change act_intrvl to customize the Active power state
3216 * scanning/processing refresh interval for Operating mode
3217 */
3218 .act_intrvl = CY_ACT_INTRVL_DFLT,
3219 /* change tch_tmout to customize the touch timeout for the
3220 * Active power state for Operating mode
3221 */
3222 .tch_tmout = CY_TCH_TMOUT_DFLT,
3223 /* change lp_intrvl to customize the Low Power power state
3224 * scanning/processing refresh interval for Operating mode
3225 */
3226 .lp_intrvl = CY_LP_INTRVL_DFLT,
3227 .sleep_gpio = -1,
3228 .resout_gpio = -1,
3229 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3230 .resume = cyttsp_platform_resume,
3231 .init = cyttsp_platform_init,
3232};
3233
3234static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3235 .panel_maxx = 1083,
3236 .panel_maxy = 659,
3237 .disp_minx = 30,
3238 .disp_maxx = 1053,
3239 .disp_miny = 30,
3240 .disp_maxy = 629,
3241 .correct_fw_ver = 8,
3242 .fw_fname = "cyttsp_8660_ffa.hex",
3243 .flags = 0x00,
3244 .gen = CY_GEN2, /* or */
3245 .use_st = CY_USE_ST,
3246 .use_mt = CY_USE_MT,
3247 .use_hndshk = CY_SEND_HNDSHK,
3248 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303249 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003250 .use_gestures = CY_USE_GESTURES,
3251 /* activate up to 4 groups
3252 * and set active distance
3253 */
3254 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3255 CY_GEST_GRP3 | CY_GEST_GRP4 |
3256 CY_ACT_DIST,
3257 /* change act_intrvl to customize the Active power state
3258 * scanning/processing refresh interval for Operating mode
3259 */
3260 .act_intrvl = CY_ACT_INTRVL_DFLT,
3261 /* change tch_tmout to customize the touch timeout for the
3262 * Active power state for Operating mode
3263 */
3264 .tch_tmout = CY_TCH_TMOUT_DFLT,
3265 /* change lp_intrvl to customize the Low Power power state
3266 * scanning/processing refresh interval for Operating mode
3267 */
3268 .lp_intrvl = CY_LP_INTRVL_DFLT,
3269 .sleep_gpio = -1,
3270 .resout_gpio = -1,
3271 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3272 .resume = cyttsp_platform_resume,
3273 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303274 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003275};
3276static void cyttsp_set_params(void)
3277{
3278 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3279 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3280 cyttsp_fluid_pdata.panel_maxx = 539;
3281 cyttsp_fluid_pdata.panel_maxy = 994;
3282 cyttsp_fluid_pdata.disp_minx = 30;
3283 cyttsp_fluid_pdata.disp_maxx = 509;
3284 cyttsp_fluid_pdata.disp_miny = 60;
3285 cyttsp_fluid_pdata.disp_maxy = 859;
3286 cyttsp_fluid_pdata.correct_fw_ver = 4;
3287 } else {
3288 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3289 cyttsp_fluid_pdata.panel_maxx = 550;
3290 cyttsp_fluid_pdata.panel_maxy = 1013;
3291 cyttsp_fluid_pdata.disp_minx = 35;
3292 cyttsp_fluid_pdata.disp_maxx = 515;
3293 cyttsp_fluid_pdata.disp_miny = 69;
3294 cyttsp_fluid_pdata.disp_maxy = 869;
3295 cyttsp_fluid_pdata.correct_fw_ver = 5;
3296 }
3297
3298}
3299
3300static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3301 {
3302 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3303 .platform_data = &cyttsp_fluid_pdata,
3304#ifndef CY_USE_TIMER
3305 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3306#endif /* CY_USE_TIMER */
3307 },
3308};
3309
3310static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3311 {
3312 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3313 .platform_data = &cyttsp_tmg240_pdata,
3314#ifndef CY_USE_TIMER
3315 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3316#endif /* CY_USE_TIMER */
3317 },
3318};
3319#endif
3320
3321static struct regulator *vreg_tmg200;
3322
3323#define TS_PEN_IRQ_GPIO 61
3324static int tmg200_power(int vreg_on)
3325{
3326 int rc = -EINVAL;
3327
3328 if (!vreg_tmg200) {
3329 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3330 __func__, rc);
3331 return rc;
3332 }
3333
3334 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3335 regulator_disable(vreg_tmg200);
3336 if (rc < 0)
3337 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3338 __func__, vreg_on ? "enable" : "disable", rc);
3339
3340 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003341 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003342
3343 return rc;
3344}
3345
3346static int tmg200_dev_setup(bool enable)
3347{
3348 int rc;
3349
3350 if (enable) {
3351 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3352 if (IS_ERR(vreg_tmg200)) {
3353 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3354 __func__, PTR_ERR(vreg_tmg200));
3355 rc = PTR_ERR(vreg_tmg200);
3356 return rc;
3357 }
3358
3359 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3360 if (rc) {
3361 pr_err("%s: regulator_set_voltage() = %d\n",
3362 __func__, rc);
3363 goto reg_put;
3364 }
3365 } else {
3366 /* put voltage sources */
3367 regulator_put(vreg_tmg200);
3368 }
3369 return 0;
3370reg_put:
3371 regulator_put(vreg_tmg200);
3372 return rc;
3373}
3374
3375static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3376 .ts_name = "msm_tmg200_ts",
3377 .dis_min_x = 0,
3378 .dis_max_x = 1023,
3379 .dis_min_y = 0,
3380 .dis_max_y = 599,
3381 .min_tid = 0,
3382 .max_tid = 255,
3383 .min_touch = 0,
3384 .max_touch = 255,
3385 .min_width = 0,
3386 .max_width = 255,
3387 .power_on = tmg200_power,
3388 .dev_setup = tmg200_dev_setup,
3389 .nfingers = 2,
3390 .irq_gpio = TS_PEN_IRQ_GPIO,
3391 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3392};
3393
3394static struct i2c_board_info cy8ctmg200_board_info[] = {
3395 {
3396 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3397 .platform_data = &cy8ctmg200_pdata,
3398 }
3399};
3400
Zhang Chang Ken211df572011-07-05 19:16:39 -04003401static struct regulator *vreg_tma340;
3402
3403static int tma340_power(int vreg_on)
3404{
3405 int rc = -EINVAL;
3406
3407 if (!vreg_tma340) {
3408 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3409 __func__, rc);
3410 return rc;
3411 }
3412
3413 rc = vreg_on ? regulator_enable(vreg_tma340) :
3414 regulator_disable(vreg_tma340);
3415 if (rc < 0)
3416 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3417 __func__, vreg_on ? "enable" : "disable", rc);
3418
3419 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003420 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003421
3422 return rc;
3423}
3424
3425static struct kobject *tma340_prop_kobj;
3426
3427static int tma340_dragon_dev_setup(bool enable)
3428{
3429 int rc;
3430
3431 if (enable) {
3432 vreg_tma340 = regulator_get(NULL, "8901_l2");
3433 if (IS_ERR(vreg_tma340)) {
3434 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3435 __func__, PTR_ERR(vreg_tma340));
3436 rc = PTR_ERR(vreg_tma340);
3437 return rc;
3438 }
3439
3440 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3441 if (rc) {
3442 pr_err("%s: regulator_set_voltage() = %d\n",
3443 __func__, rc);
3444 goto reg_put;
3445 }
3446 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3447 tma340_prop_kobj = kobject_create_and_add("board_properties",
3448 NULL);
3449 if (tma340_prop_kobj) {
3450 rc = sysfs_create_group(tma340_prop_kobj,
3451 &tma300_properties_attr_group);
3452 if (rc) {
3453 kobject_put(tma340_prop_kobj);
3454 pr_err("%s: failed to create board_properties\n",
3455 __func__);
3456 goto reg_put;
3457 }
3458 }
3459
3460 } else {
3461 /* put voltage sources */
3462 regulator_put(vreg_tma340);
3463 /* destroy virtual keys */
3464 if (tma340_prop_kobj) {
3465 sysfs_remove_group(tma340_prop_kobj,
3466 &tma300_properties_attr_group);
3467 kobject_put(tma340_prop_kobj);
3468 }
3469 }
3470 return 0;
3471reg_put:
3472 regulator_put(vreg_tma340);
3473 return rc;
3474}
3475
3476
3477static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3478 .ts_name = "cy8ctma340",
3479 .dis_min_x = 0,
3480 .dis_max_x = 479,
3481 .dis_min_y = 0,
3482 .dis_max_y = 799,
3483 .min_tid = 0,
3484 .max_tid = 255,
3485 .min_touch = 0,
3486 .max_touch = 255,
3487 .min_width = 0,
3488 .max_width = 255,
3489 .power_on = tma340_power,
3490 .dev_setup = tma340_dragon_dev_setup,
3491 .nfingers = 2,
3492 .irq_gpio = TS_PEN_IRQ_GPIO,
3493 .resout_gpio = -1,
3494};
3495
3496static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3497 {
3498 I2C_BOARD_INFO("cy8ctma340", 0x24),
3499 .platform_data = &cy8ctma340_dragon_pdata,
3500 }
3501};
3502
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003503#ifdef CONFIG_SERIAL_MSM_HS
3504static int configure_uart_gpios(int on)
3505{
3506 int ret = 0, i;
3507 int uart_gpios[] = {53, 54, 55, 56};
3508 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3509 if (on) {
3510 ret = msm_gpiomux_get(uart_gpios[i]);
3511 if (unlikely(ret))
3512 break;
3513 } else {
3514 ret = msm_gpiomux_put(uart_gpios[i]);
3515 if (unlikely(ret))
3516 return ret;
3517 }
3518 }
3519 if (ret)
3520 for (; i >= 0; i--)
3521 msm_gpiomux_put(uart_gpios[i]);
3522 return ret;
3523}
3524static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3525 .inject_rx_on_wakeup = 1,
3526 .rx_to_inject = 0xFD,
3527 .gpio_config = configure_uart_gpios,
3528};
3529#endif
3530
3531
3532#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3533
3534static struct gpio_led gpio_exp_leds_config[] = {
3535 {
3536 .name = "left_led1:green",
3537 .gpio = GPIO_LEFT_LED_1,
3538 .active_low = 1,
3539 .retain_state_suspended = 0,
3540 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3541 },
3542 {
3543 .name = "left_led2:red",
3544 .gpio = GPIO_LEFT_LED_2,
3545 .active_low = 1,
3546 .retain_state_suspended = 0,
3547 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3548 },
3549 {
3550 .name = "left_led3:green",
3551 .gpio = GPIO_LEFT_LED_3,
3552 .active_low = 1,
3553 .retain_state_suspended = 0,
3554 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3555 },
3556 {
3557 .name = "wlan_led:orange",
3558 .gpio = GPIO_LEFT_LED_WLAN,
3559 .active_low = 1,
3560 .retain_state_suspended = 0,
3561 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3562 },
3563 {
3564 .name = "left_led5:green",
3565 .gpio = GPIO_LEFT_LED_5,
3566 .active_low = 1,
3567 .retain_state_suspended = 0,
3568 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3569 },
3570 {
3571 .name = "right_led1:green",
3572 .gpio = GPIO_RIGHT_LED_1,
3573 .active_low = 1,
3574 .retain_state_suspended = 0,
3575 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3576 },
3577 {
3578 .name = "right_led2:red",
3579 .gpio = GPIO_RIGHT_LED_2,
3580 .active_low = 1,
3581 .retain_state_suspended = 0,
3582 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3583 },
3584 {
3585 .name = "right_led3:green",
3586 .gpio = GPIO_RIGHT_LED_3,
3587 .active_low = 1,
3588 .retain_state_suspended = 0,
3589 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3590 },
3591 {
3592 .name = "bt_led:blue",
3593 .gpio = GPIO_RIGHT_LED_BT,
3594 .active_low = 1,
3595 .retain_state_suspended = 0,
3596 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3597 },
3598 {
3599 .name = "right_led5:green",
3600 .gpio = GPIO_RIGHT_LED_5,
3601 .active_low = 1,
3602 .retain_state_suspended = 0,
3603 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3604 },
3605};
3606
3607static struct gpio_led_platform_data gpio_leds_pdata = {
3608 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3609 .leds = gpio_exp_leds_config,
3610};
3611
3612static struct platform_device gpio_leds = {
3613 .name = "leds-gpio",
3614 .id = -1,
3615 .dev = {
3616 .platform_data = &gpio_leds_pdata,
3617 },
3618};
3619
3620static struct gpio_led fluid_gpio_leds[] = {
3621 {
3622 .name = "dual_led:green",
3623 .gpio = GPIO_LED1_GREEN_N,
3624 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3625 .active_low = 1,
3626 .retain_state_suspended = 0,
3627 },
3628 {
3629 .name = "dual_led:red",
3630 .gpio = GPIO_LED2_RED_N,
3631 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3632 .active_low = 1,
3633 .retain_state_suspended = 0,
3634 },
3635};
3636
3637static struct gpio_led_platform_data gpio_led_pdata = {
3638 .leds = fluid_gpio_leds,
3639 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3640};
3641
3642static struct platform_device fluid_leds_gpio = {
3643 .name = "leds-gpio",
3644 .id = -1,
3645 .dev = {
3646 .platform_data = &gpio_led_pdata,
3647 },
3648};
3649
3650#endif
3651
3652#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3653
3654static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3655 .phys_addr_base = 0x00106000,
3656 .reg_offsets = {
3657 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3658 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3659 },
3660 .phys_size = SZ_8K,
3661 .log_len = 4096, /* log's buffer length in bytes */
3662 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3663};
3664
3665static struct platform_device msm_rpm_log_device = {
3666 .name = "msm_rpm_log",
3667 .id = -1,
3668 .dev = {
3669 .platform_data = &msm_rpm_log_pdata,
3670 },
3671};
3672#endif
3673
3674#ifdef CONFIG_BATTERY_MSM8X60
3675static struct msm_charger_platform_data msm_charger_data = {
3676 .safety_time = 180,
3677 .update_time = 1,
3678 .max_voltage = 4200,
3679 .min_voltage = 3200,
3680};
3681
3682static struct platform_device msm_charger_device = {
3683 .name = "msm-charger",
3684 .id = -1,
3685 .dev = {
3686 .platform_data = &msm_charger_data,
3687 }
3688};
3689#endif
3690
3691/*
3692 * Consumer specific regulator names:
3693 * regulator name consumer dev_name
3694 */
3695static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3696 REGULATOR_SUPPLY("8058_l0", NULL),
3697};
3698static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3699 REGULATOR_SUPPLY("8058_l1", NULL),
3700};
3701static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3702 REGULATOR_SUPPLY("8058_l2", NULL),
3703};
3704static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3705 REGULATOR_SUPPLY("8058_l3", NULL),
3706};
3707static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3708 REGULATOR_SUPPLY("8058_l4", NULL),
3709};
3710static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3711 REGULATOR_SUPPLY("8058_l5", NULL),
3712};
3713static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3714 REGULATOR_SUPPLY("8058_l6", NULL),
3715};
3716static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3717 REGULATOR_SUPPLY("8058_l7", NULL),
3718};
3719static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3720 REGULATOR_SUPPLY("8058_l8", NULL),
3721};
3722static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3723 REGULATOR_SUPPLY("8058_l9", NULL),
3724};
3725static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3726 REGULATOR_SUPPLY("8058_l10", NULL),
3727};
3728static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3729 REGULATOR_SUPPLY("8058_l11", NULL),
3730};
3731static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3732 REGULATOR_SUPPLY("8058_l12", NULL),
3733};
3734static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3735 REGULATOR_SUPPLY("8058_l13", NULL),
3736};
3737static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3738 REGULATOR_SUPPLY("8058_l14", NULL),
3739};
3740static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3741 REGULATOR_SUPPLY("8058_l15", NULL),
3742};
3743static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3744 REGULATOR_SUPPLY("8058_l16", NULL),
3745};
3746static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3747 REGULATOR_SUPPLY("8058_l17", NULL),
3748};
3749static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3750 REGULATOR_SUPPLY("8058_l18", NULL),
3751};
3752static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3753 REGULATOR_SUPPLY("8058_l19", NULL),
3754};
3755static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3756 REGULATOR_SUPPLY("8058_l20", NULL),
3757};
3758static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3759 REGULATOR_SUPPLY("8058_l21", NULL),
3760};
3761static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3762 REGULATOR_SUPPLY("8058_l22", NULL),
3763};
3764static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3765 REGULATOR_SUPPLY("8058_l23", NULL),
3766};
3767static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3768 REGULATOR_SUPPLY("8058_l24", NULL),
3769};
3770static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3771 REGULATOR_SUPPLY("8058_l25", NULL),
3772};
3773static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3774 REGULATOR_SUPPLY("8058_s0", NULL),
3775};
3776static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3777 REGULATOR_SUPPLY("8058_s1", NULL),
3778};
3779static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3780 REGULATOR_SUPPLY("8058_s2", NULL),
3781};
3782static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3783 REGULATOR_SUPPLY("8058_s3", NULL),
3784};
3785static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3786 REGULATOR_SUPPLY("8058_s4", NULL),
3787};
3788static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3789 REGULATOR_SUPPLY("8058_lvs0", NULL),
3790};
3791static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3792 REGULATOR_SUPPLY("8058_lvs1", NULL),
3793};
3794static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3795 REGULATOR_SUPPLY("8058_ncp", NULL),
3796};
3797
3798static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3799 REGULATOR_SUPPLY("8901_l0", NULL),
3800};
3801static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3802 REGULATOR_SUPPLY("8901_l1", NULL),
3803};
3804static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3805 REGULATOR_SUPPLY("8901_l2", NULL),
3806};
3807static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3808 REGULATOR_SUPPLY("8901_l3", NULL),
3809};
3810static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3811 REGULATOR_SUPPLY("8901_l4", NULL),
3812};
3813static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3814 REGULATOR_SUPPLY("8901_l5", NULL),
3815};
3816static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3817 REGULATOR_SUPPLY("8901_l6", NULL),
3818};
3819static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3820 REGULATOR_SUPPLY("8901_s2", NULL),
3821};
3822static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3823 REGULATOR_SUPPLY("8901_s3", NULL),
3824};
3825static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3826 REGULATOR_SUPPLY("8901_s4", NULL),
3827};
3828static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3829 REGULATOR_SUPPLY("8901_lvs0", NULL),
3830};
3831static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3832 REGULATOR_SUPPLY("8901_lvs1", NULL),
3833};
3834static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3835 REGULATOR_SUPPLY("8901_lvs2", NULL),
3836};
3837static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3838 REGULATOR_SUPPLY("8901_lvs3", NULL),
3839};
3840static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3841 REGULATOR_SUPPLY("8901_mvs0", NULL),
3842};
3843
David Collins6f032ba2011-08-31 14:08:15 -07003844/* Pin control regulators */
3845static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
3846 REGULATOR_SUPPLY("8058_l8_pc", NULL),
3847};
3848static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
3849 REGULATOR_SUPPLY("8058_l20_pc", NULL),
3850};
3851static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
3852 REGULATOR_SUPPLY("8058_l21_pc", NULL),
3853};
3854static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
3855 REGULATOR_SUPPLY("8058_s2_pc", NULL),
3856};
3857static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
3858 REGULATOR_SUPPLY("8901_l0_pc", NULL),
3859};
3860static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
3861 REGULATOR_SUPPLY("8901_s4_pc", NULL),
3862};
3863
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003864#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3865 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
David Collins6f032ba2011-08-31 14:08:15 -07003866 _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003867 _always_on) \
David Collins6f032ba2011-08-31 14:08:15 -07003868 { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003869 .init_data = { \
3870 .constraints = { \
David Collins6f032ba2011-08-31 14:08:15 -07003871 .valid_modes_mask = _modes, \
3872 .valid_ops_mask = _ops, \
3873 .min_uV = _min_uV, \
3874 .max_uV = _max_uV, \
3875 .input_uV = _min_uV, \
3876 .apply_uV = _apply_uV, \
3877 .always_on = _always_on, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003878 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003879 .consumer_supplies = vreg_consumers_##_id, \
3880 .num_consumer_supplies = \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003881 ARRAY_SIZE(vreg_consumers_##_id), \
3882 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003883 .id = RPM_VREG_ID_##_id, \
3884 .default_uV = _default_uV, \
3885 .peak_uA = _peak_uA, \
3886 .avg_uA = _avg_uA, \
3887 .pull_down_enable = _pull_down, \
3888 .pin_ctrl = _pin_ctrl, \
3889 .freq = RPM_VREG_FREQ_##_freq, \
3890 .pin_fn = _pin_fn, \
3891 .force_mode = _force_mode, \
3892 .state = _state, \
3893 .sleep_selectable = _sleep_selectable, \
3894 }
3895
3896/* Pin control initialization */
3897#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
3898 { \
3899 .init_data = { \
3900 .constraints = { \
3901 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
3902 .always_on = _always_on, \
3903 }, \
3904 .num_consumer_supplies = \
3905 ARRAY_SIZE(vreg_consumers_##_id##_PC), \
3906 .consumer_supplies = vreg_consumers_##_id##_PC, \
3907 }, \
3908 .id = RPM_VREG_ID_##_id##_PC, \
3909 .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003910 .pin_ctrl = _pin_ctrl, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003911 }
3912
3913/*
3914 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3915 * via the peak_uA value specified in the table below. If the value is less
3916 * than the high power min threshold for the regulator, then the regulator will
3917 * be set to LPM. Otherwise, it will be set to HPM.
3918 *
3919 * This value can be further overridden by specifying an initial mode via
3920 * .init_data.constraints.initial_mode.
3921 */
3922
David Collins6f032ba2011-08-31 14:08:15 -07003923#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3924 _init_peak_uA) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003925 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3926 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3927 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3928 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3929 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003930 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3931 RPM_VREG_PIN_FN_8660_ENABLE, \
3932 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003933 _sleep_selectable, _always_on)
3934
David Collins6f032ba2011-08-31 14:08:15 -07003935#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3936 _init_peak_uA, _freq) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003937 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3938 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3939 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3940 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3941 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003942 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
3943 RPM_VREG_PIN_FN_8660_ENABLE, \
3944 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3945 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003946
David Collins6f032ba2011-08-31 14:08:15 -07003947#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003948 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
3949 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003950 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3951 RPM_VREG_PIN_FN_8660_ENABLE, \
3952 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3953 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003954
David Collins6f032ba2011-08-31 14:08:15 -07003955#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003956 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
3957 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003958 _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3959 RPM_VREG_PIN_FN_8660_ENABLE, \
3960 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3961 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003962
David Collins6f032ba2011-08-31 14:08:15 -07003963#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
3964#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
3965#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
3966#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
3967#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003968
David Collins6f032ba2011-08-31 14:08:15 -07003969/* RPM early regulator constraints */
3970static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
3971 /* ID a_on pd ss min_uV max_uV init_ip freq */
3972 RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
3973 RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003974};
3975
David Collins6f032ba2011-08-31 14:08:15 -07003976/* RPM regulator constraints */
3977static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
3978 /* ID a_on pd ss min_uV max_uV init_ip */
3979 RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
3980 RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
3981 RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
3982 RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
3983 RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
3984 RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3985 RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
3986 RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
3987 RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
3988 RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
3989 RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
3990 RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
3991 RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
3992 RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
3993 RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
3994 RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3995 RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
3996 RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
3997 RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
3998 RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
3999 RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4000 RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
4001 RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
4002 RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4003 RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4004 RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004005
David Collins6f032ba2011-08-31 14:08:15 -07004006 /* ID a_on pd ss min_uV max_uV init_ip freq */
4007 RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
4008 RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
4009 RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
4010
4011 /* ID a_on pd ss */
4012 RPM_VS(PM8058_LVS0, 0, 1, 0),
4013 RPM_VS(PM8058_LVS1, 0, 1, 0),
4014
4015 /* ID a_on pd ss min_uV max_uV */
4016 RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
4017
4018 /* ID a_on pd ss min_uV max_uV init_ip */
4019 RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4020 RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4021 RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
4022 RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4023 RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4024 RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4025 RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
4026
4027 /* ID a_on pd ss min_uV max_uV init_ip freq */
4028 RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
4029 RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
4030 RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
4031
4032 /* ID a_on pd ss */
4033 RPM_VS(PM8901_LVS0, 1, 1, 0),
4034 RPM_VS(PM8901_LVS1, 0, 1, 0),
4035 RPM_VS(PM8901_LVS2, 0, 1, 0),
4036 RPM_VS(PM8901_LVS3, 0, 1, 0),
4037 RPM_VS(PM8901_MVS0, 0, 1, 0),
4038
4039 /* ID a_on pin_func pin_ctrl */
4040 RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4041 RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4042 RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4043 RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
4044 RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4045 RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4046};
4047
4048static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
4049 .init_data = rpm_regulator_early_init_data,
4050 .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
4051 .version = RPM_VREG_VERSION_8660,
4052 .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
4053 .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
4054};
4055
4056static struct rpm_regulator_platform_data rpm_regulator_pdata = {
4057 .init_data = rpm_regulator_init_data,
4058 .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
4059 .version = RPM_VREG_VERSION_8660,
4060};
4061
4062static struct platform_device rpm_regulator_early_device = {
4063 .name = "rpm-regulator",
4064 .id = 0,
4065 .dev = {
4066 .platform_data = &rpm_regulator_early_pdata,
4067 },
4068};
4069
4070static struct platform_device rpm_regulator_device = {
4071 .name = "rpm-regulator",
4072 .id = 1,
4073 .dev = {
4074 .platform_data = &rpm_regulator_pdata,
4075 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004076};
4077
4078static struct platform_device *early_regulators[] __initdata = {
4079 &msm_device_saw_s0,
4080 &msm_device_saw_s1,
David Collins6f032ba2011-08-31 14:08:15 -07004081 &rpm_regulator_early_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004082};
4083
4084static struct platform_device *early_devices[] __initdata = {
4085#ifdef CONFIG_MSM_BUS_SCALING
4086 &msm_bus_apps_fabric,
4087 &msm_bus_sys_fabric,
4088 &msm_bus_mm_fabric,
4089 &msm_bus_sys_fpb,
4090 &msm_bus_cpss_fpb,
4091#endif
4092 &msm_device_dmov_adm0,
4093 &msm_device_dmov_adm1,
4094};
4095
4096#if (defined(CONFIG_MARIMBA_CORE)) && \
4097 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4098
4099static int bluetooth_power(int);
4100static struct platform_device msm_bt_power_device = {
4101 .name = "bt_power",
4102 .id = -1,
4103 .dev = {
4104 .platform_data = &bluetooth_power,
4105 },
4106};
4107#endif
4108
4109static struct platform_device msm_tsens_device = {
4110 .name = "tsens-tm",
4111 .id = -1,
4112};
4113
4114static struct platform_device *rumi_sim_devices[] __initdata = {
4115 &smc91x_device,
4116 &msm_device_uart_dm12,
4117#ifdef CONFIG_I2C_QUP
4118 &msm_gsbi3_qup_i2c_device,
4119 &msm_gsbi4_qup_i2c_device,
4120 &msm_gsbi7_qup_i2c_device,
4121 &msm_gsbi8_qup_i2c_device,
4122 &msm_gsbi9_qup_i2c_device,
4123 &msm_gsbi12_qup_i2c_device,
4124#endif
4125#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004126 &msm_device_ssbi2,
4127 &msm_device_ssbi3,
4128#endif
4129#ifdef CONFIG_ANDROID_PMEM
4130 &android_pmem_device,
4131 &android_pmem_adsp_device,
4132 &android_pmem_audio_device,
4133 &android_pmem_smipool_device,
4134#endif
4135#ifdef CONFIG_MSM_ROTATOR
4136 &msm_rotator_device,
4137#endif
4138 &msm_fb_device,
4139 &msm_kgsl_3d0,
4140 &msm_kgsl_2d0,
4141 &msm_kgsl_2d1,
4142 &lcdc_samsung_panel_device,
4143#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4144 &hdmi_msm_device,
4145#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4146#ifdef CONFIG_MSM_CAMERA
4147#ifdef CONFIG_MT9E013
4148 &msm_camera_sensor_mt9e013,
4149#endif
4150#ifdef CONFIG_IMX074
4151 &msm_camera_sensor_imx074,
4152#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004153#ifdef CONFIG_VX6953
4154 &msm_camera_sensor_vx6953,
4155#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004156#ifdef CONFIG_WEBCAM_OV7692
4157 &msm_camera_sensor_webcam_ov7692,
4158#endif
4159#ifdef CONFIG_WEBCAM_OV9726
4160 &msm_camera_sensor_webcam_ov9726,
4161#endif
4162#ifdef CONFIG_QS_S5K4E1
4163 &msm_camera_sensor_qs_s5k4e1,
4164#endif
4165#endif
4166#ifdef CONFIG_MSM_GEMINI
4167 &msm_gemini_device,
4168#endif
4169#ifdef CONFIG_MSM_VPE
4170 &msm_vpe_device,
4171#endif
4172 &msm_device_vidc,
4173};
4174
4175#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4176enum {
4177 SX150X_CORE,
4178 SX150X_DOCKING,
4179 SX150X_SURF,
4180 SX150X_LEFT_FHA,
4181 SX150X_RIGHT_FHA,
4182 SX150X_SOUTH,
4183 SX150X_NORTH,
4184 SX150X_CORE_FLUID,
4185};
4186
4187static struct sx150x_platform_data sx150x_data[] __initdata = {
4188 [SX150X_CORE] = {
4189 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4190 .oscio_is_gpo = false,
4191 .io_pullup_ena = 0x0c08,
4192 .io_pulldn_ena = 0x4060,
4193 .io_open_drain_ena = 0x000c,
4194 .io_polarity = 0,
4195 .irq_summary = -1, /* see fixup_i2c_configs() */
4196 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4197 },
4198 [SX150X_DOCKING] = {
4199 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4200 .oscio_is_gpo = false,
4201 .io_pullup_ena = 0x5e06,
4202 .io_pulldn_ena = 0x81b8,
4203 .io_open_drain_ena = 0,
4204 .io_polarity = 0,
4205 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4206 UI_INT2_N),
4207 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4208 GPIO_DOCKING_EXPANDER_BASE -
4209 GPIO_EXPANDER_GPIO_BASE,
4210 },
4211 [SX150X_SURF] = {
4212 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4213 .oscio_is_gpo = false,
4214 .io_pullup_ena = 0,
4215 .io_pulldn_ena = 0,
4216 .io_open_drain_ena = 0,
4217 .io_polarity = 0,
4218 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4219 UI_INT1_N),
4220 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4221 GPIO_SURF_EXPANDER_BASE -
4222 GPIO_EXPANDER_GPIO_BASE,
4223 },
4224 [SX150X_LEFT_FHA] = {
4225 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4226 .oscio_is_gpo = false,
4227 .io_pullup_ena = 0,
4228 .io_pulldn_ena = 0x40,
4229 .io_open_drain_ena = 0,
4230 .io_polarity = 0,
4231 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4232 UI_INT3_N),
4233 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4234 GPIO_LEFT_KB_EXPANDER_BASE -
4235 GPIO_EXPANDER_GPIO_BASE,
4236 },
4237 [SX150X_RIGHT_FHA] = {
4238 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4239 .oscio_is_gpo = true,
4240 .io_pullup_ena = 0,
4241 .io_pulldn_ena = 0,
4242 .io_open_drain_ena = 0,
4243 .io_polarity = 0,
4244 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4245 UI_INT3_N),
4246 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4247 GPIO_RIGHT_KB_EXPANDER_BASE -
4248 GPIO_EXPANDER_GPIO_BASE,
4249 },
4250 [SX150X_SOUTH] = {
4251 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4252 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4253 GPIO_SOUTH_EXPANDER_BASE -
4254 GPIO_EXPANDER_GPIO_BASE,
4255 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4256 },
4257 [SX150X_NORTH] = {
4258 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4259 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4260 GPIO_NORTH_EXPANDER_BASE -
4261 GPIO_EXPANDER_GPIO_BASE,
4262 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4263 .oscio_is_gpo = true,
4264 .io_open_drain_ena = 0x30,
4265 },
4266 [SX150X_CORE_FLUID] = {
4267 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4268 .oscio_is_gpo = false,
4269 .io_pullup_ena = 0x0408,
4270 .io_pulldn_ena = 0x4060,
4271 .io_open_drain_ena = 0x0008,
4272 .io_polarity = 0,
4273 .irq_summary = -1, /* see fixup_i2c_configs() */
4274 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4275 },
4276};
4277
4278#ifdef CONFIG_SENSORS_MSM_ADC
4279/* Configuration of EPM expander is done when client
4280 * request an adc read
4281 */
4282static struct sx150x_platform_data sx150x_epmdata = {
4283 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4284 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4285 GPIO_EPM_EXPANDER_BASE -
4286 GPIO_EXPANDER_GPIO_BASE,
4287 .irq_summary = -1,
4288};
4289#endif
4290
4291/* sx150x_low_power_cfg
4292 *
4293 * This data and init function are used to put unused gpio-expander output
4294 * lines into their low-power states at boot. The init
4295 * function must be deferred until a later init stage because the i2c
4296 * gpio expander drivers do not probe until after they are registered
4297 * (see register_i2c_devices) and the work-queues for those registrations
4298 * are processed. Because these lines are unused, there is no risk of
4299 * competing with a device driver for the gpio.
4300 *
4301 * gpio lines whose low-power states are input are naturally in their low-
4302 * power configurations once probed, see the platform data structures above.
4303 */
4304struct sx150x_low_power_cfg {
4305 unsigned gpio;
4306 unsigned val;
4307};
4308
4309static struct sx150x_low_power_cfg
4310common_sx150x_lp_cfgs[] __initdata = {
4311 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4312 {GPIO_EXT_GPS_LNA_EN, 0},
4313 {GPIO_MSM_WAKES_BT, 0},
4314 {GPIO_USB_UICC_EN, 0},
4315 {GPIO_BATT_GAUGE_EN, 0},
4316};
4317
4318static struct sx150x_low_power_cfg
4319surf_ffa_sx150x_lp_cfgs[] __initdata = {
4320 {GPIO_MIPI_DSI_RST_N, 0},
4321 {GPIO_DONGLE_PWR_EN, 0},
4322 {GPIO_CAP_TS_SLEEP, 1},
4323 {GPIO_WEB_CAMIF_RESET_N, 0},
4324};
4325
4326static void __init
4327cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4328{
4329 unsigned n;
4330 int rc;
4331
4332 for (n = 0; n < nelems; ++n) {
4333 rc = gpio_request(cfgs[n].gpio, NULL);
4334 if (!rc) {
4335 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4336 gpio_free(cfgs[n].gpio);
4337 }
4338
4339 if (rc) {
4340 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4341 __func__, cfgs[n].gpio, rc);
4342 }
Steve Muckle9161d302010-02-11 11:50:40 -08004343 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004344}
4345
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004346static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004347{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004348 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4349 ARRAY_SIZE(common_sx150x_lp_cfgs));
4350 if (!machine_is_msm8x60_fluid())
4351 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4352 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4353 return 0;
4354}
4355module_init(cfg_sx150xs_low_power);
4356
4357#ifdef CONFIG_I2C
4358static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4359 {
4360 I2C_BOARD_INFO("sx1509q", 0x3e),
4361 .platform_data = &sx150x_data[SX150X_CORE]
4362 },
4363};
4364
4365static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4366 {
4367 I2C_BOARD_INFO("sx1509q", 0x3f),
4368 .platform_data = &sx150x_data[SX150X_DOCKING]
4369 },
4370};
4371
4372static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4373 {
4374 I2C_BOARD_INFO("sx1509q", 0x70),
4375 .platform_data = &sx150x_data[SX150X_SURF]
4376 }
4377};
4378
4379static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4380 {
4381 I2C_BOARD_INFO("sx1508q", 0x21),
4382 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4383 },
4384 {
4385 I2C_BOARD_INFO("sx1508q", 0x22),
4386 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4387 }
4388};
4389
4390static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4391 {
4392 I2C_BOARD_INFO("sx1508q", 0x23),
4393 .platform_data = &sx150x_data[SX150X_SOUTH]
4394 },
4395 {
4396 I2C_BOARD_INFO("sx1508q", 0x20),
4397 .platform_data = &sx150x_data[SX150X_NORTH]
4398 }
4399};
4400
4401static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4402 {
4403 I2C_BOARD_INFO("sx1509q", 0x3e),
4404 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4405 },
4406};
4407
4408#ifdef CONFIG_SENSORS_MSM_ADC
4409static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4410 {
4411 I2C_BOARD_INFO("sx1509q", 0x3e),
4412 .platform_data = &sx150x_epmdata
4413 },
4414};
4415#endif
4416#endif
4417#endif
4418
4419#ifdef CONFIG_SENSORS_MSM_ADC
4420static struct resource resources_adc[] = {
4421 {
4422 .start = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4423 .end = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4424 .flags = IORESOURCE_IRQ,
4425 },
4426};
4427
4428static struct adc_access_fn xoadc_fn = {
4429 pm8058_xoadc_select_chan_and_start_conv,
4430 pm8058_xoadc_read_adc_code,
4431 pm8058_xoadc_get_properties,
4432 pm8058_xoadc_slot_request,
4433 pm8058_xoadc_restore_slot,
4434 pm8058_xoadc_calibrate,
4435};
4436
4437#if defined(CONFIG_I2C) && \
4438 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4439static struct regulator *vreg_adc_epm1;
4440
4441static struct i2c_client *epm_expander_i2c_register_board(void)
4442
4443{
4444 struct i2c_adapter *i2c_adap;
4445 struct i2c_client *client = NULL;
4446 i2c_adap = i2c_get_adapter(0x0);
4447
4448 if (i2c_adap == NULL)
4449 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4450
4451 if (i2c_adap != NULL)
4452 client = i2c_new_device(i2c_adap,
4453 &fluid_expanders_i2c_epm_info[0]);
4454 return client;
4455
4456}
4457
4458static unsigned int msm_adc_gpio_configure_expander_enable(void)
4459{
4460 int rc = 0;
4461 static struct i2c_client *epm_i2c_client;
4462
4463 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4464
4465 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4466
4467 if (IS_ERR(vreg_adc_epm1)) {
4468 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4469 return 0;
4470 }
4471
4472 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4473 if (rc)
4474 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4475 "regulator set voltage failed\n");
4476
4477 rc = regulator_enable(vreg_adc_epm1);
4478 if (rc) {
4479 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4480 "Error while enabling regulator for epm s3 %d\n", rc);
4481 return rc;
4482 }
4483
4484 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4485 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4486
4487 msleep(1000);
4488
4489 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4490 if (!rc) {
4491 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4492 "Configure 5v boost\n");
4493 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4494 } else {
4495 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4496 "Error for epm 5v boost en\n");
4497 goto exit_vreg_epm;
4498 }
4499
4500 msleep(500);
4501
4502 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4503 if (!rc) {
4504 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4505 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4506 "Configure epm 3.3v\n");
4507 } else {
4508 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4509 "Error for gpio 3.3ven\n");
4510 goto exit_vreg_epm;
4511 }
4512 msleep(500);
4513
4514 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4515 "Trying to request EPM LVLSFT_EN\n");
4516 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4517 if (!rc) {
4518 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4519 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4520 "Configure the lvlsft\n");
4521 } else {
4522 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4523 "Error for epm lvlsft_en\n");
4524 goto exit_vreg_epm;
4525 }
4526
4527 msleep(500);
4528
4529 if (!epm_i2c_client)
4530 epm_i2c_client = epm_expander_i2c_register_board();
4531
4532 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4533 if (!rc)
4534 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4535 if (rc) {
4536 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4537 ": GPIO PWR MON Enable issue\n");
4538 goto exit_vreg_epm;
4539 }
4540
4541 msleep(1000);
4542
4543 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4544 if (!rc) {
4545 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4546 if (rc) {
4547 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4548 ": ADC1_PWDN error direction out\n");
4549 goto exit_vreg_epm;
4550 }
4551 }
4552
4553 msleep(100);
4554
4555 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4556 if (!rc) {
4557 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4558 if (rc) {
4559 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4560 ": ADC2_PWD error direction out\n");
4561 goto exit_vreg_epm;
4562 }
4563 }
4564
4565 msleep(1000);
4566
4567 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4568 if (!rc) {
4569 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4570 if (rc) {
4571 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4572 "Gpio request problem %d\n", rc);
4573 goto exit_vreg_epm;
4574 }
4575 }
4576
4577 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4578 if (!rc) {
4579 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4580 if (rc) {
4581 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4582 ": EPM_SPI_ADC1_CS_N error\n");
4583 goto exit_vreg_epm;
4584 }
4585 }
4586
4587 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4588 if (!rc) {
4589 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4590 if (rc) {
4591 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4592 ": EPM_SPI_ADC2_Cs_N error\n");
4593 goto exit_vreg_epm;
4594 }
4595 }
4596
4597 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4598 "the power monitor reset for epm\n");
4599
4600 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4601 if (!rc) {
4602 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4603 if (rc) {
4604 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4605 ": Error in the power mon reset\n");
4606 goto exit_vreg_epm;
4607 }
4608 }
4609
4610 msleep(1000);
4611
4612 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4613
4614 msleep(500);
4615
4616 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4617
4618 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4619
4620 return rc;
4621
4622exit_vreg_epm:
4623 regulator_disable(vreg_adc_epm1);
4624
4625 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4626 " rc = %d.\n", rc);
4627 return rc;
4628};
4629
4630static unsigned int msm_adc_gpio_configure_expander_disable(void)
4631{
4632 int rc = 0;
4633
4634 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4635 gpio_free(GPIO_PWR_MON_RESET_N);
4636
4637 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4638 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4639
4640 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4641 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4642
4643 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4644 gpio_free(GPIO_PWR_MON_START);
4645
4646 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4647 gpio_free(GPIO_ADC1_PWDN_N);
4648
4649 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4650 gpio_free(GPIO_ADC2_PWDN_N);
4651
4652 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4653 gpio_free(GPIO_PWR_MON_ENABLE);
4654
4655 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4656 gpio_free(GPIO_EPM_LVLSFT_EN);
4657
4658 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4659 gpio_free(GPIO_EPM_5V_BOOST_EN);
4660
4661 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4662 gpio_free(GPIO_EPM_3_3V_EN);
4663
4664 rc = regulator_disable(vreg_adc_epm1);
4665 if (rc)
4666 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4667 "Error while enabling regulator for epm s3 %d\n", rc);
4668 regulator_put(vreg_adc_epm1);
4669
4670 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4671 return rc;
4672};
4673
4674unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4675{
4676 int rc = 0;
4677
4678 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4679 cs_enable);
4680
4681 if (cs_enable < 16) {
4682 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4683 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4684 } else {
4685 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4686 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4687 }
4688 return rc;
4689};
4690
4691unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4692{
4693 int rc = 0;
4694
4695 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4696
4697 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4698
4699 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4700
4701 return rc;
4702};
4703#endif
4704
4705static struct msm_adc_channels msm_adc_channels_data[] = {
4706 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4707 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4708 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4709 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4710 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4711 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4712 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4713 CHAN_PATH_TYPE4,
4714 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4715 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4716 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4717 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4718 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4719 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4720 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4721 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4722 CHAN_PATH_TYPE12,
4723 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4724 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4725 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4726 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4727 CHAN_PATH_TYPE_NONE,
4728 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4729 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4730 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4731 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4732 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4733 scale_xtern_chgr_cur},
4734 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4735 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4736 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4737 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4738 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4739 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4740 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4741 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4742 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4743 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4744 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4745 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4746};
4747
4748static char *msm_adc_fluid_device_names[] = {
4749 "ADS_ADC1",
4750 "ADS_ADC2",
4751};
4752
4753static struct msm_adc_platform_data msm_adc_pdata = {
4754 .channel = msm_adc_channels_data,
4755 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4756#if defined(CONFIG_I2C) && \
4757 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4758 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4759 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4760 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4761 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4762#endif
4763};
4764
4765static struct platform_device msm_adc_device = {
4766 .name = "msm_adc",
4767 .id = -1,
4768 .dev = {
4769 .platform_data = &msm_adc_pdata,
4770 },
4771};
4772
4773static void pmic8058_xoadc_mpp_config(void)
4774{
4775 int rc;
4776
4777 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4778 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4779 if (rc)
4780 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4781
4782 rc = pm8058_mpp_config_analog_input(XOADC_MPP_3,
4783 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
4784 if (rc)
4785 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
4786
4787 rc = pm8058_mpp_config_analog_input(XOADC_MPP_5,
4788 PM_MPP_AIN_AMUX_CH9, PM_MPP_AOUT_CTL_DISABLE);
4789 if (rc)
4790 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
4791
4792 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
4793 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
4794 if (rc)
4795 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
4796
4797 rc = pm8058_mpp_config_analog_input(XOADC_MPP_8,
4798 PM_MPP_AIN_AMUX_CH8, PM_MPP_AOUT_CTL_DISABLE);
4799 if (rc)
4800 pr_err("%s: Config mpp8 on pmic 8058 failed\n", __func__);
4801
4802 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
4803 PM_MPP_AIN_AMUX_CH7, PM_MPP_AOUT_CTL_DISABLE);
4804 if (rc)
4805 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
4806}
4807
4808static struct regulator *vreg_ldo18_adc;
4809
4810static int pmic8058_xoadc_vreg_config(int on)
4811{
4812 int rc;
4813
4814 if (on) {
4815 rc = regulator_enable(vreg_ldo18_adc);
4816 if (rc)
4817 pr_err("%s: Enable of regulator ldo18_adc "
4818 "failed\n", __func__);
4819 } else {
4820 rc = regulator_disable(vreg_ldo18_adc);
4821 if (rc)
4822 pr_err("%s: Disable of regulator ldo18_adc "
4823 "failed\n", __func__);
4824 }
4825
4826 return rc;
4827}
4828
4829static int pmic8058_xoadc_vreg_setup(void)
4830{
4831 int rc;
4832
4833 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4834 if (IS_ERR(vreg_ldo18_adc)) {
4835 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4836 __func__, PTR_ERR(vreg_ldo18_adc));
4837 rc = PTR_ERR(vreg_ldo18_adc);
4838 goto fail;
4839 }
4840
4841 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4842 if (rc) {
4843 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4844 goto fail;
4845 }
4846
4847 return rc;
4848fail:
4849 regulator_put(vreg_ldo18_adc);
4850 return rc;
4851}
4852
4853static void pmic8058_xoadc_vreg_shutdown(void)
4854{
4855 regulator_put(vreg_ldo18_adc);
4856}
4857
4858/* usec. For this ADC,
4859 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4860 * Each channel has different configuration, thus at the time of starting
4861 * the conversion, xoadc will return actual conversion time
4862 * */
4863static struct adc_properties pm8058_xoadc_data = {
4864 .adc_reference = 2200, /* milli-voltage for this adc */
4865 .bitresolution = 15,
4866 .bipolar = 0,
4867 .conversiontime = 54,
4868};
4869
4870static struct xoadc_platform_data xoadc_pdata = {
4871 .xoadc_prop = &pm8058_xoadc_data,
4872 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4873 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4874 .xoadc_num = XOADC_PMIC_0,
4875 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4876 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4877};
4878#endif
4879
4880#ifdef CONFIG_MSM_SDIO_AL
4881
4882static unsigned mdm2ap_status = 140;
4883
4884static int configure_mdm2ap_status(int on)
4885{
4886 int ret = 0;
4887 if (on)
4888 ret = msm_gpiomux_get(mdm2ap_status);
4889 else
4890 ret = msm_gpiomux_put(mdm2ap_status);
4891
4892 if (ret)
4893 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4894 on);
4895
4896 return ret;
4897}
4898
4899
4900static int get_mdm2ap_status(void)
4901{
4902 return gpio_get_value(mdm2ap_status);
4903}
4904
4905static struct sdio_al_platform_data sdio_al_pdata = {
4906 .config_mdm2ap_status = configure_mdm2ap_status,
4907 .get_mdm2ap_status = get_mdm2ap_status,
4908 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004909 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004910 .peer_sdioc_version_major = 0x0004,
4911 .peer_sdioc_boot_version_minor = 0x0001,
4912 .peer_sdioc_boot_version_major = 0x0003
4913};
4914
4915struct platform_device msm_device_sdio_al = {
4916 .name = "msm_sdio_al",
4917 .id = -1,
4918 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004919 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004920 .platform_data = &sdio_al_pdata,
4921 },
4922};
4923
4924#endif /* CONFIG_MSM_SDIO_AL */
4925
4926static struct platform_device *charm_devices[] __initdata = {
4927 &msm_charm_modem,
4928#ifdef CONFIG_MSM_SDIO_AL
4929 &msm_device_sdio_al,
4930#endif
4931};
4932
Lei Zhou338cab82011-08-19 13:38:17 -04004933#ifdef CONFIG_SND_SOC_MSM8660_APQ
4934static struct platform_device *dragon_alsa_devices[] __initdata = {
4935 &msm_pcm,
4936 &msm_pcm_routing,
4937 &msm_cpudai0,
4938 &msm_cpudai1,
4939 &msm_cpudai_hdmi_rx,
4940 &msm_cpudai_bt_rx,
4941 &msm_cpudai_bt_tx,
4942 &msm_cpudai_fm_rx,
4943 &msm_cpudai_fm_tx,
4944 &msm_cpu_fe,
4945 &msm_stub_codec,
4946 &msm_lpa_pcm,
4947};
4948#endif
4949
4950static struct platform_device *asoc_devices[] __initdata = {
4951 &asoc_msm_pcm,
4952 &asoc_msm_dai0,
4953 &asoc_msm_dai1,
4954};
4955
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004956static struct platform_device *surf_devices[] __initdata = {
4957 &msm_device_smd,
4958 &msm_device_uart_dm12,
4959#ifdef CONFIG_I2C_QUP
4960 &msm_gsbi3_qup_i2c_device,
4961 &msm_gsbi4_qup_i2c_device,
4962 &msm_gsbi7_qup_i2c_device,
4963 &msm_gsbi8_qup_i2c_device,
4964 &msm_gsbi9_qup_i2c_device,
4965 &msm_gsbi12_qup_i2c_device,
4966#endif
4967#ifdef CONFIG_SERIAL_MSM_HS
4968 &msm_device_uart_dm1,
4969#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05304970#ifdef CONFIG_MSM_SSBI
4971 &msm_device_ssbi_pmic1,
4972#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004973#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004974 &msm_device_ssbi2,
4975 &msm_device_ssbi3,
4976#endif
4977#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
4978 &isp1763_device,
4979#endif
4980
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004981#if defined (CONFIG_MSM_8x60_VOIP)
4982 &asoc_msm_mvs,
4983 &asoc_mvs_dai0,
4984 &asoc_mvs_dai1,
4985#endif
Lei Zhou338cab82011-08-19 13:38:17 -04004986
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004987#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
4988 &msm_device_otg,
4989#endif
4990#ifdef CONFIG_USB_GADGET_MSM_72K
4991 &msm_device_gadget_peripheral,
4992#endif
4993#ifdef CONFIG_USB_G_ANDROID
4994 &android_usb_device,
4995#endif
4996#ifdef CONFIG_BATTERY_MSM
4997 &msm_batt_device,
4998#endif
4999#ifdef CONFIG_ANDROID_PMEM
5000 &android_pmem_device,
5001 &android_pmem_adsp_device,
5002 &android_pmem_audio_device,
5003 &android_pmem_smipool_device,
5004#endif
5005#ifdef CONFIG_MSM_ROTATOR
5006 &msm_rotator_device,
5007#endif
5008 &msm_fb_device,
5009 &msm_kgsl_3d0,
5010 &msm_kgsl_2d0,
5011 &msm_kgsl_2d1,
5012 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005013#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5014 &lcdc_nt35582_panel_device,
5015#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005016#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
5017 &lcdc_samsung_oled_panel_device,
5018#endif
5019#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
5020 &lcdc_auo_wvga_panel_device,
5021#endif
5022#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
5023 &hdmi_msm_device,
5024#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
5025#ifdef CONFIG_FB_MSM_MIPI_DSI
5026 &mipi_dsi_toshiba_panel_device,
5027 &mipi_dsi_novatek_panel_device,
5028#endif
5029#ifdef CONFIG_MSM_CAMERA
5030#ifdef CONFIG_MT9E013
5031 &msm_camera_sensor_mt9e013,
5032#endif
5033#ifdef CONFIG_IMX074
5034 &msm_camera_sensor_imx074,
5035#endif
5036#ifdef CONFIG_WEBCAM_OV7692
5037 &msm_camera_sensor_webcam_ov7692,
5038#endif
5039#ifdef CONFIG_WEBCAM_OV9726
5040 &msm_camera_sensor_webcam_ov9726,
5041#endif
5042#ifdef CONFIG_QS_S5K4E1
5043 &msm_camera_sensor_qs_s5k4e1,
5044#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04005045#ifdef CONFIG_VX6953
5046 &msm_camera_sensor_vx6953,
5047#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005048#endif
5049#ifdef CONFIG_MSM_GEMINI
5050 &msm_gemini_device,
5051#endif
5052#ifdef CONFIG_MSM_VPE
5053 &msm_vpe_device,
5054#endif
5055
5056#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5057 &msm_rpm_log_device,
5058#endif
5059#if defined(CONFIG_MSM_RPM_STATS_LOG)
5060 &msm_rpm_stat_device,
5061#endif
5062 &msm_device_vidc,
5063#if (defined(CONFIG_MARIMBA_CORE)) && \
5064 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5065 &msm_bt_power_device,
5066#endif
5067#ifdef CONFIG_SENSORS_MSM_ADC
5068 &msm_adc_device,
5069#endif
David Collins6f032ba2011-08-31 14:08:15 -07005070 &rpm_regulator_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005071
5072#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5073 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5074 &qcrypto_device,
5075#endif
5076
5077#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5078 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5079 &qcedev_device,
5080#endif
5081
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005082
5083#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5084#ifdef CONFIG_MSM_USE_TSIF1
5085 &msm_device_tsif[1],
5086#else
5087 &msm_device_tsif[0],
5088#endif /* CONFIG_MSM_USE_TSIF1 */
5089#endif /* CONFIG_TSIF */
5090
5091#ifdef CONFIG_HW_RANDOM_MSM
5092 &msm_device_rng,
5093#endif
5094
5095 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005096 &msm_rpm_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005097
5098};
5099
5100static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5101 /* Kernel SMI memory pool for video core, used for firmware */
5102 /* and encoder, decoder scratch buffers */
5103 /* Kernel SMI memory pool should always precede the user space */
5104 /* SMI memory pool, as the video core will use offset address */
5105 /* from the Firmware base */
5106 [MEMTYPE_SMI_KERNEL] = {
5107 .start = KERNEL_SMI_BASE,
5108 .limit = KERNEL_SMI_SIZE,
5109 .size = KERNEL_SMI_SIZE,
5110 .flags = MEMTYPE_FLAGS_FIXED,
5111 },
5112 /* User space SMI memory pool for video core */
5113 /* used for encoder, decoder input & output buffers */
5114 [MEMTYPE_SMI] = {
5115 .start = USER_SMI_BASE,
5116 .limit = USER_SMI_SIZE,
5117 .flags = MEMTYPE_FLAGS_FIXED,
5118 },
5119 [MEMTYPE_EBI0] = {
5120 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5121 },
5122 [MEMTYPE_EBI1] = {
5123 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5124 },
5125};
5126
5127static void __init size_pmem_devices(void)
5128{
5129#ifdef CONFIG_ANDROID_PMEM
5130 android_pmem_adsp_pdata.size = pmem_adsp_size;
5131 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
5132 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5133 android_pmem_pdata.size = pmem_sf_size;
5134#endif
5135}
5136
5137static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5138{
5139 msm8x60_reserve_table[p->memory_type].size += p->size;
5140}
5141
5142static void __init reserve_pmem_memory(void)
5143{
5144#ifdef CONFIG_ANDROID_PMEM
5145 reserve_memory_for(&android_pmem_adsp_pdata);
5146 reserve_memory_for(&android_pmem_smipool_pdata);
5147 reserve_memory_for(&android_pmem_audio_pdata);
5148 reserve_memory_for(&android_pmem_pdata);
5149 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5150#endif
5151}
5152
5153static void __init msm8x60_calculate_reserve_sizes(void)
5154{
5155 size_pmem_devices();
5156 reserve_pmem_memory();
5157}
5158
5159static int msm8x60_paddr_to_memtype(unsigned int paddr)
5160{
5161 if (paddr >= 0x40000000 && paddr < 0x60000000)
5162 return MEMTYPE_EBI1;
5163 if (paddr >= 0x38000000 && paddr < 0x40000000)
5164 return MEMTYPE_SMI;
5165 return MEMTYPE_NONE;
5166}
5167
5168static struct reserve_info msm8x60_reserve_info __initdata = {
5169 .memtype_reserve_table = msm8x60_reserve_table,
5170 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5171 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5172};
5173
5174static void __init msm8x60_reserve(void)
5175{
5176 reserve_info = &msm8x60_reserve_info;
5177 msm_reserve();
5178}
5179
5180#define EXT_CHG_VALID_MPP 10
5181#define EXT_CHG_VALID_MPP_2 11
5182
5183#ifdef CONFIG_ISL9519_CHARGER
5184static int isl_detection_setup(void)
5185{
5186 int ret = 0;
5187
5188 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5189 PM8058_MPP_DIG_LEVEL_S3,
5190 PM_MPP_DIN_TO_INT);
5191 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5192 PM8058_MPP_DIG_LEVEL_S3,
5193 PM_MPP_BI_PULLUP_10KOHM
5194 );
5195 return ret;
5196}
5197
5198static struct isl_platform_data isl_data __initdata = {
5199 .chgcurrent = 700,
5200 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5201 .chg_detection_config = isl_detection_setup,
5202 .max_system_voltage = 4200,
5203 .min_system_voltage = 3200,
5204 .term_current = 120,
5205 .input_current = 2048,
5206};
5207
5208static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5209 {
5210 I2C_BOARD_INFO("isl9519q", 0x9),
5211 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5212 .platform_data = &isl_data,
5213 },
5214};
5215#endif
5216
5217#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5218static int smb137b_detection_setup(void)
5219{
5220 int ret = 0;
5221
5222 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5223 PM8058_MPP_DIG_LEVEL_S3,
5224 PM_MPP_DIN_TO_INT);
5225 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5226 PM8058_MPP_DIG_LEVEL_S3,
5227 PM_MPP_BI_PULLUP_10KOHM);
5228 return ret;
5229}
5230
5231static struct smb137b_platform_data smb137b_data __initdata = {
5232 .chg_detection_config = smb137b_detection_setup,
5233 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5234 .batt_mah_rating = 950,
5235};
5236
5237static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5238 {
5239 I2C_BOARD_INFO("smb137b", 0x08),
5240 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5241 .platform_data = &smb137b_data,
5242 },
5243};
5244#endif
5245
5246#ifdef CONFIG_PMIC8058
5247#define PMIC_GPIO_SDC3_DET 22
5248
5249static int pm8058_gpios_init(void)
5250{
5251 int i;
5252 int rc;
5253 struct pm8058_gpio_cfg {
5254 int gpio;
5255 struct pm8058_gpio cfg;
5256 };
5257
5258 struct pm8058_gpio_cfg gpio_cfgs[] = {
5259 { /* FFA ethernet */
5260 6,
5261 {
5262 .direction = PM_GPIO_DIR_IN,
5263 .pull = PM_GPIO_PULL_DN,
5264 .vin_sel = 2,
5265 .function = PM_GPIO_FUNC_NORMAL,
5266 .inv_int_pol = 0,
5267 },
5268 },
5269#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5270 {
5271 PMIC_GPIO_SDC3_DET - 1,
5272 {
5273 .direction = PM_GPIO_DIR_IN,
5274 .pull = PM_GPIO_PULL_UP_30,
5275 .vin_sel = 2,
5276 .function = PM_GPIO_FUNC_NORMAL,
5277 .inv_int_pol = 0,
5278 },
5279 },
5280#endif
5281 { /* core&surf gpio expander */
5282 UI_INT1_N,
5283 {
5284 .direction = PM_GPIO_DIR_IN,
5285 .pull = PM_GPIO_PULL_NO,
5286 .vin_sel = PM_GPIO_VIN_S3,
5287 .function = PM_GPIO_FUNC_NORMAL,
5288 .inv_int_pol = 0,
5289 },
5290 },
5291 { /* docking gpio expander */
5292 UI_INT2_N,
5293 {
5294 .direction = PM_GPIO_DIR_IN,
5295 .pull = PM_GPIO_PULL_NO,
5296 .vin_sel = PM_GPIO_VIN_S3,
5297 .function = PM_GPIO_FUNC_NORMAL,
5298 .inv_int_pol = 0,
5299 },
5300 },
5301 { /* FHA/keypad gpio expanders */
5302 UI_INT3_N,
5303 {
5304 .direction = PM_GPIO_DIR_IN,
5305 .pull = PM_GPIO_PULL_NO,
5306 .vin_sel = PM_GPIO_VIN_S3,
5307 .function = PM_GPIO_FUNC_NORMAL,
5308 .inv_int_pol = 0,
5309 },
5310 },
5311 { /* TouchDisc Interrupt */
5312 5,
5313 {
5314 .direction = PM_GPIO_DIR_IN,
5315 .pull = PM_GPIO_PULL_UP_1P5,
5316 .vin_sel = 2,
5317 .function = PM_GPIO_FUNC_NORMAL,
5318 .inv_int_pol = 0,
5319 }
5320 },
5321 { /* Timpani Reset */
5322 20,
5323 {
5324 .direction = PM_GPIO_DIR_OUT,
5325 .output_value = 1,
5326 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5327 .pull = PM_GPIO_PULL_DN,
5328 .out_strength = PM_GPIO_STRENGTH_HIGH,
5329 .function = PM_GPIO_FUNC_NORMAL,
5330 .vin_sel = 2,
5331 .inv_int_pol = 0,
5332 }
5333 },
5334 { /* PMIC ID interrupt */
5335 36,
5336 {
5337 .direction = PM_GPIO_DIR_IN,
5338 .pull = PM_GPIO_PULL_UP_1P5,
5339 .function = PM_GPIO_FUNC_NORMAL,
5340 .vin_sel = 2,
5341 .inv_int_pol = 0,
5342 }
5343 },
5344 };
5345
5346#if defined(CONFIG_HAPTIC_ISA1200) || \
5347 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5348
5349 struct pm8058_gpio_cfg en_hap_gpio_cfg = {
5350 PMIC_GPIO_HAP_ENABLE,
5351 {
5352 .direction = PM_GPIO_DIR_OUT,
5353 .pull = PM_GPIO_PULL_NO,
5354 .out_strength = PM_GPIO_STRENGTH_HIGH,
5355 .function = PM_GPIO_FUNC_NORMAL,
5356 .inv_int_pol = 0,
5357 .vin_sel = 2,
5358 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5359 .output_value = 0,
5360 }
5361
5362 };
5363#endif
5364
5365#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5366 struct pm8058_gpio_cfg line_in_gpio_cfg = {
5367 18,
5368 {
5369 .direction = PM_GPIO_DIR_IN,
5370 .pull = PM_GPIO_PULL_UP_1P5,
5371 .vin_sel = 2,
5372 .function = PM_GPIO_FUNC_NORMAL,
5373 .inv_int_pol = 0,
5374 }
5375 };
5376#endif
5377
5378#if defined(CONFIG_QS_S5K4E1)
5379 {
5380 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
5381 26,
5382 {
5383 .direction = PM_GPIO_DIR_OUT,
5384 .output_value = 0,
5385 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5386 .pull = PM_GPIO_PULL_DN,
5387 .out_strength = PM_GPIO_STRENGTH_HIGH,
5388 .function = PM_GPIO_FUNC_NORMAL,
5389 .vin_sel = 2,
5390 .inv_int_pol = 0,
5391 }
5392 };
5393#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005394#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5395 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
5396 GPIO_NT35582_BL_EN_HW_PIN - 1,
5397 {
5398 .direction = PM_GPIO_DIR_OUT,
5399 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5400 .output_value = 1,
5401 .pull = PM_GPIO_PULL_UP_30,
5402 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
5403 .vin_sel = PM_GPIO_VIN_L5,
5404 .out_strength = PM_GPIO_STRENGTH_HIGH,
5405 .function = PM_GPIO_FUNC_NORMAL,
5406 .inv_int_pol = 0,
5407 }
5408 };
5409#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005410#if defined(CONFIG_HAPTIC_ISA1200) || \
5411 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5412 if (machine_is_msm8x60_fluid()) {
5413 rc = pm8058_gpio_config(en_hap_gpio_cfg.gpio,
5414 &en_hap_gpio_cfg.cfg);
5415 if (rc < 0) {
5416 pr_err("%s pmic haptics gpio config failed\n",
5417 __func__);
5418 return rc;
5419 }
5420 }
5421#endif
5422
5423#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5424 /* Line_in only for 8660 ffa & surf */
5425 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005426 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005427 machine_is_msm8x60_fusn_ffa()) {
5428 rc = pm8058_gpio_config(line_in_gpio_cfg.gpio,
5429 &line_in_gpio_cfg.cfg);
5430 if (rc < 0) {
5431 pr_err("%s pmic line_in gpio config failed\n",
5432 __func__);
5433 return rc;
5434 }
5435 }
5436#endif
5437
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005438#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5439 if (machine_is_msm8x60_dragon()) {
5440 rc = pm8058_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
5441 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5442 if (rc < 0) {
5443 pr_err("%s pmic gpio config failed\n", __func__);
5444 return rc;
5445 }
5446 }
5447#endif
5448
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005449#if defined(CONFIG_QS_S5K4E1)
5450 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5451 if (machine_is_msm8x60_fluid()) {
5452 rc = pm8058_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
5453 &qs_hc37_cam_pd_gpio_cfg.cfg);
5454 if (rc < 0) {
5455 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5456 __func__);
5457 return rc;
5458 }
5459 }
5460 }
5461#endif
5462
5463 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
5464 rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
5465 &gpio_cfgs[i].cfg);
5466 if (rc < 0) {
5467 pr_err("%s pmic gpio config failed\n",
5468 __func__);
5469 return rc;
5470 }
5471 }
5472
5473 return 0;
5474}
5475
5476static const unsigned int ffa_keymap[] = {
5477 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5478 KEY(0, 1, KEY_UP), /* NAV - UP */
5479 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5480 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5481
5482 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5483 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5484 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5485 KEY(1, 3, KEY_VOLUMEDOWN),
5486
5487 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5488
5489 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5490 KEY(4, 1, KEY_UP), /* USER_UP */
5491 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5492 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5493 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5494
5495 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5496 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5497 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5498 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5499 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5500};
5501
Zhang Chang Ken683be172011-08-10 17:45:34 -04005502static const unsigned int dragon_keymap[] = {
5503 KEY(0, 0, KEY_MENU),
5504 KEY(0, 2, KEY_1),
5505 KEY(0, 3, KEY_4),
5506 KEY(0, 4, KEY_7),
5507
5508 KEY(1, 0, KEY_UP),
5509 KEY(1, 1, KEY_LEFT),
5510 KEY(1, 2, KEY_DOWN),
5511 KEY(1, 3, KEY_5),
5512 KEY(1, 4, KEY_8),
5513
5514 KEY(2, 0, KEY_HOME),
5515 KEY(2, 1, KEY_REPLY),
5516 KEY(2, 2, KEY_2),
5517 KEY(2, 3, KEY_6),
5518 KEY(2, 4, KEY_0),
5519
5520 KEY(3, 0, KEY_VOLUMEUP),
5521 KEY(3, 1, KEY_RIGHT),
5522 KEY(3, 2, KEY_3),
5523 KEY(3, 3, KEY_9),
5524 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5525
5526 KEY(4, 0, KEY_VOLUMEDOWN),
5527 KEY(4, 1, KEY_BACK),
5528 KEY(4, 2, KEY_CAMERA),
5529 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5530};
5531
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005532static struct resource resources_keypad[] = {
5533 {
5534 .start = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5535 .end = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5536 .flags = IORESOURCE_IRQ,
5537 },
5538 {
5539 .start = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5540 .end = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5541 .flags = IORESOURCE_IRQ,
5542 },
5543};
5544
5545static struct matrix_keymap_data ffa_keymap_data = {
5546 .keymap_size = ARRAY_SIZE(ffa_keymap),
5547 .keymap = ffa_keymap,
5548};
5549
5550static struct pmic8058_keypad_data ffa_keypad_data = {
5551 .input_name = "ffa-keypad",
5552 .input_phys_device = "ffa-keypad/input0",
5553 .num_rows = 6,
5554 .num_cols = 5,
5555 .rows_gpio_start = 8,
5556 .cols_gpio_start = 0,
5557 .debounce_ms = {8, 10},
5558 .scan_delay_ms = 32,
5559 .row_hold_ns = 91500,
5560 .wakeup = 1,
5561 .keymap_data = &ffa_keymap_data,
5562};
5563
Zhang Chang Ken683be172011-08-10 17:45:34 -04005564static struct matrix_keymap_data dragon_keymap_data = {
5565 .keymap_size = ARRAY_SIZE(dragon_keymap),
5566 .keymap = dragon_keymap,
5567};
5568
5569static struct pmic8058_keypad_data dragon_keypad_data = {
5570 .input_name = "dragon-keypad",
5571 .input_phys_device = "dragon-keypad/input0",
5572 .num_rows = 6,
5573 .num_cols = 5,
5574 .rows_gpio_start = 8,
5575 .cols_gpio_start = 0,
5576 .debounce_ms = {8, 10},
5577 .scan_delay_ms = 32,
5578 .row_hold_ns = 91500,
5579 .wakeup = 1,
5580 .keymap_data = &dragon_keymap_data,
5581};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005582static const unsigned int fluid_keymap[] = {
5583 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5584 KEY(0, 1, KEY_UP), /* NAV - UP */
5585 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5586 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5587
5588 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5589 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5590 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5591 KEY(1, 3, KEY_VOLUMEUP),
5592
5593 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5594
5595 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5596 KEY(4, 1, KEY_UP), /* USER_UP */
5597 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5598 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5599 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5600
Jilai Wang9a895102011-07-12 14:00:35 -04005601 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005602 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5603 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5604 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5605 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5606};
5607
5608static struct matrix_keymap_data fluid_keymap_data = {
5609 .keymap_size = ARRAY_SIZE(fluid_keymap),
5610 .keymap = fluid_keymap,
5611};
5612
5613static struct pmic8058_keypad_data fluid_keypad_data = {
5614 .input_name = "fluid-keypad",
5615 .input_phys_device = "fluid-keypad/input0",
5616 .num_rows = 6,
5617 .num_cols = 5,
5618 .rows_gpio_start = 8,
5619 .cols_gpio_start = 0,
5620 .debounce_ms = {8, 10},
5621 .scan_delay_ms = 32,
5622 .row_hold_ns = 91500,
5623 .wakeup = 1,
5624 .keymap_data = &fluid_keymap_data,
5625};
5626
5627static struct resource resources_pwrkey[] = {
5628 {
5629 .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5630 .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5631 .flags = IORESOURCE_IRQ,
5632 },
5633 {
5634 .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5635 .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5636 .flags = IORESOURCE_IRQ,
5637 },
5638};
5639
5640static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
5641 .pull_up = 1,
5642 .kpd_trigger_delay_us = 970,
5643 .wakeup = 1,
5644 .pwrkey_time_ms = 500,
5645};
5646
5647static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
5648 .initial_vibrate_ms = 500,
5649 .level_mV = 3000,
5650 .max_timeout_ms = 15000,
5651};
5652
5653#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5654#define PM8058_OTHC_CNTR_BASE0 0xA0
5655#define PM8058_OTHC_CNTR_BASE1 0x134
5656#define PM8058_OTHC_CNTR_BASE2 0x137
5657#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5658
5659static struct othc_accessory_info othc_accessories[] = {
5660 {
5661 .accessory = OTHC_SVIDEO_OUT,
5662 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5663 | OTHC_ADC_DETECT,
5664 .key_code = SW_VIDEOOUT_INSERT,
5665 .enabled = false,
5666 .adc_thres = {
5667 .min_threshold = 20,
5668 .max_threshold = 40,
5669 },
5670 },
5671 {
5672 .accessory = OTHC_ANC_HEADPHONE,
5673 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5674 OTHC_SWITCH_DETECT,
5675 .gpio = PM8058_LINE_IN_DET_GPIO,
5676 .active_low = 1,
5677 .key_code = SW_HEADPHONE_INSERT,
5678 .enabled = true,
5679 },
5680 {
5681 .accessory = OTHC_ANC_HEADSET,
5682 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5683 .gpio = PM8058_LINE_IN_DET_GPIO,
5684 .active_low = 1,
5685 .key_code = SW_HEADPHONE_INSERT,
5686 .enabled = true,
5687 },
5688 {
5689 .accessory = OTHC_HEADPHONE,
5690 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5691 .key_code = SW_HEADPHONE_INSERT,
5692 .enabled = true,
5693 },
5694 {
5695 .accessory = OTHC_MICROPHONE,
5696 .detect_flags = OTHC_GPIO_DETECT,
5697 .gpio = PM8058_LINE_IN_DET_GPIO,
5698 .active_low = 1,
5699 .key_code = SW_MICROPHONE_INSERT,
5700 .enabled = true,
5701 },
5702 {
5703 .accessory = OTHC_HEADSET,
5704 .detect_flags = OTHC_MICBIAS_DETECT,
5705 .key_code = SW_HEADPHONE_INSERT,
5706 .enabled = true,
5707 },
5708};
5709
5710static struct othc_switch_info switch_info[] = {
5711 {
5712 .min_adc_threshold = 0,
5713 .max_adc_threshold = 100,
5714 .key_code = KEY_PLAYPAUSE,
5715 },
5716 {
5717 .min_adc_threshold = 100,
5718 .max_adc_threshold = 200,
5719 .key_code = KEY_REWIND,
5720 },
5721 {
5722 .min_adc_threshold = 200,
5723 .max_adc_threshold = 500,
5724 .key_code = KEY_FASTFORWARD,
5725 },
5726};
5727
5728static struct othc_n_switch_config switch_config = {
5729 .voltage_settling_time_ms = 0,
5730 .num_adc_samples = 3,
5731 .adc_channel = CHANNEL_ADC_HDSET,
5732 .switch_info = switch_info,
5733 .num_keys = ARRAY_SIZE(switch_info),
5734 .default_sw_en = true,
5735 .default_sw_idx = 0,
5736};
5737
5738static struct hsed_bias_config hsed_bias_config = {
5739 /* HSED mic bias config info */
5740 .othc_headset = OTHC_HEADSET_NO,
5741 .othc_lowcurr_thresh_uA = 100,
5742 .othc_highcurr_thresh_uA = 600,
5743 .othc_hyst_prediv_us = 7800,
5744 .othc_period_clkdiv_us = 62500,
5745 .othc_hyst_clk_us = 121000,
5746 .othc_period_clk_us = 312500,
5747 .othc_wakeup = 1,
5748};
5749
5750static struct othc_hsed_config hsed_config_1 = {
5751 .hsed_bias_config = &hsed_bias_config,
5752 /*
5753 * The detection delay and switch reporting delay are
5754 * required to encounter a hardware bug (spurious switch
5755 * interrupts on slow insertion/removal of the headset).
5756 * This will introduce a delay in reporting the accessory
5757 * insertion and removal to the userspace.
5758 */
5759 .detection_delay_ms = 1500,
5760 /* Switch info */
5761 .switch_debounce_ms = 1500,
5762 .othc_support_n_switch = false,
5763 .switch_config = &switch_config,
5764 .ir_gpio = -1,
5765 /* Accessory info */
5766 .accessories_support = true,
5767 .accessories = othc_accessories,
5768 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5769};
5770
5771static struct othc_regulator_config othc_reg = {
5772 .regulator = "8058_l5",
5773 .max_uV = 2850000,
5774 .min_uV = 2850000,
5775};
5776
5777/* MIC_BIAS0 is configured as normal MIC BIAS */
5778static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5779 .micbias_select = OTHC_MICBIAS_0,
5780 .micbias_capability = OTHC_MICBIAS,
5781 .micbias_enable = OTHC_SIGNAL_OFF,
5782 .micbias_regulator = &othc_reg,
5783};
5784
5785/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5786static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5787 .micbias_select = OTHC_MICBIAS_1,
5788 .micbias_capability = OTHC_MICBIAS_HSED,
5789 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5790 .micbias_regulator = &othc_reg,
5791 .hsed_config = &hsed_config_1,
5792 .hsed_name = "8660_handset",
5793};
5794
5795/* MIC_BIAS2 is configured as normal MIC BIAS */
5796static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5797 .micbias_select = OTHC_MICBIAS_2,
5798 .micbias_capability = OTHC_MICBIAS,
5799 .micbias_enable = OTHC_SIGNAL_OFF,
5800 .micbias_regulator = &othc_reg,
5801};
5802
5803static struct resource resources_othc_0[] = {
5804 {
5805 .name = "othc_base",
5806 .start = PM8058_OTHC_CNTR_BASE0,
5807 .end = PM8058_OTHC_CNTR_BASE0,
5808 .flags = IORESOURCE_IO,
5809 },
5810};
5811
5812static struct resource resources_othc_1[] = {
5813 {
5814 .start = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5815 .end = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5816 .flags = IORESOURCE_IRQ,
5817 },
5818 {
5819 .start = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5820 .end = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5821 .flags = IORESOURCE_IRQ,
5822 },
5823 {
5824 .name = "othc_base",
5825 .start = PM8058_OTHC_CNTR_BASE1,
5826 .end = PM8058_OTHC_CNTR_BASE1,
5827 .flags = IORESOURCE_IO,
5828 },
5829};
5830
5831static struct resource resources_othc_2[] = {
5832 {
5833 .name = "othc_base",
5834 .start = PM8058_OTHC_CNTR_BASE2,
5835 .end = PM8058_OTHC_CNTR_BASE2,
5836 .flags = IORESOURCE_IO,
5837 },
5838};
5839
5840static void __init msm8x60_init_pm8058_othc(void)
5841{
5842 int i;
5843
5844 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5845 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5846 machine_is_msm8x60_fusn_ffa()) {
5847 /* 3-switch headset supported only by V2 FFA and FLUID */
5848 hsed_config_1.accessories_adc_support = true,
5849 /* ADC based accessory detection works only on V2 and FLUID */
5850 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5851 hsed_config_1.othc_support_n_switch = true;
5852 }
5853
5854 /* IR GPIO is absent on FLUID */
5855 if (machine_is_msm8x60_fluid())
5856 hsed_config_1.ir_gpio = -1;
5857
5858 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5859 if (machine_is_msm8x60_fluid()) {
5860 switch (othc_accessories[i].accessory) {
5861 case OTHC_ANC_HEADPHONE:
5862 case OTHC_ANC_HEADSET:
5863 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5864 break;
5865 case OTHC_MICROPHONE:
5866 othc_accessories[i].enabled = false;
5867 break;
5868 case OTHC_SVIDEO_OUT:
5869 othc_accessories[i].enabled = true;
5870 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5871 break;
5872 }
5873 }
5874 }
5875}
5876#endif
5877
5878static struct resource resources_pm8058_charger[] = {
5879 { .name = "CHGVAL",
5880 .start = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5881 .end = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5882 .flags = IORESOURCE_IRQ,
5883 },
5884 { .name = "CHGINVAL",
5885 .start = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5886 .end = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5887 .flags = IORESOURCE_IRQ,
5888 },
5889 {
5890 .name = "CHGILIM",
5891 .start = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5892 .end = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5893 .flags = IORESOURCE_IRQ,
5894 },
5895 {
5896 .name = "VCP",
5897 .start = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5898 .end = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5899 .flags = IORESOURCE_IRQ,
5900 },
5901 {
5902 .name = "ATC_DONE",
5903 .start = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5904 .end = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5905 .flags = IORESOURCE_IRQ,
5906 },
5907 {
5908 .name = "ATCFAIL",
5909 .start = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5910 .end = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5911 .flags = IORESOURCE_IRQ,
5912 },
5913 {
5914 .name = "AUTO_CHGDONE",
5915 .start = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5916 .end = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5917 .flags = IORESOURCE_IRQ,
5918 },
5919 {
5920 .name = "AUTO_CHGFAIL",
5921 .start = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5922 .end = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5923 .flags = IORESOURCE_IRQ,
5924 },
5925 {
5926 .name = "CHGSTATE",
5927 .start = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5928 .end = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5929 .flags = IORESOURCE_IRQ,
5930 },
5931 {
5932 .name = "FASTCHG",
5933 .start = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5934 .end = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5935 .flags = IORESOURCE_IRQ,
5936 },
5937 {
5938 .name = "CHG_END",
5939 .start = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5940 .end = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5941 .flags = IORESOURCE_IRQ,
5942 },
5943 {
5944 .name = "BATTTEMP",
5945 .start = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5946 .end = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5947 .flags = IORESOURCE_IRQ,
5948 },
5949 {
5950 .name = "CHGHOT",
5951 .start = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5952 .end = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5953 .flags = IORESOURCE_IRQ,
5954 },
5955 {
5956 .name = "CHGTLIMIT",
5957 .start = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5958 .end = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5959 .flags = IORESOURCE_IRQ,
5960 },
5961 {
5962 .name = "CHG_GONE",
5963 .start = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5964 .end = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5965 .flags = IORESOURCE_IRQ,
5966 },
5967 {
5968 .name = "VCPMAJOR",
5969 .start = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5970 .end = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5971 .flags = IORESOURCE_IRQ,
5972 },
5973 {
5974 .name = "VBATDET",
5975 .start = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5976 .end = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5977 .flags = IORESOURCE_IRQ,
5978 },
5979 {
5980 .name = "BATFET",
5981 .start = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5982 .end = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5983 .flags = IORESOURCE_IRQ,
5984 },
5985 {
5986 .name = "BATT_REPLACE",
5987 .start = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5988 .end = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5989 .flags = IORESOURCE_IRQ,
5990 },
5991 {
5992 .name = "BATTCONNECT",
5993 .start = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5994 .end = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5995 .flags = IORESOURCE_IRQ,
5996 },
5997 {
5998 .name = "VBATDET_LOW",
5999 .start = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6000 .end = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6001 .flags = IORESOURCE_IRQ,
6002 },
6003};
6004
6005static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
6006{
6007 struct pm8058_gpio pwm_gpio_config = {
6008 .direction = PM_GPIO_DIR_OUT,
6009 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
6010 .output_value = 0,
6011 .pull = PM_GPIO_PULL_NO,
6012 .vin_sel = PM_GPIO_VIN_VPH,
6013 .out_strength = PM_GPIO_STRENGTH_HIGH,
6014 .function = PM_GPIO_FUNC_2,
6015 };
6016
6017 int rc = -EINVAL;
6018 int id, mode, max_mA;
6019
6020 id = mode = max_mA = 0;
6021 switch (ch) {
6022 case 0:
6023 case 1:
6024 case 2:
6025 if (on) {
6026 id = 24 + ch;
6027 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
6028 if (rc)
6029 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
6030 __func__, id, rc);
6031 }
6032 break;
6033
6034 case 6:
6035 id = PM_PWM_LED_FLASH;
6036 mode = PM_PWM_CONF_PWM1;
6037 max_mA = 300;
6038 break;
6039
6040 case 7:
6041 id = PM_PWM_LED_FLASH1;
6042 mode = PM_PWM_CONF_PWM1;
6043 max_mA = 300;
6044 break;
6045
6046 default:
6047 break;
6048 }
6049
6050 if (ch >= 6 && ch <= 7) {
6051 if (!on) {
6052 mode = PM_PWM_CONF_NONE;
6053 max_mA = 0;
6054 }
6055 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6056 if (rc)
6057 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6058 __func__, ch, rc);
6059 }
6060 return rc;
6061
6062}
6063
6064static struct pm8058_pwm_pdata pm8058_pwm_data = {
6065 .config = pm8058_pwm_config,
6066};
6067
6068#define PM8058_GPIO_INT 88
6069
6070static struct pm8058_gpio_platform_data pm8058_gpio_data = {
6071 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6072 .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
6073 .init = pm8058_gpios_init,
6074};
6075
6076static struct pm8058_gpio_platform_data pm8058_mpp_data = {
6077 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
6078 .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
6079};
6080
6081static struct resource resources_rtc[] = {
6082 {
6083 .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6084 .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6085 .flags = IORESOURCE_IRQ,
6086 },
6087 {
6088 .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6089 .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6090 .flags = IORESOURCE_IRQ,
6091 },
6092};
6093
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306094static struct pm8058_rtc_platform_data pm8058_rtc_pdata = {
6095 .rtc_alarm_powerup = false,
6096};
6097
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006098static struct pmic8058_led pmic8058_flash_leds[] = {
6099 [0] = {
6100 .name = "camera:flash0",
6101 .max_brightness = 15,
6102 .id = PMIC8058_ID_FLASH_LED_0,
6103 },
6104 [1] = {
6105 .name = "camera:flash1",
6106 .max_brightness = 15,
6107 .id = PMIC8058_ID_FLASH_LED_1,
6108 },
6109};
6110
6111static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6112 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6113 .leds = pmic8058_flash_leds,
6114};
6115
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006116static struct pmic8058_led pmic8058_dragon_leds[] = {
6117 [0] = {
6118 /* RED */
6119 .name = "led_drv0",
6120 .max_brightness = 15,
6121 .id = PMIC8058_ID_LED_0,
6122 },/* 300 mA flash led0 drv sink */
6123 [1] = {
6124 /* Yellow */
6125 .name = "led_drv1",
6126 .max_brightness = 15,
6127 .id = PMIC8058_ID_LED_1,
6128 },/* 300 mA flash led0 drv sink */
6129 [2] = {
6130 /* Green */
6131 .name = "led_drv2",
6132 .max_brightness = 15,
6133 .id = PMIC8058_ID_LED_2,
6134 },/* 300 mA flash led0 drv sink */
6135 [3] = {
6136 .name = "led_psensor",
6137 .max_brightness = 15,
6138 .id = PMIC8058_ID_LED_KB_LIGHT,
6139 },/* 300 mA flash led0 drv sink */
6140};
6141
6142static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6143 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6144 .leds = pmic8058_dragon_leds,
6145};
6146
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006147static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6148 [0] = {
6149 .name = "led:drv0",
6150 .max_brightness = 15,
6151 .id = PMIC8058_ID_FLASH_LED_0,
6152 },/* 300 mA flash led0 drv sink */
6153 [1] = {
6154 .name = "led:drv1",
6155 .max_brightness = 15,
6156 .id = PMIC8058_ID_FLASH_LED_1,
6157 },/* 300 mA flash led1 sink */
6158 [2] = {
6159 .name = "led:drv2",
6160 .max_brightness = 20,
6161 .id = PMIC8058_ID_LED_0,
6162 },/* 40 mA led0 sink */
6163 [3] = {
6164 .name = "keypad:drv",
6165 .max_brightness = 15,
6166 .id = PMIC8058_ID_LED_KB_LIGHT,
6167 },/* 300 mA keypad drv sink */
6168};
6169
6170static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6171 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6172 .leds = pmic8058_fluid_flash_leds,
6173};
6174
6175static struct resource resources_temp_alarm[] = {
6176 {
6177 .start = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6178 .end = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6179 .flags = IORESOURCE_IRQ,
6180 },
6181};
6182
6183static struct resource resources_pm8058_misc[] = {
6184 {
6185 .start = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6186 .end = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6187 .flags = IORESOURCE_IRQ,
6188 },
6189};
6190
6191static struct resource resources_pm8058_batt_alarm[] = {
6192 {
6193 .start = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6194 .end = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6195 .flags = IORESOURCE_IRQ,
6196 },
6197};
6198
6199#define PM8058_SUBDEV_KPD 0
6200#define PM8058_SUBDEV_LED 1
6201#define PM8058_SUBDEV_VIB 2
6202
6203static struct mfd_cell pm8058_subdevs[] = {
6204 {
6205 .name = "pm8058-keypad",
6206 .id = -1,
6207 .num_resources = ARRAY_SIZE(resources_keypad),
6208 .resources = resources_keypad,
6209 },
6210 { .name = "pm8058-led",
6211 .id = -1,
6212 },
6213 {
6214 .name = "pm8058-vib",
6215 .id = -1,
6216 },
6217 { .name = "pm8058-gpio",
6218 .id = -1,
6219 .platform_data = &pm8058_gpio_data,
6220 .pdata_size = sizeof(pm8058_gpio_data),
6221 },
6222 { .name = "pm8058-mpp",
6223 .id = -1,
6224 .platform_data = &pm8058_mpp_data,
6225 .pdata_size = sizeof(pm8058_mpp_data),
6226 },
6227 { .name = "pm8058-pwrkey",
6228 .id = -1,
6229 .resources = resources_pwrkey,
6230 .num_resources = ARRAY_SIZE(resources_pwrkey),
6231 .platform_data = &pwrkey_pdata,
6232 .pdata_size = sizeof(pwrkey_pdata),
6233 },
6234 {
6235 .name = "pm8058-pwm",
6236 .id = -1,
6237 .platform_data = &pm8058_pwm_data,
6238 .pdata_size = sizeof(pm8058_pwm_data),
6239 },
6240#ifdef CONFIG_SENSORS_MSM_ADC
6241 {
6242 .name = "pm8058-xoadc",
6243 .id = -1,
6244 .num_resources = ARRAY_SIZE(resources_adc),
6245 .resources = resources_adc,
6246 .platform_data = &xoadc_pdata,
6247 .pdata_size = sizeof(xoadc_pdata),
6248 },
6249#endif
6250#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
6251 {
6252 .name = "pm8058-othc",
6253 .id = 0,
6254 .platform_data = &othc_config_pdata_0,
6255 .pdata_size = sizeof(othc_config_pdata_0),
6256 .num_resources = ARRAY_SIZE(resources_othc_0),
6257 .resources = resources_othc_0,
6258 },
6259 {
6260 /* OTHC1 module has headset/switch dection */
6261 .name = "pm8058-othc",
6262 .id = 1,
6263 .num_resources = ARRAY_SIZE(resources_othc_1),
6264 .resources = resources_othc_1,
6265 .platform_data = &othc_config_pdata_1,
6266 .pdata_size = sizeof(othc_config_pdata_1),
6267 },
6268 {
6269 .name = "pm8058-othc",
6270 .id = 2,
6271 .platform_data = &othc_config_pdata_2,
6272 .pdata_size = sizeof(othc_config_pdata_2),
6273 .num_resources = ARRAY_SIZE(resources_othc_2),
6274 .resources = resources_othc_2,
6275 },
6276#endif
6277 {
6278 .name = "pm8058-rtc",
6279 .id = -1,
6280 .num_resources = ARRAY_SIZE(resources_rtc),
6281 .resources = resources_rtc,
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306282 .platform_data = &pm8058_rtc_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006283 },
6284 {
6285 .name = "pm8058-tm",
6286 .id = -1,
6287 .num_resources = ARRAY_SIZE(resources_temp_alarm),
6288 .resources = resources_temp_alarm,
6289 },
6290 { .name = "pm8058-upl",
6291 .id = -1,
6292 },
6293 {
6294 .name = "pm8058-misc",
6295 .id = -1,
6296 .num_resources = ARRAY_SIZE(resources_pm8058_misc),
6297 .resources = resources_pm8058_misc,
6298 },
6299 { .name = "pm8058-batt-alarm",
6300 .id = -1,
6301 .num_resources = ARRAY_SIZE(resources_pm8058_batt_alarm),
6302 .resources = resources_pm8058_batt_alarm,
6303 },
6304};
6305
Terence Hampson90508a92011-08-09 10:40:08 -04006306static struct pmic8058_charger_data pmic8058_charger_dragon = {
6307 .max_source_current = 1800,
6308 .charger_type = CHG_TYPE_AC,
6309};
6310
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006311static struct mfd_cell pm8058_charger_sub_dev = {
6312 .name = "pm8058-charger",
6313 .id = -1,
6314 .num_resources = ARRAY_SIZE(resources_pm8058_charger),
6315 .resources = resources_pm8058_charger,
6316};
6317
6318static struct pm8058_platform_data pm8058_platform_data = {
6319 .irq_base = PM8058_IRQ_BASE,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306320 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006321
6322 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
6323 .sub_devices = pm8058_subdevs,
6324 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6325};
6326
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306327#ifdef CONFIG_MSM_SSBI
6328static struct msm_ssbi_platform_data msm8x60_ssbi_pm8058_pdata __devinitdata = {
6329 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
6330 .slave = {
6331 .name = "pm8058-core",
6332 .platform_data = &pm8058_platform_data,
6333 },
6334};
6335#endif
6336#endif /* CONFIG_PMIC8058 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006337
6338#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6339 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6340#define TDISC_I2C_SLAVE_ADDR 0x67
6341#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6342#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6343
6344static const char *vregs_tdisc_name[] = {
6345 "8058_l5",
6346 "8058_s3",
6347};
6348
6349static const int vregs_tdisc_val[] = {
6350 2850000,/* uV */
6351 1800000,
6352};
6353static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6354
6355static int tdisc_shinetsu_setup(void)
6356{
6357 int rc, i;
6358
6359 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6360 if (rc) {
6361 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6362 __func__);
6363 return rc;
6364 }
6365
6366 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6367 if (rc) {
6368 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6369 __func__);
6370 goto fail_gpio_oe;
6371 }
6372
6373 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6374 if (rc) {
6375 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6376 __func__);
6377 gpio_free(GPIO_JOYSTICK_EN);
6378 goto fail_gpio_oe;
6379 }
6380
6381 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6382 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6383 if (IS_ERR(vregs_tdisc[i])) {
6384 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6385 __func__, vregs_tdisc_name[i],
6386 PTR_ERR(vregs_tdisc[i]));
6387 rc = PTR_ERR(vregs_tdisc[i]);
6388 goto vreg_get_fail;
6389 }
6390
6391 rc = regulator_set_voltage(vregs_tdisc[i],
6392 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6393 if (rc) {
6394 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6395 __func__, rc);
6396 goto vreg_set_voltage_fail;
6397 }
6398 }
6399
6400 return rc;
6401vreg_set_voltage_fail:
6402 i++;
6403vreg_get_fail:
6404 while (i)
6405 regulator_put(vregs_tdisc[--i]);
6406fail_gpio_oe:
6407 gpio_free(PMIC_GPIO_TDISC);
6408 return rc;
6409}
6410
6411static void tdisc_shinetsu_release(void)
6412{
6413 int i;
6414
6415 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6416 regulator_put(vregs_tdisc[i]);
6417
6418 gpio_free(PMIC_GPIO_TDISC);
6419 gpio_free(GPIO_JOYSTICK_EN);
6420}
6421
6422static int tdisc_shinetsu_enable(void)
6423{
6424 int i, rc = -EINVAL;
6425
6426 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6427 rc = regulator_enable(vregs_tdisc[i]);
6428 if (rc < 0) {
6429 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6430 __func__, vregs_tdisc_name[i], rc);
6431 goto vreg_fail;
6432 }
6433 }
6434
6435 /* Enable the OE (output enable) gpio */
6436 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6437 /* voltage and gpio stabilization delay */
6438 msleep(50);
6439
6440 return 0;
6441vreg_fail:
6442 while (i)
6443 regulator_disable(vregs_tdisc[--i]);
6444 return rc;
6445}
6446
6447static int tdisc_shinetsu_disable(void)
6448{
6449 int i, rc;
6450
6451 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6452 rc = regulator_disable(vregs_tdisc[i]);
6453 if (rc < 0) {
6454 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6455 __func__, vregs_tdisc_name[i], rc);
6456 goto tdisc_reg_fail;
6457 }
6458 }
6459
6460 /* Disable the OE (output enable) gpio */
6461 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6462
6463 return 0;
6464
6465tdisc_reg_fail:
6466 while (i)
6467 regulator_enable(vregs_tdisc[--i]);
6468 return rc;
6469}
6470
6471static struct tdisc_abs_values tdisc_abs = {
6472 .x_max = 32,
6473 .y_max = 32,
6474 .x_min = -32,
6475 .y_min = -32,
6476 .pressure_max = 32,
6477 .pressure_min = 0,
6478};
6479
6480static struct tdisc_platform_data tdisc_data = {
6481 .tdisc_setup = tdisc_shinetsu_setup,
6482 .tdisc_release = tdisc_shinetsu_release,
6483 .tdisc_enable = tdisc_shinetsu_enable,
6484 .tdisc_disable = tdisc_shinetsu_disable,
6485 .tdisc_wakeup = 0,
6486 .tdisc_gpio = PMIC_GPIO_TDISC,
6487 .tdisc_report_keys = true,
6488 .tdisc_report_relative = true,
6489 .tdisc_report_absolute = false,
6490 .tdisc_report_wheel = false,
6491 .tdisc_reverse_x = false,
6492 .tdisc_reverse_y = true,
6493 .tdisc_abs = &tdisc_abs,
6494};
6495
6496static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6497 {
6498 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6499 .irq = TDISC_INT,
6500 .platform_data = &tdisc_data,
6501 },
6502};
6503#endif
6504
6505#define PM_GPIO_CDC_RST_N 20
6506#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6507
6508static struct regulator *vreg_timpani_1;
6509static struct regulator *vreg_timpani_2;
6510
6511static unsigned int msm_timpani_setup_power(void)
6512{
6513 int rc;
6514
6515 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6516 if (IS_ERR(vreg_timpani_1)) {
6517 pr_err("%s: Unable to get 8058_l0\n", __func__);
6518 return -ENODEV;
6519 }
6520
6521 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6522 if (IS_ERR(vreg_timpani_2)) {
6523 pr_err("%s: Unable to get 8058_s3\n", __func__);
6524 regulator_put(vreg_timpani_1);
6525 return -ENODEV;
6526 }
6527
6528 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6529 if (rc) {
6530 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6531 goto fail;
6532 }
6533
6534 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6535 if (rc) {
6536 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6537 goto fail;
6538 }
6539
6540 rc = regulator_enable(vreg_timpani_1);
6541 if (rc) {
6542 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6543 goto fail;
6544 }
6545
6546 /* The settings for LDO0 should be set such that
6547 * it doesn't require to reset the timpani. */
6548 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6549 if (rc < 0) {
6550 pr_err("Timpani regulator optimum mode setting failed\n");
6551 goto fail;
6552 }
6553
6554 rc = regulator_enable(vreg_timpani_2);
6555 if (rc) {
6556 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6557 regulator_disable(vreg_timpani_1);
6558 goto fail;
6559 }
6560
6561 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6562 if (rc) {
6563 pr_err("%s: GPIO Request %d failed\n", __func__,
6564 GPIO_CDC_RST_N);
6565 regulator_disable(vreg_timpani_1);
6566 regulator_disable(vreg_timpani_2);
6567 goto fail;
6568 } else {
6569 gpio_direction_output(GPIO_CDC_RST_N, 1);
6570 usleep_range(1000, 1050);
6571 gpio_direction_output(GPIO_CDC_RST_N, 0);
6572 usleep_range(1000, 1050);
6573 gpio_direction_output(GPIO_CDC_RST_N, 1);
6574 gpio_free(GPIO_CDC_RST_N);
6575 }
6576 return rc;
6577
6578fail:
6579 regulator_put(vreg_timpani_1);
6580 regulator_put(vreg_timpani_2);
6581 return rc;
6582}
6583
6584static void msm_timpani_shutdown_power(void)
6585{
6586 int rc;
6587
6588 rc = regulator_disable(vreg_timpani_1);
6589 if (rc)
6590 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6591
6592 regulator_put(vreg_timpani_1);
6593
6594 rc = regulator_disable(vreg_timpani_2);
6595 if (rc)
6596 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6597
6598 regulator_put(vreg_timpani_2);
6599}
6600
6601/* Power analog function of codec */
6602static struct regulator *vreg_timpani_cdc_apwr;
6603static int msm_timpani_codec_power(int vreg_on)
6604{
6605 int rc = 0;
6606
6607 if (!vreg_timpani_cdc_apwr) {
6608
6609 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6610
6611 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6612 pr_err("%s: vreg_get failed (%ld)\n",
6613 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6614 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6615 return rc;
6616 }
6617 }
6618
6619 if (vreg_on) {
6620
6621 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6622 2200000, 2200000);
6623 if (rc) {
6624 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6625 __func__);
6626 goto vreg_fail;
6627 }
6628
6629 rc = regulator_enable(vreg_timpani_cdc_apwr);
6630 if (rc) {
6631 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6632 goto vreg_fail;
6633 }
6634 } else {
6635 rc = regulator_disable(vreg_timpani_cdc_apwr);
6636 if (rc) {
6637 pr_err("%s: vreg_disable failed %d\n",
6638 __func__, rc);
6639 goto vreg_fail;
6640 }
6641 }
6642
6643 return 0;
6644
6645vreg_fail:
6646 regulator_put(vreg_timpani_cdc_apwr);
6647 vreg_timpani_cdc_apwr = NULL;
6648 return rc;
6649}
6650
6651static struct marimba_codec_platform_data timpani_codec_pdata = {
6652 .marimba_codec_power = msm_timpani_codec_power,
6653};
6654
6655#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6656#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6657
6658static struct marimba_platform_data timpani_pdata = {
6659 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6660 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6661 .marimba_setup = msm_timpani_setup_power,
6662 .marimba_shutdown = msm_timpani_shutdown_power,
6663 .codec = &timpani_codec_pdata,
6664 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6665};
6666
6667#define TIMPANI_I2C_SLAVE_ADDR 0xD
6668
6669static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6670 {
6671 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6672 .platform_data = &timpani_pdata,
6673 },
6674};
6675
Lei Zhou338cab82011-08-19 13:38:17 -04006676#ifdef CONFIG_SND_SOC_WM8903
6677static struct wm8903_platform_data wm8903_pdata = {
6678 .gpio_cfg[2] = 0x3A8,
6679};
6680
6681#define WM8903_I2C_SLAVE_ADDR 0x34
6682static struct i2c_board_info wm8903_codec_i2c_info[] = {
6683 {
6684 I2C_BOARD_INFO("wm8903", WM8903_I2C_SLAVE_ADDR >> 1),
6685 .platform_data = &wm8903_pdata,
6686 },
6687};
6688#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006689#ifdef CONFIG_PMIC8901
6690
6691#define PM8901_GPIO_INT 91
6692
6693static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6694 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6695 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6696};
6697
6698static struct resource pm8901_temp_alarm[] = {
6699 {
6700 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6701 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6702 .flags = IORESOURCE_IRQ,
6703 },
6704 {
6705 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6706 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6707 .flags = IORESOURCE_IRQ,
6708 },
6709};
6710
6711/*
6712 * Consumer specific regulator names:
6713 * regulator name consumer dev_name
6714 */
6715static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6716 REGULATOR_SUPPLY("8901_mpp0", NULL),
6717};
6718static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6719 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6720};
6721static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6722 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6723};
6724
6725#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6726 _always_on, _active_high) \
6727 [PM8901_VREG_ID_##_id] = { \
6728 .init_data = { \
6729 .constraints = { \
6730 .valid_modes_mask = _modes, \
6731 .valid_ops_mask = _ops, \
6732 .min_uV = _min_uV, \
6733 .max_uV = _max_uV, \
6734 .input_uV = _min_uV, \
6735 .apply_uV = _apply_uV, \
6736 .always_on = _always_on, \
6737 }, \
6738 .consumer_supplies = vreg_consumers_8901_##_id, \
6739 .num_consumer_supplies = \
6740 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6741 }, \
6742 .active_high = _active_high, \
6743 }
6744
6745#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6746 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6747 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6748
6749#define PM8901_VREG_INIT_VS(_id) \
6750 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6751 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6752
6753static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6754 PM8901_VREG_INIT_MPP(MPP0, 1),
6755
6756 PM8901_VREG_INIT_VS(USB_OTG),
6757 PM8901_VREG_INIT_VS(HDMI_MVS),
6758};
6759
6760#define PM8901_VREG(_id) { \
6761 .name = "pm8901-regulator", \
6762 .id = _id, \
6763 .platform_data = &pm8901_vreg_init_pdata[_id], \
6764 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6765}
6766
6767static struct mfd_cell pm8901_subdevs[] = {
6768 { .name = "pm8901-mpp",
6769 .id = -1,
6770 .platform_data = &pm8901_mpp_data,
6771 .pdata_size = sizeof(pm8901_mpp_data),
6772 },
6773 { .name = "pm8901-tm",
6774 .id = -1,
6775 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6776 .resources = pm8901_temp_alarm,
6777 },
6778 PM8901_VREG(PM8901_VREG_ID_MPP0),
6779 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6780 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6781};
6782
6783static struct pm8901_platform_data pm8901_platform_data = {
6784 .irq_base = PM8901_IRQ_BASE,
6785 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6786 .sub_devices = pm8901_subdevs,
6787 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6788};
6789
6790static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6791 {
6792 I2C_BOARD_INFO("pm8901-core", 0x55),
6793 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6794 .platform_data = &pm8901_platform_data,
6795 },
6796};
6797
6798#endif /* CONFIG_PMIC8901 */
6799
6800#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6801 || defined(CONFIG_GPIO_SX150X_MODULE))
6802
6803static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006804static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006805
6806struct bahama_config_register{
6807 u8 reg;
6808 u8 value;
6809 u8 mask;
6810};
6811
6812enum version{
6813 VER_1_0,
6814 VER_2_0,
6815 VER_UNSUPPORTED = 0xFF
6816};
6817
6818static u8 read_bahama_ver(void)
6819{
6820 int rc;
6821 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6822 u8 bahama_version;
6823
6824 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6825 if (rc < 0) {
6826 printk(KERN_ERR
6827 "%s: version read failed: %d\n",
6828 __func__, rc);
6829 return VER_UNSUPPORTED;
6830 } else {
6831 printk(KERN_INFO
6832 "%s: version read got: 0x%x\n",
6833 __func__, bahama_version);
6834 }
6835
6836 switch (bahama_version) {
6837 case 0x08: /* varient of bahama v1 */
6838 case 0x10:
6839 case 0x00:
6840 return VER_1_0;
6841 case 0x09: /* variant of bahama v2 */
6842 return VER_2_0;
6843 default:
6844 return VER_UNSUPPORTED;
6845 }
6846}
6847
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006848static int msm_bahama_setup_power_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006849static unsigned int msm_bahama_setup_power(void)
6850{
6851 int rc = 0;
6852 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006853
6854 if (machine_is_msm8x60_dragon())
6855 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6856
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006857 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6858
6859 if (IS_ERR(vreg_bahama)) {
6860 rc = PTR_ERR(vreg_bahama);
6861 pr_err("%s: regulator_get %s = %d\n", __func__,
6862 msm_bahama_regulator, rc);
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006863 return rc;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006864 }
6865
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006866 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6867 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006868 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6869 msm_bahama_regulator, rc);
6870 goto unget;
6871 }
6872
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006873 rc = regulator_enable(vreg_bahama);
6874 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006875 pr_err("%s: regulator_enable %s = %d\n", __func__,
6876 msm_bahama_regulator, rc);
6877 goto unget;
6878 }
6879
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006880 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6881 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006882 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006883 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006884 goto unenable;
6885 }
6886
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006887 gpio_direction_output(msm_bahama_sys_rst, 0);
6888 usleep_range(1000, 1050);
6889 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
6890 usleep_range(1000, 1050);
6891 msm_bahama_setup_power_enable = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006892 return rc;
6893
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006894unenable:
6895 regulator_disable(vreg_bahama);
6896unget:
6897 regulator_put(vreg_bahama);
6898 return rc;
6899};
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006900
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006901static unsigned int msm_bahama_shutdown_power(int value)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006902{
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006903 if (msm_bahama_setup_power_enable) {
6904 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
6905 gpio_free(msm_bahama_sys_rst);
6906 regulator_disable(vreg_bahama);
6907 regulator_put(vreg_bahama);
6908 msm_bahama_setup_power_enable = 0;
6909 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006910
6911 return 0;
6912};
6913
6914static unsigned int msm_bahama_core_config(int type)
6915{
6916 int rc = 0;
6917
6918 if (type == BAHAMA_ID) {
6919
6920 int i;
6921 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6922
6923 const struct bahama_config_register v20_init[] = {
6924 /* reg, value, mask */
6925 { 0xF4, 0x84, 0xFF }, /* AREG */
6926 { 0xF0, 0x04, 0xFF } /* DREG */
6927 };
6928
6929 if (read_bahama_ver() == VER_2_0) {
6930 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6931 u8 value = v20_init[i].value;
6932 rc = marimba_write_bit_mask(&config,
6933 v20_init[i].reg,
6934 &value,
6935 sizeof(v20_init[i].value),
6936 v20_init[i].mask);
6937 if (rc < 0) {
6938 printk(KERN_ERR
6939 "%s: reg %d write failed: %d\n",
6940 __func__, v20_init[i].reg, rc);
6941 return rc;
6942 }
6943 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6944 " mask 0x%02x\n",
6945 __func__, v20_init[i].reg,
6946 v20_init[i].value, v20_init[i].mask);
6947 }
6948 }
6949 }
6950 printk(KERN_INFO "core type: %d\n", type);
6951
6952 return rc;
6953}
6954
6955static struct regulator *fm_regulator_s3;
6956static struct msm_xo_voter *fm_clock;
6957
6958static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6959{
6960 int rc = 0;
6961 struct pm8058_gpio cfg = {
6962 .direction = PM_GPIO_DIR_IN,
6963 .pull = PM_GPIO_PULL_NO,
6964 .vin_sel = PM_GPIO_VIN_S3,
6965 .function = PM_GPIO_FUNC_NORMAL,
6966 .inv_int_pol = 0,
6967 };
6968
6969 if (!fm_regulator_s3) {
6970 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
6971 if (IS_ERR(fm_regulator_s3)) {
6972 rc = PTR_ERR(fm_regulator_s3);
6973 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
6974 __func__, rc);
6975 goto out;
6976 }
6977 }
6978
6979
6980 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
6981 if (rc < 0) {
6982 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
6983 __func__, rc);
6984 goto fm_fail_put;
6985 }
6986
6987 rc = regulator_enable(fm_regulator_s3);
6988 if (rc < 0) {
6989 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
6990 __func__, rc);
6991 goto fm_fail_put;
6992 }
6993
6994 /*Vote for XO clock*/
6995 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
6996
6997 if (IS_ERR(fm_clock)) {
6998 rc = PTR_ERR(fm_clock);
6999 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
7000 __func__, rc);
7001 goto fm_fail_switch;
7002 }
7003
7004 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
7005 if (rc < 0) {
7006 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
7007 __func__, rc);
7008 goto fm_fail_vote;
7009 }
7010
7011 /*GPIO 18 on PMIC is FM_IRQ*/
7012 rc = pm8058_gpio_config(FM_GPIO, &cfg);
7013 if (rc) {
7014 printk(KERN_ERR "%s: return val of pm8058_gpio_config: %d\n",
7015 __func__, rc);
7016 goto fm_fail_clock;
7017 }
7018 goto out;
7019
7020fm_fail_clock:
7021 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7022fm_fail_vote:
7023 msm_xo_put(fm_clock);
7024fm_fail_switch:
7025 regulator_disable(fm_regulator_s3);
7026fm_fail_put:
7027 regulator_put(fm_regulator_s3);
7028out:
7029 return rc;
7030};
7031
7032static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
7033{
7034 int rc = 0;
7035 if (fm_regulator_s3 != NULL) {
7036 rc = regulator_disable(fm_regulator_s3);
7037 if (rc < 0) {
7038 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
7039 __func__, rc);
7040 }
7041 regulator_put(fm_regulator_s3);
7042 fm_regulator_s3 = NULL;
7043 }
7044 printk(KERN_ERR "%s: Voting off for XO", __func__);
7045
7046 if (fm_clock != NULL) {
7047 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7048 if (rc < 0) {
7049 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
7050 __func__, rc);
7051 }
7052 msm_xo_put(fm_clock);
7053 }
7054 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
7055}
7056
7057/* Slave id address for FM/CDC/QMEMBIST
7058 * Values can be programmed using Marimba slave id 0
7059 * should there be a conflict with other I2C devices
7060 * */
7061#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
7062#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
7063
7064static struct marimba_fm_platform_data marimba_fm_pdata = {
7065 .fm_setup = fm_radio_setup,
7066 .fm_shutdown = fm_radio_shutdown,
7067 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
7068 .is_fm_soc_i2s_master = false,
7069 .config_i2s_gpio = NULL,
7070};
7071
7072/*
7073Just initializing the BAHAMA related slave
7074*/
7075static struct marimba_platform_data marimba_pdata = {
7076 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
7077 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
7078 .bahama_setup = msm_bahama_setup_power,
7079 .bahama_shutdown = msm_bahama_shutdown_power,
7080 .bahama_core_config = msm_bahama_core_config,
7081 .fm = &marimba_fm_pdata,
7082 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
7083};
7084
7085
7086static struct i2c_board_info msm_marimba_board_info[] = {
7087 {
7088 I2C_BOARD_INFO("marimba", 0xc),
7089 .platform_data = &marimba_pdata,
7090 }
7091};
7092#endif /* CONFIG_MAIMBA_CORE */
7093
7094#ifdef CONFIG_I2C
7095#define I2C_SURF 1
7096#define I2C_FFA (1 << 1)
7097#define I2C_RUMI (1 << 2)
7098#define I2C_SIM (1 << 3)
7099#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007100#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007101
7102struct i2c_registry {
7103 u8 machs;
7104 int bus;
7105 struct i2c_board_info *info;
7106 int len;
7107};
7108
7109static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007110#ifdef CONFIG_PMIC8901
7111 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007112 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007113 MSM_SSBI2_I2C_BUS_ID,
7114 pm8901_boardinfo,
7115 ARRAY_SIZE(pm8901_boardinfo),
7116 },
7117#endif
7118#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7119 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007120 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007121 MSM_GSBI8_QUP_I2C_BUS_ID,
7122 core_expander_i2c_info,
7123 ARRAY_SIZE(core_expander_i2c_info),
7124 },
7125 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007126 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007127 MSM_GSBI8_QUP_I2C_BUS_ID,
7128 docking_expander_i2c_info,
7129 ARRAY_SIZE(docking_expander_i2c_info),
7130 },
7131 {
7132 I2C_SURF,
7133 MSM_GSBI8_QUP_I2C_BUS_ID,
7134 surf_expanders_i2c_info,
7135 ARRAY_SIZE(surf_expanders_i2c_info),
7136 },
7137 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007138 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007139 MSM_GSBI3_QUP_I2C_BUS_ID,
7140 fha_expanders_i2c_info,
7141 ARRAY_SIZE(fha_expanders_i2c_info),
7142 },
7143 {
7144 I2C_FLUID,
7145 MSM_GSBI3_QUP_I2C_BUS_ID,
7146 fluid_expanders_i2c_info,
7147 ARRAY_SIZE(fluid_expanders_i2c_info),
7148 },
7149 {
7150 I2C_FLUID,
7151 MSM_GSBI8_QUP_I2C_BUS_ID,
7152 fluid_core_expander_i2c_info,
7153 ARRAY_SIZE(fluid_core_expander_i2c_info),
7154 },
7155#endif
7156#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
7157 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
7158 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007159 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007160 MSM_GSBI3_QUP_I2C_BUS_ID,
7161 msm_i2c_gsbi3_tdisc_info,
7162 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7163 },
7164#endif
7165 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007166 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007167 MSM_GSBI3_QUP_I2C_BUS_ID,
7168 cy8ctmg200_board_info,
7169 ARRAY_SIZE(cy8ctmg200_board_info),
7170 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007171 {
7172 I2C_DRAGON,
7173 MSM_GSBI3_QUP_I2C_BUS_ID,
7174 cy8ctma340_dragon_board_info,
7175 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7176 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007177#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7178 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7179 {
7180 I2C_FLUID,
7181 MSM_GSBI3_QUP_I2C_BUS_ID,
7182 cyttsp_fluid_info,
7183 ARRAY_SIZE(cyttsp_fluid_info),
7184 },
7185 {
7186 I2C_FFA | I2C_SURF,
7187 MSM_GSBI3_QUP_I2C_BUS_ID,
7188 cyttsp_ffa_info,
7189 ARRAY_SIZE(cyttsp_ffa_info),
7190 },
7191#endif
7192#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007193 {
7194 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007195 MSM_GSBI4_QUP_I2C_BUS_ID,
7196 msm_camera_boardinfo,
7197 ARRAY_SIZE(msm_camera_boardinfo),
7198 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007199 {
7200 I2C_DRAGON,
7201 MSM_GSBI4_QUP_I2C_BUS_ID,
7202 msm_camera_dragon_boardinfo,
7203 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7204 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007205#endif
7206 {
7207 I2C_SURF | I2C_FFA | I2C_FLUID,
7208 MSM_GSBI7_QUP_I2C_BUS_ID,
7209 msm_i2c_gsbi7_timpani_info,
7210 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7211 },
7212#if defined(CONFIG_MARIMBA_CORE)
7213 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007214 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007215 MSM_GSBI7_QUP_I2C_BUS_ID,
7216 msm_marimba_board_info,
7217 ARRAY_SIZE(msm_marimba_board_info),
7218 },
7219#endif /* CONFIG_MARIMBA_CORE */
7220#ifdef CONFIG_ISL9519_CHARGER
7221 {
7222 I2C_SURF | I2C_FFA,
7223 MSM_GSBI8_QUP_I2C_BUS_ID,
7224 isl_charger_i2c_info,
7225 ARRAY_SIZE(isl_charger_i2c_info),
7226 },
7227#endif
7228#if defined(CONFIG_HAPTIC_ISA1200) || \
7229 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7230 {
7231 I2C_FLUID,
7232 MSM_GSBI8_QUP_I2C_BUS_ID,
7233 msm_isa1200_board_info,
7234 ARRAY_SIZE(msm_isa1200_board_info),
7235 },
7236#endif
7237#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7238 {
7239 I2C_FLUID,
7240 MSM_GSBI8_QUP_I2C_BUS_ID,
7241 smb137b_charger_i2c_info,
7242 ARRAY_SIZE(smb137b_charger_i2c_info),
7243 },
7244#endif
7245#if defined(CONFIG_BATTERY_BQ27520) || \
7246 defined(CONFIG_BATTERY_BQ27520_MODULE)
7247 {
7248 I2C_FLUID,
7249 MSM_GSBI8_QUP_I2C_BUS_ID,
7250 msm_bq27520_board_info,
7251 ARRAY_SIZE(msm_bq27520_board_info),
7252 },
7253#endif
Lei Zhou338cab82011-08-19 13:38:17 -04007254#if defined(CONFIG_SND_SOC_WM8903) || defined(CONFIG_SND_SOC_WM8903_MODULE)
7255 {
7256 I2C_DRAGON,
7257 MSM_GSBI8_QUP_I2C_BUS_ID,
7258 wm8903_codec_i2c_info,
7259 ARRAY_SIZE(wm8903_codec_i2c_info),
7260 },
7261#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007262};
7263#endif /* CONFIG_I2C */
7264
7265static void fixup_i2c_configs(void)
7266{
7267#ifdef CONFIG_I2C
7268#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7269 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7270 sx150x_data[SX150X_CORE].irq_summary =
7271 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007272 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7273 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007274 sx150x_data[SX150X_CORE].irq_summary =
7275 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7276 else if (machine_is_msm8x60_fluid())
7277 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7278 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7279#endif
7280 /*
7281 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7282 * implies that the regulator connected to MPP0 is enabled when
7283 * MPP0 is low.
7284 */
7285 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7286 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7287 else
7288 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7289#endif
7290}
7291
7292static void register_i2c_devices(void)
7293{
7294#ifdef CONFIG_I2C
7295 u8 mach_mask = 0;
7296 int i;
7297
7298 /* Build the matching 'supported_machs' bitmask */
7299 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7300 mach_mask = I2C_SURF;
7301 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7302 mach_mask = I2C_FFA;
7303 else if (machine_is_msm8x60_rumi3())
7304 mach_mask = I2C_RUMI;
7305 else if (machine_is_msm8x60_sim())
7306 mach_mask = I2C_SIM;
7307 else if (machine_is_msm8x60_fluid())
7308 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007309 else if (machine_is_msm8x60_dragon())
7310 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007311 else
7312 pr_err("unmatched machine ID in register_i2c_devices\n");
7313
7314 /* Run the array and install devices as appropriate */
7315 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7316 if (msm8x60_i2c_devices[i].machs & mach_mask)
7317 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7318 msm8x60_i2c_devices[i].info,
7319 msm8x60_i2c_devices[i].len);
7320 }
7321#endif
7322}
7323
7324static void __init msm8x60_init_uart12dm(void)
7325{
7326#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7327 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7328 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7329
7330 if (!fpga_mem)
7331 pr_err("%s(): Error getting memory\n", __func__);
7332
7333 /* Advanced mode */
7334 writew(0xFFFF, fpga_mem + 0x15C);
7335 /* FPGA_UART_SEL */
7336 writew(0, fpga_mem + 0x172);
7337 /* FPGA_GPIO_CONFIG_117 */
7338 writew(1, fpga_mem + 0xEA);
7339 /* FPGA_GPIO_CONFIG_118 */
7340 writew(1, fpga_mem + 0xEC);
7341 mb();
7342 iounmap(fpga_mem);
7343#endif
7344}
7345
7346#define MSM_GSBI9_PHYS 0x19900000
7347#define GSBI_DUAL_MODE_CODE 0x60
7348
7349static void __init msm8x60_init_buses(void)
7350{
7351#ifdef CONFIG_I2C_QUP
7352 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7353 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7354 writel_relaxed(0x6 << 4, gsbi_mem);
7355 /* Ensure protocol code is written before proceeding further */
7356 mb();
7357 iounmap(gsbi_mem);
7358
7359 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7360 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7361 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7362 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7363
7364#ifdef CONFIG_MSM_GSBI9_UART
7365 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7366 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7367 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7368 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7369 iounmap(gsbi_mem);
7370 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7371 }
7372#endif
7373 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7374 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7375#endif
7376#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7377 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7378#endif
7379#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007380 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7381 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7382#endif
7383
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05307384#ifdef CONFIG_MSM_SSBI
7385 msm_device_ssbi_pmic1.dev.platform_data =
7386 &msm8x60_ssbi_pm8058_pdata;
7387#endif
7388
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007389 if (machine_is_msm8x60_fluid()) {
7390#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7391 (defined(CONFIG_SMB137B_CHARGER) || \
7392 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7393 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7394#endif
7395#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7396 msm_gsbi10_qup_spi_device.dev.platform_data =
7397 &msm_gsbi10_qup_spi_pdata;
7398#endif
7399 }
7400
7401#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7402 /*
7403 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7404 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7405 * and ID notifications are available only on V2 surf and FFA
7406 * with a hardware workaround.
7407 */
7408 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7409 (machine_is_msm8x60_surf() ||
7410 (machine_is_msm8x60_ffa() &&
7411 pmic_id_notif_supported)))
7412 msm_otg_pdata.phy_can_powercollapse = 1;
7413 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7414#endif
7415
7416#ifdef CONFIG_USB_GADGET_MSM_72K
7417 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7418#endif
7419
7420#ifdef CONFIG_SERIAL_MSM_HS
7421 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7422 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7423#endif
7424#ifdef CONFIG_MSM_GSBI9_UART
7425 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7426 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7427 if (IS_ERR(msm_device_uart_gsbi9))
7428 pr_err("%s(): Failed to create uart gsbi9 device\n",
7429 __func__);
7430 }
7431#endif
7432
7433#ifdef CONFIG_MSM_BUS_SCALING
7434
7435 /* RPM calls are only enabled on V2 */
7436 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7437 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7438 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7439 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7440 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7441 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7442 }
7443
7444 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7445 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7446 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7447 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7448 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7449#endif
7450}
7451
7452static void __init msm8x60_map_io(void)
7453{
7454 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7455 msm_map_msm8x60_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007456
7457 if (socinfo_init() < 0)
7458 pr_err("socinfo_init() failed!\n");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007459}
7460
7461/*
7462 * Most segments of the EBI2 bus are disabled by default.
7463 */
7464static void __init msm8x60_init_ebi2(void)
7465{
7466 uint32_t ebi2_cfg;
7467 void *ebi2_cfg_ptr;
Terence Hampsonb36a38c2011-09-19 19:10:40 -04007468 struct clk *mem_clk = clk_get_sys("msm_ebi2", "mem_clk");
7469
7470 if (IS_ERR(mem_clk)) {
7471 pr_err("%s: clk_get_sys(%s,%s), failed", __func__,
7472 "msm_ebi2", "mem_clk");
7473 return;
7474 }
7475 clk_enable(mem_clk);
7476 clk_put(mem_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007477
7478 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7479 if (ebi2_cfg_ptr != 0) {
7480 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7481
7482 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007483 machine_is_msm8x60_fluid() ||
7484 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007485 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7486 else if (machine_is_msm8x60_sim())
7487 ebi2_cfg |= (1 << 4); /* CS2 */
7488 else if (machine_is_msm8x60_rumi3())
7489 ebi2_cfg |= (1 << 5); /* CS3 */
7490
7491 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7492 iounmap(ebi2_cfg_ptr);
7493 }
7494
7495 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007496 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007497 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7498 if (ebi2_cfg_ptr != 0) {
7499 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7500 writel_relaxed(0UL, ebi2_cfg_ptr);
7501
7502 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7503 * LAN9221 Ethernet controller reads and writes.
7504 * The lowest 4 bits are the read delay, the next
7505 * 4 are the write delay. */
7506 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7507#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7508 /*
7509 * RECOVERY=5, HOLD_WR=1
7510 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7511 * WAIT_WR=1, WAIT_RD=2
7512 */
7513 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7514 /*
7515 * HOLD_RD=1
7516 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7517 */
7518 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7519#else
7520 /* EBI2 CS3 muxed address/data,
7521 * two cyc addr enable */
7522 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7523
7524#endif
7525 iounmap(ebi2_cfg_ptr);
7526 }
7527 }
7528}
7529
7530static void __init msm8x60_configure_smc91x(void)
7531{
7532 if (machine_is_msm8x60_sim()) {
7533
7534 smc91x_resources[0].start = 0x1b800300;
7535 smc91x_resources[0].end = 0x1b8003ff;
7536
7537 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7538 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7539
7540 } else if (machine_is_msm8x60_rumi3()) {
7541
7542 smc91x_resources[0].start = 0x1d000300;
7543 smc91x_resources[0].end = 0x1d0003ff;
7544
7545 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7546 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7547 }
7548}
7549
7550static void __init msm8x60_init_tlmm(void)
7551{
7552 if (machine_is_msm8x60_rumi3())
7553 msm_gpio_install_direct_irq(0, 0, 1);
7554}
7555
7556#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7557 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7558 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7559 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7560 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7561
7562/* 8x60 is having 5 SDCC controllers */
7563#define MAX_SDCC_CONTROLLER 5
7564
7565struct msm_sdcc_gpio {
7566 /* maximum 10 GPIOs per SDCC controller */
7567 s16 no;
7568 /* name of this GPIO */
7569 const char *name;
7570 bool always_on;
7571 bool is_enabled;
7572};
7573
7574#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7575static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7576 {159, "sdc1_dat_0"},
7577 {160, "sdc1_dat_1"},
7578 {161, "sdc1_dat_2"},
7579 {162, "sdc1_dat_3"},
7580#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7581 {163, "sdc1_dat_4"},
7582 {164, "sdc1_dat_5"},
7583 {165, "sdc1_dat_6"},
7584 {166, "sdc1_dat_7"},
7585#endif
7586 {167, "sdc1_clk"},
7587 {168, "sdc1_cmd"}
7588};
7589#endif
7590
7591#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7592static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7593 {143, "sdc2_dat_0"},
7594 {144, "sdc2_dat_1", 1},
7595 {145, "sdc2_dat_2"},
7596 {146, "sdc2_dat_3"},
7597#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7598 {147, "sdc2_dat_4"},
7599 {148, "sdc2_dat_5"},
7600 {149, "sdc2_dat_6"},
7601 {150, "sdc2_dat_7"},
7602#endif
7603 {151, "sdc2_cmd"},
7604 {152, "sdc2_clk", 1}
7605};
7606#endif
7607
7608#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7609static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7610 {95, "sdc5_cmd"},
7611 {96, "sdc5_dat_3"},
7612 {97, "sdc5_clk", 1},
7613 {98, "sdc5_dat_2"},
7614 {99, "sdc5_dat_1", 1},
7615 {100, "sdc5_dat_0"}
7616};
7617#endif
7618
7619struct msm_sdcc_pad_pull_cfg {
7620 enum msm_tlmm_pull_tgt pull;
7621 u32 pull_val;
7622};
7623
7624struct msm_sdcc_pad_drv_cfg {
7625 enum msm_tlmm_hdrive_tgt drv;
7626 u32 drv_val;
7627};
7628
7629#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7630static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7631 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7632 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7633 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7634};
7635
7636static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7637 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7638 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7639};
7640
7641static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7642 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7643 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7644 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7645};
7646
7647static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7648 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7649 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7650};
7651#endif
7652
7653#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7654static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7655 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7656 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7657 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7658};
7659
7660static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7661 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7662 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7663};
7664
7665static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7666 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7667 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7668 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7669};
7670
7671static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7672 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7673 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7674};
7675#endif
7676
7677struct msm_sdcc_pin_cfg {
7678 /*
7679 * = 1 if controller pins are using gpios
7680 * = 0 if controller has dedicated MSM pins
7681 */
7682 u8 is_gpio;
7683 u8 cfg_sts;
7684 u8 gpio_data_size;
7685 struct msm_sdcc_gpio *gpio_data;
7686 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7687 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7688 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7689 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7690 u8 pad_drv_data_size;
7691 u8 pad_pull_data_size;
7692 u8 sdio_lpm_gpio_cfg;
7693};
7694
7695
7696static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7697#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7698 [0] = {
7699 .is_gpio = 1,
7700 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7701 .gpio_data = sdc1_gpio_cfg
7702 },
7703#endif
7704#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7705 [1] = {
7706 .is_gpio = 1,
7707 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7708 .gpio_data = sdc2_gpio_cfg
7709 },
7710#endif
7711#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7712 [2] = {
7713 .is_gpio = 0,
7714 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7715 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7716 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7717 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7718 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7719 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7720 },
7721#endif
7722#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7723 [3] = {
7724 .is_gpio = 0,
7725 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7726 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7727 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7728 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7729 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7730 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7731 },
7732#endif
7733#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7734 [4] = {
7735 .is_gpio = 1,
7736 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7737 .gpio_data = sdc5_gpio_cfg
7738 }
7739#endif
7740};
7741
7742static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7743{
7744 int rc = 0;
7745 struct msm_sdcc_pin_cfg *curr;
7746 int n;
7747
7748 curr = &sdcc_pin_cfg_data[dev_id - 1];
7749 if (!curr->gpio_data)
7750 goto out;
7751
7752 for (n = 0; n < curr->gpio_data_size; n++) {
7753 if (enable) {
7754
7755 if (curr->gpio_data[n].always_on &&
7756 curr->gpio_data[n].is_enabled)
7757 continue;
7758 pr_debug("%s: enable: %s\n", __func__,
7759 curr->gpio_data[n].name);
7760 rc = gpio_request(curr->gpio_data[n].no,
7761 curr->gpio_data[n].name);
7762 if (rc) {
7763 pr_err("%s: gpio_request(%d, %s)"
7764 "failed", __func__,
7765 curr->gpio_data[n].no,
7766 curr->gpio_data[n].name);
7767 goto free_gpios;
7768 }
7769 /* set direction as output for all GPIOs */
7770 rc = gpio_direction_output(
7771 curr->gpio_data[n].no, 1);
7772 if (rc) {
7773 pr_err("%s: gpio_direction_output"
7774 "(%d, 1) failed\n", __func__,
7775 curr->gpio_data[n].no);
7776 goto free_gpios;
7777 }
7778 curr->gpio_data[n].is_enabled = 1;
7779 } else {
7780 /*
7781 * now free this GPIO which will put GPIO
7782 * in low power mode and will also put GPIO
7783 * in input mode
7784 */
7785 if (curr->gpio_data[n].always_on)
7786 continue;
7787 pr_debug("%s: disable: %s\n", __func__,
7788 curr->gpio_data[n].name);
7789 gpio_free(curr->gpio_data[n].no);
7790 curr->gpio_data[n].is_enabled = 0;
7791 }
7792 }
7793 curr->cfg_sts = enable;
7794 goto out;
7795
7796free_gpios:
7797 for (; n >= 0; n--)
7798 gpio_free(curr->gpio_data[n].no);
7799out:
7800 return rc;
7801}
7802
7803static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7804{
7805 int rc = 0;
7806 struct msm_sdcc_pin_cfg *curr;
7807 int n;
7808
7809 curr = &sdcc_pin_cfg_data[dev_id - 1];
7810 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7811 goto out;
7812
7813 if (enable) {
7814 /*
7815 * set up the normal driver strength and
7816 * pull config for pads
7817 */
7818 for (n = 0; n < curr->pad_drv_data_size; n++) {
7819 if (curr->sdio_lpm_gpio_cfg) {
7820 if (curr->pad_drv_on_data[n].drv ==
7821 TLMM_HDRV_SDC4_DATA)
7822 continue;
7823 }
7824 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7825 curr->pad_drv_on_data[n].drv_val);
7826 }
7827 for (n = 0; n < curr->pad_pull_data_size; n++) {
7828 if (curr->sdio_lpm_gpio_cfg) {
7829 if (curr->pad_pull_on_data[n].pull ==
7830 TLMM_PULL_SDC4_DATA)
7831 continue;
7832 }
7833 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7834 curr->pad_pull_on_data[n].pull_val);
7835 }
7836 } else {
7837 /* set the low power config for pads */
7838 for (n = 0; n < curr->pad_drv_data_size; n++) {
7839 if (curr->sdio_lpm_gpio_cfg) {
7840 if (curr->pad_drv_off_data[n].drv ==
7841 TLMM_HDRV_SDC4_DATA)
7842 continue;
7843 }
7844 msm_tlmm_set_hdrive(
7845 curr->pad_drv_off_data[n].drv,
7846 curr->pad_drv_off_data[n].drv_val);
7847 }
7848 for (n = 0; n < curr->pad_pull_data_size; n++) {
7849 if (curr->sdio_lpm_gpio_cfg) {
7850 if (curr->pad_pull_off_data[n].pull ==
7851 TLMM_PULL_SDC4_DATA)
7852 continue;
7853 }
7854 msm_tlmm_set_pull(
7855 curr->pad_pull_off_data[n].pull,
7856 curr->pad_pull_off_data[n].pull_val);
7857 }
7858 }
7859 curr->cfg_sts = enable;
7860out:
7861 return rc;
7862}
7863
7864struct sdcc_reg {
7865 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7866 const char *reg_name;
7867 /*
7868 * is set voltage supported for this regulator?
7869 * 0 = not supported, 1 = supported
7870 */
7871 unsigned char set_voltage_sup;
7872 /* voltage level to be set */
7873 unsigned int level;
7874 /* VDD/VCC/VCCQ voltage regulator handle */
7875 struct regulator *reg;
7876 /* is this regulator enabled? */
7877 bool enabled;
7878 /* is this regulator needs to be always on? */
7879 bool always_on;
7880 /* is operating power mode setting required for this regulator? */
7881 bool op_pwr_mode_sup;
7882 /* Load values for low power and high power mode */
7883 unsigned int lpm_uA;
7884 unsigned int hpm_uA;
7885};
7886/* all SDCC controllers requires VDD/VCC voltage */
7887static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7888/* only SDCC1 requires VCCQ voltage */
7889static struct sdcc_reg sdcc_vccq_reg_data[1];
7890/* all SDCC controllers may require voting for VDD PAD voltage */
7891static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7892
7893struct sdcc_reg_data {
7894 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7895 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7896 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7897 unsigned char sts; /* regulator enable/disable status */
7898};
7899/* msm8x60 have 5 SDCC controllers */
7900static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7901
7902static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7903{
7904 int rc = 0;
7905
7906 /* Get the regulator handle */
7907 vreg->reg = regulator_get(NULL, vreg->reg_name);
7908 if (IS_ERR(vreg->reg)) {
7909 rc = PTR_ERR(vreg->reg);
7910 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7911 __func__, vreg->reg_name, rc);
7912 goto out;
7913 }
7914
7915 /* Set the voltage level if required */
7916 if (vreg->set_voltage_sup) {
7917 rc = regulator_set_voltage(vreg->reg, vreg->level,
7918 vreg->level);
7919 if (rc) {
7920 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7921 __func__, vreg->reg_name, rc);
7922 goto vreg_put;
7923 }
7924 }
7925 goto out;
7926
7927vreg_put:
7928 regulator_put(vreg->reg);
7929out:
7930 return rc;
7931}
7932
7933static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7934{
7935 regulator_put(vreg->reg);
7936}
7937
7938/* this init function should be called only once for each SDCC */
7939static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7940{
7941 int rc = 0;
7942 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7943 struct sdcc_reg_data *curr;
7944
7945 curr = &sdcc_vreg_data[dev_id - 1];
7946 curr_vdd_reg = curr->vdd_data;
7947 curr_vccq_reg = curr->vccq_data;
7948 curr_vddp_reg = curr->vddp_data;
7949
7950 if (init) {
7951 /*
7952 * get the regulator handle from voltage regulator framework
7953 * and then try to set the voltage level for the regulator
7954 */
7955 if (curr_vdd_reg) {
7956 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7957 if (rc)
7958 goto out;
7959 }
7960 if (curr_vccq_reg) {
7961 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
7962 if (rc)
7963 goto vdd_reg_deinit;
7964 }
7965 if (curr_vddp_reg) {
7966 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
7967 if (rc)
7968 goto vccq_reg_deinit;
7969 }
7970 goto out;
7971 } else
7972 /* deregister with all regulators from regulator framework */
7973 goto vddp_reg_deinit;
7974
7975vddp_reg_deinit:
7976 if (curr_vddp_reg)
7977 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
7978vccq_reg_deinit:
7979 if (curr_vccq_reg)
7980 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
7981vdd_reg_deinit:
7982 if (curr_vdd_reg)
7983 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
7984out:
7985 return rc;
7986}
7987
7988static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
7989{
7990 int rc;
7991
7992 if (!vreg->enabled) {
7993 rc = regulator_enable(vreg->reg);
7994 if (rc) {
7995 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
7996 __func__, vreg->reg_name, rc);
7997 goto out;
7998 }
7999 vreg->enabled = 1;
8000 }
8001
8002 /* Put always_on regulator in HPM (high power mode) */
8003 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8004 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
8005 if (rc < 0) {
8006 pr_err("%s: reg=%s: HPM setting failed"
8007 " hpm_uA=%d, rc=%d\n",
8008 __func__, vreg->reg_name,
8009 vreg->hpm_uA, rc);
8010 goto vreg_disable;
8011 }
8012 rc = 0;
8013 }
8014 goto out;
8015
8016vreg_disable:
8017 regulator_disable(vreg->reg);
8018 vreg->enabled = 0;
8019out:
8020 return rc;
8021}
8022
8023static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
8024{
8025 int rc;
8026
8027 /* Never disable always_on regulator */
8028 if (!vreg->always_on) {
8029 rc = regulator_disable(vreg->reg);
8030 if (rc) {
8031 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
8032 __func__, vreg->reg_name, rc);
8033 goto out;
8034 }
8035 vreg->enabled = 0;
8036 }
8037
8038 /* Put always_on regulator in LPM (low power mode) */
8039 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8040 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
8041 if (rc < 0) {
8042 pr_err("%s: reg=%s: LPM setting failed"
8043 " lpm_uA=%d, rc=%d\n",
8044 __func__,
8045 vreg->reg_name,
8046 vreg->lpm_uA, rc);
8047 goto out;
8048 }
8049 rc = 0;
8050 }
8051
8052out:
8053 return rc;
8054}
8055
8056static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
8057{
8058 int rc = 0;
8059 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
8060 struct sdcc_reg_data *curr;
8061
8062 curr = &sdcc_vreg_data[dev_id - 1];
8063 curr_vdd_reg = curr->vdd_data;
8064 curr_vccq_reg = curr->vccq_data;
8065 curr_vddp_reg = curr->vddp_data;
8066
8067 /* check if regulators are initialized or not? */
8068 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
8069 (curr_vccq_reg && !curr_vccq_reg->reg) ||
8070 (curr_vddp_reg && !curr_vddp_reg->reg)) {
8071 /* initialize voltage regulators required for this SDCC */
8072 rc = msm_sdcc_vreg_init(dev_id, 1);
8073 if (rc) {
8074 pr_err("%s: regulator init failed = %d\n",
8075 __func__, rc);
8076 goto out;
8077 }
8078 }
8079
8080 if (curr->sts == enable)
8081 goto out;
8082
8083 if (curr_vdd_reg) {
8084 if (enable)
8085 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
8086 else
8087 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
8088 if (rc)
8089 goto out;
8090 }
8091
8092 if (curr_vccq_reg) {
8093 if (enable)
8094 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
8095 else
8096 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
8097 if (rc)
8098 goto out;
8099 }
8100
8101 if (curr_vddp_reg) {
8102 if (enable)
8103 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
8104 else
8105 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
8106 if (rc)
8107 goto out;
8108 }
8109 curr->sts = enable;
8110
8111out:
8112 return rc;
8113}
8114
8115static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
8116{
8117 u32 rc_pin_cfg = 0;
8118 u32 rc_vreg_cfg = 0;
8119 u32 rc = 0;
8120 struct platform_device *pdev;
8121 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8122
8123 pdev = container_of(dv, struct platform_device, dev);
8124
8125 /* setup gpio/pad */
8126 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8127 if (curr_pin_cfg->cfg_sts == !!vdd)
8128 goto setup_vreg;
8129
8130 if (curr_pin_cfg->is_gpio)
8131 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
8132 else
8133 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
8134
8135setup_vreg:
8136 /* setup voltage regulators */
8137 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
8138
8139 if (rc_pin_cfg || rc_vreg_cfg)
8140 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
8141
8142 return rc;
8143}
8144
8145static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
8146{
8147 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8148 struct platform_device *pdev;
8149
8150 pdev = container_of(dv, struct platform_device, dev);
8151 /* setup gpio/pad */
8152 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8153
8154 if (curr_pin_cfg->cfg_sts == active)
8155 return;
8156
8157 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
8158 if (curr_pin_cfg->is_gpio)
8159 msm_sdcc_setup_gpio(pdev->id, active);
8160 else
8161 msm_sdcc_setup_pad(pdev->id, active);
8162 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8163}
8164
8165static int msm_sdc3_get_wpswitch(struct device *dev)
8166{
8167 struct platform_device *pdev;
8168 int status;
8169 pdev = container_of(dev, struct platform_device, dev);
8170
8171 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8172 if (status) {
8173 pr_err("%s:Failed to request GPIO %d\n",
8174 __func__, GPIO_SDC_WP);
8175 } else {
8176 status = gpio_direction_input(GPIO_SDC_WP);
8177 if (!status) {
8178 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8179 pr_info("%s: WP Status for Slot %d = %d\n",
8180 __func__, pdev->id, status);
8181 }
8182 gpio_free(GPIO_SDC_WP);
8183 }
8184 return status;
8185}
8186
8187#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8188int sdc5_register_status_notify(void (*callback)(int, void *),
8189 void *dev_id)
8190{
8191 sdc5_status_notify_cb = callback;
8192 sdc5_status_notify_cb_devid = dev_id;
8193 return 0;
8194}
8195#endif
8196
8197#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8198int sdc2_register_status_notify(void (*callback)(int, void *),
8199 void *dev_id)
8200{
8201 sdc2_status_notify_cb = callback;
8202 sdc2_status_notify_cb_devid = dev_id;
8203 return 0;
8204}
8205#endif
8206
8207/* Interrupt handler for SDC2 and SDC5 detection
8208 * This function uses dual-edge interrputs settings in order
8209 * to get SDIO detection when the GPIO is rising and SDIO removal
8210 * when the GPIO is falling */
8211static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8212{
8213 int status;
8214
8215 if (!machine_is_msm8x60_fusion() &&
8216 !machine_is_msm8x60_fusn_ffa())
8217 return IRQ_NONE;
8218
8219 status = gpio_get_value(MDM2AP_SYNC);
8220 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8221 __func__, status);
8222
8223#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8224 if (sdc2_status_notify_cb) {
8225 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8226 sdc2_status_notify_cb(status,
8227 sdc2_status_notify_cb_devid);
8228 }
8229#endif
8230
8231#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8232 if (sdc5_status_notify_cb) {
8233 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8234 sdc5_status_notify_cb(status,
8235 sdc5_status_notify_cb_devid);
8236 }
8237#endif
8238 return IRQ_HANDLED;
8239}
8240
8241static int msm8x60_multi_sdio_init(void)
8242{
8243 int ret, irq_num;
8244
8245 if (!machine_is_msm8x60_fusion() &&
8246 !machine_is_msm8x60_fusn_ffa())
8247 return 0;
8248
8249 ret = msm_gpiomux_get(MDM2AP_SYNC);
8250 if (ret) {
8251 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8252 __func__, MDM2AP_SYNC, ret);
8253 return ret;
8254 }
8255
8256 irq_num = gpio_to_irq(MDM2AP_SYNC);
8257
8258 ret = request_irq(irq_num,
8259 msm8x60_multi_sdio_slot_status_irq,
8260 IRQ_TYPE_EDGE_BOTH,
8261 "sdio_multidetection", NULL);
8262
8263 if (ret) {
8264 pr_err("%s:Failed to request irq, ret=%d\n",
8265 __func__, ret);
8266 return ret;
8267 }
8268
8269 return ret;
8270}
8271
8272#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8273#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8274static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8275{
8276 int status;
8277
8278 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8279 , "SD_HW_Detect");
8280 if (status) {
8281 pr_err("%s:Failed to request GPIO %d\n", __func__,
8282 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8283 } else {
8284 status = gpio_direction_input(
8285 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8286 if (!status)
8287 status = !(gpio_get_value_cansleep(
8288 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8289 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8290 }
8291 return (unsigned int) status;
8292}
8293#endif
8294#endif
8295
8296#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8297static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8298{
8299 struct platform_device *pdev;
8300 enum msm_mpm_pin pin;
8301 int ret = 0;
8302
8303 pdev = container_of(dev, struct platform_device, dev);
8304
8305 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8306 if (pdev->id == 4)
8307 pin = MSM_MPM_PIN_SDC4_DAT1;
8308 else
8309 return -EINVAL;
8310
8311 switch (mode) {
8312 case SDC_DAT1_DISABLE:
8313 ret = msm_mpm_enable_pin(pin, 0);
8314 break;
8315 case SDC_DAT1_ENABLE:
8316 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8317 ret = msm_mpm_enable_pin(pin, 1);
8318 break;
8319 case SDC_DAT1_ENWAKE:
8320 ret = msm_mpm_set_pin_wake(pin, 1);
8321 break;
8322 case SDC_DAT1_DISWAKE:
8323 ret = msm_mpm_set_pin_wake(pin, 0);
8324 break;
8325 default:
8326 ret = -EINVAL;
8327 break;
8328 }
8329 return ret;
8330}
8331#endif
8332#endif
8333
8334#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8335static struct mmc_platform_data msm8x60_sdc1_data = {
8336 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8337 .translate_vdd = msm_sdcc_setup_power,
8338#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8339 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8340#else
8341 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8342#endif
8343 .msmsdcc_fmin = 400000,
8344 .msmsdcc_fmid = 24000000,
8345 .msmsdcc_fmax = 48000000,
8346 .nonremovable = 1,
8347 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008348};
8349#endif
8350
8351#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8352static struct mmc_platform_data msm8x60_sdc2_data = {
8353 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8354 .translate_vdd = msm_sdcc_setup_power,
8355 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8356 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8357 .msmsdcc_fmin = 400000,
8358 .msmsdcc_fmid = 24000000,
8359 .msmsdcc_fmax = 48000000,
8360 .nonremovable = 0,
8361 .pclk_src_dfab = 1,
8362 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008363#ifdef CONFIG_MSM_SDIO_AL
8364 .is_sdio_al_client = 1,
8365#endif
8366};
8367#endif
8368
8369#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8370static struct mmc_platform_data msm8x60_sdc3_data = {
8371 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8372 .translate_vdd = msm_sdcc_setup_power,
8373 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8374 .wpswitch = msm_sdc3_get_wpswitch,
8375#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8376 .status = msm8x60_sdcc_slot_status,
8377 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8378 PMIC_GPIO_SDC3_DET - 1),
8379 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8380#endif
8381 .msmsdcc_fmin = 400000,
8382 .msmsdcc_fmid = 24000000,
8383 .msmsdcc_fmax = 48000000,
8384 .nonremovable = 0,
8385 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008386};
8387#endif
8388
8389#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8390static struct mmc_platform_data msm8x60_sdc4_data = {
8391 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8392 .translate_vdd = msm_sdcc_setup_power,
8393 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8394 .msmsdcc_fmin = 400000,
8395 .msmsdcc_fmid = 24000000,
8396 .msmsdcc_fmax = 48000000,
8397 .nonremovable = 0,
8398 .pclk_src_dfab = 1,
8399 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008400};
8401#endif
8402
8403#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8404static struct mmc_platform_data msm8x60_sdc5_data = {
8405 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8406 .translate_vdd = msm_sdcc_setup_power,
8407 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8408 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8409 .msmsdcc_fmin = 400000,
8410 .msmsdcc_fmid = 24000000,
8411 .msmsdcc_fmax = 48000000,
8412 .nonremovable = 0,
8413 .pclk_src_dfab = 1,
8414 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008415#ifdef CONFIG_MSM_SDIO_AL
8416 .is_sdio_al_client = 1,
8417#endif
8418};
8419#endif
8420
8421static void __init msm8x60_init_mmc(void)
8422{
8423#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8424 /* SDCC1 : eMMC card connected */
8425 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8426 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8427 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8428 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308429 sdcc_vreg_data[0].vdd_data->always_on = 1;
8430 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8431 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8432 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008433
8434 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8435 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8436 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8437 sdcc_vreg_data[0].vccq_data->always_on = 1;
8438
8439 msm_add_sdcc(1, &msm8x60_sdc1_data);
8440#endif
8441#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8442 /*
8443 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8444 * and no card is connected on 8660 SURF/FFA/FLUID.
8445 */
8446 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8447 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8448 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8449 sdcc_vreg_data[1].vdd_data->level = 1800000;
8450
8451 sdcc_vreg_data[1].vccq_data = NULL;
8452
8453 if (machine_is_msm8x60_fusion())
8454 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8455 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8456#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8457 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8458 msm_sdcc_setup_gpio(2, 1);
8459#endif
8460 msm_add_sdcc(2, &msm8x60_sdc2_data);
8461 }
8462#endif
8463#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8464 /* SDCC3 : External card slot connected */
8465 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8466 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8467 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8468 sdcc_vreg_data[2].vdd_data->level = 2850000;
8469 sdcc_vreg_data[2].vdd_data->always_on = 1;
8470 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8471 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8472 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8473
8474 sdcc_vreg_data[2].vccq_data = NULL;
8475
8476 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8477 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8478 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8479 sdcc_vreg_data[2].vddp_data->level = 2850000;
8480 sdcc_vreg_data[2].vddp_data->always_on = 1;
8481 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8482 /* Sleep current required is ~300 uA. But min. RPM
8483 * vote can be in terms of mA (min. 1 mA).
8484 * So let's vote for 2 mA during sleep.
8485 */
8486 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8487 /* Max. Active current required is 16 mA */
8488 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8489
8490 if (machine_is_msm8x60_fluid())
8491 msm8x60_sdc3_data.wpswitch = NULL;
8492 msm_add_sdcc(3, &msm8x60_sdc3_data);
8493#endif
8494#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8495 /* SDCC4 : WLAN WCN1314 chip is connected */
8496 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8497 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8498 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8499 sdcc_vreg_data[3].vdd_data->level = 1800000;
8500
8501 sdcc_vreg_data[3].vccq_data = NULL;
8502
8503 msm_add_sdcc(4, &msm8x60_sdc4_data);
8504#endif
8505#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8506 /*
8507 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8508 * and no card is connected on 8660 SURF/FFA/FLUID.
8509 */
8510 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8511 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8512 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8513 sdcc_vreg_data[4].vdd_data->level = 1800000;
8514
8515 sdcc_vreg_data[4].vccq_data = NULL;
8516
8517 if (machine_is_msm8x60_fusion())
8518 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8519 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8520#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8521 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8522 msm_sdcc_setup_gpio(5, 1);
8523#endif
8524 msm_add_sdcc(5, &msm8x60_sdc5_data);
8525 }
8526#endif
8527}
8528
8529#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8530static inline void display_common_power(int on) {}
8531#else
8532
8533#define _GET_REGULATOR(var, name) do { \
8534 if (var == NULL) { \
8535 var = regulator_get(NULL, name); \
8536 if (IS_ERR(var)) { \
8537 pr_err("'%s' regulator not found, rc=%ld\n", \
8538 name, PTR_ERR(var)); \
8539 var = NULL; \
8540 } \
8541 } \
8542} while (0)
8543
8544static int dsub_regulator(int on)
8545{
8546 static struct regulator *dsub_reg;
8547 static struct regulator *mpp0_reg;
8548 static int dsub_reg_enabled;
8549 int rc = 0;
8550
8551 _GET_REGULATOR(dsub_reg, "8901_l3");
8552 if (IS_ERR(dsub_reg)) {
8553 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8554 __func__, PTR_ERR(dsub_reg));
8555 return PTR_ERR(dsub_reg);
8556 }
8557
8558 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8559 if (IS_ERR(mpp0_reg)) {
8560 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8561 __func__, PTR_ERR(mpp0_reg));
8562 return PTR_ERR(mpp0_reg);
8563 }
8564
8565 if (on && !dsub_reg_enabled) {
8566 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8567 if (rc) {
8568 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8569 " err=%d", __func__, rc);
8570 goto dsub_regulator_err;
8571 }
8572 rc = regulator_enable(dsub_reg);
8573 if (rc) {
8574 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8575 " err=%d", __func__, rc);
8576 goto dsub_regulator_err;
8577 }
8578 rc = regulator_enable(mpp0_reg);
8579 if (rc) {
8580 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8581 " err=%d", __func__, rc);
8582 goto dsub_regulator_err;
8583 }
8584 dsub_reg_enabled = 1;
8585 } else if (!on && dsub_reg_enabled) {
8586 rc = regulator_disable(dsub_reg);
8587 if (rc)
8588 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8589 " err=%d", __func__, rc);
8590 rc = regulator_disable(mpp0_reg);
8591 if (rc)
8592 printk(KERN_WARNING "%s: failed to disable reg "
8593 "8901_mpp0 err=%d", __func__, rc);
8594 dsub_reg_enabled = 0;
8595 }
8596
8597 return rc;
8598
8599dsub_regulator_err:
8600 regulator_put(mpp0_reg);
8601 regulator_put(dsub_reg);
8602 return rc;
8603}
8604
8605static int display_power_on;
8606static void setup_display_power(void)
8607{
8608 if (display_power_on)
8609 if (lcdc_vga_enabled) {
8610 dsub_regulator(1);
8611 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8612 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8613 if (machine_is_msm8x60_ffa() ||
8614 machine_is_msm8x60_fusn_ffa())
8615 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8616 } else {
8617 dsub_regulator(0);
8618 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8619 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8620 if (machine_is_msm8x60_ffa() ||
8621 machine_is_msm8x60_fusn_ffa())
8622 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8623 }
8624 else {
8625 dsub_regulator(0);
8626 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8627 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8628 /* BACKLIGHT */
8629 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8630 /* LVDS */
8631 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8632 }
8633}
8634
8635#define _GET_REGULATOR(var, name) do { \
8636 if (var == NULL) { \
8637 var = regulator_get(NULL, name); \
8638 if (IS_ERR(var)) { \
8639 pr_err("'%s' regulator not found, rc=%ld\n", \
8640 name, PTR_ERR(var)); \
8641 var = NULL; \
8642 } \
8643 } \
8644} while (0)
8645
8646#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8647
8648static void display_common_power(int on)
8649{
8650 int rc;
8651 static struct regulator *display_reg;
8652
8653 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8654 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8655 if (on) {
8656 /* LVDS */
8657 _GET_REGULATOR(display_reg, "8901_l2");
8658 if (!display_reg)
8659 return;
8660 rc = regulator_set_voltage(display_reg,
8661 3300000, 3300000);
8662 if (rc)
8663 goto out;
8664 rc = regulator_enable(display_reg);
8665 if (rc)
8666 goto out;
8667 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8668 "LVDS_STDN_OUT_N");
8669 if (rc) {
8670 printk(KERN_ERR "%s: LVDS gpio %d request"
8671 "failed\n", __func__,
8672 GPIO_LVDS_SHUTDOWN_N);
8673 goto out2;
8674 }
8675
8676 /* BACKLIGHT */
8677 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8678 if (rc) {
8679 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8680 "failed\n", __func__,
8681 GPIO_BACKLIGHT_EN);
8682 goto out3;
8683 }
8684
8685 if (machine_is_msm8x60_ffa() ||
8686 machine_is_msm8x60_fusn_ffa()) {
8687 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8688 "DONGLE_PWR_EN");
8689 if (rc) {
8690 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8691 " %d request failed\n", __func__,
8692 GPIO_DONGLE_PWR_EN);
8693 goto out4;
8694 }
8695 }
8696
8697 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8698 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8699 if (machine_is_msm8x60_ffa() ||
8700 machine_is_msm8x60_fusn_ffa())
8701 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8702 mdelay(20);
8703 display_power_on = 1;
8704 setup_display_power();
8705 } else {
8706 if (display_power_on) {
8707 display_power_on = 0;
8708 setup_display_power();
8709 mdelay(20);
8710 if (machine_is_msm8x60_ffa() ||
8711 machine_is_msm8x60_fusn_ffa())
8712 gpio_free(GPIO_DONGLE_PWR_EN);
8713 goto out4;
8714 }
8715 }
8716 }
8717#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8718 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8719 else if (machine_is_msm8x60_fluid()) {
8720 static struct regulator *fluid_reg;
8721 static struct regulator *fluid_reg2;
8722
8723 if (on) {
8724 _GET_REGULATOR(fluid_reg, "8901_l2");
8725 if (!fluid_reg)
8726 return;
8727 _GET_REGULATOR(fluid_reg2, "8058_s3");
8728 if (!fluid_reg2) {
8729 regulator_put(fluid_reg);
8730 return;
8731 }
8732 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8733 if (rc) {
8734 regulator_put(fluid_reg2);
8735 regulator_put(fluid_reg);
8736 return;
8737 }
8738 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8739 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8740 regulator_enable(fluid_reg);
8741 regulator_enable(fluid_reg2);
8742 msleep(20);
8743 gpio_direction_output(GPIO_RESX_N, 0);
8744 udelay(10);
8745 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8746 display_power_on = 1;
8747 setup_display_power();
8748 } else {
8749 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8750 gpio_free(GPIO_RESX_N);
8751 msleep(20);
8752 regulator_disable(fluid_reg2);
8753 regulator_disable(fluid_reg);
8754 regulator_put(fluid_reg2);
8755 regulator_put(fluid_reg);
8756 display_power_on = 0;
8757 setup_display_power();
8758 fluid_reg = NULL;
8759 fluid_reg2 = NULL;
8760 }
8761 }
8762#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008763#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8764 else if (machine_is_msm8x60_dragon()) {
8765 static struct regulator *dragon_reg;
8766 static struct regulator *dragon_reg2;
8767
8768 if (on) {
8769 _GET_REGULATOR(dragon_reg, "8901_l2");
8770 if (!dragon_reg)
8771 return;
8772 _GET_REGULATOR(dragon_reg2, "8058_l16");
8773 if (!dragon_reg2) {
8774 regulator_put(dragon_reg);
8775 dragon_reg = NULL;
8776 return;
8777 }
8778
8779 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8780 if (rc) {
8781 pr_err("%s: gpio %d request failed with rc=%d\n",
8782 __func__, GPIO_NT35582_BL_EN, rc);
8783 regulator_put(dragon_reg);
8784 regulator_put(dragon_reg2);
8785 dragon_reg = NULL;
8786 dragon_reg2 = NULL;
8787 return;
8788 }
8789
8790 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8791 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8792 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8793 pr_err("%s: config gpio '%d' failed!\n",
8794 __func__, GPIO_NT35582_RESET);
8795 gpio_free(GPIO_NT35582_BL_EN);
8796 regulator_put(dragon_reg);
8797 regulator_put(dragon_reg2);
8798 dragon_reg = NULL;
8799 dragon_reg2 = NULL;
8800 return;
8801 }
8802
8803 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8804 if (rc) {
8805 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8806 __func__, GPIO_NT35582_RESET, rc);
8807 gpio_free(GPIO_NT35582_BL_EN);
8808 regulator_put(dragon_reg);
8809 regulator_put(dragon_reg2);
8810 dragon_reg = NULL;
8811 dragon_reg2 = NULL;
8812 return;
8813 }
8814
8815 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8816 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8817 regulator_enable(dragon_reg);
8818 regulator_enable(dragon_reg2);
8819 msleep(20);
8820
8821 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8822 msleep(20);
8823 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8824 msleep(20);
8825 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8826 msleep(50);
8827
8828 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8829
8830 display_power_on = 1;
8831 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8832 gpio_free(GPIO_NT35582_RESET);
8833 gpio_free(GPIO_NT35582_BL_EN);
8834 regulator_disable(dragon_reg2);
8835 regulator_disable(dragon_reg);
8836 regulator_put(dragon_reg2);
8837 regulator_put(dragon_reg);
8838 display_power_on = 0;
8839 dragon_reg = NULL;
8840 dragon_reg2 = NULL;
8841 }
8842 }
8843#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008844 return;
8845
8846out4:
8847 gpio_free(GPIO_BACKLIGHT_EN);
8848out3:
8849 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8850out2:
8851 regulator_disable(display_reg);
8852out:
8853 regulator_put(display_reg);
8854 display_reg = NULL;
8855}
8856#undef _GET_REGULATOR
8857#endif
8858
8859static int mipi_dsi_panel_power(int on);
8860
8861#define LCDC_NUM_GPIO 28
8862#define LCDC_GPIO_START 0
8863
8864static void lcdc_samsung_panel_power(int on)
8865{
8866 int n, ret = 0;
8867
8868 display_common_power(on);
8869
8870 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8871 if (on) {
8872 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8873 if (unlikely(ret)) {
8874 pr_err("%s not able to get gpio\n", __func__);
8875 break;
8876 }
8877 } else
8878 gpio_free(LCDC_GPIO_START + n);
8879 }
8880
8881 if (ret) {
8882 for (n--; n >= 0; n--)
8883 gpio_free(LCDC_GPIO_START + n);
8884 }
8885
8886 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8887}
8888
8889#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8890#define _GET_REGULATOR(var, name) do { \
8891 var = regulator_get(NULL, name); \
8892 if (IS_ERR(var)) { \
8893 pr_err("'%s' regulator not found, rc=%ld\n", \
8894 name, IS_ERR(var)); \
8895 var = NULL; \
8896 return -ENODEV; \
8897 } \
8898} while (0)
8899
8900static int hdmi_enable_5v(int on)
8901{
8902 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8903 static struct regulator *reg_8901_mpp0; /* External 5V */
8904 static int prev_on;
8905 int rc;
8906
8907 if (on == prev_on)
8908 return 0;
8909
8910 if (!reg_8901_hdmi_mvs)
8911 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8912 if (!reg_8901_mpp0)
8913 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8914
8915 if (on) {
8916 rc = regulator_enable(reg_8901_mpp0);
8917 if (rc) {
8918 pr_err("'%s' regulator enable failed, rc=%d\n",
8919 "reg_8901_mpp0", rc);
8920 return rc;
8921 }
8922 rc = regulator_enable(reg_8901_hdmi_mvs);
8923 if (rc) {
8924 pr_err("'%s' regulator enable failed, rc=%d\n",
8925 "8901_hdmi_mvs", rc);
8926 return rc;
8927 }
8928 pr_info("%s(on): success\n", __func__);
8929 } else {
8930 rc = regulator_disable(reg_8901_hdmi_mvs);
8931 if (rc)
8932 pr_warning("'%s' regulator disable failed, rc=%d\n",
8933 "8901_hdmi_mvs", rc);
8934 rc = regulator_disable(reg_8901_mpp0);
8935 if (rc)
8936 pr_warning("'%s' regulator disable failed, rc=%d\n",
8937 "reg_8901_mpp0", rc);
8938 pr_info("%s(off): success\n", __func__);
8939 }
8940
8941 prev_on = on;
8942
8943 return 0;
8944}
8945
8946static int hdmi_core_power(int on, int show)
8947{
8948 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8949 static int prev_on;
8950 int rc;
8951
8952 if (on == prev_on)
8953 return 0;
8954
8955 if (!reg_8058_l16)
8956 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8957
8958 if (on) {
8959 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8960 if (!rc)
8961 rc = regulator_enable(reg_8058_l16);
8962 if (rc) {
8963 pr_err("'%s' regulator enable failed, rc=%d\n",
8964 "8058_l16", rc);
8965 return rc;
8966 }
8967 rc = gpio_request(170, "HDMI_DDC_CLK");
8968 if (rc) {
8969 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8970 "HDMI_DDC_CLK", 170, rc);
8971 goto error1;
8972 }
8973 rc = gpio_request(171, "HDMI_DDC_DATA");
8974 if (rc) {
8975 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8976 "HDMI_DDC_DATA", 171, rc);
8977 goto error2;
8978 }
8979 rc = gpio_request(172, "HDMI_HPD");
8980 if (rc) {
8981 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8982 "HDMI_HPD", 172, rc);
8983 goto error3;
8984 }
8985 pr_info("%s(on): success\n", __func__);
8986 } else {
8987 gpio_free(170);
8988 gpio_free(171);
8989 gpio_free(172);
8990 rc = regulator_disable(reg_8058_l16);
8991 if (rc)
8992 pr_warning("'%s' regulator disable failed, rc=%d\n",
8993 "8058_l16", rc);
8994 pr_info("%s(off): success\n", __func__);
8995 }
8996
8997 prev_on = on;
8998
8999 return 0;
9000
9001error3:
9002 gpio_free(171);
9003error2:
9004 gpio_free(170);
9005error1:
9006 regulator_disable(reg_8058_l16);
9007 return rc;
9008}
9009
9010static int hdmi_cec_power(int on)
9011{
9012 static struct regulator *reg_8901_l3; /* HDMI_CEC */
9013 static int prev_on;
9014 int rc;
9015
9016 if (on == prev_on)
9017 return 0;
9018
9019 if (!reg_8901_l3)
9020 _GET_REGULATOR(reg_8901_l3, "8901_l3");
9021
9022 if (on) {
9023 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
9024 if (!rc)
9025 rc = regulator_enable(reg_8901_l3);
9026 if (rc) {
9027 pr_err("'%s' regulator enable failed, rc=%d\n",
9028 "8901_l3", rc);
9029 return rc;
9030 }
9031 rc = gpio_request(169, "HDMI_CEC_VAR");
9032 if (rc) {
9033 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9034 "HDMI_CEC_VAR", 169, rc);
9035 goto error;
9036 }
9037 pr_info("%s(on): success\n", __func__);
9038 } else {
9039 gpio_free(169);
9040 rc = regulator_disable(reg_8901_l3);
9041 if (rc)
9042 pr_warning("'%s' regulator disable failed, rc=%d\n",
9043 "8901_l3", rc);
9044 pr_info("%s(off): success\n", __func__);
9045 }
9046
9047 prev_on = on;
9048
9049 return 0;
9050error:
9051 regulator_disable(reg_8901_l3);
9052 return rc;
9053}
9054
9055#undef _GET_REGULATOR
9056
9057#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
9058
9059static int lcdc_panel_power(int on)
9060{
9061 int flag_on = !!on;
9062 static int lcdc_power_save_on;
9063
9064 if (lcdc_power_save_on == flag_on)
9065 return 0;
9066
9067 lcdc_power_save_on = flag_on;
9068
9069 lcdc_samsung_panel_power(on);
9070
9071 return 0;
9072}
9073
9074#ifdef CONFIG_MSM_BUS_SCALING
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009075static struct msm_bus_vectors mdp_init_vectors[] = {
9076 /* For now, 0th array entry is reserved.
9077 * Please leave 0 as is and don't use it
9078 */
9079 {
9080 .src = MSM_BUS_MASTER_MDP_PORT0,
9081 .dst = MSM_BUS_SLAVE_SMI,
9082 .ab = 0,
9083 .ib = 0,
9084 },
9085 /* Master and slaves can be from different fabrics */
9086 {
9087 .src = MSM_BUS_MASTER_MDP_PORT0,
9088 .dst = MSM_BUS_SLAVE_EBI_CH0,
9089 .ab = 0,
9090 .ib = 0,
9091 },
9092};
9093
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009094#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9095static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
9096 /* If HDMI is used as primary */
9097 {
9098 .src = MSM_BUS_MASTER_MDP_PORT0,
9099 .dst = MSM_BUS_SLAVE_SMI,
9100 .ab = 2000000000,
9101 .ib = 2000000000,
9102 },
9103 /* Master and slaves can be from different fabrics */
9104 {
9105 .src = MSM_BUS_MASTER_MDP_PORT0,
9106 .dst = MSM_BUS_SLAVE_EBI_CH0,
9107 .ab = 2000000000,
9108 .ib = 2000000000,
9109 },
9110};
9111
9112static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9113 {
9114 ARRAY_SIZE(mdp_init_vectors),
9115 mdp_init_vectors,
9116 },
9117 {
9118 ARRAY_SIZE(hdmi_as_primary_vectors),
9119 hdmi_as_primary_vectors,
9120 },
9121 {
9122 ARRAY_SIZE(hdmi_as_primary_vectors),
9123 hdmi_as_primary_vectors,
9124 },
9125 {
9126 ARRAY_SIZE(hdmi_as_primary_vectors),
9127 hdmi_as_primary_vectors,
9128 },
9129 {
9130 ARRAY_SIZE(hdmi_as_primary_vectors),
9131 hdmi_as_primary_vectors,
9132 },
9133 {
9134 ARRAY_SIZE(hdmi_as_primary_vectors),
9135 hdmi_as_primary_vectors,
9136 },
9137};
9138#else
9139#ifdef CONFIG_FB_MSM_LCDC_DSUB
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009140static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9141 /* Default case static display/UI/2d/3d if FB SMI */
9142 {
9143 .src = MSM_BUS_MASTER_MDP_PORT0,
9144 .dst = MSM_BUS_SLAVE_SMI,
9145 .ab = 388800000,
9146 .ib = 486000000,
9147 },
9148 /* Master and slaves can be from different fabrics */
9149 {
9150 .src = MSM_BUS_MASTER_MDP_PORT0,
9151 .dst = MSM_BUS_SLAVE_EBI_CH0,
9152 .ab = 0,
9153 .ib = 0,
9154 },
9155};
9156
9157static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9158 /* Default case static display/UI/2d/3d if FB SMI */
9159 {
9160 .src = MSM_BUS_MASTER_MDP_PORT0,
9161 .dst = MSM_BUS_SLAVE_SMI,
9162 .ab = 0,
9163 .ib = 0,
9164 },
9165 /* Master and slaves can be from different fabrics */
9166 {
9167 .src = MSM_BUS_MASTER_MDP_PORT0,
9168 .dst = MSM_BUS_SLAVE_EBI_CH0,
9169 .ab = 388800000,
9170 .ib = 486000000 * 2,
9171 },
9172};
9173static struct msm_bus_vectors mdp_vga_vectors[] = {
9174 /* VGA and less video */
9175 {
9176 .src = MSM_BUS_MASTER_MDP_PORT0,
9177 .dst = MSM_BUS_SLAVE_SMI,
9178 .ab = 458092800,
9179 .ib = 572616000,
9180 },
9181 {
9182 .src = MSM_BUS_MASTER_MDP_PORT0,
9183 .dst = MSM_BUS_SLAVE_EBI_CH0,
9184 .ab = 458092800,
9185 .ib = 572616000 * 2,
9186 },
9187};
9188static struct msm_bus_vectors mdp_720p_vectors[] = {
9189 /* 720p and less video */
9190 {
9191 .src = MSM_BUS_MASTER_MDP_PORT0,
9192 .dst = MSM_BUS_SLAVE_SMI,
9193 .ab = 471744000,
9194 .ib = 589680000,
9195 },
9196 /* Master and slaves can be from different fabrics */
9197 {
9198 .src = MSM_BUS_MASTER_MDP_PORT0,
9199 .dst = MSM_BUS_SLAVE_EBI_CH0,
9200 .ab = 471744000,
9201 .ib = 589680000 * 2,
9202 },
9203};
9204
9205static struct msm_bus_vectors mdp_1080p_vectors[] = {
9206 /* 1080p and less video */
9207 {
9208 .src = MSM_BUS_MASTER_MDP_PORT0,
9209 .dst = MSM_BUS_SLAVE_SMI,
9210 .ab = 575424000,
9211 .ib = 719280000,
9212 },
9213 /* Master and slaves can be from different fabrics */
9214 {
9215 .src = MSM_BUS_MASTER_MDP_PORT0,
9216 .dst = MSM_BUS_SLAVE_EBI_CH0,
9217 .ab = 575424000,
9218 .ib = 719280000 * 2,
9219 },
9220};
9221
9222#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009223static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9224 /* Default case static display/UI/2d/3d if FB SMI */
9225 {
9226 .src = MSM_BUS_MASTER_MDP_PORT0,
9227 .dst = MSM_BUS_SLAVE_SMI,
9228 .ab = 175110000,
9229 .ib = 218887500,
9230 },
9231 /* Master and slaves can be from different fabrics */
9232 {
9233 .src = MSM_BUS_MASTER_MDP_PORT0,
9234 .dst = MSM_BUS_SLAVE_EBI_CH0,
9235 .ab = 0,
9236 .ib = 0,
9237 },
9238};
9239
9240static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9241 /* Default case static display/UI/2d/3d if FB SMI */
9242 {
9243 .src = MSM_BUS_MASTER_MDP_PORT0,
9244 .dst = MSM_BUS_SLAVE_SMI,
9245 .ab = 0,
9246 .ib = 0,
9247 },
9248 /* Master and slaves can be from different fabrics */
9249 {
9250 .src = MSM_BUS_MASTER_MDP_PORT0,
9251 .dst = MSM_BUS_SLAVE_EBI_CH0,
9252 .ab = 216000000,
9253 .ib = 270000000 * 2,
9254 },
9255};
9256static struct msm_bus_vectors mdp_vga_vectors[] = {
9257 /* VGA and less video */
9258 {
9259 .src = MSM_BUS_MASTER_MDP_PORT0,
9260 .dst = MSM_BUS_SLAVE_SMI,
9261 .ab = 216000000,
9262 .ib = 270000000,
9263 },
9264 {
9265 .src = MSM_BUS_MASTER_MDP_PORT0,
9266 .dst = MSM_BUS_SLAVE_EBI_CH0,
9267 .ab = 216000000,
9268 .ib = 270000000 * 2,
9269 },
9270};
9271
9272static struct msm_bus_vectors mdp_720p_vectors[] = {
9273 /* 720p and less video */
9274 {
9275 .src = MSM_BUS_MASTER_MDP_PORT0,
9276 .dst = MSM_BUS_SLAVE_SMI,
9277 .ab = 230400000,
9278 .ib = 288000000,
9279 },
9280 /* Master and slaves can be from different fabrics */
9281 {
9282 .src = MSM_BUS_MASTER_MDP_PORT0,
9283 .dst = MSM_BUS_SLAVE_EBI_CH0,
9284 .ab = 230400000,
9285 .ib = 288000000 * 2,
9286 },
9287};
9288
9289static struct msm_bus_vectors mdp_1080p_vectors[] = {
9290 /* 1080p and less video */
9291 {
9292 .src = MSM_BUS_MASTER_MDP_PORT0,
9293 .dst = MSM_BUS_SLAVE_SMI,
9294 .ab = 334080000,
9295 .ib = 417600000,
9296 },
9297 /* Master and slaves can be from different fabrics */
9298 {
9299 .src = MSM_BUS_MASTER_MDP_PORT0,
9300 .dst = MSM_BUS_SLAVE_EBI_CH0,
9301 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009302 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009303 },
9304};
9305
9306#endif
9307static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9308 {
9309 ARRAY_SIZE(mdp_init_vectors),
9310 mdp_init_vectors,
9311 },
9312 {
9313 ARRAY_SIZE(mdp_sd_smi_vectors),
9314 mdp_sd_smi_vectors,
9315 },
9316 {
9317 ARRAY_SIZE(mdp_sd_ebi_vectors),
9318 mdp_sd_ebi_vectors,
9319 },
9320 {
9321 ARRAY_SIZE(mdp_vga_vectors),
9322 mdp_vga_vectors,
9323 },
9324 {
9325 ARRAY_SIZE(mdp_720p_vectors),
9326 mdp_720p_vectors,
9327 },
9328 {
9329 ARRAY_SIZE(mdp_1080p_vectors),
9330 mdp_1080p_vectors,
9331 },
9332};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009333#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009334static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9335 mdp_bus_scale_usecases,
9336 ARRAY_SIZE(mdp_bus_scale_usecases),
9337 .name = "mdp",
9338};
9339
9340#endif
9341#ifdef CONFIG_MSM_BUS_SCALING
9342static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9343 /* For now, 0th array entry is reserved.
9344 * Please leave 0 as is and don't use it
9345 */
9346 {
9347 .src = MSM_BUS_MASTER_MDP_PORT0,
9348 .dst = MSM_BUS_SLAVE_SMI,
9349 .ab = 0,
9350 .ib = 0,
9351 },
9352 /* Master and slaves can be from different fabrics */
9353 {
9354 .src = MSM_BUS_MASTER_MDP_PORT0,
9355 .dst = MSM_BUS_SLAVE_EBI_CH0,
9356 .ab = 0,
9357 .ib = 0,
9358 },
9359};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009360#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9361static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9362 /* For now, 0th array entry is reserved.
9363 * Please leave 0 as is and don't use it
9364 */
9365 {
9366 .src = MSM_BUS_MASTER_MDP_PORT0,
9367 .dst = MSM_BUS_SLAVE_SMI,
9368 .ab = 2000000000,
9369 .ib = 2000000000,
9370 },
9371 /* Master and slaves can be from different fabrics */
9372 {
9373 .src = MSM_BUS_MASTER_MDP_PORT0,
9374 .dst = MSM_BUS_SLAVE_EBI_CH0,
9375 .ab = 2000000000,
9376 .ib = 2000000000,
9377 },
9378};
9379#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009380static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9381 /* For now, 0th array entry is reserved.
9382 * Please leave 0 as is and don't use it
9383 */
9384 {
9385 .src = MSM_BUS_MASTER_MDP_PORT0,
9386 .dst = MSM_BUS_SLAVE_SMI,
9387 .ab = 566092800,
9388 .ib = 707616000,
9389 },
9390 /* Master and slaves can be from different fabrics */
9391 {
9392 .src = MSM_BUS_MASTER_MDP_PORT0,
9393 .dst = MSM_BUS_SLAVE_EBI_CH0,
9394 .ab = 566092800,
9395 .ib = 707616000,
9396 },
9397};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009398#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009399static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9400 {
9401 ARRAY_SIZE(dtv_bus_init_vectors),
9402 dtv_bus_init_vectors,
9403 },
9404 {
9405 ARRAY_SIZE(dtv_bus_def_vectors),
9406 dtv_bus_def_vectors,
9407 },
9408};
9409static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9410 dtv_bus_scale_usecases,
9411 ARRAY_SIZE(dtv_bus_scale_usecases),
9412 .name = "dtv",
9413};
9414
9415static struct lcdc_platform_data dtv_pdata = {
9416 .bus_scale_table = &dtv_bus_scale_pdata,
9417};
9418#endif
9419
9420
9421static struct lcdc_platform_data lcdc_pdata = {
9422 .lcdc_power_save = lcdc_panel_power,
9423};
9424
9425
9426#define MDP_VSYNC_GPIO 28
9427
9428/*
9429 * MIPI_DSI only use 8058_LDO0 which need always on
9430 * therefore it need to be put at low power mode if
9431 * it was not used instead of turn it off.
9432 */
9433static int mipi_dsi_panel_power(int on)
9434{
9435 int flag_on = !!on;
9436 static int mipi_dsi_power_save_on;
9437 static struct regulator *ldo0;
9438 int rc = 0;
9439
9440 if (mipi_dsi_power_save_on == flag_on)
9441 return 0;
9442
9443 mipi_dsi_power_save_on = flag_on;
9444
9445 if (ldo0 == NULL) { /* init */
9446 ldo0 = regulator_get(NULL, "8058_l0");
9447 if (IS_ERR(ldo0)) {
9448 pr_debug("%s: LDO0 failed\n", __func__);
9449 rc = PTR_ERR(ldo0);
9450 return rc;
9451 }
9452
9453 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9454 if (rc)
9455 goto out;
9456
9457 rc = regulator_enable(ldo0);
9458 if (rc)
9459 goto out;
9460 }
9461
9462 if (on) {
9463 /* set ldo0 to HPM */
9464 rc = regulator_set_optimum_mode(ldo0, 100000);
9465 if (rc < 0)
9466 goto out;
9467 } else {
9468 /* set ldo0 to LPM */
9469 rc = regulator_set_optimum_mode(ldo0, 9000);
9470 if (rc < 0)
9471 goto out;
9472 }
9473
9474 return 0;
9475out:
9476 regulator_disable(ldo0);
9477 regulator_put(ldo0);
9478 ldo0 = NULL;
9479 return rc;
9480}
9481
9482static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9483 .vsync_gpio = MDP_VSYNC_GPIO,
9484 .dsi_power_save = mipi_dsi_panel_power,
9485};
9486
9487#ifdef CONFIG_FB_MSM_TVOUT
9488static struct regulator *reg_8058_l13;
9489
9490static int atv_dac_power(int on)
9491{
9492 int rc = 0;
9493 #define _GET_REGULATOR(var, name) do { \
9494 var = regulator_get(NULL, name); \
9495 if (IS_ERR(var)) { \
9496 pr_info("'%s' regulator not found, rc=%ld\n", \
9497 name, IS_ERR(var)); \
9498 var = NULL; \
9499 return -ENODEV; \
9500 } \
9501 } while (0)
9502
9503 if (!reg_8058_l13)
9504 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9505 #undef _GET_REGULATOR
9506
9507 if (on) {
9508 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9509 if (rc) {
9510 pr_info("%s: '%s' regulator set voltage failed,\
9511 rc=%d\n", __func__, "8058_l13", rc);
9512 return rc;
9513 }
9514
9515 rc = regulator_enable(reg_8058_l13);
9516 if (rc) {
9517 pr_err("%s: '%s' regulator enable failed,\
9518 rc=%d\n", __func__, "8058_l13", rc);
9519 return rc;
9520 }
9521 } else {
9522 rc = regulator_force_disable(reg_8058_l13);
9523 if (rc)
9524 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9525 __func__, "8058_l13", rc);
9526 }
9527 return rc;
9528
9529}
9530#endif
9531
9532#ifdef CONFIG_FB_MSM_MIPI_DSI
9533int mdp_core_clk_rate_table[] = {
9534 85330000,
9535 85330000,
9536 160000000,
9537 200000000,
9538};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009539#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
9540int mdp_core_clk_rate_table[] = {
9541 200000000,
9542 200000000,
9543 200000000,
9544 200000000,
9545};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009546#else
9547int mdp_core_clk_rate_table[] = {
9548 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009549 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009550 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009551 200000000,
9552};
9553#endif
9554
9555static struct msm_panel_common_pdata mdp_pdata = {
9556 .gpio = MDP_VSYNC_GPIO,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009557#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9558 .mdp_core_clk_rate = 200000000,
9559#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009560 .mdp_core_clk_rate = 59080000,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009561#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009562 .mdp_core_clk_table = mdp_core_clk_rate_table,
9563 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9564#ifdef CONFIG_MSM_BUS_SCALING
9565 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9566#endif
9567 .mdp_rev = MDP_REV_41,
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07009568 .writeback_offset = writeback_offset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009569};
9570
9571#ifdef CONFIG_FB_MSM_TVOUT
9572
9573#ifdef CONFIG_MSM_BUS_SCALING
9574static struct msm_bus_vectors atv_bus_init_vectors[] = {
9575 /* For now, 0th array entry is reserved.
9576 * Please leave 0 as is and don't use it
9577 */
9578 {
9579 .src = MSM_BUS_MASTER_MDP_PORT0,
9580 .dst = MSM_BUS_SLAVE_SMI,
9581 .ab = 0,
9582 .ib = 0,
9583 },
9584 /* Master and slaves can be from different fabrics */
9585 {
9586 .src = MSM_BUS_MASTER_MDP_PORT0,
9587 .dst = MSM_BUS_SLAVE_EBI_CH0,
9588 .ab = 0,
9589 .ib = 0,
9590 },
9591};
9592static struct msm_bus_vectors atv_bus_def_vectors[] = {
9593 /* For now, 0th array entry is reserved.
9594 * Please leave 0 as is and don't use it
9595 */
9596 {
9597 .src = MSM_BUS_MASTER_MDP_PORT0,
9598 .dst = MSM_BUS_SLAVE_SMI,
9599 .ab = 236390400,
9600 .ib = 265939200,
9601 },
9602 /* Master and slaves can be from different fabrics */
9603 {
9604 .src = MSM_BUS_MASTER_MDP_PORT0,
9605 .dst = MSM_BUS_SLAVE_EBI_CH0,
9606 .ab = 236390400,
9607 .ib = 265939200,
9608 },
9609};
9610static struct msm_bus_paths atv_bus_scale_usecases[] = {
9611 {
9612 ARRAY_SIZE(atv_bus_init_vectors),
9613 atv_bus_init_vectors,
9614 },
9615 {
9616 ARRAY_SIZE(atv_bus_def_vectors),
9617 atv_bus_def_vectors,
9618 },
9619};
9620static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9621 atv_bus_scale_usecases,
9622 ARRAY_SIZE(atv_bus_scale_usecases),
9623 .name = "atv",
9624};
9625#endif
9626
9627static struct tvenc_platform_data atv_pdata = {
9628 .poll = 0,
9629 .pm_vid_en = atv_dac_power,
9630#ifdef CONFIG_MSM_BUS_SCALING
9631 .bus_scale_table = &atv_bus_scale_pdata,
9632#endif
9633};
9634#endif
9635
9636static void __init msm_fb_add_devices(void)
9637{
9638#ifdef CONFIG_FB_MSM_LCDC_DSUB
9639 mdp_pdata.mdp_core_clk_table = NULL;
9640 mdp_pdata.num_mdp_clk = 0;
9641 mdp_pdata.mdp_core_clk_rate = 200000000;
9642#endif
9643 if (machine_is_msm8x60_rumi3())
9644 msm_fb_register_device("mdp", NULL);
9645 else
9646 msm_fb_register_device("mdp", &mdp_pdata);
9647
9648 msm_fb_register_device("lcdc", &lcdc_pdata);
9649 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9650#ifdef CONFIG_MSM_BUS_SCALING
9651 msm_fb_register_device("dtv", &dtv_pdata);
9652#endif
9653#ifdef CONFIG_FB_MSM_TVOUT
9654 msm_fb_register_device("tvenc", &atv_pdata);
9655 msm_fb_register_device("tvout_device", NULL);
9656#endif
9657}
9658
9659#if (defined(CONFIG_MARIMBA_CORE)) && \
9660 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9661
9662static const struct {
9663 char *name;
9664 int vmin;
9665 int vmax;
9666} bt_regs_info[] = {
9667 { "8058_s3", 1800000, 1800000 },
9668 { "8058_s2", 1300000, 1300000 },
9669 { "8058_l8", 2900000, 3050000 },
9670};
9671
9672static struct {
9673 bool enabled;
9674} bt_regs_status[] = {
9675 { false },
9676 { false },
9677 { false },
9678};
9679static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9680
9681static int bahama_bt(int on)
9682{
9683 int rc;
9684 int i;
9685 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9686
9687 struct bahama_variant_register {
9688 const size_t size;
9689 const struct bahama_config_register *set;
9690 };
9691
9692 const struct bahama_config_register *p;
9693
9694 u8 version;
9695
9696 const struct bahama_config_register v10_bt_on[] = {
9697 { 0xE9, 0x00, 0xFF },
9698 { 0xF4, 0x80, 0xFF },
9699 { 0xE4, 0x00, 0xFF },
9700 { 0xE5, 0x00, 0x0F },
9701#ifdef CONFIG_WLAN
9702 { 0xE6, 0x38, 0x7F },
9703 { 0xE7, 0x06, 0xFF },
9704#endif
9705 { 0xE9, 0x21, 0xFF },
9706 { 0x01, 0x0C, 0x1F },
9707 { 0x01, 0x08, 0x1F },
9708 };
9709
9710 const struct bahama_config_register v20_bt_on_fm_off[] = {
9711 { 0x11, 0x0C, 0xFF },
9712 { 0x13, 0x01, 0xFF },
9713 { 0xF4, 0x80, 0xFF },
9714 { 0xF0, 0x00, 0xFF },
9715 { 0xE9, 0x00, 0xFF },
9716#ifdef CONFIG_WLAN
9717 { 0x81, 0x00, 0x7F },
9718 { 0x82, 0x00, 0xFF },
9719 { 0xE6, 0x38, 0x7F },
9720 { 0xE7, 0x06, 0xFF },
9721#endif
9722 { 0xE9, 0x21, 0xFF },
9723 };
9724
9725 const struct bahama_config_register v20_bt_on_fm_on[] = {
9726 { 0x11, 0x0C, 0xFF },
9727 { 0x13, 0x01, 0xFF },
9728 { 0xF4, 0x86, 0xFF },
9729 { 0xF0, 0x06, 0xFF },
9730 { 0xE9, 0x00, 0xFF },
9731#ifdef CONFIG_WLAN
9732 { 0x81, 0x00, 0x7F },
9733 { 0x82, 0x00, 0xFF },
9734 { 0xE6, 0x38, 0x7F },
9735 { 0xE7, 0x06, 0xFF },
9736#endif
9737 { 0xE9, 0x21, 0xFF },
9738 };
9739
9740 const struct bahama_config_register v10_bt_off[] = {
9741 { 0xE9, 0x00, 0xFF },
9742 };
9743
9744 const struct bahama_config_register v20_bt_off_fm_off[] = {
9745 { 0xF4, 0x84, 0xFF },
9746 { 0xF0, 0x04, 0xFF },
9747 { 0xE9, 0x00, 0xFF }
9748 };
9749
9750 const struct bahama_config_register v20_bt_off_fm_on[] = {
9751 { 0xF4, 0x86, 0xFF },
9752 { 0xF0, 0x06, 0xFF },
9753 { 0xE9, 0x00, 0xFF }
9754 };
9755 const struct bahama_variant_register bt_bahama[2][3] = {
9756 {
9757 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9758 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9759 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9760 },
9761 {
9762 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9763 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9764 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9765 }
9766 };
9767
9768 u8 offset = 0; /* index into bahama configs */
9769
9770 on = on ? 1 : 0;
9771 version = read_bahama_ver();
9772
9773 if (version == VER_UNSUPPORTED) {
9774 dev_err(&msm_bt_power_device.dev,
9775 "%s: unsupported version\n",
9776 __func__);
9777 return -EIO;
9778 }
9779
9780 if (version == VER_2_0) {
9781 if (marimba_get_fm_status(&config))
9782 offset = 0x01;
9783 }
9784
9785 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9786 if (on && (version == VER_2_0)) {
9787 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9788 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9789 && (bt_regs_status[i].enabled == true)) {
9790 if (regulator_disable(bt_regs[i])) {
9791 dev_err(&msm_bt_power_device.dev,
9792 "%s: regulator disable failed",
9793 __func__);
9794 }
9795 bt_regs_status[i].enabled = false;
9796 break;
9797 }
9798 }
9799 }
9800
9801 p = bt_bahama[on][version + offset].set;
9802
9803 dev_info(&msm_bt_power_device.dev,
9804 "%s: found version %d\n", __func__, version);
9805
9806 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9807 u8 value = (p+i)->value;
9808 rc = marimba_write_bit_mask(&config,
9809 (p+i)->reg,
9810 &value,
9811 sizeof((p+i)->value),
9812 (p+i)->mask);
9813 if (rc < 0) {
9814 dev_err(&msm_bt_power_device.dev,
9815 "%s: reg %d write failed: %d\n",
9816 __func__, (p+i)->reg, rc);
9817 return rc;
9818 }
9819 dev_dbg(&msm_bt_power_device.dev,
9820 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9821 __func__, (p+i)->reg,
9822 value, (p+i)->mask);
9823 }
9824 /* Update BT Status */
9825 if (on)
9826 marimba_set_bt_status(&config, true);
9827 else
9828 marimba_set_bt_status(&config, false);
9829
9830 return 0;
9831}
9832
9833static int bluetooth_use_regulators(int on)
9834{
9835 int i, recover = -1, rc = 0;
9836
9837 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9838 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9839 bt_regs_info[i].name) :
9840 (regulator_put(bt_regs[i]), NULL);
9841 if (IS_ERR(bt_regs[i])) {
9842 rc = PTR_ERR(bt_regs[i]);
9843 dev_err(&msm_bt_power_device.dev,
9844 "regulator %s get failed (%d)\n",
9845 bt_regs_info[i].name, rc);
9846 recover = i - 1;
9847 bt_regs[i] = NULL;
9848 break;
9849 }
9850
9851 if (!on)
9852 continue;
9853
9854 rc = regulator_set_voltage(bt_regs[i],
9855 bt_regs_info[i].vmin,
9856 bt_regs_info[i].vmax);
9857 if (rc < 0) {
9858 dev_err(&msm_bt_power_device.dev,
9859 "regulator %s voltage set (%d)\n",
9860 bt_regs_info[i].name, rc);
9861 recover = i;
9862 break;
9863 }
9864 }
9865
9866 if (on && (recover > -1))
9867 for (i = recover; i >= 0; i--) {
9868 regulator_put(bt_regs[i]);
9869 bt_regs[i] = NULL;
9870 }
9871
9872 return rc;
9873}
9874
9875static int bluetooth_switch_regulators(int on)
9876{
9877 int i, rc = 0;
9878
9879 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9880 if (on && (bt_regs_status[i].enabled == false)) {
9881 rc = regulator_enable(bt_regs[i]);
9882 if (rc < 0) {
9883 dev_err(&msm_bt_power_device.dev,
9884 "regulator %s %s failed (%d)\n",
9885 bt_regs_info[i].name,
9886 "enable", rc);
9887 if (i > 0) {
9888 while (--i) {
9889 regulator_disable(bt_regs[i]);
9890 bt_regs_status[i].enabled
9891 = false;
9892 }
9893 break;
9894 }
9895 }
9896 bt_regs_status[i].enabled = true;
9897 } else if (!on && (bt_regs_status[i].enabled == true)) {
9898 rc = regulator_disable(bt_regs[i]);
9899 if (rc < 0) {
9900 dev_err(&msm_bt_power_device.dev,
9901 "regulator %s %s failed (%d)\n",
9902 bt_regs_info[i].name,
9903 "disable", rc);
9904 break;
9905 }
9906 bt_regs_status[i].enabled = false;
9907 }
9908 }
9909 return rc;
9910}
9911
9912static struct msm_xo_voter *bt_clock;
9913
9914static int bluetooth_power(int on)
9915{
9916 int rc = 0;
9917 int id;
9918
9919 /* In case probe function fails, cur_connv_type would be -1 */
9920 id = adie_get_detected_connectivity_type();
9921 if (id != BAHAMA_ID) {
9922 pr_err("%s: unexpected adie connectivity type: %d\n",
9923 __func__, id);
9924 return -ENODEV;
9925 }
9926
9927 if (on) {
9928
9929 rc = bluetooth_use_regulators(1);
9930 if (rc < 0)
9931 goto out;
9932
9933 rc = bluetooth_switch_regulators(1);
9934
9935 if (rc < 0)
9936 goto fail_put;
9937
9938 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9939
9940 if (IS_ERR(bt_clock)) {
9941 pr_err("Couldn't get TCXO_D0 voter\n");
9942 goto fail_switch;
9943 }
9944
9945 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9946
9947 if (rc < 0) {
9948 pr_err("Failed to vote for TCXO_DO ON\n");
9949 goto fail_vote;
9950 }
9951
9952 rc = bahama_bt(1);
9953
9954 if (rc < 0)
9955 goto fail_clock;
9956
9957 msleep(10);
9958
9959 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9960
9961 if (rc < 0) {
9962 pr_err("Failed to vote for TCXO_DO pin control\n");
9963 goto fail_vote;
9964 }
9965 } else {
9966 /* check for initial RFKILL block (power off) */
9967 /* some RFKILL versions/configurations rfkill_register */
9968 /* calls here for an initial set_block */
9969 /* avoid calling i2c and regulator before unblock (on) */
9970 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
9971 dev_info(&msm_bt_power_device.dev,
9972 "%s: initialized OFF/blocked\n", __func__);
9973 goto out;
9974 }
9975
9976 bahama_bt(0);
9977
9978fail_clock:
9979 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
9980fail_vote:
9981 msm_xo_put(bt_clock);
9982fail_switch:
9983 bluetooth_switch_regulators(0);
9984fail_put:
9985 bluetooth_use_regulators(0);
9986 }
9987
9988out:
9989 if (rc < 0)
9990 on = 0;
9991 dev_info(&msm_bt_power_device.dev,
9992 "Bluetooth power switch: state %d result %d\n", on, rc);
9993
9994 return rc;
9995}
9996
9997#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
9998
9999static void __init msm8x60_cfg_smsc911x(void)
10000{
10001 smsc911x_resources[1].start =
10002 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10003 smsc911x_resources[1].end =
10004 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10005}
10006
10007#ifdef CONFIG_MSM_RPM
10008static struct msm_rpm_platform_data msm_rpm_data = {
10009 .reg_base_addrs = {
10010 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
10011 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
10012 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
10013 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
10014 },
10015
10016 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
10017 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
10018 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
10019 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
10020 .msm_apps_ipc_rpm_val = 4,
10021};
10022#endif
10023
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010024void msm_fusion_setup_pinctrl(void)
10025{
10026 struct msm_xo_voter *a1;
10027
10028 if (socinfo_get_platform_subtype() == 0x3) {
10029 /*
10030 * Vote for the A1 clock to be in pin control mode before
10031 * the external images are loaded.
10032 */
10033 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
10034 BUG_ON(!a1);
10035 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
10036 }
10037}
10038
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010039struct msm_board_data {
10040 struct msm_gpiomux_configs *gpiomux_cfgs;
10041};
10042
10043static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
10044 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10045};
10046
10047static struct msm_board_data msm8x60_sim_board_data __initdata = {
10048 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10049};
10050
10051static struct msm_board_data msm8x60_surf_board_data __initdata = {
10052 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10053};
10054
10055static struct msm_board_data msm8x60_ffa_board_data __initdata = {
10056 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10057};
10058
10059static struct msm_board_data msm8x60_fluid_board_data __initdata = {
10060 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
10061};
10062
10063static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
10064 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10065};
10066
10067static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
10068 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10069};
10070
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010071static struct msm_board_data msm8x60_dragon_board_data __initdata = {
10072 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
10073};
10074
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010075static void __init msm8x60_init(struct msm_board_data *board_data)
10076{
10077 uint32_t soc_platform_version;
10078
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070010079 pmic_reset_irq = PM8058_RESOUT_IRQ(PM8058_IRQ_BASE);
10080
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010081 /*
10082 * Initialize RPM first as other drivers and devices may need
10083 * it for their initialization.
10084 */
10085#ifdef CONFIG_MSM_RPM
10086 BUG_ON(msm_rpm_init(&msm_rpm_data));
10087#endif
10088 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
10089 ARRAY_SIZE(msm_rpmrs_levels)));
10090 if (msm_xo_init())
10091 pr_err("Failed to initialize XO votes\n");
10092
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010093 msm8x60_check_2d_hardware();
10094
10095 /* Change SPM handling of core 1 if PMM 8160 is present. */
10096 soc_platform_version = socinfo_get_platform_version();
10097 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
10098 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
10099 struct msm_spm_platform_data *spm_data;
10100
10101 spm_data = &msm_spm_data_v1[1];
10102 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10103 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10104
10105 spm_data = &msm_spm_data[1];
10106 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10107 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10108 }
10109
10110 /*
10111 * Initialize SPM before acpuclock as the latter calls into SPM
10112 * driver to set ACPU voltages.
10113 */
10114 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10115 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
10116 else
10117 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
10118
10119 /*
10120 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
10121 * devices so that the RPM doesn't drop into a low power mode that an
10122 * un-reworked SURF cannot resume from.
10123 */
10124 if (machine_is_msm8x60_surf()) {
David Collins6f032ba2011-08-31 14:08:15 -070010125 int i;
10126
10127 for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
10128 if (rpm_regulator_init_data[i].id
10129 == RPM_VREG_ID_PM8901_L4
10130 || rpm_regulator_init_data[i].id
10131 == RPM_VREG_ID_PM8901_L6)
10132 rpm_regulator_init_data[i]
10133 .init_data.constraints.always_on = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010134 }
10135
10136 /*
10137 * Disable regulator info printing so that regulator registration
10138 * messages do not enter the kmsg log.
10139 */
10140 regulator_suppress_info_printing();
10141
10142 /* Initialize regulators needed for clock_init. */
10143 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
10144
Stephen Boydbb600ae2011-08-02 20:11:40 -070010145 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010146
10147 /* Buses need to be initialized before early-device registration
10148 * to get the platform data for fabrics.
10149 */
10150 msm8x60_init_buses();
10151 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
10152 /* CPU frequency control is not supported on simulated targets. */
10153 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
Matt Wagantallec57f062011-08-16 23:54:46 -070010154 acpuclk_init(&acpuclk_8x60_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010155
Terence Hampsonb36a38c2011-09-19 19:10:40 -040010156 /*
10157 * Enable EBI2 only for boards which make use of it. Leave
10158 * it disabled for all others for additional power savings.
10159 */
10160 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10161 machine_is_msm8x60_rumi3() ||
10162 machine_is_msm8x60_sim() ||
10163 machine_is_msm8x60_fluid() ||
10164 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010165 msm8x60_init_ebi2();
10166 msm8x60_init_tlmm();
10167 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10168 msm8x60_init_uart12dm();
10169 msm8x60_init_mmc();
10170
10171#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10172 msm8x60_init_pm8058_othc();
10173#endif
10174
10175 if (machine_is_msm8x60_fluid()) {
10176 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10177 platform_data = &fluid_keypad_data;
10178 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10179 = sizeof(fluid_keypad_data);
Zhang Chang Ken683be172011-08-10 17:45:34 -040010180 } else if (machine_is_msm8x60_dragon()) {
10181 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10182 platform_data = &dragon_keypad_data;
10183 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10184 = sizeof(dragon_keypad_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010185 } else {
10186 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10187 platform_data = &ffa_keypad_data;
10188 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10189 = sizeof(ffa_keypad_data);
10190
10191 }
10192
10193 /* Disable END_CALL simulation function of powerkey on fluid */
10194 if (machine_is_msm8x60_fluid()) {
10195 pwrkey_pdata.pwrkey_time_ms = 0;
10196 }
10197
Jilai Wang53d27a82011-07-13 14:32:58 -040010198 /* Specify reset pin for OV9726 */
10199 if (machine_is_msm8x60_dragon()) {
10200 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10201 ov9726_sensor_8660_info.mount_angle = 270;
10202 }
10203
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010204 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10205 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010206 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010207 msm8x60_cfg_smsc911x();
10208 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10209 platform_add_devices(msm_footswitch_devices,
10210 msm_num_footswitch_devices);
10211 platform_add_devices(surf_devices,
10212 ARRAY_SIZE(surf_devices));
10213
10214#ifdef CONFIG_MSM_DSPS
10215 if (machine_is_msm8x60_fluid()) {
10216 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10217 msm8x60_init_dsps();
10218 }
10219#endif
10220
10221#ifdef CONFIG_USB_EHCI_MSM_72K
10222 /*
10223 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10224 * fluid
10225 */
10226 if (machine_is_msm8x60_fluid()) {
10227 pm8901_mpp_config_digital_out(1,
10228 PM8901_MPP_DIG_LEVEL_L5, 1);
10229 }
10230 msm_add_host(0, &msm_usb_host_pdata);
10231#endif
Lei Zhou338cab82011-08-19 13:38:17 -040010232
10233#ifdef CONFIG_SND_SOC_MSM8660_APQ
10234 if (machine_is_msm8x60_dragon())
10235 platform_add_devices(dragon_alsa_devices,
10236 ARRAY_SIZE(dragon_alsa_devices));
10237 else
10238#endif
10239 platform_add_devices(asoc_devices,
10240 ARRAY_SIZE(asoc_devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010241 } else {
10242 msm8x60_configure_smc91x();
10243 platform_add_devices(rumi_sim_devices,
10244 ARRAY_SIZE(rumi_sim_devices));
10245 }
10246#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010247 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10248 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010249 msm8x60_cfg_isp1763();
10250#endif
10251#ifdef CONFIG_BATTERY_MSM8X60
10252 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010253 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010254 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10255 platform_device_register(&msm_charger_device);
10256#endif
10257
10258 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10259 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10260
Terence Hampson90508a92011-08-09 10:40:08 -040010261 if (machine_is_msm8x60_dragon()) {
10262 pm8058_charger_sub_dev.platform_data
10263 = &pmic8058_charger_dragon;
10264 pm8058_charger_sub_dev.pdata_size
10265 = sizeof(pmic8058_charger_dragon);
10266 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010267 if (!machine_is_msm8x60_fluid())
10268 pm8058_platform_data.charger_sub_device
10269 = &pm8058_charger_sub_dev;
10270
10271#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10272 if (machine_is_msm8x60_fluid())
10273 platform_device_register(&msm_gsbi10_qup_spi_device);
10274 else
10275 platform_device_register(&msm_gsbi1_qup_spi_device);
10276#endif
10277
10278#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10279 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10280 if (machine_is_msm8x60_fluid())
10281 cyttsp_set_params();
10282#endif
10283 if (!machine_is_msm8x60_sim())
10284 msm_fb_add_devices();
10285 fixup_i2c_configs();
10286 register_i2c_devices();
10287
Terence Hampson1c73fef2011-07-19 17:10:49 -040010288 if (machine_is_msm8x60_dragon())
10289 smsc911x_config.reset_gpio
10290 = GPIO_ETHERNET_RESET_N_DRAGON;
10291
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010292 platform_device_register(&smsc911x_device);
10293
10294#if (defined(CONFIG_SPI_QUP)) && \
10295 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010296 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10297 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010298
10299 if (machine_is_msm8x60_fluid()) {
10300#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10301 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10302 spi_register_board_info(lcdc_samsung_spi_board_info,
10303 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10304 } else
10305#endif
10306 {
10307#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10308 spi_register_board_info(lcdc_auo_spi_board_info,
10309 ARRAY_SIZE(lcdc_auo_spi_board_info));
10310#endif
10311 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010312#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10313 } else if (machine_is_msm8x60_dragon()) {
10314 spi_register_board_info(lcdc_nt35582_spi_board_info,
10315 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10316#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010317 }
10318#endif
10319
10320 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10321 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10322 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10323 msm_pm_data);
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -060010324 BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010325
10326#ifdef CONFIG_SENSORS_MSM_ADC
10327 if (machine_is_msm8x60_fluid()) {
10328 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10329 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10330 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10331 msm_adc_pdata.gpio_config = APROC_CONFIG;
10332 else
10333 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10334 }
10335 msm_adc_pdata.target_hw = MSM_8x60;
10336#endif
10337#ifdef CONFIG_MSM8X60_AUDIO
10338 msm_snddev_init();
10339#endif
10340#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10341 if (machine_is_msm8x60_fluid())
10342 platform_device_register(&fluid_leds_gpio);
10343 else
10344 platform_device_register(&gpio_leds);
10345#endif
10346
10347 /* configure pmic leds */
10348 if (machine_is_msm8x60_fluid()) {
10349 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10350 platform_data = &pm8058_fluid_flash_leds_data;
10351 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10352 = sizeof(pm8058_fluid_flash_leds_data);
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -040010353 } else if (machine_is_msm8x60_dragon()) {
10354 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10355 platform_data = &pm8058_dragon_leds_data;
10356 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10357 = sizeof(pm8058_dragon_leds_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010358 } else {
10359 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10360 platform_data = &pm8058_flash_leds_data;
10361 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10362 = sizeof(pm8058_flash_leds_data);
10363 }
10364
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010365 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10366 machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010367 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10368 platform_data = &pmic_vib_pdata;
10369 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10370 pdata_size = sizeof(pmic_vib_pdata);
10371 }
10372
10373 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010374
10375 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10376 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010377}
10378
10379static void __init msm8x60_rumi3_init(void)
10380{
10381 msm8x60_init(&msm8x60_rumi3_board_data);
10382}
10383
10384static void __init msm8x60_sim_init(void)
10385{
10386 msm8x60_init(&msm8x60_sim_board_data);
10387}
10388
10389static void __init msm8x60_surf_init(void)
10390{
10391 msm8x60_init(&msm8x60_surf_board_data);
10392}
10393
10394static void __init msm8x60_ffa_init(void)
10395{
10396 msm8x60_init(&msm8x60_ffa_board_data);
10397}
10398
10399static void __init msm8x60_fluid_init(void)
10400{
10401 msm8x60_init(&msm8x60_fluid_board_data);
10402}
10403
10404static void __init msm8x60_charm_surf_init(void)
10405{
10406 msm8x60_init(&msm8x60_charm_surf_board_data);
10407}
10408
10409static void __init msm8x60_charm_ffa_init(void)
10410{
10411 msm8x60_init(&msm8x60_charm_ffa_board_data);
10412}
10413
10414static void __init msm8x60_charm_init_early(void)
10415{
10416 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010417}
10418
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010419static void __init msm8x60_dragon_init(void)
10420{
10421 msm8x60_init(&msm8x60_dragon_board_data);
10422}
10423
Steve Mucklea55df6e2010-01-07 12:43:24 -080010424MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10425 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010426 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010427 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010428 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010429 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010430 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010431MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010432
10433MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10434 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010435 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010436 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010437 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010438 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010439 .init_early = msm8x60_charm_init_early,
10440MACHINE_END
10441
10442MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10443 .map_io = msm8x60_map_io,
10444 .reserve = msm8x60_reserve,
10445 .init_irq = msm8x60_init_irq,
10446 .init_machine = msm8x60_surf_init,
10447 .timer = &msm_timer,
10448 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010449MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010450
10451MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10452 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010453 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010454 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010455 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010456 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010457 .init_early = msm8x60_charm_init_early,
10458MACHINE_END
10459
10460MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10461 .map_io = msm8x60_map_io,
10462 .reserve = msm8x60_reserve,
10463 .init_irq = msm8x60_init_irq,
10464 .init_machine = msm8x60_fluid_init,
10465 .timer = &msm_timer,
10466 .init_early = msm8x60_charm_init_early,
10467MACHINE_END
10468
10469MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10470 .map_io = msm8x60_map_io,
10471 .reserve = msm8x60_reserve,
10472 .init_irq = msm8x60_init_irq,
10473 .init_machine = msm8x60_charm_surf_init,
10474 .timer = &msm_timer,
10475 .init_early = msm8x60_charm_init_early,
10476MACHINE_END
10477
10478MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10479 .map_io = msm8x60_map_io,
10480 .reserve = msm8x60_reserve,
10481 .init_irq = msm8x60_init_irq,
10482 .init_machine = msm8x60_charm_ffa_init,
10483 .timer = &msm_timer,
10484 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010485MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010486
10487MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10488 .map_io = msm8x60_map_io,
10489 .reserve = msm8x60_reserve,
10490 .init_irq = msm8x60_init_irq,
10491 .init_machine = msm8x60_dragon_init,
10492 .timer = &msm_timer,
10493 .init_early = msm8x60_charm_init_early,
10494MACHINE_END