blob: 06d214f62539a5195f6d33dfb6e8bf630d228c9c [file] [log] [blame]
Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __ASM__ARCH_CAMERA_H
15#define __ASM__ARCH_CAMERA_H
16
17#include <linux/list.h>
18#include <linux/poll.h>
19#include <linux/cdev.h>
20#include <linux/platform_device.h>
21#include <linux/wakelock.h>
Kevin Chaneb6b6072012-01-17 11:54:54 -080022#include <linux/regulator/consumer.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070023#include "linux/types.h"
24
25#include <mach/board.h>
26#include <media/msm_camera.h>
Ankit Premrajkac6864b82011-07-15 11:43:41 -070027#include <mach/msm_subsystem_map.h>
Ankit Premrajka748a70a2011-11-01 08:22:04 -070028#include <linux/ion.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029
30#define CONFIG_MSM_CAMERA_DEBUG
31#ifdef CONFIG_MSM_CAMERA_DEBUG
32#define CDBG(fmt, args...) pr_debug(fmt, ##args)
33#else
34#define CDBG(fmt, args...) do { } while (0)
35#endif
36
37#define PAD_TO_2K(a, b) ((!b) ? a : (((a)+2047) & ~2047))
38
39#define MSM_CAMERA_MSG 0
40#define MSM_CAMERA_EVT 1
41#define NUM_WB_EXP_NEUTRAL_REGION_LINES 4
42#define NUM_WB_EXP_STAT_OUTPUT_BUFFERS 3
43#define NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS 16
44#define NUM_STAT_OUTPUT_BUFFERS 3
45#define NUM_AF_STAT_OUTPUT_BUFFERS 3
Mingcheng Zhu996be182011-10-16 16:04:23 -070046#define max_control_command_size 512
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047#define CROP_LEN 36
48
49enum vfe_mode_of_operation{
50 VFE_MODE_OF_OPERATION_CONTINUOUS,
51 VFE_MODE_OF_OPERATION_SNAPSHOT,
52 VFE_MODE_OF_OPERATION_VIDEO,
53 VFE_MODE_OF_OPERATION_RAW_SNAPSHOT,
54 VFE_MODE_OF_OPERATION_ZSL,
55 VFE_LAST_MODE_OF_OPERATION_ENUM
56};
57
58enum msm_queue {
59 MSM_CAM_Q_CTRL, /* control command or control command status */
60 MSM_CAM_Q_VFE_EVT, /* adsp event */
61 MSM_CAM_Q_VFE_MSG, /* adsp message */
62 MSM_CAM_Q_V4L2_REQ, /* v4l2 request */
63 MSM_CAM_Q_VPE_MSG, /* vpe message */
64 MSM_CAM_Q_PP_MSG, /* pp message */
65};
66
67enum vfe_resp_msg {
68 VFE_EVENT,
69 VFE_MSG_GENERAL,
70 VFE_MSG_SNAPSHOT,
71 VFE_MSG_OUTPUT_P, /* preview (continuous mode ) */
72 VFE_MSG_OUTPUT_T, /* thumbnail (snapshot mode )*/
73 VFE_MSG_OUTPUT_S, /* main image (snapshot mode )*/
74 VFE_MSG_OUTPUT_V, /* video (continuous mode ) */
75 VFE_MSG_STATS_AEC,
76 VFE_MSG_STATS_AF,
77 VFE_MSG_STATS_AWB,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080078 VFE_MSG_STATS_RS, /* 10 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070079 VFE_MSG_STATS_CS,
80 VFE_MSG_STATS_IHIST,
81 VFE_MSG_STATS_SKIN,
82 VFE_MSG_STATS_WE, /* AEC + AWB */
83 VFE_MSG_SYNC_TIMER0,
84 VFE_MSG_SYNC_TIMER1,
85 VFE_MSG_SYNC_TIMER2,
86 VFE_MSG_COMMON,
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070087 VFE_MSG_V32_START,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080088 VFE_MSG_V32_START_RECORDING, /* 20 */
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070089 VFE_MSG_V32_CAPTURE,
90 VFE_MSG_OUTPUT_IRQ,
Suresh Vankadara055cb8e2012-01-18 00:50:04 +053091 VFE_MSG_V2X_PREVIEW,
92 VFE_MSG_V2X_CAPTURE,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080093 VFE_MSG_OUTPUT_PRIMARY,
94 VFE_MSG_OUTPUT_SECONDARY,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095};
96
97enum vpe_resp_msg {
98 VPE_MSG_GENERAL,
99 VPE_MSG_OUTPUT_V, /* video (continuous mode ) */
100 VPE_MSG_OUTPUT_ST_L,
101 VPE_MSG_OUTPUT_ST_R,
102};
103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104enum msm_stereo_state {
105 STEREO_VIDEO_IDLE,
106 STEREO_VIDEO_ACTIVE,
107 STEREO_SNAP_IDLE,
108 STEREO_SNAP_STARTED,
109 STEREO_SNAP_BUFFER1_PROCESSING,
110 STEREO_SNAP_BUFFER2_PROCESSING,
111 STEREO_RAW_SNAP_IDLE,
112 STEREO_RAW_SNAP_STARTED,
113};
114
115enum msm_ispif_intftype {
116 PIX0,
117 RDI0,
118 PIX1,
119 RDI1,
120 PIX2,
121 RDI2,
122};
123
124enum msm_ispif_vc {
125 VC0,
126 VC1,
127 VC2,
128 VC3,
129};
130
131enum msm_ispif_cid {
132 CID0,
133 CID1,
134 CID2,
135 CID3,
136 CID4,
137 CID5,
138 CID6,
139 CID7,
140 CID8,
141 CID9,
142 CID10,
143 CID11,
144 CID12,
145 CID13,
146 CID14,
147 CID15,
148};
149
150struct msm_ispif_params {
151 uint8_t intftype;
152 uint16_t cid_mask;
153 uint8_t csid;
154};
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700155
156struct msm_ispif_params_list {
157 uint32_t len;
158 struct msm_ispif_params params[3];
159};
160
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700161struct msm_vpe_phy_info {
162 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530163 uint32_t planar0_off;
164 uint32_t planar1_off;
165 uint32_t planar2_off;
166 uint32_t p0_phy;
167 uint32_t p1_phy;
168 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700169 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
170 uint32_t frame_id;
171};
172
173struct msm_camera_csid_vc_cfg {
174 uint8_t cid;
175 uint8_t dt;
176 uint8_t decode_format;
177};
178
179struct msm_camera_csid_lut_params {
180 uint8_t num_cid;
181 struct msm_camera_csid_vc_cfg *vc_cfg;
182};
183
184struct msm_camera_csid_params {
185 uint8_t lane_cnt;
186 uint8_t lane_assign;
187 struct msm_camera_csid_lut_params lut_params;
188};
189
190struct msm_camera_csiphy_params {
191 uint8_t lane_cnt;
192 uint8_t settle_cnt;
193};
194
Kevin Chana980f392011-08-01 20:55:00 -0700195struct msm_camera_csi2_params {
196 struct msm_camera_csid_params csid_params;
197 struct msm_camera_csiphy_params csiphy_params;
198};
199
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700200#define VFE31_OUTPUT_MODE_PT (0x1 << 0)
201#define VFE31_OUTPUT_MODE_S (0x1 << 1)
202#define VFE31_OUTPUT_MODE_V (0x1 << 2)
203#define VFE31_OUTPUT_MODE_P (0x1 << 3)
204#define VFE31_OUTPUT_MODE_T (0x1 << 4)
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530205#define VFE31_OUTPUT_MODE_P_ALL_CHNLS (0x1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700206
207#define CSI_EMBED_DATA 0x12
Rajakumar Govindaram6bc004a2011-12-05 20:58:19 -0800208#define CSI_YUV422_8 0x1E
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700209#define CSI_RAW8 0x2A
210#define CSI_RAW10 0x2B
211#define CSI_RAW12 0x2C
212
213#define CSI_DECODE_6BIT 0
214#define CSI_DECODE_8BIT 1
215#define CSI_DECODE_10BIT 2
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -0800216#define CSI_DECODE_DPCM_10_8_10 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700217
218struct msm_vfe_phy_info {
219 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530220 uint32_t planar0_off;
221 uint32_t planar1_off;
222 uint32_t planar2_off;
223 uint32_t p0_phy;
224 uint32_t p1_phy;
225 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700226 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
227 uint32_t frame_id;
228};
229
230struct msm_vfe_stats_msg {
Lakshmi Narayana Kalavala4ab97a92011-07-26 15:30:14 -0700231 uint8_t awb_ymin;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232 uint32_t aec_buff;
233 uint32_t awb_buff;
234 uint32_t af_buff;
235 uint32_t ihist_buff;
236 uint32_t rs_buff;
237 uint32_t cs_buff;
238 uint32_t skin_buff;
239 uint32_t status_bits;
240 uint32_t frame_id;
241};
242
243struct video_crop_t{
244 uint32_t in1_w;
245 uint32_t out1_w;
246 uint32_t in1_h;
247 uint32_t out1_h;
248 uint32_t in2_w;
249 uint32_t out2_w;
250 uint32_t in2_h;
251 uint32_t out2_h;
252 uint8_t update_flag;
253};
254
255struct msm_vpe_buf_info {
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530256 uint32_t p0_phy;
257 uint32_t p1_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700258 struct timespec ts;
259 uint32_t frame_id;
260 struct video_crop_t vpe_crop;
261};
262
263struct msm_vfe_resp {
264 enum vfe_resp_msg type;
265 struct msm_cam_evt_msg evt_msg;
266 struct msm_vfe_phy_info phy;
267 struct msm_vfe_stats_msg stats_msg;
268 struct msm_vpe_buf_info vpe_bf;
269 void *extdata;
270 int32_t extlen;
271};
272
273struct msm_vpe_resp {
274 enum vpe_resp_msg type;
275 struct msm_cam_evt_msg evt_msg;
276 struct msm_vpe_phy_info phy;
277 void *extdata;
278 int32_t extlen;
279};
280
281struct msm_vpe_callback {
282 void (*vpe_resp)(struct msm_vpe_resp *,
283 enum msm_queue, void *syncdata,
284 void *time_stamp, gfp_t gfp);
285 void* (*vpe_alloc)(int, void *syncdata, gfp_t gfp);
286 void (*vpe_free)(void *ptr);
287};
288
289struct msm_vfe_callback {
290 void (*vfe_resp)(struct msm_vfe_resp *,
291 enum msm_queue, void *syncdata,
292 gfp_t gfp);
293 void* (*vfe_alloc)(int, void *syncdata, gfp_t gfp);
294 void (*vfe_free)(void *ptr);
295};
296
297struct msm_camvfe_fn {
298 int (*vfe_init)(struct msm_vfe_callback *,
299 struct platform_device *);
300 int (*vfe_enable)(struct camera_enable_cmd *);
301 int (*vfe_config)(struct msm_vfe_cfg_cmd *, void *);
302 int (*vfe_disable)(struct camera_enable_cmd *,
303 struct platform_device *dev);
304 void (*vfe_release)(struct platform_device *);
305 void (*vfe_stop)(void);
306};
307
308struct msm_camvfe_params {
309 struct msm_vfe_cfg_cmd *vfe_cfg;
310 void *data;
311};
312
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700313struct msm_mctl_pp_params {
314 struct msm_mctl_pp_cmd *cmd;
315 void *data;
316};
317
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700318struct msm_camvpe_fn {
319 int (*vpe_reg)(struct msm_vpe_callback *);
320 int (*vpe_cfg_update) (void *);
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530321 void (*send_frame_to_vpe) (uint32_t planar0_off, uint32_t planar1_off,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700322 struct timespec *ts, int output_id);
323 int (*vpe_config)(struct msm_vpe_cfg_cmd *, void *);
324 void (*vpe_cfg_offset)(int frame_pack, uint32_t pyaddr,
325 uint32_t pcbcraddr, struct timespec *ts, int output_id,
326 struct msm_st_half st_half, int frameid);
327 int *dis;
328};
329
330struct msm_sensor_ctrl {
331 int (*s_init)(const struct msm_camera_sensor_info *);
332 int (*s_release)(void);
333 int (*s_config)(void __user *);
334 enum msm_camera_type s_camera_type;
335 uint32_t s_mount_angle;
336 enum msm_st_frame_packing s_video_packing;
337 enum msm_st_frame_packing s_snap_packing;
338};
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700339
340struct msm_actuator_ctrl {
341 int (*a_init_table)(void);
Rajakumar Govindaramdf6af9c2011-12-01 21:26:20 -0800342 int (*a_power_up)(void *);
343 int (*a_power_down)(void *);
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700344 int (*a_create_subdevice)(void *, void *);
345 int (*a_config)(void __user *);
346};
347
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700348struct msm_strobe_flash_ctrl {
349 int (*strobe_flash_init)
350 (struct msm_camera_sensor_strobe_flash_data *);
351 int (*strobe_flash_release)
352 (struct msm_camera_sensor_strobe_flash_data *, int32_t);
353 int (*strobe_flash_charge)(int32_t, int32_t, uint32_t);
354};
355
356/* this structure is used in kernel */
357struct msm_queue_cmd {
358 struct list_head list_config;
359 struct list_head list_control;
360 struct list_head list_frame;
361 struct list_head list_pict;
362 struct list_head list_vpe_frame;
363 enum msm_queue type;
364 void *command;
365 atomic_t on_heap;
366 struct timespec ts;
367 uint32_t error_code;
368};
369
370struct msm_device_queue {
371 struct list_head list;
372 spinlock_t lock;
373 wait_queue_head_t wait;
374 int max;
375 int len;
376 const char *name;
377};
378
379struct msm_sync {
380 /* These two queues are accessed from a process context only
381 * They contain pmem descriptors for the preview frames and the stats
382 * coming from the camera sensor.
383 */
384 struct hlist_head pmem_frames;
385 struct hlist_head pmem_stats;
386
387 /* The message queue is used by the control thread to send commands
388 * to the config thread, and also by the DSP to send messages to the
389 * config thread. Thus it is the only queue that is accessed from
390 * both interrupt and process context.
391 */
392 struct msm_device_queue event_q;
393
394 /* This queue contains preview frames. It is accessed by the DSP (in
395 * in interrupt context, and by the frame thread.
396 */
397 struct msm_device_queue frame_q;
398 int unblock_poll_frame;
399 int unblock_poll_pic_frame;
400
401 /* This queue contains snapshot frames. It is accessed by the DSP (in
402 * interrupt context, and by the control thread.
403 */
404 struct msm_device_queue pict_q;
405 int get_pic_abort;
406 struct msm_device_queue vpe_q;
407
408 struct msm_camera_sensor_info *sdata;
409 struct msm_camvfe_fn vfefn;
410 struct msm_camvpe_fn vpefn;
411 struct msm_sensor_ctrl sctrl;
412 struct msm_strobe_flash_ctrl sfctrl;
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700413 struct msm_actuator_ctrl actctrl;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700414 struct wake_lock wake_lock;
415 struct platform_device *pdev;
416 int16_t ignore_qcmd_type;
417 uint8_t ignore_qcmd;
418 uint8_t opencnt;
419 void *cropinfo;
420 int croplen;
421 int core_powered_on;
422
423 struct fd_roi_info fdroiinfo;
424
425 atomic_t vpe_enable;
426 uint32_t pp_mask;
427 uint8_t pp_frame_avail;
428 struct msm_queue_cmd *pp_prev;
429 struct msm_queue_cmd *pp_snap;
430 struct msm_queue_cmd *pp_thumb;
431 int video_fd;
432
433 const char *apps_id;
434
435 struct mutex lock;
436 struct list_head list;
437 uint8_t liveshot_enabled;
438 struct msm_cam_v4l2_device *pcam_sync;
439
440 uint8_t stereocam_enabled;
441 struct msm_queue_cmd *pp_stereocam;
442 struct msm_queue_cmd *pp_stereocam2;
443 struct msm_queue_cmd *pp_stereosnap;
444 enum msm_stereo_state stereo_state;
445 int stcam_quality_ind;
446 uint32_t stcam_conv_value;
447
448 spinlock_t pmem_frame_spinlock;
449 spinlock_t pmem_stats_spinlock;
450 spinlock_t abort_pict_lock;
451 int snap_count;
452 int thumb_count;
453};
454
455#define MSM_APPS_ID_V4L2 "msm_v4l2"
456#define MSM_APPS_ID_PROP "msm_qct"
457
458struct msm_cam_device {
459 struct msm_sync *sync; /* most-frequently accessed */
460 struct device *device;
461 struct cdev cdev;
462 /* opened is meaningful only for the config and frame nodes,
463 * which may be opened only once.
464 */
465 atomic_t opened;
466};
467
468struct msm_control_device {
469 struct msm_cam_device *pmsm;
470
471 /* Used for MSM_CAM_IOCTL_CTRL_CMD_DONE responses */
472 uint8_t ctrl_data[max_control_command_size];
473 struct msm_ctrl_cmd ctrl;
474 struct msm_queue_cmd qcmd;
475
476 /* This queue used by the config thread to send responses back to the
477 * control thread. It is accessed only from a process context.
478 */
479 struct msm_device_queue ctrl_q;
480};
481
482struct register_address_value_pair {
483 uint16_t register_address;
484 uint16_t register_value;
485};
486
487struct msm_pmem_region {
488 struct hlist_node list;
489 unsigned long paddr;
490 unsigned long len;
491 struct file *file;
492 struct msm_pmem_info info;
Ankit Premrajkac6864b82011-07-15 11:43:41 -0700493 struct msm_mapped_buffer *msm_buffer;
494 int subsys_id;
Ankit Premrajka748a70a2011-11-01 08:22:04 -0700495 struct ion_handle *handle;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700496};
497
498struct axidata {
499 uint32_t bufnum1;
500 uint32_t bufnum2;
501 uint32_t bufnum3;
502 struct msm_pmem_region *region;
503};
504
505#ifdef CONFIG_MSM_CAMERA_FLASH
506int msm_camera_flash_set_led_state(
507 struct msm_camera_sensor_flash_data *fdata,
508 unsigned led_state);
509int msm_strobe_flash_init(struct msm_sync *sync, uint32_t sftype);
510int msm_flash_ctrl(struct msm_camera_sensor_info *sdata,
511 struct flash_ctrl_data *flash_info);
512#else
513static inline int msm_camera_flash_set_led_state(
514 struct msm_camera_sensor_flash_data *fdata,
515 unsigned led_state)
516{
517 return -ENOTSUPP;
518}
519static inline int msm_strobe_flash_init(
520 struct msm_sync *sync, uint32_t sftype)
521{
522 return -ENOTSUPP;
523}
524static inline int msm_flash_ctrl(
525 struct msm_camera_sensor_info *sdata,
526 struct flash_ctrl_data *flash_info)
527{
528 return -ENOTSUPP;
529}
530#endif
531
532
533
534void msm_camvfe_init(void);
535int msm_camvfe_check(void *);
536void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *);
537void msm_camvpe_fn_init(struct msm_camvpe_fn *, void *);
538int msm_camera_drv_start(struct platform_device *dev,
539 int (*sensor_probe)(const struct msm_camera_sensor_info *,
540 struct msm_sensor_ctrl *));
541
542enum msm_camio_clk_type {
543 CAMIO_VFE_MDC_CLK,
544 CAMIO_MDC_CLK,
545 CAMIO_VFE_CLK,
546 CAMIO_VFE_AXI_CLK,
547
548 CAMIO_VFE_CAMIF_CLK,
549 CAMIO_VFE_PBDG_CLK,
550 CAMIO_CAM_MCLK_CLK,
551 CAMIO_CAMIF_PAD_PBDG_CLK,
552
553 CAMIO_CSI0_VFE_CLK,
554 CAMIO_CSI1_VFE_CLK,
555 CAMIO_VFE_PCLK,
556
557 CAMIO_CSI_SRC_CLK,
558 CAMIO_CSI0_CLK,
559 CAMIO_CSI1_CLK,
560 CAMIO_CSI0_PCLK,
561 CAMIO_CSI1_PCLK,
562
563 CAMIO_CSI1_SRC_CLK,
564 CAMIO_CSI_PIX_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700565 CAMIO_CSI_PIX1_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700566 CAMIO_CSI_RDI_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700567 CAMIO_CSI_RDI1_CLK,
568 CAMIO_CSI_RDI2_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700569 CAMIO_CSIPHY0_TIMER_CLK,
570 CAMIO_CSIPHY1_TIMER_CLK,
571
572 CAMIO_JPEG_CLK,
573 CAMIO_JPEG_PCLK,
574 CAMIO_VPE_CLK,
575 CAMIO_VPE_PCLK,
576
577 CAMIO_CSI0_PHY_CLK,
578 CAMIO_CSI1_PHY_CLK,
579 CAMIO_CSIPHY_TIMER_SRC_CLK,
580
581 CAMIO_MAX_CLK
582};
583
584enum msm_camio_clk_src_type {
585 MSM_CAMIO_CLK_SRC_INTERNAL,
586 MSM_CAMIO_CLK_SRC_EXTERNAL,
587 MSM_CAMIO_CLK_SRC_MAX
588};
589
590enum msm_s_test_mode {
591 S_TEST_OFF,
592 S_TEST_1,
593 S_TEST_2,
594 S_TEST_3
595};
596
597enum msm_s_resolution {
598 S_QTR_SIZE,
599 S_FULL_SIZE,
600 S_INVALID_SIZE
601};
602
603enum msm_s_reg_update {
604 /* Sensor egisters that need to be updated during initialization */
605 S_REG_INIT,
606 /* Sensor egisters that needs periodic I2C writes */
607 S_UPDATE_PERIODIC,
608 /* All the sensor Registers will be updated */
609 S_UPDATE_ALL,
610 /* Not valid update */
611 S_UPDATE_INVALID
612};
613
614enum msm_s_setting {
615 S_RES_PREVIEW,
616 S_RES_CAPTURE
617};
618
619enum msm_bus_perf_setting {
620 S_INIT,
621 S_PREVIEW,
622 S_VIDEO,
623 S_CAPTURE,
624 S_ZSL,
625 S_STEREO_VIDEO,
626 S_STEREO_CAPTURE,
627 S_DEFAULT,
628 S_EXIT
629};
630
Nishant Pandit24153d82011-08-27 16:05:13 +0530631enum msm_cam_mode {
632 MODE_R,
633 MODE_L,
634 MODE_DUAL
635};
636
Kevin Chan85af4552011-10-25 15:07:58 -0700637struct msm_cam_clk_info {
638 const char *clk_name;
639 long clk_rate;
640};
641
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700642int msm_camio_enable(struct platform_device *dev);
643int msm_camio_jpeg_clk_enable(void);
644int msm_camio_jpeg_clk_disable(void);
645int msm_camio_vpe_clk_enable(uint32_t);
646int msm_camio_vpe_clk_disable(void);
647
Nishant Pandit24153d82011-08-27 16:05:13 +0530648void msm_camio_mode_config(enum msm_cam_mode mode);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700649int msm_camio_clk_enable(enum msm_camio_clk_type clk);
650int msm_camio_clk_disable(enum msm_camio_clk_type clk);
651int msm_camio_clk_config(uint32_t freq);
652void msm_camio_clk_rate_set(int rate);
Shuzhen Wange49436a2011-09-28 16:07:27 -0700653int msm_camio_vfe_clk_rate_set(int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700654void msm_camio_clk_rate_set_2(struct clk *clk, int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700655void msm_camio_clk_axi_rate_set(int rate);
656void msm_disable_io_gpio_clk(struct platform_device *);
657
658void msm_camio_camif_pad_reg_reset(void);
659void msm_camio_camif_pad_reg_reset_2(void);
660
661void msm_camio_vfe_blk_reset(void);
662
Nishant Pandit24153d82011-08-27 16:05:13 +0530663int32_t msm_camio_3d_enable(const struct msm_camera_sensor_info *sinfo);
664void msm_camio_3d_disable(void);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700665void msm_camio_clk_sel(enum msm_camio_clk_src_type);
666void msm_camio_disable(struct platform_device *);
667int msm_camio_probe_on(struct platform_device *);
668int msm_camio_probe_off(struct platform_device *);
669int msm_camio_sensor_clk_off(struct platform_device *);
670int msm_camio_sensor_clk_on(struct platform_device *);
671int msm_camio_csi_config(struct msm_camera_csi_params *csi_params);
672int msm_camio_csiphy_config(struct msm_camera_csiphy_params *csiphy_params);
673int msm_camio_csid_config(struct msm_camera_csid_params *csid_params);
674void msm_io_read_interrupt(void);
675int add_axi_qos(void);
676int update_axi_qos(uint32_t freq);
677void release_axi_qos(void);
678void msm_io_w(u32 data, void __iomem *addr);
679void msm_io_w_mb(u32 data, void __iomem *addr);
680u32 msm_io_r(void __iomem *addr);
681u32 msm_io_r_mb(void __iomem *addr);
682void msm_io_dump(void __iomem *addr, int size);
683void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len);
684void msm_camio_set_perf_lvl(enum msm_bus_perf_setting);
Kevin Chan09f4e662011-12-16 08:17:02 -0800685void msm_camio_bus_scale_cfg(
686 struct msm_bus_scale_pdata *, enum msm_bus_perf_setting);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700687
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700688void *msm_isp_sync_alloc(int size, gfp_t gfp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700689
690void msm_isp_sync_free(void *ptr);
Kevin Chan85af4552011-10-25 15:07:58 -0700691
692int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
693 struct clk **clk_ptr, int num_clk, int enable);
Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -0800694int msm_cam_core_reset(void);
Kevin Chaneb6b6072012-01-17 11:54:54 -0800695
696int msm_camera_config_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
697 int num_vreg, struct regulator **reg_ptr, int config);
698int msm_camera_enable_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
699 int num_vreg, struct regulator **reg_ptr, int enable);
700
701int msm_camera_config_gpio_table
702 (struct msm_camera_sensor_info *sinfo, int gpio_en);
703int msm_camera_request_gpio_table
704 (struct msm_camera_sensor_info *sinfo, int gpio_en);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700705#endif