Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 13 | /include/ "skeleton.dtsi" |
Mitchel Humpherys | b3f40d1 | 2012-10-05 16:26:58 -0700 | [diff] [blame] | 14 | /include/ "msm9625-ion.dtsi" |
Girish Mahadevan | fc5f5c3 | 2012-10-23 16:27:28 -0700 | [diff] [blame] | 15 | /include/ "msm9625-pm.dtsi" |
Pushkar Joshi | faf92a7 | 2012-10-29 17:45:27 -0700 | [diff] [blame] | 16 | /include/ "msm9625-coresight.dtsi" |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Qualcomm MSM 9625"; |
| 20 | compatible = "qcom,msm9625"; |
| 21 | interrupt-parent = <&intc>; |
| 22 | |
| 23 | intc: interrupt-controller@F9000000 { |
| 24 | compatible = "qcom,msm-qgic2"; |
| 25 | interrupt-controller; |
| 26 | #interrupt-cells = <3>; |
| 27 | reg = <0xF9000000 0x1000>, |
| 28 | <0xF9002000 0x1000>; |
| 29 | }; |
| 30 | |
Abhimanyu Kapur | 490d20c | 2012-06-22 17:34:20 -0700 | [diff] [blame] | 31 | l2: cache-controller@f9040000 { |
| 32 | compatible = "arm,pl310-cache"; |
| 33 | reg = <0xf9040000 0x1000>; |
Abhimanyu Kapur | 490d20c | 2012-06-22 17:34:20 -0700 | [diff] [blame] | 34 | cache-unified; |
| 35 | cache-level = <2>; |
| 36 | }; |
| 37 | |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 38 | msmgpio: gpio@fd510000 { |
| 39 | compatible = "qcom,msm-gpio"; |
Rohit Vaswani | b1cc493 | 2012-07-23 21:30:11 -0700 | [diff] [blame] | 40 | gpio-controller; |
| 41 | #gpio-cells = <2>; |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 42 | interrupt-controller; |
| 43 | #interrupt-cells = <2>; |
| 44 | reg = <0xfd510000 0x4000>; |
Rohit Vaswani | d200152 | 2012-12-05 19:23:44 -0800 | [diff] [blame] | 45 | interrupts = <0 208 0>; |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 46 | }; |
| 47 | |
Rohit Vaswani | a512956 | 2012-06-12 20:11:23 -0700 | [diff] [blame] | 48 | timer: msm-qtimer@f9021000 { |
Syed Rameez Mustafa | 0824d6c | 2012-11-29 18:53:56 -0800 | [diff] [blame] | 49 | compatible = "arm,armv7-timer"; |
Rohit Vaswani | a512956 | 2012-06-12 20:11:23 -0700 | [diff] [blame] | 50 | reg = <0xF9021000 0x1000>; |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 51 | interrupts = <0 7 0>; |
Rohit Vaswani | a512956 | 2012-06-12 20:11:23 -0700 | [diff] [blame] | 52 | irq-is-not-percpu; |
Abhimanyu Kapur | af4c4d5 | 2012-10-01 14:15:10 -0700 | [diff] [blame] | 53 | clock-frequency = <19200000>; |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 54 | }; |
Jin Hong | 8d32858 | 2012-05-01 15:45:29 -0700 | [diff] [blame] | 55 | |
Yan He | 3cb97ba | 2012-05-13 16:45:24 -0700 | [diff] [blame] | 56 | qcom,sps@f9980000 { |
| 57 | compatible = "qcom,msm_sps"; |
| 58 | reg = <0xf9984000 0x15000>, |
| 59 | <0xf9999000 0xb000>, |
Yan He | 6f9ae71 | 2012-09-20 12:55:47 -0700 | [diff] [blame] | 60 | <0xfe803000 0x4800>; |
Yan He | 3cb97ba | 2012-05-13 16:45:24 -0700 | [diff] [blame] | 61 | interrupts = <0 94 0>; |
| 62 | qcom,device-type = <2>; |
| 63 | }; |
| 64 | |
Jin Hong | 8d32858 | 2012-05-01 15:45:29 -0700 | [diff] [blame] | 65 | serial@f991f000 { |
| 66 | compatible = "qcom,msm-lsuart-v14"; |
| 67 | reg = <0xf991f000 0x1000>; |
| 68 | interrupts = <0 109 0>; |
| 69 | }; |
Sahitya Tummala | 9ba4b28 | 2012-06-19 11:41:51 +0530 | [diff] [blame] | 70 | |
Jack Pham | a01e9c1 | 2012-09-25 21:37:03 -0700 | [diff] [blame] | 71 | usb@f9a55000 { |
| 72 | compatible = "qcom,hsusb-otg"; |
| 73 | reg = <0xf9a55000 0x400>; |
| 74 | interrupts = <0 134 0 0 140 0>; |
| 75 | interrupt-names = "core_irq", "async_irq"; |
| 76 | HSUSB_VDDCX-supply = <&pm8019_l12>; |
| 77 | HSUSB_1p8-supply = <&pm8019_l2>; |
| 78 | HSUSB_3p3-supply = <&pm8019_l4>; |
David Collins | 84d39b2 | 2012-11-01 14:40:08 -0700 | [diff] [blame] | 79 | vbus_otg-supply = <&usb_vbus>; |
Jack Pham | a01e9c1 | 2012-09-25 21:37:03 -0700 | [diff] [blame] | 80 | |
| 81 | qcom,hsusb-otg-phy-type = <2>; |
| 82 | qcom,hsusb-otg-mode = <1>; |
| 83 | qcom,hsusb-otg-otg-control = <1>; |
| 84 | qcom,hsusb-otg-disable-reset; |
| 85 | }; |
| 86 | |
| 87 | android_usb@fc42b0c8 { |
| 88 | compatible = "qcom,android-usb"; |
| 89 | reg = <0xfc42b0c8 0xc8>; |
| 90 | }; |
| 91 | |
Ofir Cohen | b1d5261 | 2012-11-14 09:37:38 +0200 | [diff] [blame] | 92 | hsic@f9a15000 { |
| 93 | compatible = "qcom,hsic-host"; |
| 94 | reg = <0xf9a15000 0x400>; |
| 95 | interrupts = <0 136 0>; |
| 96 | interrupt-names = "core_irq"; |
| 97 | HSIC_VDDCX-supply = <&pm8019_l12>; |
| 98 | HSIC_GDSC-supply = <&gdsc_usb_hsic>; |
| 99 | }; |
| 100 | |
Jack Pham | d61ff56 | 2012-11-21 19:25:53 +0200 | [diff] [blame] | 101 | qcom,usbbam@f9a44000 { |
| 102 | compatible = "qcom,usb-bam-msm"; |
| 103 | reg = <0xf9a44000 0x11000>; |
| 104 | reg-names = "hsusb"; |
| 105 | interrupts = <0 135 0>; |
| 106 | interrupt-names = "hsusb"; |
| 107 | qcom,usb-active-bam = <1>; |
| 108 | qcom,usb-total-bam-num = <3>; |
| 109 | qcom,usb-bam-num-pipes = <16>; |
| 110 | qcom,ignore-core-reset-ack; |
| 111 | |
| 112 | qcom,pipe0 { |
| 113 | label = "usb-to-ipa"; |
| 114 | qcom,usb-bam-type = <1>; |
| 115 | qcom,usb-bam-mem-type = <2>; |
| 116 | qcom,src-bam-physical-address = <0xf9a44000>; |
| 117 | qcom,src-bam-pipe-index = <1>; |
| 118 | qcom,data-fifo-size = <0x600>; |
| 119 | qcom,descriptor-fifo-size = <0x300>; |
| 120 | }; |
| 121 | |
| 122 | qcom,pipe1 { |
| 123 | label = "ipa-to-usb"; |
| 124 | qcom,usb-bam-type = <1>; |
| 125 | qcom,usb-bam-mem-type = <2>; |
| 126 | qcom,dst-bam-physical-address = <0xf9a44000>; |
| 127 | qcom,dst-bam-pipe-index = <0>; |
| 128 | qcom,data-fifo-size = <0x600>; |
| 129 | qcom,descriptor-fifo-size = <0x100>; |
| 130 | }; |
| 131 | }; |
| 132 | |
Sahitya Tummala | 9ba4b28 | 2012-06-19 11:41:51 +0530 | [diff] [blame] | 133 | qcom,nand@f9ac0000 { |
| 134 | compatible = "qcom,msm-nand"; |
| 135 | reg = <0xf9ac0000 0x1000>, |
| 136 | <0xf9ac4000 0x8000>; |
| 137 | reg-names = "nand_phys", |
| 138 | "bam_phys"; |
| 139 | interrupts = <0 247 0>; |
| 140 | interrupt-names = "bam_irq"; |
| 141 | }; |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 142 | |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 143 | spi@f9924000 { |
| 144 | cell-index = <0>; |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 145 | compatible = "qcom,spi-qup-v2"; |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 146 | reg = <0xf9924000 0x1000>; |
| 147 | interrupts = <0 96 0>; |
| 148 | spi-max-frequency = <25000000>; |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 149 | #address-cells = <1>; |
| 150 | #size-cells = <0>; |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 151 | gpios = <&msmgpio 7 0>, /* CLK */ |
| 152 | <&msmgpio 5 0>, /* MISO */ |
| 153 | <&msmgpio 4 0>; /* MOSI */ |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 154 | |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 155 | cs-gpios = <&msmgpio 6 0>; |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 156 | |
| 157 | ethernet-switch@0 { |
| 158 | compatible = "simtec,ks8851"; |
| 159 | reg = <0>; |
| 160 | interrupt-parent = <&msmgpio>; |
| 161 | interrupts = <75 0>; |
Gilad Avidov | 09c78ec | 2012-10-18 09:34:35 -0600 | [diff] [blame] | 162 | spi-max-frequency = <4800000>; |
Rohit Vaswani | 0045df4 | 2012-06-29 16:21:48 -0700 | [diff] [blame] | 163 | }; |
| 164 | }; |
Hanumant Singh | 6c4bf06 | 2012-09-06 15:51:10 -0700 | [diff] [blame] | 165 | |
| 166 | qcom,wdt@f9017000 { |
| 167 | compatible = "qcom,msm-watchdog"; |
| 168 | reg = <0xf9017000 0x1000>; |
| 169 | interrupts = <1 2 0>, <1 1 0>; |
| 170 | qcom,bark-time = <11000>; |
| 171 | qcom,pet-time = <10000>; |
| 172 | qcom,ipi-ping = <0>; |
| 173 | }; |
Kenneth Heitke | c264240 | 2012-09-18 18:56:47 -0600 | [diff] [blame] | 174 | |
Girish Mahadevan | c65a711 | 2012-09-19 11:15:56 -0600 | [diff] [blame] | 175 | rpm_bus: qcom,rpm-smd { |
| 176 | compatible = "qcom,rpm-smd"; |
| 177 | rpm-channel-name = "rpm_requests"; |
| 178 | rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| 179 | }; |
| 180 | |
Kenneth Heitke | c264240 | 2012-09-18 18:56:47 -0600 | [diff] [blame] | 181 | spmi_bus: qcom,spmi@fc4c0000 { |
| 182 | cell-index = <0>; |
| 183 | compatible = "qcom,spmi-pmic-arb"; |
| 184 | reg = <0xfc4cf000 0x1000>, |
| 185 | <0Xfc4cb000 0x1000>; |
| 186 | /* 190,ee0_krait_hlos_spmi_periph_irq */ |
| 187 | /* 187,channel_0_krait_hlos_trans_done_irq */ |
| 188 | interrupts = <0 190 0 0 187 0>; |
| 189 | qcom,pmic-arb-ee = <0>; |
| 190 | qcom,pmic-arb-channel = <0>; |
| 191 | qcom,pmic-arb-ppid-map = <0x02400000>, /* TEMP_ALARM */ |
| 192 | <0x03100001>, /* VADC1_USR */ |
| 193 | <0x06100002>, /* RTC_ALARM */ |
| 194 | <0x06200003>, /* RTC_TIMER */ |
| 195 | <0x0a000004>, /* MPP1 */ |
| 196 | <0x0a100005>, /* MPP2 */ |
| 197 | <0x0a200006>, /* MPP3 */ |
| 198 | <0x0a300007>, /* MPP4 */ |
| 199 | <0x0a400008>, /* MPP5 */ |
| 200 | <0x0a500009>, /* MPP6 */ |
| 201 | <0x0c20000a>, /* GPIO3 */ |
| 202 | <0x0c30000b>, /* GPIO4 */ |
| 203 | <0x0c50000c>, /* GPIO6 */ |
| 204 | <0x0080000d>; /* PON */ |
| 205 | }; |
Kenneth Heitke | f92a8c7 | 2012-10-10 17:15:05 -0600 | [diff] [blame] | 206 | |
| 207 | i2c@f9925000 { |
| 208 | cell-index = <3>; |
| 209 | compatible = "qcom,i2c-qup"; |
| 210 | reg = <0xf9925000 0x1000>; |
| 211 | #address-cells = <1>; |
| 212 | #size-cells = <0>; |
| 213 | reg-names = "qup_phys_addr"; |
| 214 | interrupts = <0 97 0>; |
| 215 | interrupt-names = "qup_err_intr"; |
| 216 | qcom,i2c-bus-freq = <100000>; |
| 217 | qcom,i2c-src-freq = <24000000>; |
| 218 | }; |
Oluwafemi Adeyemi | bbbcc6e | 2012-09-14 17:24:26 -0700 | [diff] [blame] | 219 | |
| 220 | sdcc2: qcom,sdcc@f98a4000 { |
| 221 | cell-index = <2>; /* SDC2 SD card slot */ |
| 222 | compatible = "qcom,msm-sdcc"; |
| 223 | reg = <0xf98a4000 0x800>, |
| 224 | <0xf98a4800 0x100>, |
| 225 | <0xf9884000 0x7000>; |
| 226 | reg-names = "core_mem", "dml_mem", "bam_mem"; |
| 227 | |
| 228 | vdd-supply = <&ext_2p95v>; |
| 229 | |
| 230 | vdd-io-supply = <&pm8019_l13>; |
Oluwafemi Adeyemi | 6cdfdb8 | 2012-11-02 13:36:29 -0700 | [diff] [blame] | 231 | qcom,vdd-io-always-on; |
| 232 | qcom,vdd-io-lpm-sup; |
| 233 | qcom,vdd-io-voltage-level = <1800000 2950000>; |
| 234 | qcom,vdd-io-current-level = <6 22000>; |
Oluwafemi Adeyemi | bbbcc6e | 2012-09-14 17:24:26 -0700 | [diff] [blame] | 235 | |
Oluwafemi Adeyemi | 6cdfdb8 | 2012-11-02 13:36:29 -0700 | [diff] [blame] | 236 | qcom,pad-pull-on = <0x0 0x3 0x3>; |
| 237 | qcom,pad-pull-off = <0x0 0x3 0x3>; |
| 238 | qcom,pad-drv-on = <0x7 0x4 0x4>; |
| 239 | qcom,pad-drv-off = <0x0 0x0 0x0>; |
Oluwafemi Adeyemi | bbbcc6e | 2012-09-14 17:24:26 -0700 | [diff] [blame] | 240 | |
Oluwafemi Adeyemi | 6cdfdb8 | 2012-11-02 13:36:29 -0700 | [diff] [blame] | 241 | qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| 242 | qcom,sup-voltages = <2950 2950>; |
| 243 | qcom,bus-width = <4>; |
| 244 | qcom,xpc; |
| 245 | qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; |
| 246 | qcom,current-limit = <800>; |
Oluwafemi Adeyemi | bbbcc6e | 2012-09-14 17:24:26 -0700 | [diff] [blame] | 247 | |
| 248 | interrupt-parent = <&sdcc2>; |
| 249 | #address-cells = <0>; |
| 250 | interrupts = <0 1 2>; |
| 251 | #interrupt-cells = <1>; |
| 252 | interrupt-map-mask = <0xffffffff>; |
| 253 | interrupt-map = <0 &intc 0 125 0 |
| 254 | 1 &intc 0 220 0 |
| 255 | 2 &msmgpio 66 0x3>; |
| 256 | interrupt-names = "core_irq", "bam_irq", "status_irq"; |
| 257 | cd-gpios = <&msmgpio 66 0>; |
| 258 | }; |
Oluwafemi Adeyemi | 4926a9e | 2012-09-14 17:39:59 -0700 | [diff] [blame] | 259 | |
| 260 | sdcc3: qcom,sdcc@f9864000 { |
| 261 | cell-index = <3>; /* SDC3 SDIO slot */ |
| 262 | compatible = "qcom,msm-sdcc"; |
| 263 | reg = <0xf9864000 0x800>, |
| 264 | <0xf9864800 0x100>, |
| 265 | <0xf9844000 0x7000>; |
| 266 | reg-names = "core_mem", "dml_mem", "bam_mem"; |
| 267 | interrupts = <0 127 0>, <0 223 0>; |
| 268 | interrupt-names = "core_irq", "bam_irq"; |
| 269 | |
| 270 | gpios = <&msmgpio 25 0>, |
| 271 | <&msmgpio 24 0>, |
| 272 | <&msmgpio 16 0>, |
| 273 | <&msmgpio 17 0>, |
| 274 | <&msmgpio 18 0>, |
| 275 | <&msmgpio 19 0>; |
Oluwafemi Adeyemi | 6cdfdb8 | 2012-11-02 13:36:29 -0700 | [diff] [blame] | 276 | qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; |
Oluwafemi Adeyemi | 4926a9e | 2012-09-14 17:39:59 -0700 | [diff] [blame] | 277 | |
Oluwafemi Adeyemi | 6cdfdb8 | 2012-11-02 13:36:29 -0700 | [diff] [blame] | 278 | qcom,clk-rates = <400000 25000000 50000000 100000000>; |
| 279 | qcom,sup-voltages = <2950 2950>; |
| 280 | qcom,bus-width = <4>; |
| 281 | qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50"; |
Oluwafemi Adeyemi | 4926a9e | 2012-09-14 17:39:59 -0700 | [diff] [blame] | 282 | }; |
Jeff Hugo | cdcb8aa | 2012-10-16 13:41:20 -0600 | [diff] [blame] | 283 | |
| 284 | qcom,bam_dmux@fc834000 { |
| 285 | compatible = "qcom,bam_dmux"; |
| 286 | reg = <0xfc834000 0x7000>; |
| 287 | interrupts = <0 29 1>; |
| 288 | }; |
Tianyi Gou | f6ffa87 | 2012-10-22 14:22:58 -0700 | [diff] [blame] | 289 | |
Talel Atias | 4919639 | 2012-11-20 19:20:14 +0200 | [diff] [blame] | 290 | qcom,ipa@fd4c0000 { |
| 291 | compatible = "qcom,ipa"; |
| 292 | reg = <0xfd4c0000 0x26000>, |
| 293 | <0xfd4c4000 0x14818>; |
| 294 | reg-names = "ipa-base", "bam-base"; |
| 295 | interrupts = <0 252 0>, |
| 296 | <0 253 0>; |
| 297 | interrupt-names = "ipa-irq", "bam-irq"; |
| 298 | |
| 299 | qcom,pipe1 { |
| 300 | label = "a2-to-ipa"; |
| 301 | qcom,src-bam-physical-address = <0xfc834000>; |
| 302 | qcom,ipa-bam-mem-type = <0>; |
| 303 | qcom,src-bam-pipe-index = <1>; |
| 304 | qcom,dst-bam-physical-address = <0xfd4c0000>; |
| 305 | qcom,dst-bam-pipe-index = <6>; |
| 306 | qcom,data-fifo-offset = <0x1000>; |
| 307 | qcom,data-fifo-size = <0xd00>; |
| 308 | qcom,descriptor-fifo-offset = <0x1d00>; |
| 309 | qcom,descriptor-fifo-size = <0x300>; |
| 310 | }; |
| 311 | |
| 312 | qcom,pipe2 { |
| 313 | label = "ipa-to-a2"; |
| 314 | qcom,src-bam-physical-address = <0xfd4c0000>; |
| 315 | qcom,ipa-bam-mem-type = <0>; |
| 316 | qcom,src-bam-pipe-index = <7>; |
| 317 | qcom,dst-bam-physical-address = <0xfc834000>; |
| 318 | qcom,dst-bam-pipe-index = <0>; |
| 319 | qcom,data-fifo-offset = <0x00>; |
| 320 | qcom,data-fifo-size = <0xd00>; |
| 321 | qcom,descriptor-fifo-offset = <0xd00>; |
| 322 | qcom,descriptor-fifo-size = <0x300>; |
| 323 | }; |
| 324 | }; |
| 325 | |
Tianyi Gou | f6ffa87 | 2012-10-22 14:22:58 -0700 | [diff] [blame] | 326 | qcom,acpuclk@f9010000 { |
| 327 | compatible = "qcom,acpuclk-9625"; |
| 328 | reg = <0xf9010008 0x10>, |
| 329 | <0xf9008004 0x4>; |
| 330 | reg-names = "rcg_base", "pwr_base"; |
| 331 | a5_cpu-supply = <&pm8019_l10_corner_ao>; |
| 332 | a5_mem-supply = <&pm8019_l12_ao>; |
| 333 | }; |
Tianyi Gou | 343bd93 | 2012-10-29 11:03:03 -0700 | [diff] [blame] | 334 | |
| 335 | gdsc_usb_hsic: qcom,gdsc@fc400404 { |
| 336 | compatible = "qcom,gdsc"; |
| 337 | reg = <0xfc400404 0x4>; |
| 338 | regulator-name = "gdsc_usb_hsic"; |
| 339 | }; |
Siddartha Mohanadoss | 650af6b | 2012-10-25 20:09:11 -0700 | [diff] [blame] | 340 | |
| 341 | tsens@fc4a8000 { |
| 342 | compatible = "qcom,msm-tsens"; |
| 343 | reg = <0xfc4a8000 0x2000>, |
| 344 | <0xfc4b8000 0x1000>; |
| 345 | reg-names = "tsens_physical", "tsens_eeprom_physical"; |
| 346 | interrupts = <0 184 0>; |
| 347 | qcom,sensors = <5>; |
| 348 | qcom,slope = <3200 3200 3200 3200 3200>; |
| 349 | }; |
Hariprasad Dhalinarasimha | e9ad1da | 2012-11-14 18:21:56 -0800 | [diff] [blame] | 350 | |
| 351 | qcom,msm-rng@f9bff000 { |
| 352 | compatible = "qcom,msm-rng"; |
| 353 | reg = <0xf9bff000 0x200>; |
| 354 | qcom,msm-rng-iface-clk; |
Venkat Sudhir | 49965c7 | 2012-10-23 14:06:10 -0700 | [diff] [blame] | 355 | }; |
| 356 | |
| 357 | wcd9xxx_intc: wcd9xxx-irq { |
| 358 | compatible = "qcom,wcd9xxx-irq"; |
| 359 | interrupt-controller; |
| 360 | #interrupt-cells = <1>; |
| 361 | interrupt-parent = <&msmgpio>; |
| 362 | interrupts = <20 0>; |
| 363 | interrupt-names = "cdc-int"; |
| 364 | }; |
| 365 | |
| 366 | i2c@f9925000 { |
| 367 | cell-index = <3>; |
| 368 | compatible = "qcom,i2c-qup"; |
| 369 | reg = <0xf9925000 0x1000>; |
| 370 | #address-cells = <1>; |
| 371 | #size-cells = <0>; |
| 372 | reg-names = "qup_phys_addr"; |
| 373 | interrupts = <0 97 0>; |
| 374 | interrupt-names = "qup_err_intr"; |
| 375 | qcom,i2c-bus-freq = <100000>; |
| 376 | qcom,i2c-src-freq = <24000000>; |
| 377 | |
| 378 | wcd9xxx_codec@0d{ |
| 379 | compatible = "qcom,wcd9xxx-i2c"; |
| 380 | reg = <0x0d>; |
| 381 | qcom,cdc-reset-gpio = <&msmgpio 22 0>; |
| 382 | interrupt-parent = <&wcd9xxx_intc>; |
| 383 | interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>; |
| 384 | cdc-vdd-buck-supply = <&pm8019_l11>; |
| 385 | qcom,cdc-vdd-buck-voltage = <1800000 1800000>; |
| 386 | qcom,cdc-vdd-buck-current = <25000>; |
| 387 | |
| 388 | cdc-vdd-tx-h-supply = <&pm8019_l11>; |
| 389 | qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; |
| 390 | qcom,cdc-vdd-tx-h-current = <25000>; |
| 391 | |
| 392 | cdc-vdd-rx-h-supply = <&pm8019_l11>; |
| 393 | qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; |
| 394 | qcom,cdc-vdd-rx-h-current = <25000>; |
| 395 | |
| 396 | cdc-vddpx-1-supply = <&pm8019_l11>; |
| 397 | qcom,cdc-vddpx-1-voltage = <1800000 1800000>; |
| 398 | qcom,cdc-vddpx-1-current = <10000>; |
| 399 | |
| 400 | cdc-vdd-a-1p2v-supply = <&pm8019_l9>; |
| 401 | qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>; |
| 402 | qcom,cdc-vdd-a-1p2v-current = <10000>; |
| 403 | |
| 404 | cdc-vddcx-1-supply = <&pm8019_l9>; |
| 405 | qcom,cdc-vddcx-1-voltage = <1200000 1200000>; |
| 406 | qcom,cdc-vddcx-1-current = <10000>; |
| 407 | |
| 408 | cdc-vddcx-2-supply = <&pm8019_l9>; |
| 409 | qcom,cdc-vddcx-2-voltage = <1200000 1200000>; |
| 410 | qcom,cdc-vddcx-2-current = <10000>; |
| 411 | |
| 412 | qcom,cdc-micbias-ldoh-v = <0x3>; |
| 413 | qcom,cdc-micbias-cfilt1-mv = <1800>; |
| 414 | qcom,cdc-micbias-cfilt2-mv = <2700>; |
| 415 | qcom,cdc-micbias-cfilt3-mv = <1800>; |
| 416 | qcom,cdc-micbias1-cfilt-sel = <0x0>; |
| 417 | qcom,cdc-micbias2-cfilt-sel = <0x1>; |
| 418 | qcom,cdc-micbias3-cfilt-sel = <0x2>; |
| 419 | qcom,cdc-micbias4-cfilt-sel = <0x2>; |
| 420 | }; |
| 421 | |
| 422 | wcd9xxx_codec@77{ |
| 423 | compatible = "qcom,wcd9xxx-i2c"; |
| 424 | reg = <0x77>; |
| 425 | }; |
| 426 | |
| 427 | wcd9xxx_codec@66{ |
| 428 | compatible = "qcom,wcd9xxx-i2c"; |
| 429 | reg = <0x66>; |
| 430 | }; |
| 431 | |
| 432 | wcd9xxx_codec@55{ |
| 433 | compatible = "qcom,wcd9xxx-i2c"; |
| 434 | reg = <0x55>; |
| 435 | }; |
| 436 | }; |
| 437 | |
| 438 | sound { |
| 439 | compatible = "qcom,mdm9625-audio-taiko"; |
| 440 | qcom,model = "mdm9625-taiko-i2s-snd-card"; |
| 441 | |
| 442 | qcom,audio-routing = |
| 443 | "RX_BIAS", "MCLK", |
| 444 | "LDO_H", "MCLK", |
| 445 | "Ext Spk Bottom Pos", "LINEOUT1", |
| 446 | "Ext Spk Bottom Neg", "LINEOUT3", |
| 447 | "Ext Spk Top Pos", "LINEOUT2", |
| 448 | "Ext Spk Top Neg", "LINEOUT4", |
| 449 | "AMIC1", "MIC BIAS1 External", |
| 450 | "MIC BIAS1 External", "Handset Mic", |
| 451 | "AMIC2", "MIC BIAS2 External", |
| 452 | "MIC BIAS2 External", "Headset Mic", |
| 453 | "AMIC3", "MIC BIAS3 Internal1", |
| 454 | "MIC BIAS3 Internal1", "ANCRight Headset Mic", |
| 455 | "AMIC4", "MIC BIAS1 Internal2", |
| 456 | "MIC BIAS1 Internal2", "ANCLeft Headset Mic", |
| 457 | "DMIC1", "MIC BIAS1 External", |
| 458 | "MIC BIAS1 External", "Digital Mic1", |
| 459 | "DMIC2", "MIC BIAS1 External", |
| 460 | "MIC BIAS1 External", "Digital Mic2", |
| 461 | "DMIC3", "MIC BIAS3 External", |
| 462 | "MIC BIAS3 External", "Digital Mic3", |
| 463 | "DMIC4", "MIC BIAS3 External", |
| 464 | "MIC BIAS3 External", "Digital Mic4", |
| 465 | "DMIC5", "MIC BIAS4 External", |
| 466 | "MIC BIAS4 External", "Digital Mic5", |
| 467 | "DMIC6", "MIC BIAS4 External", |
| 468 | "MIC BIAS4 External", "Digital Mic6"; |
| 469 | qcom,taiko-mclk-clk-freq = <12288000>; |
| 470 | }; |
| 471 | |
| 472 | qcom,msm-adsp-loader { |
| 473 | compatible = "qcom,adsp-loader"; |
Venkat Sudhir | 480db8a | 2012-11-09 15:31:50 -0800 | [diff] [blame] | 474 | qcom,adsp-state = <2>; |
Venkat Sudhir | 49965c7 | 2012-10-23 14:06:10 -0700 | [diff] [blame] | 475 | }; |
| 476 | |
| 477 | qcom,msm-pcm { |
| 478 | compatible = "qcom,msm-pcm-dsp"; |
| 479 | }; |
| 480 | |
| 481 | qcom,msm-pcm-routing { |
| 482 | compatible = "qcom,msm-pcm-routing"; |
| 483 | }; |
| 484 | |
| 485 | qcom,msm-compr-dsp { |
| 486 | compatible = "qcom,msm-compr-dsp"; |
| 487 | }; |
| 488 | |
| 489 | qcom,msm-voip-dsp { |
| 490 | compatible = "qcom,msm-voip-dsp"; |
| 491 | }; |
| 492 | |
| 493 | qcom,msm-pcm-voice { |
| 494 | compatible = "qcom,msm-pcm-voice"; |
| 495 | }; |
| 496 | |
| 497 | qcom,msm-dai-fe { |
| 498 | compatible = "qcom,msm-dai-fe"; |
| 499 | }; |
| 500 | |
| 501 | qcom,msm-pcm-afe { |
| 502 | compatible = "qcom,msm-pcm-afe"; |
| 503 | }; |
| 504 | |
| 505 | qcom,msm-pcm-hostless { |
| 506 | compatible = "qcom,msm-pcm-hostless"; |
| 507 | }; |
| 508 | |
| 509 | qcom,msm-dai-mi2s { |
| 510 | compatible = "qcom,msm-dai-mi2s"; |
| 511 | qcom,msm-dai-q6-mi2s-prim { |
| 512 | compatible = "qcom,msm-dai-q6-mi2s"; |
| 513 | qcom,msm-dai-q6-mi2s-dev-id = <0>; |
| 514 | qcom,msm-mi2s-rx-lines = <2>; |
| 515 | qcom,msm-mi2s-tx-lines = <1>; |
| 516 | }; |
| 517 | }; |
| 518 | |
| 519 | qcom,msm-dai-q6 { |
| 520 | compatible = "qcom,msm-dai-q6"; |
| 521 | }; |
Vikram Mulukutla | 7f4ed0d | 2012-11-05 15:26:51 -0800 | [diff] [blame] | 522 | |
| 523 | qcom,mss { |
| 524 | compatible = "qcom,pil-q6v5-mss"; |
| 525 | interrupts = <0 24 1>; |
| 526 | }; |
Jeff Hugo | 27a6cf0 | 2012-11-29 15:46:50 -0700 | [diff] [blame] | 527 | |
| 528 | qcom,smem@fa00000 { |
| 529 | compatible = "qcom,smem"; |
| 530 | reg = <0xfa00000 0x200000>, |
| 531 | <0xfa006000 0x1000>, |
| 532 | <0xfc428000 0x4000>; |
| 533 | reg-names = "smem", "irq-reg-base", "aux-mem1"; |
| 534 | |
| 535 | qcom,smd-modem { |
| 536 | compatible = "qcom,smd"; |
| 537 | qcom,smd-edge = <0>; |
| 538 | qcom,smd-irq-offset = <0x8>; |
| 539 | qcom,smd-irq-bitmask = <0x1000>; |
| 540 | qcom,pil-string = "modem"; |
| 541 | interrupts = <0 25 1>; |
| 542 | }; |
| 543 | |
| 544 | qcom,smsm-modem { |
| 545 | compatible = "qcom,smsm"; |
| 546 | qcom,smsm-edge = <0>; |
| 547 | qcom,smsm-irq-offset = <0x8>; |
| 548 | qcom,smsm-irq-bitmask = <0x2000>; |
| 549 | interrupts = <0 26 1>; |
| 550 | }; |
| 551 | |
| 552 | qcom,smd-adsp { |
| 553 | compatible = "qcom,smd"; |
| 554 | qcom,smd-edge = <1>; |
| 555 | qcom,smd-irq-offset = <0x8>; |
| 556 | qcom,smd-irq-bitmask = <0x100>; |
| 557 | qcom,pil-string = "adsp"; |
| 558 | interrupts = <0 156 1>; |
| 559 | }; |
| 560 | |
| 561 | qcom,smsm-adsp { |
| 562 | compatible = "qcom,smsm"; |
| 563 | qcom,smsm-edge = <1>; |
| 564 | qcom,smsm-irq-offset = <0x8>; |
| 565 | qcom,smsm-irq-bitmask = <0x200>; |
| 566 | interrupts = <0 157 1>; |
| 567 | }; |
| 568 | |
| 569 | qcom,smd-rpm { |
| 570 | compatible = "qcom,smd"; |
| 571 | qcom,smd-edge = <15>; |
| 572 | qcom,smd-irq-offset = <0x8>; |
| 573 | qcom,smd-irq-bitmask = <0x1>; |
| 574 | interrupts = <0 168 1>; |
| 575 | qcom,irq-no-suspend; |
| 576 | }; |
| 577 | }; |
Rohit Vaswani | 3fc6034 | 2012-04-23 18:55:15 -0700 | [diff] [blame] | 578 | }; |
David Collins | a2b73f2 | 2012-09-13 17:32:16 -0700 | [diff] [blame] | 579 | |
David Collins | 722a651 | 2012-09-14 11:09:18 -0700 | [diff] [blame] | 580 | /include/ "msm-pm8019-rpm-regulator.dtsi" |
David Collins | a2b73f2 | 2012-09-13 17:32:16 -0700 | [diff] [blame] | 581 | /include/ "msm-pm8019.dtsi" |
David Collins | 56b4112 | 2012-09-24 17:09:23 -0700 | [diff] [blame] | 582 | /include/ "msm9625-regulator.dtsi" |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 583 | |
| 584 | &pm8019_vadc { |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 585 | chan@31 { |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 586 | label = "batt_id_therm"; |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 587 | reg = <0x31>; |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 588 | qcom,decimation = <0>; |
| 589 | qcom,pre-div-channel-scaling = <0>; |
| 590 | qcom,calibration-type = "ratiometric"; |
| 591 | qcom,scale-function = <0>; |
| 592 | qcom,hw-settle-time = <0>; |
| 593 | qcom,fast-avg-setup = <0>; |
| 594 | }; |
| 595 | |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 596 | chan@33 { |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 597 | label = "pa_therm1"; |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 598 | reg = <0x33>; |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 599 | qcom,decimation = <0>; |
| 600 | qcom,pre-div-channel-scaling = <0>; |
| 601 | qcom,calibration-type = "ratiometric"; |
| 602 | qcom,scale-function = <2>; |
| 603 | qcom,hw-settle-time = <0>; |
| 604 | qcom,fast-avg-setup = <0>; |
| 605 | }; |
| 606 | |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 607 | chan@34 { |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 608 | label = "pa_therm2"; |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 609 | reg = <0x34>; |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 610 | qcom,decimation = <0>; |
| 611 | qcom,pre-div-channel-scaling = <0>; |
| 612 | qcom,calibration-type = "ratiometric"; |
| 613 | qcom,scale-function = <2>; |
| 614 | qcom,hw-settle-time = <0>; |
| 615 | qcom,fast-avg-setup = <0>; |
| 616 | }; |
| 617 | |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 618 | chan@32 { |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 619 | label = "xo_therm"; |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 620 | reg = <0x32>; |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 621 | qcom,decimation = <0>; |
| 622 | qcom,pre-div-channel-scaling = <0>; |
| 623 | qcom,calibration-type = "ratiometric"; |
| 624 | qcom,scale-function = <4>; |
| 625 | qcom,hw-settle-time = <0>; |
| 626 | qcom,fast-avg-setup = <0>; |
| 627 | }; |
| 628 | |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 629 | chan@3c { |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 630 | label = "xo_therm_amux"; |
Siddartha Mohanadoss | 96be0a0 | 2012-12-07 14:38:48 -0800 | [diff] [blame^] | 631 | reg = <0x3c>; |
Siddartha Mohanadoss | c47fcce | 2012-09-25 17:21:50 -0700 | [diff] [blame] | 632 | qcom,decimation = <0>; |
| 633 | qcom,pre-div-channel-scaling = <0>; |
| 634 | qcom,calibration-type = "ratiometric"; |
| 635 | qcom,scale-function = <4>; |
| 636 | qcom,hw-settle-time = <0>; |
| 637 | qcom,fast-avg-setup = <0>; |
| 638 | }; |
| 639 | }; |